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ISL54050
Data Sheet June 11, 2007 FN6356.2
Ultra Low ON-Resistance, +1.65V to +4.5V, Single Supply, Dual SPDT Analog Switch
The Intersil ISL54050 device is a low ON-resistance, low voltage, bidirectional, dual single-pole/double-throw (SPDT) analog switch designed to operate from a single +1.65V to +4.5V supply. Targeted applications include battery powered equipment that benefit from low rON (0.29) and fast switching speeds (tON = 40ns, tOFF = 20ns). The digital logic input is 1.8V logic-compatible when using a single +3V supply. Cell phones, for example, often face ASIC functionality limitations. The number of analog input or GPIO pins may be limited and digital geometries are not well suited to analog switch performance. This part may be used to "mux-in" additional functionality while reducing ASIC design risk. The ISL54050 is offered in small form factor package, alleviating board space limitations. The ISL54050 is a committed dual single-pole/double-throw (SPDT) that consist of two normally open (NO) and two normally closed (NC) switches. This configuration can be used as a dual 2-to-1 multiplexer. The ISL54050 is pin compatible with the NLAS5223 and NLAS5223L.
TABLE 1. FEATURES AT A GLANCE ISL54050 Number of Switches SW 4.3V rON 4.3V tON/tOFF 3V rON 3V tON/tOFF 1.8V rON 1.8V tON/tOFF Package 2 SPDT or 2-1 MUX 0.29 40ns/20ns 0.33 50ns/27ns 0.55 70ns/54ns 10 Ld 1.8mmx1.4mmx0.5mm TQFN
Features
* Pb-Free Plus Anneal Available (RoHS Compliant) * Pin Compatible Replacement for the NLAS5223 and NLAS5223L * ON-Resistance (rON) - V+ = +4.3V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.29 - V+ = +3.0V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.33 - V+ = +1.8V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.55 * rON Matching Between Channels . . . . . . . . . . . . . . . . . 0.06 * rON Flatness Across Signal Range . . . . . . . . . . . . . . . . 0.03 * Single Supply Operation . . . . . . . . . . . . . . . +1.65V to +4.5V * Low Power Consumption (PD). . . . . . . . . . . . . . . <0.45W * Fast Switching Action (V+ = +4.3V) - tON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40ns - tOFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20ns * ESD HBM Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>8kV * Break-before-Make * 1.8V Logic Compatible (+3V supply) * Low ICC Current when VinH is not at the V+ Rail * Available in 10 Ld 1.8mmx1.4mmx0.5mm TQFN
Applications
* Battery powered, Handheld, and Portable Equipment - Cellular/mobile Phones - Pagers - Laptops, Notebooks, Palmtops * Portable Test and Measurement * Medical Equipment * Audio and Video Switching
Related Literature
* Technical Brief TB363 "Guidelines for Handling and Processing Moisture Sensitive Surface Mount Devices (SMDs)" * Application Note AN557 "Recommended Test Procedures for Analog Switches"
Ordering Information
PART NUMBER (Note) ISL54050IRUZ-T A PART MARKING TEMP. RANGE (C) -40 to +85 PACKAGE (Pb-free) 10 Ld 1.8mmx1.4mmx0.5mm TQFN Tape and Reel (0.40mm pitch) PKG. DWG. # L10.1.8x1.4A
NOTE: Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pbfree peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020C.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2006, 2007. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
ISL54050 Pinout
(Note 1) ISL54050 (10 LD TQFN) TOP VIEW
NC2 7 IN2 8 GND 6 5 NC1
Pin Descriptions
PIN V+ GND IN COM FUNCTION System Power Supply Input (+1.65V to +4.5V) Ground Connection Digital Control Input Analog Switch Common Pin Analog Switch Normally Open Pin Analog Switch Normally Closed Pin
COM2
9
4
IN1
NO NC
NO2
10 1 V+ 2 NO1
3
COM1
NOTE: 1. Switches Shown for Logic "0" Input.
Truth Table
LOGIC 0 1 NOTE: NC1 and NC2 ON OFF NO1 and NO2 OFF ON
Logic "0" 0.5V. Logic "1" 1.4V with a 3V supply.
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FN6356.2 June 11, 2007
ISL54050
Absolute Maximum Ratings
V+ to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 5.5V Input Voltages NO, NC, IN (Note 2). . . . . . . . . . . . . . . . . . . . -0.5V to ((V+) + 0.5V) Output Voltages COM (Note 2). . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to ((V+) + 0.5V) Continuous Current NO, NC, or COM . . . . . . . . . . . . . . . . . 300mA Peak Current NO, NC, or COM (Pulsed 1ms, 10% Duty Cycle, Max) . . . . . . . . . . . . . . . . . . 500mA ESD Rating Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>8kV Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>500V Charged Device Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . >1.4kV
Thermal Information
Thermal Resistance (Typical) JA (C/W) 10 Ld TQFN Package (Note 3) . . . . . . . . . . . . . . . 143 Maximum Junction Temperature (Plastic Package). . . . . . . +150C Maximum Storage Temperature Range . . . . . . . . . . . -65C to +150C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Operating Conditions
Temperature Range ISL54050IRUZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40C to +85C
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. Extended operation above the recommended operating conditions could result in decreased reliability. The Absolute Maximum Ratings are stress only ratings and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES: 2. Signals on NC, NO, IN, or COM exceeding V+ or GND are clamped by internal diodes. Limit forward diode current to maximum current ratings. 3. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Electrical Specifications - 4.3V Supply
Test Conditions: V+ = +3.9V to +4.5V, GND = 0V, VINH = 1.6V, VINL = 0.5V (Notes 4, 8), Unless Otherwise Specified. TEST CONDITIONS TEMP (C) MIN (Note 5) TYP MAX (Note 5) UNITS
PARAMETER ANALOG SWITCH CHARACTERISTICS Analog Signal Range, VANALOG ON-Resistance, rON
Full V+ = 3.9V, ICOM = 100mA, VNO or VNC = 0V to V+, (See Figure 5) V+ = 3.9V, ICOM = 100mA, VNO or VNC = Voltage at max rON, (Note 7) V+ = 3.9V, ICOM = 100mA, VNO or VNC = 0V to V+, (Note 6) V+ = 4.5V, VCOM = 0.3V, 3V, VNO or VNC = 3V, 0.3V 25 Full 25 Full 25 Full 25 Full V+ = 4.5V, VCOM = 0.3V, 3V, or VNO or VNC = 0.3V, 3V or floating 25 Full
0 0.30 0.35 0.06 0.08 0.03 0.04 -100 -195 -100 -195
V+
V
rON Matching Between Channels, rON rON Flatness, rFLAT(ON)
NO or NC OFF Leakage Current, INO(OFF) or INC(OFF) COM ON Leakage Current, ICOM(ON) DYNAMIC CHARACTERISTICS Turn-ON Time, tON
100 195 100 195
nA nA nA nA
V+ = 3.9V, VNO or VNC = 3.0V, RL = 50, CL = 35pF, (See Figure 1) V+ = 3.9V, VNO or VNC = 3.0V, RL = 50, CL = 35pF, (See Figure 1) V+ = 4.5V, VNO or VNC = 3.0V, RL = 50, CL = 35pF, (See Figure 3) CL = 1.0nF, VG = 0V, RG = 0, See Figure 2 RL = 50, CL = 5pF, f = 100kHz, VCOM = 1VRMS, (See Figure 4)
25 Full 25 Full Full 25 25
40 50 20 30 8 170 62
ns ns ns ns ns pC dB
Turn-OFF Time, tOFF
Break-Before-Make Time Delay, tD Charge Injection, Q OFF Isolation
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FN6356.2 June 11, 2007
ISL54050
Electrical Specifications - 4.3V Supply
Test Conditions: V+ = +3.9V to +4.5V, GND = 0V, VINH = 1.6V, VINL = 0.5V (Notes 4, 8), Unless Otherwise Specified. (Continued) TEST CONDITIONS RL = 50, CL = 5pF, f = 100kHz, VCOM = 1VRMS, (See Figure 6) f = 20Hz to 20kHz, VCOM = 2VP-P, RL = 600 TEMP (C) 25 25 25 25 MIN (Note 5) TYP -85 0.005 62 176 MAX (Note 5) UNITS dB % pF pF
PARAMETER Crosstalk (Channel-to-Channel) Total Harmonic Distortion
NO or NC OFF Capacitance, COFF f = 1MHz, VNO or VNC = VCOM = 0V, (See Figure 7) COM ON Capacitance, CCOM(ON) f = 1MHz, VNO or VNC = VCOM = 0V, (See Figure 7)
POWER SUPPLY CHARACTERISTICS Power Supply Range Positive Supply Current, I+ V+ = +4.5V, VIN = 0V or V+ Full 25 Full Positive Supply Current, I+ V+ = +4.2V, VIN = 2.85V 25 1.65 4.5 0.1 1 12 V A A A
DIGITAL INPUT CHARACTERISTICS Input Voltage Low, VINL Input Voltage High, VINH Input Current, IINH, IINL NOTES: 4. VIN = input voltage to perform proper function. 5. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. 6. Flatness is defined as the difference between maximum and minimum value of on-resistance over the specified analog signal range. 7. rON matching between channels is calculated by subtracting the channel with the highest max rON value from the channel with lowest max rON value, between NC1 and NC2 or between NO1 and NO2. 8. Parts are 100% tested at +25C. Limits across full temperature range are guaranteed by design and correlation. V+ = 4.5V, VIN = 0V or V+ Full Full Full 1.6 -0.5 0.5 0.5 V V A
Electrical Specifications - 3V Supply
Test Conditions: V+ = +2.7V to +3.3V, GND = 0V, VINH = 1.4V, VINL = 0.5V (Notes 4, 8), Unless Otherwise Specified. TEST CONDITIONS TEMP (C) MIN (Note 5) TYP MAX (Note 5) UNITS
PARAMETER ANALOG SWITCH CHARACTERISTICS Analog Signal Range, VANALOG ON-Resistance, rON
Full V+ = 2.7V, ICOM = 100mA, VNO or VNC = 0V to V+, (See Figure 5) V+ = 2.7V, ICOM = 100mA, VNO or VNC = Voltage at max rON, (Note 7) V+ = 2.7V, ICOM = 100mA, VNO or VNC = 0V to V+, (Note 6) V+ = 3.3V, VCOM = 0.3V, 3V, VNO or VNC = 3V, 0.3V 25 Full 25 Full 25 Full 25 Full V+ = 3.3V, VCOM = 0.3V, 3V, or VNO or VNC = 0.3V, 3V, or floating 25 Full
0 0.35
V+ 0.5 0.7 0.06 0.07 0.08 0.03 0.15 0.15 0.9 30 0.8 30
V nA nA nA nA
rON Matching Between Channels, rON rON Flatness, rFLAT(ON)
NO or NC OFF Leakage Current, INO(OFF) or INC(OFF) COM ON Leakage Current, ICOM(ON) DYNAMIC CHARACTERISTICS Turn-ON Time, tON
V+ = 2.7V, VNO or VNC = 1.5V, RL = 50, CL = 35pF, (See Figure 1)
25 Full
50 60
ns ns
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FN6356.2 June 11, 2007
ISL54050
Electrical Specifications - 3V Supply
Test Conditions: V+ = +2.7V to +3.3V, GND = 0V, VINH = 1.4V, VINL = 0.5V (Notes 4, 8), Unless Otherwise Specified. (Continued) TEST CONDITIONS V+ = 2.7V, VNO or VNC = 1.5V, RL = 50, CL = 35pF, (See Figure 1) V+ = 3.3V, VNO or VNC = 1.5V, RL = 50, CL = 35pF, (See Figure 3) CL = 1.0nF, VG = 0V, RG = 0, (See Figure 2) RL = 50, CL = 5pF, f = 100kHz, VCOM = 1VRMS, (See Figure 4) RL = 50, CL = 5pF, f = 100kHz, VCOM = 1VRMS, (See Figure 6) f = 20Hz to 20kHz, VCOM = 2VP-P, RL = 600 TEMP (C) 25 Full Full 25 25 25 25 25 25 MIN (Note 5) TYP 27 35 9 94 62 -85 0.005 65 181 MAX (Note 5) UNITS ns ns ns pC dB dB % pF pF
PARAMETER Turn-OFF Time, tOFF
Break-Before-Make Time Delay, tD Charge Injection, Q OFF Isolation Crosstalk (Channel-to-Channel) Total Harmonic Distortion
NO or NC OFF Capacitance, COFF f = 1MHz, VNO or VNC = VCOM = 0V, (See Figure 7) COM ON Capacitance, CCOM(ON) f = 1MHz, VNO or VNC = VCOM = 0V, (See Figure 7)
POWER SUPPLY CHARACTERISTICS Positive Supply Current, I+ V+ = +3.6V, VIN = 0V or V+ 25 Full DIGITAL INPUT CHARACTERISTICS Input Voltage Low, VINL Input Voltage High, VINH Input Current, IINH, IINL V+ = 3.3V, VIN = 0V or V+ 25 25 Full 1.4 -0.5 0.5 0.5 V V A 0.01 0.52 A A
Electrical Specifications - 1.8V Supply
Test Conditions: V+ = +1.65V to +2V, GND = 0V, VINH = 1.0V, VINL = 0.4V (Notes 4, 8), Unless Otherwise Specified. TEST CONDITIONS TEMP (C) MIN (Note 5) TYP MAX (Note 5) UNITS
PARAMETER ANALOG SWITCH CHARACTERISTICS Analog Signal Range, VANALOG ON-Resistance, rON
Full V+ = 1.65V, ICOM = 100mA, VNO or VNC = 0V to V+, (See Figure 5) 25 Full
0 0.7
V+ 0.8 0.85
V
DYNAMIC CHARACTERISTICS Turn-ON Time, tON V+ = 1.65V, VNO or VNC = 1.0V, RL = 50, CL = 35pF, (See Figure 1) V+ = 1.65V, VNO or VNC = 1.0V, RL = 50, CL = 35pF, (See Figure 1) V+ = 2.0V, VNO or VNC = 1.0V, RL = 50, CL = 35pF, (See Figure 3) CL = 1.0nF, VG = 0V, RG = 0, (See Figure 2) 25 Full 25 Full Full 25 25 25 70 80 54 65 10 42 70 186 ns ns ns ns ns pC pF pF
Turn-OFF Time, tOFF
Break-Before-Make Time Delay, td Charge Injection, Q
NO or NC OFF Capacitance, COFF f = 1MHz, VNO or VNC = VCOM = 0V, (See Figure 7) COM ON Capacitance, CCOM(ON) f = 1MHz, VNO or VNC = VCOM = 0V, (See Figure 7)
DIGITAL INPUT CHARACTERISTICS Input Voltage Low, VINL Input Voltage High, VINH Input Current, IINH, IINL V+ = 2.0V, VIN = 0V or V+ 25 25 Full 1.0 -0.5 0.5 0.4 V V A
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FN6356.2 June 11, 2007
ISL54050 Test Circuits and Waveforms
V+ V+ LOGIC INPUT 0V tOFF SWITCH INPUT VNO 90% SWITCH OUTPUT 0V tON VOUT 90% LOGIC INPUT SWITCH INPUT NO or NC COM IN GND RL 50 CL 35pF VOUT 50% tr < 5ns tf < 5ns C
Logic input waveform is inverted for switches that have the opposite logic sense.
Repeat test for all switches. CL includes fixture and stray capacitance. RL V OUT = V (NO or NC) --------------------------R L + r ( ON ) FIGURE 1B. TEST CIRCUIT
FIGURE 1A. MEASUREMENT POINTS FIGURE 1. SWITCHING TIMES
V+
C
SWITCH OUTPUT VOUT
VOUT
RG
NO or NC
COM
VOUT
V+ LOGIC INPUT ON OFF 0V Q = VOUT x CL ON
VG
GND
IN
CL LOGIC INPUT
Repeat test for all switches. FIGURE 2A. MEASUREMENT POINTS FIGURE 2. CHARGE INJECTION FIGURE 2B. TEST CIRCUIT
V+ V+ LOGIC INPUT 0V VNX
NO
C
COM
NC
VOUT RL 50 CL 35pF
SWITCH OUTPUT VOUT
90% 0V tD LOGIC INPUT
IN GND
FIGURE 3A. MEASUREMENT POINTS
Repeat test for all switches. CL includes fixture and stray capacitance. FIGURE 3B. TEST CIRCUIT
FIGURE 3. BREAK-BEFORE-MAKE TIME
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FN6356.2 June 11, 2007
ISL54050 Test Circuits and Waveforms (Continued)
V+ C SIGNAL GENERATOR V+ C
NO or NC
rON = V1/100mA
NO or NC
IN
0V or V+
VNX 100mA V1 IN 0V or V+
ANALYZER RL
COM
GND
COM
GND
Signal direction through switch is reversed, worst case values are recorded. Repeat test for all switches. FIGURE 4. OFF ISOLATION TEST CIRCUIT
Repeat test for all switches. FIGURE 5. rON TEST CIRCUIT
V+ C V+ C SIGNAL GENERATOR
NO or NC COM
50
NO or NC
IN1 0V or V+ IMPEDANCE ANALYZER ANALYZER RL
COM NC or NO
IN
0V or V+
N.C.
COM
GND
GND
Signal direction through switch is reversed, worst case values are recorded. Repeat test for all switches. FIGURE 6. CROSSTALK TEST CIRCUIT
Repeat test for all switches. FIGURE 7. CAPACITANCE TEST CIRCUIT
Detailed Description
The ISL54050 is a bidirectional, dual single pole/double throw (SPDT) analog switch that offers precise switching capability from a single 1.65V to 4.5V supply with low ON-resistance (0.29) and high speed operation (tON = 40ns, tOFF = 20ns). The device is especially well suited for portable battery powered equipment due to its low operating supply voltage (1.65V), low power consumption (4.5W max), low leakage currents (195nA max), and the tiny TQFN package. The ultra low ON-resistance and rON flatness provide very low insertion loss and distortion to applications that require signal reproduction.
During an overvoltage transient event, such as occurs during system level IEC 61000 ESD testing, substrate currents can be generated in the IC that can trigger parasitic SCR structures to turn ON, creating a low impedance path from the V+ power supply to ground. This will result in a significant amount of current flow in the IC, which can potentially create a latch-up state or permanently damage the IC. The external V+ resistor limits the current during this over-stress situation and has been found to prevent latch-up or destructive damage for many overvoltage transient events. Under normal operation the sub-microamp IDD current of the IC produces an insignificant voltage drop across the 100 series resistor resulting in no impact to switch operation or performance.
External V+ Series Resistor
For improved ESD and latch-up immunity, Intersil recommends adding a 100 resistor in series with the V+ power supply pin of the ISL54050 IC (see Figure 8). 7
FN6356.2 June 11, 2007
ISL54050
V+ OPTIONAL PROTECTION RESISTOR
NO
C
OPTIONAL SCHOTTKY DIODE V+ OPTIONAL PROTECTION RESISTOR COM
100 INX VNX
NC
VCOM
IN GND OPTIONAL SCHOTTKY DIODE GND
FIGURE 8. V+ SERIES RESISTOR FOR ENHANCED ESD AND LATCH-UP IMMUNITY
FIGURE 9. OVERVOLTAGE PROTECTION
Supply Sequencing and Overvoltage Protection
With any CMOS device, proper power supply sequencing is required to protect the device from excessive input currents which might permanently damage the IC. All I/O pins contain ESD protection diodes from the pin to V+ and to GND (see Figure 9). To prevent forward biasing these diodes, V+ must be applied before any input signals, and the input signal voltages must remain between V+ and GND. If these conditions cannot be guaranteed, then precautions must be implemented to prohibit the current and voltage at the logic pin and signal pins from exceeding the maximum ratings of the switch. The following two methods can be used to provided additional protection to limit the current in the event that the voltage at a signal pin or logic pin goes below ground or above the V+ rail. Logic inputs can be protected by adding a 1k resistor in series with the logic input (see Figure 9). The resistor limits the input current below the threshold that produces permanent damage, and the sub-micro amp input current produces an insignificant voltage drop during normal operation. This method is not acceptable for the signal path inputs. Adding a series resistor to the switch input defeats the purpose of using a low rON switch. Connecting schottky diodes to the signal pins as shown in Figure 9 will shunt the fault current to the supply or to ground thereby protecting the switch. These schottky diodes must be sized to handle the expected fault current.
Power-Supply Considerations
The ISL54050 construction is typical of most single supply CMOS analog switches, in that they have two supply pins: V+ and GND. V+ and GND drive the internal CMOS switches and set their analog voltage limits. Unlike switches with a 4V maximum supply voltage, the ISL54050 5.5V maximum supply voltage provides plenty of room for the 10% tolerance of 4.3V supplies, as well as room for overshoot and noise spikes. The minimum recommended supply voltage is 1.65V. It is important to note that the input signal range, switching times, and ON-resistance degrade at lower supply voltages. Refer to the Electrical Specification tables and "Typical Performance Curves" on page 9 for details. V+ and GND also power the internal logic and level shifters. The level shifters convert the input logic levels to switched V+ and GND signals to drive the analog switch gate terminals. This family of switches cannot be operated with bipolar supplies, because the input switching point becomes negative in this configuration.
Logic-Level Thresholds
This switch family is 1.8V CMOS compatible (0.5V and 1.4V) over a supply range of 2.7V to 4.5V (see Figure 19). At 2.7V the VIL level is about 0.53V. This is still above the 1.8V CMOS guaranteed low output maximum level of 0.5V, but noise margin is reduced. The digital input stages draw supply current whenever the digital input voltage is not at one of the supply rails. Driving the digital input signals from GND to V+ with a fast transition time minimizes power dissipation. The ISL54050 has been designed to minimize the supply current whenever the digital input voltage is not driven to the supply rails (0V to V+). For example, driving the device with 2.85V logic (0V to 2.85V) while operating with a 4.2V supply, the device draws only 12A of current (see Figure 17 for VIN = 2.85V).
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FN6356.2 June 11, 2007
ISL54050
Frequency Performance
In 50 systems, the ISL54050 has a -3dB bandwidth of 120MHz (see Figure 22). The frequency response is very consistent over a wide V+ range and for varying analog signal levels. An OFF switch acts like a capacitor and passes higher frequencies with less attenuation, resulting in signal feed through from a switch's input to its output. Off isolation is the resistance to this feed through, while crosstalk indicates the amount of feed through from one switch to another. Figure 23 details the high off isolation and crosstalk rejection provided by this part. At 100kHz, off isolation is about 62dB in 50 systems, decreasing approximately 20dB per decade as frequency increases. Higher load impedances decrease off isolation and crosstalk rejection due to the voltage divider action of the switch OFF impedance and the load impedance.
Leakage Considerations
Reverse ESD protection diodes are internally connected between each analog-signal pin and both V+ and GND. One of these diodes conducts if any analog signal exceeds V+ or GND. Virtually all the analog leakage current comes from the ESD diodes to V+ or GND. Although the ESD diodes on a given signal pin are identical and therefore fairly well balanced, they are reverse biased differently. Each is biased by either V+ or GND and the analog signal. This means their leakages will vary as the signal varies. The difference in the two diode leakages to the V+ and GND pins constitutes the analog-signal-path leakage current. All analog leakage current flows between each pin and one of the supply terminals, not to the other switch terminal. This is why both sides of a given switch can show leakage currents of the same or opposite polarity. There is no connection between the analog signal paths and V+ or GND.
Typical Performance Curves TA = +25C, Unless Otherwise Specified
0.30 ICOM = 100mA 0.34 0.29 0.33 rON () rON () 0.28 0.32 0.31 0.30 0.26 V+ = 4.3V V+ = 4.5V 0 1 2 VCOM (V) 3 4 5 0.29 0.28 0 0.5 1.0 1.5 2.0 VCOM (V) 2.5 3.0 3.5 V+ = 3V V+ = 2.7V 0.35 ICOM = 100mA
0.27
V+ = 3.9V
V+ = 3.3V
0.25
FIGURE 10. ON-RESISTANCE vs SUPPLY VOLTAGE vs SWITCH VOLTAGE
FIGURE 11. ON-RESISTANCE vs SUPPLY VOLTAGE vs SWITCH VOLTAGE
0.70 ICOM = 100mA 0.65 0.60 0.55 rON () 0.50 0.45 V+ = 2V 0.40 0.35 0.30 0 0.5 1.0 VCOM (V) 1.5 2.0 V+ = 1.8V rON () V+ = 1.65V
0.35
V+ = 4.3V ICOM = 100mA +85C
0.30
+25C 0.25
-40C 0.20 0 1 2 3 VCOM (V) 4 5
FIGURE 12. ON-RESISTANCE vs SUPPLY VOLTAGE vs SWITCH VOLTAGE
FIGURE 13. ON-RESISTANCE vs SWITCH VOLTAGE
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FN6356.2 June 11, 2007
ISL54050 Typical Performance Curves TA = +25C, Unless Otherwise Specified (Continued)
0.40 V+ = 3.3V ICOM = 100mA 0.40 +85C V+ = 2.7V ICOM = 100mA
0.35
+85C rON ()
0.35 +25C
rON ()
0.30
+25C
0.30 0.25 -40C -40C 0.25
0.20
0
0.5
1.0
1.5 2.0 VCOM (V)
2.5
3.0
3.5
0
0.5
1.0
1.5 VCOM (V)
2.0
2.5
3.0
FIGURE 14. ON-RESISTANCE vs SWITCH VOLTAGE
FIGURE 15. ON-RESISTANCE vs SWITCH VOLTAGE
0.60 +85C 0.55 0.50 rON () 0.45 0.40 0.35 0.30 0.25 +25C
V+ = 1.8V ICOM = 100mA
200 V+ = 4.2V SWEEPING BOTH LOGIC INPUTS 150
-40C iON (A)
100
50
0 0 0.5 1.0 VCOM (V) 1.5 2.0
1
2 3 VIN1 AND VIN2 (V)
4
5
FIGURE 16. ON-RESISTANCE vs SWITCH VOLTAGE
FIGURE 17. SUPPLY CURRENT vs VLOGIC VOLTAGE
200
1.1 1.0 0.9 VINH AND VINL (V) VINH
150
100 Q (pC) V+ = 4.3V 50 V+ = 1.8V V+ = 3V -50
0.8 0.7 0.6 0.5 0.4
0
VINL
-100
0
1
2 VCOM (V)
3
4
5
0.3 1.5
2.0
2.5
3.0 V+ (V)
3.5
4.0
4.5
FIGURE 18. CHARGE INJECTION vs SWITCH VOLTAGE
FIGURE 19. DIGITAL SWITCHING POINT vs SUPPLY VOLTAGE
10
FN6356.2 June 11, 2007
ISL54050 Typical Performance Curves TA = +25C, Unless Otherwise Specified (Continued)
250 200
200 +85C +25C 100 -40C tOFF (ns) tON (ns)
150
150
100
+85C +25C
50
-40C
25 1.0
1.5
2.0
2.5 3.0 V+ (V)
3.5
4.0
4.5
0 1.0
1.5
2.0
2.5 3.0 V+ (V)
3.5
4.0
4.5
FIGURE 20. TURN-ON TIME vs SUPPLY VOLTAGE
FIGURE 21. TURN-OFF TIME vs SUPPLY VOLTAGE
NORMALIZED GAIN (dB)
V+ = 3V 0 GAIN
-10 -20 -30 CROSSTALK (dB) -40 -50 -60 -70 -80 -90 -100
10 V+ = 4.3V 20 30 40 50 ISOLATION 60 70 80 CROSSTALK 90 100 10k 100k 1M 10M FREQUENCY (Hz) 100M 110 500M OFF ISOLATION (dB)
-20
PHASE
0 20 PHASE () 40 60 80
RL = 50 VIN = 0.2VP-P to 2VP-P 1M 10M 100M FREQUENCY (Hz)
100 600M
-110 1k
FIGURE 22. FREQUENCY RESPONSE
FIGURE 23. CROSSTALK AND OFF ISOLATION
Die Characteristics
SUBSTRATE POTENTIAL (POWERED UP): GND TRANSISTOR COUNT: 114 PROCESS: Submicron CMOS
11
FN6356.2 June 11, 2007
ISL54050 Ultra Thin Quad Flat No-Lead Plastic Package (UTQFN)
D A B
L10.1.8x1.4A
10 LEAD ULTRA THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE MILLIMETERS SYMBOL MIN 0.45 NOMINAL 0.50 0.127 REF 0.15 1.75 1.35 0.20 1.80 1.40 0.40 BSC 0.35 0.45 0.40 0.50 10 2 3 0 12 0.45 0.55 0.25 1.85 1.45 MAX 0.55 0.05 NOTES 5 2 3 3 4 Rev. 3 6/06 NOTES: 1. Dimensioning and tolerancing conform to ASME Y14.5-1994. 2. N is the number of terminals. 3. Nd and Ne refer to the number of terminals on D and E side, respectively. 4. All dimensions are in millimeters. Angles are in degrees. 5. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 7. Maximum package warpage is 0.05mm. 8. Maximum allowable burrs is 0.076mm in all directions.
6 INDEX AREA 2X 2X 0.10 C
N
E
1 0.10 C
2
A A1
TOP VIEW
A3 b
0.10 C 0.05 C SEATING PLANE A1 SIDE VIEW A
D
C
E e L L1 N
(DATUM A) PIN #1 ID L1 NX L 1 2 NX b 5 10X 0.10 M C A B 0.05 M C 5 7 e BOTTOM VIEW (DATUM B)
Nd Ne
NX (b) 5
(A1)
C L
L SECTION "C-C" CC 2.20 1.00 0.60 e TERMINAL TIP
9. JEDEC Reference MO-255. 10. For additional information, to assist with the PCB Land Pattern Design effort, see Intersil Technical Brief TB389.
1.00
0.50 1.80 0.40 0.20 0.40 10 LAND PATTERN 0.20
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 12
FN6356.2 June 11, 2007

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