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LR38617
LR38617
DESCRIPTION
The LR38617 is a CMOS timing generator IC which generates timing pulses for driving 3 300 k/ 3 370 k-pixel CCD area sensors and processing pulses.
Timing Generator IC for 3 300 k/3 370 k-pixel CCDs
PIN CONNECTIONS
48-PIN QFP TOP VIEW
48 47 46 45 44 43 42 41 40 39 38 37
FEATURES
* Designed for 1/1.8-type 3 300 k/3 370 k-pixel CCD area sensors * Frequency of driving horizontal CCD : 18.00 MHz * In monitoring mode, it can be obtained 30 fields/s. * External shutter control function with serial data input is possible * +3.3 V and +4.5 V power supplies * Package : 48-pin QFP (P-QFP048-0707) 0.5 mm pin-pitch
OFDC 1 V1X 2 VH1AX 3 VH1BX 4 V2X 5 VDD3 6 GND 7 V3X 8 VH3AX 9 VH3BX 10 V4X 11 OFDX 12 13 14 15 16 17 18 19 20 21 22 23 24 PBLK BCPX CLPX ADCK GND FCDS FS VDD3 ACLX RS GND TIN
SHTR CCD FR NC VDD4 FH2 GND FH1 VDD4 NC NC TST1 36 ID 35 ED2 34 ED1 33 ED0 32 HD 31 GND 30 VDD3 29 VD 28 DCLK 27 CLK 26 CKO 25 CKI
(P-QFP048-0707)
In the absence of confirmation by device specification sheets, SHARP takes no responsibility for any defects that may occur in equipment using any SHARP devices shown in catalogs, data books, etc. Contact SHARP in order to obtain the latest device specification sheets before using any SHARP device.
1
LR38617
BLOCK DIAGRAM
DCLK GND CKO VDD3 CLK ED2 ED1 ED0 CKI 25 OSC TST1 37 NC 38 NC 39 VDD4 40 1/2 FH1 41 GND 42 FH2 43 RESET VDD4 44 NC 45 FR 46 CCD 47 SHTR 48 LEVEL SHIFTER RESET DECODER GATE 17 GND 16 ADCK 15 CLPX 14 BCPX 13 PBLK H COUNTER 1/2 1/7 RESET 20 VDD3 19 FS 18 FCDS DATA LATCH & SHUTTER CONTROL 24 TIN 23 GND 22 RS 21 ACLX 12 OFDX HD VD 29
36
ID
35
34
33
32
31
30
28
27
26
V COUNTER
1 OFDC
2 V1X
3 VH1AX
4 VH1BX
5 V2X
6 VDD3
7 GND
8 V3X
9 VH3AX
10 VH3BX
11 V4X
2
LR38617
PIN DESCRIPTION
PIN NO. SYMBOL IO SYMBOL POLARITY 1 2 OFDC V1X O3 O3 PIN NAME Control pulse output for OFD voltage Vertical transfer pulse output 1 Readout pulse output 1A Readout pulse output 1B Vertical transfer pulse output 2 - - Power supply Ground Vertical transfer pulse output 3 Readout pulse output 3A Readout pulse output 3B Vertical transfer pulse output 4 DESCRIPTION A pulse to control OFD voltage. A vertical transfer pulse for the CCD. Connect to V1X pin of vertical driver IC. A pulse that transfers the charge of the photo-diode to the vertical shift register. Connect to VH1AX pin of vertical driver IC. A pulse that transfers the charge of the photo-diode to the vertical shift register. Connect to VH1BX pin of vertical driver IC. A vertical transfer pulse for the CCD. Connect to V2X pin of vertical driver IC. Supply of +3.3 V power. A grounding pin. A vertical transfer pulse for the CCD. Connect to V3X pin of vertical driver IC. A pulse that transfers the charge of the photo-diode to the vertical shift register. Connect to VH3AX pin of vertical driver IC. A pulse that transfers the charge of the photo-diode to the vertical shift register. Connect to VH3BX pin of vertical driver IC. A vertical transfer pulse for the CCD. Connect to V4X pin of vertical driver IC. A pulse that sweeps the charge of the photo-diode for the electronic shutter. Connect to OFD pin of the CCD through the vertical driver IC and DC offset circuit. Held at H level in normal mode. A pulse for pre-blanking. This pulse is controlled by serial data BLKCNT. Pre-blanking pulse output BLKCNT = H; This pulse stays low during the absence of effective pixels within the vertical blanking or during the sweepout signal. BLKCNT = L; Continuous pulse The output phase of PBLK is selected by serial data.
3
VH1AX
O3
4
VH1BX
O3
5 6 7 8
V2X VDD3 GND V3X
O3 - - O3
9
VH3AX
O3
10
VH3BX
O3
11
V4X
O3
12
OFDX
O3
OFD pulse output
13
PBLK
O3
3
LR38617
PIN NO. SYMBOL IO SYMBOL POLARITY PIN NAME DESCRIPTION A pulse to clamp the optical black signal. This pulse is controlled by serial data BCPCNT. Optical black clamp pulse output BCPCNT = H; This pulse stays high during the absence of effective pixels within the vertical blanking or during the sweepout signal. BCPCNT = L; This pulse stays high during sweepout signal. 15 16 17 18 CLPX ADCK GND FCDS O3 O6MA3 - O6MA3 - Clamp pulse output AD clock output Ground CDS pulse output 1 A pulse to clamp the dummy outputs of the CCD signal. This pulse stays high during the sweepout period. An output pin for AD converter. The output phase of ADCK is selected by serial data in 90 steps. A grounding pin. A pulse to clamp the feed-through level for the CCD. The output phase and output polarity of FCDS are selected by serial data. A pulse to sample-hold the signal for the CCD. The output phase and output polarity of FS are selected by serial data. 20 21 VDD3 ACLX - ICU3 - - Power supply All clear input Supply of +3.3 V power. An input pin for resetting all internal circuits at power-on. Connect to VDD3 through the diode and GND through the capacitor. A pulse to sample-hold the signal for the CDS circuit. 22 23 24 25 26 27 RS GND TIN CKI CKO CLK O6MA3 - IC3 OSCI3 OSCO3 O6MA3 - - - - S/H pulse output Ground Test input Clock input Clock output Clock output The output phase and output polarity of RS are selected by serial data. A grounding pin. A test pin. Set to L level in normal mode. An input pin for reference clock oscillation. The frequency is 36.00 MHz. An output pin for reference clock oscillation. The output is the inverse of CKI (pin 25). An output pin to generate HD and VD pulses. The frequency is 18.00 MHz. An output pin for DSP IC. The frequency is 18.00 MHz. 28 DCLK O6MA3 Clock output Vertical reference - - pulse input Power supply Ground The output phase of DCLK is selected by serial data in 90 steps. An input pin for reference of vertical pulse. Connect to VD pin of DSP IC. Supply of +3.3 V power. A grounding pin.
14
BCPX
O3
19
FS
O6MA3
CDS pulse output 2
29 30 31
VD VDD3 GND
IC3 - -
4
LR38617
PIN NO. SYMBOL IO SYMBOL POLARITY 32 33 HD ED0 IC3 ICSU3 - PIN NAME Horizontal drive pulse input Strobe pulse input Shift register clock input Shift register data input Line index pulse - - - - output Test pin 1 No connection No connection Power supply Horizontal transfer pulse output 1 - Ground Horizontal transfer pulse output 2 - - Power supply No connection Reset pulse output DESCRIPTION An input pin for reference of horizontal pulse. Connect to HD pin of DSP IC. An input pin for the strobe pulse, to control the functions of LR38617. For details, see "Serial Data Control". An input pin for the clock of the shift register, to control the functions of LR38617. For details, see "Serial Data Control". An input pin for the data of the shift register, to control the functions of LR38617. For details, see "Serial Data Control". The pulse is used in the color separator. The signal switches between high and low at every line. A test pin. Set open or to L level in normal mode. No connection. No connection. Supply of +4.5 V power. A horizontal transfer pulse for the CCD. Connect to OH1 pin of the CCD. A grounding pin. A horizontal transfer pulse for the CCD. Connect to OH2 pin of the CCD. Supply of +4.5 V power. No connection. A pulse to reset the charge of output circuit. The output phase of FR is selected by serial data. An input pin to select CCD. L level H level or open
O3 O6MA3 O6MA43 OSCI3 OSCO3 : : : : :
34
ED1
ICSU3
-
35
ED2
ICSU3
-
36 37 38 39 40 41 42 43 44 45 46
ID TST1 NC NC VDD4 FH1 GND FH2 VDD4 NC FR
O3 ICD4 - - - O6MA43 - O6MA43 - - O6MA43
47 48
IC3 ICU3 ICSU3 ICU4 ICD4
CCD SHTR
ICU4 O3
-
CCD selection input Trigger output
: Aspect ratio 4 : 3 CCD : Aspect ratio 3 : 2 CCD
A trigger pulse for effective signal period.
Output pin (output high level is VDD3.) Output pin (output high level is VDD3.) Output pin (output high level is VDD4.) Input pin for oscillation Output pin for oscillation
: Input pin (CMOS : Input pin (CMOS : Input pin (CMOS resistor) : Input pin (CMOS : Input pin (CMOS
level) level with pull-up resistor) schmitt-trigger level with pull-up level with pull-up resistor) level with pull-down resistor)
5
LR38617
Serial Data Control
SERIAL DATA INPUT TIMING
ED0 ED1
ED2
D00 D01 D02 D03 D04 D05 D06 D07 D08 D09 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24
ED2 is shifted by the rising edge of ED1, and is latched by the pulse #1 which is generated after 167 to 222 ns delay from the rising edge of ED0. (See Fig. 2.) The latched serial data are divided into two types by the data of D00, and are relatched by the pulse #2 which is generated after 277 to 332 ns delay from the rising edge of ED0. (See Fig. 1.)
INMD is effective at the start of #3 horizontal line, and shutter control data are effective at the start of #6 or #234 horizontal line at CCD = L, or #12 HD horizontal line at CCD = H, and other data are effective at pulse #2. ED0 should be at low level during data inputs of ED1 and ED2, or while ACLX is at low level.
333 ns min. ED0 18 MHz Pulse #1 Pulse #2 166 ns 277 ns
Fig. 1 Data Latch Timing
Mode VD VH1AX VH3AX ED0 ED1 ED2 OFDC
Monitoring Odd Field
Still Even Field
Monitoring
from monitoring mode to still mode data input period 10 ms min.
from still mode to monitoring mode data input period
VD HD ED0
5 s min. 5 s min.
Fig. 2 Input Pulse Timing of ED0, ED1 and ED2
6
LR38617
SERIAL DATA INPUTS D00 = L
DATA D01-D09 D10-D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 NAME SDV0-SDV8 SDH0-SDH5 SDF0 SDF1 SDF2 SMD PWSA INMD Dummy BCPCNT VHCNT FUNCTION Integration time control in field period step by horizontal period. Integration time control in horizontal period step by 112 CLK clock period. Integration time control by field period. Electronic shutter mode control Power save control Integration mode control Dummy BCPX control VH1AX to VH3BX control Normal Monitoring Fix to Discontinuous Output DATA = L - - DATA = H AT ACLX = L All L All L
- - Power save Still L level Continuous Held at H level
All L L L L L L L
D00 = H
DATA D01 D02 D03 D04 D05 D06 D07 D08 D09 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 NAME ML1 ML2 MR1 MR2 MR3 MC1 MC2 MC3 MS1 MS2 MS3 MF1 MF2 MF3 MA1 MA2 MD1 MD2 MD3 MP1 MP2 PLCH BLKCNT Dummy FUNCTION DATA = L - - DATA = H AT ACLX = L All L All L
-
All L
- Phase control - - - - Polarity control of FCDS, FS and RS pulses PBLK control Dummy Negative Positive
All L
All L All L All L All L L L L
Continuous Discontinuous Fix to L level
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LR38617
ABSOLUTE MAXIMUM RATINGS
PARAMETER Supply voltage Input voltage Output voltage Operating temperature Storage temperature SYMBOL VDD3, VDD4 VI3 VI4 VO3 VO4 TOPR TSTG RATING -0.3 to +6.0 -0.3 to VDD3 + 0.3 -0.3 to VDD4 + 0.3 -0.3 to VDD3 + 0.3 -0.3 to VDD4 + 0.3 -20 to +70 -55 to +150 UNIT V V V V V C C
ELECTRICAL CHARACTERISTICS DC Characteristics
PARAMETER Input "Low" voltage Input "High" voltage Input "Low" voltage Input "High" voltage Hysteresis voltage Input "Low" voltage Input "High" voltage Input "Low" current Input "High" current Input "Low" current Input "High" current Input "Low" current Input "High" current Input "Low" current Input "High" current Output "Low" voltage Output "High" voltage Output "Low" voltage Output "High" voltage Output "Low" voltage Output "High" voltage
(VDD3 = 3.0 V to VDD4, VDD4 = 4.2 to 5.5 V, TOPR = -20 to +70C)
SYMBOL VIL3-1 VIH3-1 VIL3-2 VIH3-2 VT+ - VT- VIL4 VIH4 |IIL3-1| |IIH3-1| |IIL3-2| |IIH3-2| |IIL4-1| |IIH4-1| |IIL4-2| |IIH4-2| VOL3-1 VOH3-1 VOL3-2 VOH3-2 VOL4 VOH4 0.8VDD4 VI = 0 V VI = VDD3 VI = 0 V VI = VDD3 VI = 0 V VI = VDD4 VI = 0 V VI = VDD4 IOL = 2 mA IOH = -1 mA IOL = 3 mA IOH = -3 mA IOL = 10 mA IOH = -10 mA VDD3 - 0.5 0.4 VDD4 - 0.5 4.0 4.0 2.0 1.0 1.0 60 2.0 2.0 60 60 2.0 0.4 VDD3 - 0.5 0.4 Schmitt-buffer 0.08VDD3 0.2VDD4 CONDITIONS MIN. 0.8VDD3 0.2VDD3 0.75VDD3 TYP. MAX. UNIT 0.2VDD3 V V V V V V V A A A A A A A A V V V V V V NOTE 1, 2
3
4 1 2, 3 4 5 6 7 8
NOTES :
1. 2. 3. 4. 5. Applied Applied Applied Applied Applied to to to to to inputs (IC3, OSCI3). input (ICU3). input (ICSU3). input (ICD4). input (ICU4). 6. Applied to output (O3). 7. Applied to outputs (OSCO3, O6MA3). (Output (OSCO3) measures on condition that input (OSCI3) level is 0 V or VDD3.) 8. Applied to output (O6MA43).
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LR38617
PACKAGE OUTLINES 48 QFP (P-QFP048-0707)
(Unit : mm)
P-0.5TYP. 36 M 37 0.08
48-0.20.08 (1.0) 25 24 7.00.2 9.00.3
0.150.05 See Detail A
(1.0)
48 1 (1.0)
13 12 (1.0)
0.10
Detail A 0.650.2 1.450.2 Package base plane 0.10.1 1.00.15 0.650.2 1.450.2
7.00.2 9.00.3
0-10 0.5 0.60.15 0.10.1 0.25
Seating plane
9

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