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CAT661
High Frequency 100mA CMOS Charge Pump, Inverter/Doubler
FEATURES
s Converts V+ to V- or V+ to 2V+ s Low output resistance, 10 max. s High power efficiency s Selectable charge pump frequency of 25kHz
H
GEN FR ALO
EE
LE
A D F R E ETM
s Pin-compatible to MAX660, LTC660 with higher
frequency operation
s Available in 8-pin SOIC andDIP packages s Lead-free, halogen-free package option
or 135kHz; optimize capacitor size.
s Low quiescent current
APPLICATIONS
s Negative voltage generator s Voltage doubler s Voltage splitter s Low EMI power source s GaAs FET biasing s Lithium battery power supply s Instrumentation s LCD contrast bias s Cellular phones, pagers
DESCRIPTION
The CAT661 is a charge-pump voltage converter. It can invert a positive input voltage to a negative output. Only two external capacitors are needed. With a guaranteed 100mA output current capability, the CAT661 can replace a switching regulator and its inductor. Lower EMI is achieved due to the absence of an inductor. In addition, the CAT661 can double a voltage supplied from a battery or power supply. Inputs from 2.5V to 5.5V will yield a doubled, 5V to 11V output. A Frequency Control pin (BOOST/FC) is provided to select either a high (typically 135kHz) or low (25kHz) internal oscillator frequency, thus allowing quiescent current vs. capacitor size trade-offs to be made. The 135kHz frequency is selected when the FC pin is connected to V+. The operating frequency can also be adjusted with an external capacitor at the OSC pin or by driving OSC with an external clock. Both 8-pin DIP and SO packages are available. For die availability, contact Catalyst Semiconductor marketing. The CAT661 can replace the MAX660 and the LTC660 in applications where higher oscillator frequency and smaller capacitors are needed. In addition, the CAT661 is pin compatible with the 7660/1044, offering an easy upgrade for applications with 100mA loads.
TYPICAL APPLICATION
+VIN 1.5V to 5.5V
1
C1 +
BOOST/FC CAP+ GND CAP-
V+ OSC
8 7 6 5
Inverted Negative Voltage Output
C1 +
1 2 3 4
BOOST/FC CAP+ GND CAP-
V+ OSC LV OUT
8 7 6 5
Doubled Positive Voltage Output
2 3 4
CAT661
CAT661
LV OUT
VIN = 2.5V to 5.5V
VOLTAGE INVERTER
POSITIVE VOLTAGE DOUBLER
(c) Catalyst Semiconductor, Inc. Characteristics subject to change without notice
1
Doc. No. MD-5003, Rev. K
CAT661
PIN CONFIGURATION
SOIC 8-Lead (V) PDIP 8-Lead (L)
BOOST/FC 1 CAP+ 2 GND 3 CAP- 4 CAT661 8 V+ 7 OSC 6 LV 5 OUT
(Top View)
PIN DESCRIPTIONS
Circuit Configuration Pin Number Name 1 Boost/FC Inverter Freqency Control for the internal oscillator. With an external oscillator BOOST/FC has no effect. Boost/FC Oscillator Frequency Open V+ 2 3 4 5 6 CAP+ GND CAPOUT LV 25kHz typical, 10kHz minimum Doubler Same as inverter. Oscillator Frequency 40kHz typical
135kHz typical, 80kHz minimum 135kHz typical, 40kHz minimum Same as inverter. Power supply. Positive voltage input. Same as inverter. Power supply ground. LV must be tied to OUT for all input voltages.
Charge Pump Capacitor. Positive terminal. Power Supply Ground. Charge pump capacitor. Negative terminal. Output for negative voltage. Low-Voltage selection pin. When the input voltage is less than 3V, connect LV to GND. For input voltages above 3V, LV may be connected to GND or left open. If OSC is driven externally, connect LV to GND. Oscillator control input. An external capacitor can be connected to lower the oscillator frequency. An external oscillator can drive OSC and set the chip operating frequency. The charge-pump frequency is one-half the frequency at OSC. Power supply. Positive voltage input.
7
OSC
Same as inverter. Do not overdrive OSC in doubling mode. Standard logic levels will not be suitable. See the applications section for additional information. Positive voltage output.
8
V+
ORDERING INFORMATION
Part Number CAT661ELA CAT661EVA CAT661EVA-T3 Package PDIP, 8-lead SOIC SOIC Quanity 50/tube 100/tube 3,000/reel Package Marking 661ELA 661EVA 661EVA
Note: All packages are RoHS compliant.
Doc. No. MD-5003, Rev. K
2
CAT661
ABSOLUTE MAXIMUM RATINGS
V+ to GND ............................................................. 6V Storage Temperature ......................... -65C to 160C Input Voltage (Pins 1, 6 and 7) .. -0.3V to (V+ + 0.3V) BOOST/FC and OSC Input Voltage ........... The least negative of (Out - 0.3V) or (V+ - 6V) to (V+ + 0.3V) Output Short-circuit Duration to GND .............. 1 sec.
(OUT may be shorted to GND for 1 sec without damage but shorting OUT to V+ should be avoided.)
Lead Soldering Temperature (10 sec) ............. 300C ESD Rating-Human Body Model ..................... 2000V
Note: TA = Ambient Temperature
These are stress ratings only and functional operation is not implied. Exposure to absolute maximum ratings for prolongued time periods may affect device reliability. All voltages are with respect to ground.
Continuous Power Dissipation (TA = 70C) Plastic DIP ................................................ 730mW SO ............................................................ 500mW TDFN ............................................................... 1W
Operating Ambient Temperature Ranges CAT661E .............. -40C to 85C
ELECTRICAL CHARACTERISTICS
V+ = 5V, C1 = C2 = 100F, Boost/FC = Open, COSC = 0pF, and Test Circuit is Figure 1 unless otherwise noted. Temperature is TA = TAMIN to TAMAX unless otherwise noted. Parameter Supply Voltage Supply Current Output Current Output Resistance Symbol VS IS IOUT RO Conditions Inverter: LV = Open. RL = 1k Inverter: LV = GND. RL = 1k Doubler: LV = OUT. RL = 1k BOOST/FC = open, LV = Open BOOST/FC = V+ , LV = Open OUT is more negative than -4V C1 = C2 = 10F, BOOST/FC = V+ (C1, C2 ESR 0.5) C1 = C2 = 100F (Note 2) Oscillator Frequency FOSC (Note 3) OSC Input Current Power Efficiency IOSC PE BOOST/FC = Open BOOST/FC = V+ BOOST/FC = Open BOOST/FC = V+ RL = 1k connected between V+ and OUT, TA = 25C (Doubler) RL = 500 connected between GND and OUT, TA = 25C (Inverter) IL = 100mA to GND, TA = 25C (Inverter) Voltage Conversion Efficiency
1. In Figure 1, test circuit electrolytic capacitors C1 and C2 are 100F and have 0.2 maximum ESR. Higher ESR levels may reduce efficiency and output voltage. 2. The output resistance is a combination of the internal switch resistance and the external capacitor ESR. For maximum voltage and efficiency keep external capacitor ESR under 0.2. 3. FOSC is tested with COSC = 100pF to minimize test fixture loading. The test is correlated back to COSC=0pF to simulate the capacitance at OSC when the device is inserted into a test socket without an external COSC.
Min. 3.0 1.5 2.5
Typ
Max. 5.5 5.5 5.5
Units V
0.2 1 100 3.5 3.5 10 80 25 135 2 10 96 92 98 96 88 99 99.9
0.5 3
mA mA
10 10
kHz A %
VEFF
No load, TA = 25C
%
3
Doc. No. MD-5003, Rev. K
CAT661
Figure 1. Test Circuit Voltage Inverter
IS
V+
1 2
+ C1 100F
BOOST/FC CAP+ GND CAP-
V+ OSC LV OUT
8 7 6 5
V+ 5V External Oscillator COSC RL IL VOUT C2 + 100F
3 4
CAT661
TYPICAL OPERATING CHARACTERISTICS
Typical characteristic curves are generated using the circuit in Figure 1. Inverter test conditions are: V+ 5V, LV = GND, BOOST/FC = Open and TA = 25C unless otherwise indicated. Note that the charge-pump frequency is one-half the oscillator frequency.
Supply Current vs. Input Voltage
1400 1200
Supply Current vs. Temperature (No Load)
250
INPUT CURRENT [A]
INPUT CURRENT [A]
1000 800 600 400 200 0 1 2 3 4 5 INPUT VOLTAGE [V] 6 FC = open FC = V+
200 150 100 50
VIN = 5V
VIN = 3V
VIN = 2V
0 -50 -25 0 25 50 75 100 125
TEMPERATURE [oC]
Output Resistance vs. Input Voltage
10
Output Resistance vs. Temperature (50 load)
8
OUTPUT RESISTANCE []
OUTPUT RESISTANCE []
8 6 4 2 0 1 2 3 4 5 6 INPUT VOLTAGE [V]
7 6 5 VIN = 2V 4 3 VIN = 5V 2 -50 -25 0 25 50 75 100 125 TEMPERATURE [oC] VIN = 3V
Doc. No. MD-5003, Rev. K
4
CAT661
TYPICAL OPERATING CHARACTERISTICS Inverted Output voltage vs. Load, V+ = 5V
5.0
Output Voltage Drop vs. Load Current
1.0
OUTPUT VOLTAGE [V]
INV. OUTPUT VOLTAGE [V]
4.8 4.6 4.4 4.2 4.0 0 20 40 60 80 LOAD CURRENT [mA] 100
0.8 0.6 0.4 0.2 0.0 0 20 40 60 80 100 LOAD CURRENT [mA] V+ = 3V V+ = 5V
Oscillator Frequency vs. Supply Voltage
50
Oscillator Frequency vs. Supply Voltage
200
FREQUENCY [kHz]
FREQUENCY [kHz]
40 30 20 10 0 1 2 3 4 5 SUPPLY VOLTAGE [V] 6 FC = Open
160 120 80 40 0 1 2 3 4 5 SUPPLY VOLTAGE [V] 6 FC = V+
Supply Current vs. Oscillator Frequency
10000
100
Efficiency vs. Load Current
INPUT CURRENT [A]
1000
EFFICIENCY [%]
No No Load Ld
90 V+ =5V 80 70 60 50 40 0 50 LOAD CURRENT [mA] 100 V+ = 3V
100
10 1 10 100 1000 OSCILLATOR FREQUENCY [KHz]
5
Doc. No. MD-5003, Rev. K
CAT661
Figure 2. Test Circuit Voltage Doubler
V+ C1 + 100F V+ 5V
1 2 3 4
BOOST/FC CAP+ GND CAP-
V+ OSC LV OUT
8 7 6 5
10V VOUT External Oscillator
CAT661
C2 100F
TYPICAL OPERATING CHARACTERISTICS
Typical characteristic curves are generated using the circuit in Figure 2. Doubler test conditions are: V+ 5V, LV = GND, BOOST/FC = Open and TA = 25C unless otherwise indicated.
Supply Current vs. Input Voltage (No Load)
3000 2500 2000 1500 1000 500 0 0 1 2 3 4 5 6 INPUT VOLTAGE [V]
Output Resistance vs. Input Voltage
10
OUTPUT RESISTANCE []
INPUT CURRENT [A]
8 6 4 2 0 1 2 3 4 5 6 INPUT VOLTAGE [V]
FC = V+
FC = open
Supply Current vs. Oscillator Frequency
10000
Output Voltage Drop vs. Load Current
1.0
OUTPUT VOLTAGE [V]
INPUT CURRENT [A]
No Load 1000
0.8 0.6 0.4 0.2 0.0 V+ = 3V V+ = 5V
100
10 1 10 100 1000 OSCILLATOR FREQUENCY [KHz]
0
20
40
60
80
100
LOAD CURRENT [mA]
Doc. No. MD-5003, Rev. K
6
CAT661
APPLICATION INFORMATION
Circuit Description and Operating Theory The CAT661 switches capacitors to invert or double an input voltage. Figure 3 shows a simple switch capacitor circuit. In position 1 capacitor C1 is charged to voltage V1. The total charge on C1 is Q1 = C1V1. When the switch moves to position 2, the input capacitor C1 is discharged to voltage V2. After discharge, the charge on C1 is Q2 = C1V2. The charge transferred is: Q = Q1 - Q2 = C1 x (V1 - V2) If the switch is cycled "F" times per second, the current (charge transfer per unit time) is: I = F x Q = F x C1 (V1 - V2) Rearranging in terms of impedance: I= (V1-V2) (1/FC1) = V1-V2 REQ The 1/FC1 term can be modeled as an equivalent impedance REQ. A simple equivalent circuit is shown in figure 4. This circuit does not include the switch resistance nor does it include output voltage ripple. It does allow one to understand the switch-capacitor topology and make prudent engineering tradeoffs. For example, power conversion efficiency is set by the output impedance, which consists of REQ and switch resistance. As switching frequency is decreased, REQ, the 1/FC1 term, will dominate the output impedance, causing higher voltage losses and decreased efficiency. As the frequency is increased quiescent current increases. At high frequency this current becomes significant and the power efficiency degrades. The oscillator is designed to operate where voltage losses are a minimum. With external 150F capacitors, the internal switch resistances and the Equivalent Series Resistance (ESR) of the external capacitors determine the effective output impedance. A block diagram of the CAT661 is shown in figure 5.
Figure 3. Switched-Capacitor Building Block
Figure 4. Switched-Capacitor Equivalent Circuit
REQ V1 V2
V1
V2
C1
C2
RL
REQ = 1 FC1
C2
RL
7
Doc. No. MD-5003, Rev. K
CAT661
OSCILLATOR FREQUENCY CONTROL The switching frequency can be raised, lowered or driven from an external source. Figure 6 shows a functional diagram of the oscillator circuit. The CAT661 oscillator has four control modes: BOOST/FC Pin Connection Open BOOST/FC= V+ Open or BOOST/FC= V+ Open OSC Pin Connection Open Open External Capacitor External Clock Nominal Oscillator Frequency 25kHz 135kHz -- Frequency of external clock
If BOOST/FC and OSC are left floating (Open), the nominal oscillator frequency is 25kHz. The pump frequency is one-half the oscillator frequency. By connecting the BOOST/FC pin to V+, the charge and discharge currents are increased, and the frequency is increased by approximately 6 times. Increasing the frequency will decrease the output impedance and ripple currents. This can be an advantage at high load currents. Increasing the frequency raises quiescent current but allows smaller capacitance values for C1 and C2. If pin 7, OSC, is loaded with an external capacitor the frequency is lowered. By using the BOOST/FC pin and Figure 5. CAT661 Block Diagram
an external capacitor at OSC, the operating frequency can be set. Note that the frequency appearing at CAP+ or CAP- is one-half that of the oscillator. Driving the CAT661 from an external frequency source can be easily achieved by driving Pin 7 and leaving the BOOST pin open, as shown in figure 6. The output current from Pin 7 is small, typically 1A to 8A, so a CMOS can drive the OSC pin. For 5V applications, a TTL logic gate can be used if an external 100k pull-up resistor is used as shown in figure 7.
V+ (8) SW1 BOOST/FC 8x (1) OSC OSC (7) 2 CAP(4) VOUT (5) C2 CAP+ (2) SW2
+
C1
+
LV (6) CLOSED WHEN V+ > 3.0V GND (3) (N) = Pin Number
Doc. No. MD-5003, Rev. K
8
CAT661
CAPACITOR SELECTION Low ESR capacitors are necessary to minimize voltage losses, especially at high load currents. The exact values of C1 and C2 are not critical but low ESR capacitors are necessary. The ESR of capacitor C1, the pump capacitor, can have a pronounced effect on the output. C1 currents are approximately twice the output current and losses occur on both the charge and discharge cycle. The ESR effects are thus multiplied by four. A 0.5 ESR for C1 will have the same effect as a 2 increase in CAT661 output impedance. Output voltage ripple is determined by the value of C2 and the load current. C2 is charged and discharged at a current roughly equal to the load current. The internal switching frequency is one-half the oscillator frequency. VRIPPLE = IOUT/(FOSC x C2) + IOUT x ESRC2 For example, with a 25kHz oscillator frequency (12.5kHz switching frequency), a 150F C2 capacitor with an ESR of 0.2 and a 100mA load peak-to-peak the ripple voltage is 45mV.
VRIPPLE vs. FOSC VRIPPLE (mV) 45 25 IOUT (mA) 100 100 FOSC (kHz) 25 135 C2 (F) 150 150 C2 ESR () 0.2 0.2
Figure 6. Oscillator
V+
Figure 7. External Clocking
V+
7.0 I BOOST/FC (1)
I
REQUIRED FOR TTL LOGIC
NC + C1
OSC (7)
1 2 3 4
BOOST/FC CAP+ GND CAP-
V+ OSC LV OUT
8 7 6 5
100k OSC INPUT -V+ + C2
CAT661
~18pF 7.0 I LV (6) I
9
Doc. No. MD-5003, Rev. K
CAT661
CAPACITOR SUPPLIERS The following manufacturers supply low-ESR capacitors:
Manufacturer AVX/Kyocera
Capacitor Type TPS/TPS3
Phone 843-448-9411 402-563-6866 619-661-6835 847-843-7500
WEB www.avxcorp.com www.vishay.com www.sanyo.com www.nichicon-us.com
Email avx@avxcorp.com --
Comments Tantalum Aluminum
Vishay/Sprague 595 Sanyo Nichicon MV-AX, UGX F55 HC/HD
Svcsales@sanyo.com Aluminum -- Tantalum Aluminum
Capacitor manufacturers continually introduce new series and offer different package styles. It is recommended
that before a design is finalized capacitor manufacturers should be surveyed for their latest product offerings.
CONTROLLING LOSS IN CAT661 APPLICATIONS There are three primary sources of voltage loss: 1. Output resistance VLOSS = ILOAD x ROUT, where ROUT is the CAT661 output resistance and ILOAD is the load current. 2. Charge pump (C1) capacitor ESR: VLOSSC1 4 x ESRC1 x ILOAD, where ESRC1 is the ESR of capacitor C1. 3. Output or reservoir (C2) capacitor ESR: VLOSSC2 = ESRC2 x ILOAD, where ESRC2 is the ESR of capacitor C2. Increasing the value of C2 and/or decreasing its ESR will reduce noise and ripple. The effective output impedance of a CAT661 circuit is approximately: Rcircuit Rout 661 + (4 x ESRC1) + ESRC2 VOLTAGE INVERSION POSITIVE-TO-NEGATIVE The CAT661 easily provides a negative supply voltage from a positive supply in the system. Figure 8 shows a typical circuit. The LV pin may be left floating for positive input voltages at or above 3.3V.
TYPICAL APPLICATIONS
NC + C1
1 2 3 4
BOOST/FC CAP+
V+ OSC
8 7 6 5 C2
VIN 1.5V to 5.5V
CAT661
GND CAPLV OUT
VOUT = -VIN
+
Figure 8: Voltage Inverter
Doc. No. MD-5003, Rev. K
10
CAT661
POSITIVE VOLTAGE DOUBLER The voltage doubler circuit shown in figure 9 gives VOUT = 2 x VIN for input voltages from 2.5V to 5.5V.
1N5817*
1 + VIN 2.5V to 5.5V 2 3 4
BOOST/FC CAP+
V+ OSC
8 7 6 5 +
VOUT = 2VIN
CAT661
GND CAPLV OUT
*SCHOTTKY DIODE IS FOR START-UP ONLY
Figure 9: Voltage Doubler
PRECISION VOLTAGE DIVIDER A precision voltage divider is shown in figure 10. With load currents under 100nA, the voltage at pin 2 will be within 0.002% of V+/2 .
1 2 + V+ + 0.002% 2 IL < 100nA 3 4 +
BOOST/FC CAP+
V+ OSC
8 7 6 5
V+ 3V to 11V
CAT661
GND CAPLV OUT
Figure 10: Precision Voltage Divider (Load 100nA)
11
Doc. No. MD-5003, Rev. K
CAT661
BATTERY VOLTAGE SPLITTER Positive and negative voltages that track each other can be obtained from a battery. Figure 11 shows how a 9V battery can provide symmetrical positive and negative voltages equal to one-half the battery voltage.
BATTERY 9V 3V < VBAT < 11V
VBAT +
1 2 3 4
BOOST/FC CAP+
V+ OSC
8 7 6 5
V + BAT (4.5V) 2
CAT661
GND CAPLV OUT
-
VBAT (-4.5V) 2
+
Figure 11: Battery Splitter
CASCADE OPERATION FOR HIGHER NEGATIVE VOLTAGES The CAT661 can be cascaded as shown in figure 12 to generate more negative voltage levels. The output resistance is approximately the sum of the individual CAT661 output resistance. VOUT= -N x VIN, where N represents the number of cascaded devices.
+VIN 8 2 C1 + 3 4 CAT661 "1" 5 C1N + 2 3 4 VOUT = -NVIN CAT661 "N" 5 + C2 8
+
C2
Figure 12: Cascading to Increase Output Voltage
Doc. No. MD-5003, Rev. K
12
CAT661
PARALLEL OPERATION Paralleling CAT661 devices will lower output resistance. As shown in figure 13, each device requires its own pump capacitor, C2, but the output reservoir capacitor is shared with all devices. The value of C2 should be increased by a factor of N, where N is the number of devices.
ROUT (of CAT661) N (NUMBER OF DEVICES) +VIN 8 2 C1 + 3 4 CAT661 "1" 5 C1N + 2 3 4 CAT661 "N" 5 8
ROUT =
+
C2
Figure 13: Reduce Output Resistance by Paralleling Devices
13
Doc. No. MD-5003, Rev. K
CAT661
PACKAGE OUTLINE DRAWINGS SOIC 8-Lead 150mils (V)
SYMBOL
MIN
NOM
MAX
A A1 b c
E1 E
1.35 0.10 0.33 0.19 4.80 5.80 3.80 1.27 BSC 0.25 0.40 0
1.75 0.25 0.51 0.25 5.00 6.20 4.00 0.50 1.27 8
D E E1 e h L
PIN # 1 IDENTIFICATION TOP VIEW
D
h
A1
A
c e b L
SIDE VIEW
END VIEW
For current Tape and Reel information, download the PDF file from: http://www.catsemi.com/documents/tapeandreel.pdf.
Notes: 1. Al dimensions are in millimeters. Angles in degrees. 2. Complies with JEDEC standard MS-012.
Doc. No. MD-5003, Rev. K
14
CAT661
PDIP 8-Lead 300mils (L)
SYMBOL
MIN
NOM
MAX
A A1 A2 b
E1
5.33 0.38 2.92 0.36 1.14 0.20 9.02 7.62 6.10 7.87 2.92 3.30 3.30 0.46 1.52 0.25 9.27 7.87 2.54 BSC 6.35 7.11 10.92 3.80 4.95 0.56 1.78 0.36 10.16 8.25
b2 c D E e E1 eB
PIN # 1 IDENTIFICATION D
L
TOP VIEW
E
A
A2
A1 b2 L c
e
b
eB
SIDE VIEW
END VIEW
For current Tape and Reel information, download the PDF file from: http://www.catsemi.com/documents/tapeandreel.pdf.
Notes: 1. Al dimensions are in millimeters. Angles in degrees. 2. Complies with JEDEC standard MS-001.
15
Doc. No. MD-5003, Rev. K
CAT661
EXAMPLE OF ORDERING INFORMATION
Prefix CAT Device # 661 EVA Suffix T3
Optional Company ID
Product Number 661
Package ELA: PDIP EVA: SOIC
Tape & Reel T: Tape & Reel 3: 3000/Reel
Notes: (1) All packages are RoHS-compliant (Lead-free, Halogen-free). (2) The standard lead finish is Matte-Tin. (3) The device used in the above example is a CAT661W-T3 (SOIC, Tape & Reel).
Doc. No. MD-5003, Rev. K
16
REVISION HISTORY
Date 10/15/03 10/27/04 1/20/2005 04/22/2005 11/16/2007 Rev. G H I J K Reason Updated Description - eliminated Commercial temperature range Minor changes throughout data sheet Changed ordering information for CAT661EXA to CAT661EVA Changed ordering information for CAT661EXA-TE13 to CAT661EVA-TE13 Removed Preliminary Information from data sheet header Update Features and Description Update Package Outline Drawings and remove TDFN Add Example of Ordering Information Add Ordering Part Number Add "MD-" to document number
Copyrights, Trademarks and Patents
(c) Catalyst Semiconductor, Inc. Trademarks and registered trademarks of Catalyst Semiconductor include each of the following: Adaptive AnalogTM, Beyond MemoryTM, DPPTM, EZDimTM, LDDTM, MiniPotTM, Quad-ModeTM and Quantum Charge ProgrammableTM Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products.
CATALYST SEMICONDUCTOR MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY ARISING OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES.
Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a situation where personal injury or death may occur. Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale. Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate typical semiconductor applications and may not be complete.
Catalyst Semiconductor, Inc. Corporate Headquarters 2975 Stender Way Santa Clara, CA 95054 Phone: 408.542.1000 Fax: 408.542.1200 www.catsemi.com
Publication #: Revison: Issue date:
MD-5003 K 11/16/07

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