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CY2SSTV16857
14-Bit Registered Buffer PC2700-/PC3200-Compliant
Features
* Differential Clock Inputs up to 280 MHz * Supports LVTTL switching levels on the RESET pin * Output drivers have controlled edge rates, so no external resistors are required * Two KV ESD protection * Latch-up performance exceeds 100 mA: JESD78, Class II * Conforms to JEDEC STD (JESD82-3) for buffered DDR DIMMs * 48-pin TSSOP When RESET is LOW, the differential input receivers are disabled, and undriven (floating) data, clock, and REF voltage inputs are allowed. In addition, when RESET is LOW, all registers are reset and all outputs force to the LOW state. The LVCMOS RESET input must always be held at a valid logic HIGH or LOW level. To ensure defined outputs from the register before a stable clock has been supplied, RESET must be held in the LOW state during power-up. In the DDR registered DIMM application, RESET is specified to be completely asynchronous with respect to CLK and CLK. Therefore, no timing relationship can be guaranteed between the two. When entering reset, the register will be cleared and the outputs will be driven LOW quickly, relative to the time to disable the differential input receivers, thus ensuring no glitches on the output. However, when coming out of reset, the register will become active quickly, relative to the time to enable the differential input receivers. As long as the data inputs are low, and the clock is stable during the time from the LOW-to-HIGH transition of RESET until the input receivers are fully enabled, the design must ensure that the outputs will remain LOW.
Description
This 14-bit registered buffer is designed specifically for 2.3V to 2.7V VDD operation and is characterized for operation from 0C to + 85C. All inputs are compatible with the JEDEC Standard for SSTL_2, except the LVCMOS reset (RESET) input. All outputs are SSTL_2, Class II-compatible. The SSTV16857 operates from a differential clock (CLK and CLK). Data is measured at the crossing of CLK going HIGH, and CLK going LOW.
Block Diagram
Pin Configuration
Q1 Q2 VSS VDDQ Q3 Q4 Q5 VSS VDDQ Q6 Q7 VDDQ VSS Q8 Q9 VDDQ VSS Q10 Q11 Q12 VDDQ VSS Q13 Q14 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 D1 D2 VSS VDD D3 D4 D5 D6 D7 CLK CLK VDD VSS VREF RESET D8 D9 D10 D11 D12 VDD VSS D13 D14
RESET CLK CLK VREF D1 1D C1 R Q1
To 13 Other Channels
Cypress Semiconductor Corporation Document #: 38-07443 Rev. *D
*
3901 North First Street
*
San Jose, CA 95134 * 408-943-2600 Revised January 12, 2005
CY2SSTV16857
CY2SSTV16857
Pin Description
Pin 34 3,8,13,17,22,27,36,46 28, 37, 45 1, 2, 5, 6, 7, 10, 11, 14, 15, 18, 19, 20, 23, 24 25, 26, 29, 30, 31, 32, 33, 40, 41, 42, 43, 44, 47, 48 39, 38 4, 8, 12, 16, 21 35 Name RESET VSS VDD Q(1:14) D(1:14) CLK, CLK VDDQ VREF I/O I Ground Power O I I/I Power I Ground. 2.5V nominal supply voltage. Data outputs, SSTL_2, Class II output. Data input clocked on the crossing of the rising edge of CLK, and the falling edge of CLK. Differential clock input. Power supply voltage quiet, 2.5V nominal. Input reference voltage, 1.25V nominal. Type Description
Document #: 38-07443 Rev. *D
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CY2SSTV16857
Absolute Maximum Conditions[1, 2, 3]
This device contains circuitry designed to protect the inputs against damage due to high static voltages or electric field; however, precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. For proper operation, Vin and Vout should be constrained to the range: Parameter VDD VDD Vin Vout IOUT IIK IOK IDD/ISS LUI RPS Ts Ta Tj OJc OJA ULFL MSL ESDh Description Supply Voltage[4] Operating Voltage[4] Input Voltage Output Voltage DC Output Current Continuous Clamp Current Continuous Clamp Current Continuous current through each VDD or VSS Latch Up Immunity Power Supply Ripple Temperature, Storage Temperature, Operating Ambient Temperature, Junction Dissipation, Junction to Case Dissipation, Junction to Ambient Flammability Moisture Sensitivity ESD Protection (Human Body Model) Exceeds spec of Ripple Frequency < 100 kHz Non-functional Functional Functional Mil-Spec 883E Method 1012.1 JEDEC (JESD 51) By design and verification By design and verification 2000 22.23 74.52 V-0 MSL - 1 -65 0 100 150 +150 +70 165 VI < 0 or VI > VSS VO < 0 VSS < (Vin or Vout) < VDD. Unused inputs must always be tied to an appropriate logic voltage level (either VSS or VDD).
Condition Non-functional Functional Relative to VSS Relative to VSS
Min. 2.3 2.3 0
Max. 2.7 2.7 VDD VDDQ 50 50 -50 100
Unit VDC VDC VDC VDC mA mA mA mA mA mVp-p C C C C/W C/W Grade Grade V
Table 1. DC Electrical Specifications (VDD = Temperature = 0C to +85 C) Parameter VDD VDDQ VREF VTT VIH VIL VOL Supply Voltage Description PC1600,2100,2700 PC3200 Condition Min. 2.5 2.5 1.25 VREF - 40 mV RESET RESET VDD/VDDQ = 2.3V to 2.7V, IOL = 100 A, VDD = 2.3 to 2.7V VDD/VDDQ = 2.3V, IOL = 16 mA, VDD = 2.3V 1.7 0.7 0.2 0.35 Typ. 2.6 2.6 1.3 Max. 2.7 2.7 1.35 Unit V V V V V V V
Output Supply Voltage PC1600,2100,2700 PC3200 Reference voltage (VREF = VDDQ/2) Termination voltage Input Voltage, High Input Voltage, Low Output Voltage, Low PC1600,2100,2700 PC3200
VREF VREF+4 0 mV
Notes: 1. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required. 2. Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended period may affect reliability. 3. All terminals except VDD. 4. VDD/VDDQ terminals.
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CY2SSTV16857
Table 1. DC Electrical Specifications (VDD = Temperature = 0C to +85 C) (continued) Parameter VOH Description Output Voltage, High Condition VDD/VDDQ = 2.3V to 2.7V, IOH = -100 A, VDD=2.3 to 2.7V VDD/VDDQ = 2.3V, IOH = -16 mA IIL Input Current Data Inputs VI = 1.7V or 0.8V, VREF = 1.15V or 1.35V, VDD = 2.7V VI = 2.7V or 0,VREF = 1.15V or 1.35V, VDD = 2.7V VI = 1.7V or 0.8V, VREF = 1.15V or 1.35V, VDD = 3.6V VI = 2.7V or 0 CLK, CLK VI = 1.7V or 0.8V, VREF = 1.15V or 1.35V VI = 2.7V or 0, VREF = 1.15V or 1.35V, Vdd = 2.7V RESET VREF IIH IDD Input Current, High Dynamic Supply Current VI = VDD or VSS, VDD = 2.7V VI = 1.5V or 1.35V, VDD = 2.7 Data inputs only VI = 1.7V or 0.8V, IO = 0, VDD = 2.7V VI = 2.7V or 0, IO = 0, VDD = 2.7V Cin Input pin capacitance RESET Clock and Data Inputs Lpin Pin Inductance All VI = 1.7V or 0.8V, IO = 0, VDD = 2.7V 2.5 2.1 3 2.7 3.5 4.5 pF pF nH 90 90 5 5 5 5 1 1 5 5 A A A A A A A A mA. mA mA Min. VDD - 0.2 1.95 Typ. Max. Unit V
Table 2. AC Input Electrical Specifications (VDD = 2.5 VDC 5%, Temperature = 0C to +85C) VDD = 2.5V 0.2V Parameter FIN PW TACT TINACT TSET Description Input Clock Frequency Pulse Duration Differential Inputs Active Time CLK, CLK CLK, CLK HIGH or LOW Data inputs must be LOW after RESET HIGH 3.3 22 22 0.75 0.9 0.75 0.9 360 Condition Min. Max. 200 Unit MHz ns ns ns ns ns ns ns mV
Differential Inputs Inactive Time Data and clock inputs must be held at valid levels (not floating) after RESET LOW Set-up Time Fast slew rate, (see notes 5 and 7), Data before CLK, CLK Slow slew rate, (see notes 6 and 7), Data before CLK, CLK
THOLD IVpp
Hold Time Input Voltage, Pk-Pk
Fast slew rate, (see notes 5 and 7), Data after CLK, CLK Slow slew rate (see notes 6 and 7), Data after CLK, CLK
Notes: 5. For data signal input slew rate > 1 V/ns. 6. For data signal input slew rate > 0.5 V/ns and < 1 V/ns. 7. CLK, CLK signals input slew rates are > 1 V/ns.
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CY2SSTV16857
Table 3. AC Output Electrical Specifications (VDD = 2.5V VDC 5%, Temperature = 0C to +85C) VDD = 2.5V 0.2V Parameter FMAX TDEL TPHL TR TF Propagation Delay from CLK/CLK Q to Q RESET Rise Time Fall time Q Any Q Any Q 0.85 1.0 1.1 Description Condition Min. Max. 280 2.8 4.3 4 4 ns ns V/ns V/ns Unit
Output Buffer Characteristics
Table 4. Output Buffer Voltage vs. Current (V/I) Characteristics Pull-Down Voltage (V) 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 Min I (mA) 0 6 10 15 19 23 27 30 34 36 38 40 42 43 44 44 45 45 45 45 45 46 46 46 46 46 46 46 Max I (mA) 0 13 25 38 49 60 71 81 91 100 108 115 123 130 137 144 150 158 165 172 179 185 191 196 201 206 211 216 Min I (mA) 0 -5 -10 -15 -19 -23 -28 -31 -35 -38 -40 -44 -46 -48 -50 -51 -52 -52 -52 -53 -53 -53 -54 -54 -54 -54 -55 -55 Pull-Up Max I (mA) 0 -15 -27 -38 -49 -60 -72 -83 -96 -104 -112 -120 -125 -130 -134 -137 -140 -143 -146 -149 -152 -154 -156 -157 -159 -160 -161 -162
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CY2SSTV16857
Slew Rate
The following table describes output-buffer slew-rate characteristics that are sufficient to meet the requirements of registered DDR DIMM performance and timings. These characteristics are not necessarily production tested but can be guaranteed by design or characterization. Compliance with these rates is not mandatory if it can be adequately demonstrated that alternate characteristics meet the requirements of the registered DDR DIMM application. This information does not necessarily have to appear in the device data sheet. Obtain rise and fall time measurements by using the same procedure for obtaining "Ramp" data according to the current WIA IBIS specification. In particular it is very important to note that the following slew rates are specified at the output of the die, without package parasitics in the power, ground or output paths. The measurement points are at 20% and 80%. The slew-rate test load shall be a 50-ohm resistor to GND for Rise and a 50-ohm resistor to VDDQ for fall. The dV/dt ratio is reduced to V/ns. Table 5. Output Buffer Slew-Rate Characteristics dV/dt Rise Fall Min. 0.85 V/ns 1.00 V/ns Max. 4 V/ns 4 V/ns
LVCMOS RESET Input IDD tinact 10% VDD/2 VDD/2 tact 90% VDD 0V
IDDH IDDL
Figure 2. Voltage Waveforms Enable and Disable Times Low- and High-level Enabling[11]
VI(PP) Input tPLH Output VTT VICR VICR tPHL VTT VOH VOL
Figure 3. Voltage Waveforms Propagation Delay Times[12]
Test Configurations[9, 10]
VDD = 2.5V 0.2V Timing Diagrams
LVCMOS RESET Input
VI(PP) VICR
VDD/2 tPHL
VIH VIL VOH VOL
Timing Input tsu
Output
VTT
th VIH** VIL***
Figure 4. Voltage Waveforms Propagation Delay Times[11
VTT F ro m O u tp u t U nder Test R L = 50 O hm T e s t P o in t C L = 30 pF
Figure 5. Load Circuit[8]
Data Input
VREF*
VREF*
Figure 1. Voltage Waveforms Set-up and Hold Times[11, 13, 14]
tw Input VREF* VREF* VIH** VIL***
Figure 6. Voltage Waveforms Pulse Duration[13, 14]
Notes: 8. CL includes probe and jig capacitance. 9. IDD tested with clock and data inputs held at VDD or VSS, and IO = 0 mA. 10. All input pulses are supplied by generators having the following characteristics: PRR < 10 MHz, ZO = 50 ohm input slew rate = 1 V/ns 20% (unless otherwise specified). 11. the outputs are measured one at a time with one transition per measurement. 12. *VTT = VREF = VDDQ/2. 13. **VIH = VREF + 350 mV (AC voltage levels). 14. ***VIL = VREF - 350 mV (AC voltage levels).
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CY2SSTV16857
Ordering Information
Part Number CY2SSTV16857ZC CY2SSTV16857ZCT CY2SSTV16857ZI CY2SSTV16857ZIT Lead-Free CY2SSTV16857ZXC CY2SSTV16857ZXCT CY2SSTV16857ZXI CY2SSTV16857ZXIT 48-pin TSSOP 48-pin TSSOP -Tape and Reel 48-pin TSSOP 48-pin TSSOP -Tape and Reel Commercial, 0 to 70C Commercial, 0 to 70C Industrial, -40 to 85C Industrial, -40 to 85C 48-pin TSSOP 48-pin TSSOP -Tape and Reel 48-pin TSSOP 48-pin TSSOP -Tape and Reel Package Type Product Flow Commercial, 0 to 70C Commercial, 0 to 70C Industrial, -40 to 85C Industrial, -40 to 85C
Package Diagram
48-lead (240-mil) TSSOP II Z4824
0.500[0.019]
24 1
DIMENSIONS IN MM[INCHES] MIN. MAX.
7.950[0.313] 8.255[0.325] 5.994[0.236] 6.198[0.244]
REFERENCE JEDEC MO-153 PACKAGE WEIGHT 0.33gms PART # Z4824 STANDARD PKG. ZZ4824 LEAD FREE PKG.
25
48
12.395[0.488] 12.598[0.496]
1.100[0.043] MAX.
GAUGE PLANE
0.25[0.010]
0.20[0.008]
0.851[0.033] 0.950[0.037] 0.500[0.020] BSC 0.170[0.006] 0.279[0.011] 0.051[0.002] 0.152[0.006] SEATING PLANE 0-8
0.508[0.020] 0.762[0.030]
0.100[0.003] 0.200[0.008]
51-85059-*C
All product and company names mentioned in this document may be the trademarks of their respective holders.
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(c) Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
CY2SSTV16857
Document History Page
Document Title: CY2SSTV16857 14-Bit Registered Buffer PC2700-/PC3200-Compliant Document Number: 38-07443 Rev. ECN No. ** *A Issue Date Orig. of Change HWT RBI New Data Sheet Add power-up requirements to maximum ratings information Changed the Supply voltage (VDD) and Output supply voltage (VDDQ) values from 2.3/2.5/2.7 to 2.5/2.6/2.7Volts in the DC Electrical Specs. table Changed the Reference voltage (VREF) values from 1.15/1.25/1.35 to 1.25/1.3/1.35V in the DC Electrical Specs. table Moved the FMAX value from Min to Max in the AC Output Electrical Spec. table Changed the TR/TF max values from 15.9 to 4V/ns Added Industrial Temp. range in the ordering information Added "PC2700-/PC3200-Compliant" to the title Removed last Features bullet and second-to-last TVSOP package availability Kept only 48-pin TSSOP Added Lead Free Devices Description of Change
116562 08/21/02 122930 12/18/02
*B
125621 05/20/03
RGL
*C *D
130366 11/03/03 308314 See ECN
IJA RGL
Document #: 38-07443 Rev. *D
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