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| Integrated Circuit Systems, Inc. ICS97ULP877A 1.8V Low-Power Wide-Range Frequency Clock Driver Recommended Application: * DDR2 Memory Modules / Zero Delay Board Fan Out * Provides complete DDR DIMM logic solution with ICSSSTU32864/SSTUF32864/SSTUF32866/ SSTUA32864/SSTUA32866/SSTUA32S868/ SSTUA32S865/SSTUA32S869 Product Description/Features: * Low skew, low jitter PLL clock driver * 1 to 10 differential clock distribution (SSTL_18) * Feedback pins for input to output synchronization * Spread Spectrum tolerant inputs * Auto PD when input signal is at a certain logic state Switching Characteristics: * Period jitter: 40ps (DDR2-400/533) 30ps (DDR2-667) * Half-period jitter: 60ps (DDR2-400/533) 50ps (DDR2-667) * OUTPUT - OUTPUT skew: 40ps (DDR2-400/533) 30ps (DDR2-667) * CYCLE - CYCLE jitter 40ps Pin Configuration 1 A B C D E F G H J K 2 3 4 5 6 52-Ball BGA Top View A B C D E F G H J K 1 CLKT1 CLKC1 CLKC2 CLKT2 CLK_INT CLK_INC AGND AVDD CLKT3 CLKC3 2 CLKT0 GND GND VDDQ VDDQ VDDQ VDDQ GND GND CLKC4 3 CLKC0 GND NB VDDQ NB NB VDDQ NB GND CLKT4 4 CLKC5 GND NB VDDQ NB NB VDDQ NB GND CLKT9 5 CLKT5 GND GND OS VDDQ OE VDDQ GND GND CLKC9 6 CLKT6 CLKC6 CLKC7 CLKT7 FB_INT FB_INC FB_OUTC FB_OUTT CLKT8 CLKC8 Block Diagram CLKC1 CLKC0 CLKT1 CLKT0 VDDQ OE CLKC0 LD , OS, or OE OS (1) CLKT1 AVDD Powerdown Control and Test Logic PLL Bypass LD (1) 34 35 33 32 37 CLKT2 CLKC2 VDDQ CLKC2 CLKT2 CLK_INT CLK_INC 1 2 3 4 5 6 7 8 9 10 19 11 12 13 14 15 16 17 18 20 40 39 38 36 31 CLKC1 VDDQ LD (1) or OE CLKT5 CLKT6 CLKT0 CLKC5 CLKC6 30 29 28 27 26 25 24 23 22 21 CLKC7 CLKT7 VDDQ FB_INT FB_INC FB_OUTC FB_OUTT VDDQ OE OS CLKT3 CLKC3 CLKT4 CLKC4 VDDQ AGND AVDD VDDQ GND CLKT5 CLKC5 CLK_INT CLK_INC CLKT6 CLKC6 PLL CLKC3 CLKC4 CLKC9 CLKC8 CLKT3 CLKT4 CLKT9 CLKT8 VDDQ CLKC7 FB_INT FB_INC CLKT8 CLKC8 NOTE: 1. The Logic Detect (LD) powers down the device when a logic LOW is applied to both CLK_INT and CLK+INC. 7116--03/27/07 CLKT9 CLKC9 40-Pin MLF FB_OUTT FB_OUTC VDDQ GND CLKT7 ICS97ULP877A Pin Descriptions Te r m i n a l Name AGND AVDD CLK_INT CLK_INC FB_INT FB_INC FB_OUTT FB_OUTC OE OS GND VDDQ CLKT[0:9] CLKC[0:9] NB Analog Ground A n a l o g p ow e r Clock input with a (10K-100K Ohm) pulldown resistor Complentar y clock input with a (10K-100K Ohm) pulldown resistor Feedback clock input Complementary feedback clock input Feedback clock output Complementary feedback clock output Output Enable (Asynchronous) Output Select (tied to GND or VDDQ) Ground Logic and output power Clock outputs Complementary clock outputs No ball Description Electrical Characteristics Ground 1.8 V nominal Differential input Differential input Differential input Differential input Differential output Differential output LVCMOS input LVCMOS input Ground 1.8V nominal Differential outputs Differential outputs The PLL clock buffer, ICS97ULP877A, is designed for a VDDQ of 1.8 V, a AVDD of 1.8 V and differential data input and output levels. Package options include a plastic 52-ball VFBGA and a 40-pin MLF. ICS97ULP877A is a zero delay buffer that distributes a differential clock input pair (CLK_INT, CLK_INC) to ten differential pair of clock outputs (CLKT[0:9], CLKC[0:9]) and one differential pair feedback clock outputs (FB_OUTT, FBOUTC). The clock outputs are controlled by the input clocks (CLK_INT, CLK_INC), the feedback clocks (FB_INT, FB_INC), the LVCMOS program pins (OE, OS) and the Analog Power input (AVDD). When OE is low, the outputs (except FB_OUTT/FB_OUTC) are disabled while the internal PLL continues to maintain its locked-in frequency. OS (Output Select) is a program pin that must be tied to GND or VDDQ. When OS is high, OE will function as described above. When OS is low, OE has no effect on CLKT7/CLKC7 (they are free running in addition to FB_OUTT/FB_OUTC). When AVDD is grounded, the PLL is turned off and bypassed for test purposes. When both clock signals (CLK_INT, CLK_INC) are logic low, the device will enter a low power mode. An input logic detection circuit on the differential inputs, independent from the input buffers, will detect the logic low level and perform a low power state where all outputs, the feedback and the PLL are OFF. When the inputs transition from both being logic low to being differential signals, the PLL will be turned back on, the inputs and outputs will be enabled and the PLL will obtain phase lock between the feedback clock pair (FB_INT, FB_INC) and the input clock pair (CLK_INT, CLK_INC) within the specified stabilization time tSTAB. The PLL in ICS97ULP877A clock driver uses the input clocks (CLK_INT, CLK_INC) and the feedback clocks (FB_INT, FB_INC) to provide high-performance, low-skew, low-jitter output differential clocks (CLKT[0:9], CLKC[0:9]). ICS97ULP877A is also able to track Spread Spectrum Clocking (SSC) for reduced EMI. ICS97ULP877A is characterized for operation from 0C to 70C. 7116--03/27/07 2 ICS97ULP877A Function Table Inputs AVDD GND GND GND GND 1.8V(nom) 1.8V(nom) 1.8V(nom) 1.8V(nom) 1.8V(nom) 1.8V(nom) OE H H L L L L H H X X OS X X H L H L X X X X CLK_INT L H L H L H L H L H CLK_INT H L H L H L H L L H CLKT L H *L(Z) *L(Z), CLKT7 active *L(Z) *L(Z), CLKT7 active L H *L(Z) CLKC H L *L(Z) *L(Z), CLKC7 active *L(Z) *L(Z), CLKC7 active H L *L(Z) Outputs PLL FB_OUTT L H L H L H FB_OUTC H L H L Bypassed/Off Bypassed/Off Bypassed/Off Bypassed/Off H L On On L H *L(Z) Reser ved H L *L(Z) On On Off *L(Z) means the outputs are disabled to a low stated meeting the IODL limit. 0981C--04/05/05 3 ICS97ULP877A Absolute Maximum Ratings Supply Voltage (VDDQ & AVDD) . . . . . . . . . Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . Ambient Operating Temperature . . . . . . . . . . Storage Temperature . . . . . . . . . . . . . . . . . . . -0.5V to 2.5V GND - 0.5V to VDDQ + 0.5V 0C to +70C -65C to +150C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Electrical Characteristics - Input/Supply/Common Output Parameters TA = 0 - 70C; Supply Voltage AVDDQ, VDDQ = 1.8 V +/- 0.1V (unless otherwise stated) PARAMETER SYMBOL CONDITIONS MIN TYP Input High Current VI = VDDQ or GND I IH (CLK_INT, CLK_INC) Input Low Current (OE, VI = VDDQ or GND I IL OS, FB_INT, FB_INC) Output Disabled Low OE = L, VODL = 100mV 100 I ODL Current I DD1.8 CL = 0pf @ 270MHz Operating Supply Current I DDLD CL = 0pf Input Clamp Voltage VIK VDDQ = 1.7V Iin = -18mA V DDQ - 0.2 I OH = -100 A High-level output VOH voltage I OH = -9 mA 1.1 1.45 I OL=100 A 0.25 Low-level output voltage VOL I OL=9 mA 1 CIN VI = GND or VDDQ 2 Input Capacitance 1 COUT VOUT = GND or VDDQ 2 Output Capacitance 1 MAX 250 10 UNITS A A A 200 500 -1.2 mA A V V V V V pF pF 0.10 0.6 3 3 Guaranteed by design, not 100% tested in production. 7116--03/27/07 4 ICS97ULP877A Recommended Operating Condition (see note1) TA = 0 - 70C; Supply Voltage AVDD, VDDQ = 1.8 V +/- 0.1V (unless otherwise stated) PARAMETER Supply Voltage Low level input voltage SYMBOL VDDQ, AVDD VIL CONDITIONS MIN 1.7 TYP 1.8 MAX 1.9 0.35 x V DDQ 0.35 x V DDQ UNITS V V V V V VDDQ + 0.3 VDDQ + 0.4 VDDQ + 0.4 V DDQ/2 + 0.10 V V V V V mA mA C High level input voltage DC input signal voltage (note 2) Differential input signal voltage (note 3) Output differential crossvoltage (note 4) Input differential crossvoltage (note 4) High level output current Low level output current Operating free-air temperature VIH VIN CLK_INT, CLK_INC, FB_INC, FB_INT OE, OS CLK_INT, CLK_INC, FB_INC, 0.65 x VDDQ FB_INT OE, OS 0.65 x VDDQ -0.3 DC - CLK_INT, CLK_INC, FB_INC, FB_INT AC - CLK_INT, CLK_INC, FB_INC, FB_INT 0.3 0.6 VDDQ/2 - 0.10 VID VOX VIX IOH I OL TA VDDQ/2 - 0.15 VDD/2 VDDQ2 + 0.15 -9 9 0 70 Notes: 1. Unused inputs must be held high or low to prevent them from floating. 2. DC input signal voltage specifies the allowable DC execution of differential input. 3. Differential inputs signal voltages specifies the differential voltage [VTR-VCP] required for switching, where VTR is the true input level and VCP is the complementary input level. 4. Differential cross-point voltage is expected to track variations of VDDQ and is the voltage at which the differential signal must be crossing. 0981C--04/05/05 5 ICS97ULP877A Timing Requirements T A = 0 - 70C Supply Voltage AVDD, VDDQ = 1.8 V +/- 0.1V (unless otherwise stated) CONDITIONS PARAMETER SYMBOL MIN MAX Max clock frequency Application Frequency Range Input clock duty cycle CLK stabilization freqop freqApp dtin T STAB 1.8V+0.1V @ 25C 1.8V+0.1V @ 25C 95 160 40 410 350 60 15 UNITS MHz MHz % s NOTE: The PLL must be able to handle spread spectrum induced skew. NOTE: Operating clock frequency indicates a range over which the PLL must be able to lock, but in which it is not required to meet the other timing parameters. (Used for low speed system debug.) NOTE: Application clock frequency indicates a range over which the PLL must meet all timing parameters. NOTE: Stabilization time is the time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal, within the value specificied by the Static Phase Offset (t(AE ), after power-up. During normal operation, the stabilization time is also the time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal when CK and CK go to a logic low state, enter the power-down mode and later return to active operation. CK and CK may be left floating after they have been driven low for one complete clock cycle. 7116--03/27/07 6 ICS97ULP877A Switching Characteristics 1 TA = 0 - 70C Supply Voltage AVDD, VDDQ = 1.8 V +/- 0.1V (unless otherwise stated) PARAMETER CONDITION (MHz) SYMBOL ten OE to any output Output enable time 160 to 410 tdis Output disable time OE to any output 160 to 270 tjit (per) Period jitter 271 to 410 160 to 270 tjit(hper) Half-period jitter 271 to 410 Input Clock Input slew rate SLr1(i) Output Enable (OE), (OS) Output clock slew rate 160 to 410 SLr1(o) tjit(cc+) Cycle-to-cycle period jitter tjit(cc-) 160 to 270 t(O)dyn Dynamic Phase Offset 271 to 410 2 Static Phase Offset 271 to 410 tSPO (su) t jit (per) + t (O)dyn + t skew(o) t(O)dyn + tskew(o) t (h) 160 to 270 tskew Output to Output Skew 271 to 410 SSC modulation frequency SSC clock input frequency deviation PLL Loop bandwidth (-3 dB from unity gain) MIN TYP 4.73 5.82 -40 -30 -60 -50 1 0.5 1.5 0 0 -50 -20 -50 2.5 2.5 MAX 8 8 40 30 60 50 4 3 40 -40 50 20 50 80 60 40 30 33 -0.50 0 30.00 0.00 2.0 UNITS ns ns ps ps ps ps v/ns v/ns v/ns ps ps ps ps ps ps ps ps ps kHz % MHz Notes: 1. Switching characteristics guaranteed for application frequency range. 2. Static phase offset shifted by design. 0981C--04/05/05 7 ICS97ULP877A Parameter Measurement Information VDD VCLK VCLK ICS97ULP877A GND IBIS Model Output Load VDD/2 ICS97ULP877A C = 10pF SCOPE GND R = 10 Z = 50 Z = 60 L = 2.97" Z = 120 Z = 60 L = 2.97" GND C = 10pF R = 10 R = 1M C = 1pF Z = 50 VTT R = 1M C = 1pF VTT Note: VTT = GND VDD/2 Output Load Test Circuit Yx, FB_OUTC Yx, FB_OUTT tC(n) tJIT(CC) = tC(n) tC(n+1) tC(n+1) 7116--03/27/07 Cycle-to-Cycle Jitter 8 ICS97ULP877A Parameter Measurement Information CLK_INC CLK_INT FB_INC FB_INT t()n t()n+1 t() = n=N 1 n t()n (N is a large number of samples) Static Phase Offsel Yx Yx Yx, FB_OUTC Yx, FB_OUTT t(SKEW) Output Skew Yx, FB_OUTC Yx, FB_OUTT tC(n) Yx, FB_OUTC Yx, FB_OUTT 1 fo t(JIT_PER) = tC(n) 1 fo Period Jitter 0981C--04/05/05 9 ICS97ULP877A Parameter Measurement Information Yx, FB_OUTC Yx, FB_OUTT tJIT(HPER_n) 1 fo 1 2xfo tJIT(HPER_n+1) tJIT(HPER) = tJIT(HPER_n) Half-Period Jitter 80% 80% VID, VOD Clock Inputs and Outputs 20% 20% tSLR tSLF Input and Output Skew Rates 7116--03/27/07 10 ICS97ULP877A Parameter Measurement Information CLK CLK FBIN FBIN t(O) SSC OFF SSC ON t(O) SSC OFF SSC ON t(O)DYN t(O)DYN t(O)DYN t(O)DYN Dynamic Phase Offset OE 50% VDDQ tEN 50% VDDQ Y Y Y/Y OE 50% VDDQ Y Y tDIS 50% VDDQ Time Delay Between OE and Clock Output (Y, Y) 0981C--04/05/05 11 ICS97ULP877A VIA CARD R1 BEAD 0603 AVDD VDDQ 1 4.7uF 1206 0.1uF 0603 2200pF 0603 AGND PLL GND VIA CARD AVDD Filtering - Place the 2200pF capacitor close to the PLL. - Use a wide trace for the PLL analog power & ground. Connect PLL & caps to AGND trace & connect trace to one GND via (farthest from PLL). - Recommended bead: Fair-Rite P/N 2506036017Y0 or equivalent (0.8 Ohm DC max, 600 Ohms @ 100 MHz). 7116--03/27/07 12 ICS97ULP877A C SEATING PLANE A1 T b REF 4 3 2 1 A B C D Alpha Designations for Vertical Grid (Letters I, O, Q, and S not used) d TYP D1 Numeric Designations for Horizontal Grid D -e- TYP TOP VIEW E h TYP 0.12 C E1 c REF -e- TYP ALL DIMENSIONS IN MILLIMETERS D 7.00 Bsc E 4.50 Bsc T Min/Max 0.86/1.00 e 0.65 Bsc ----- BALL GRID ----HORIZ VERT 6 10 Max. TOTAL 60 d Min/Max 0.35/0.45 h Min/Max 0.15/0.21 D1 5.85 Bsc E1 3.25 Bsc REF. DIMENSIONS b c 0.575 0.625 ** Note: Ball grid total indicates maximum ball count for package. Lesser quantity may be used. * Source Ref.: JEDEC Publication 95, 10-0055 MO-205*, MO-225** Ordering Information ICS97ULP877AHLF-T Example: ICS XXXX y H LF- T Designation for tape and reel packaging Annealed Lead Free (Optional) Package Type H = BGA Revision Designator (will not correlate with datasheet revision) Device Type Prefix ICS = Standard Device 0981C--04/05/05 13 ICS97ULP877A Seating Plane (Ref.) ND & NE Even Index Area N A1 A3 L (ND - 1) x e (Ref.) e/2 1 2 or Anvil Singulation 1 2 Sawn Singulation Top View E2 E2/2 (Typ.) If ND & NE are Even E (NE - 1) x e (Ref.) b A C 0.08 C (Ref.) ND & NE Odd e D2/2 D2 Thermal Base D THERMALLY ENHANCED, VERY THIN, FINE PITCH QUAD FLAT / NO LEAD PLASTIC PACKAGE ALL DIMENSIONS IN MILLIMETERS N ND NE D x E BASIC D2 MIN. / MAX. E2 MIN. / MAX. L MIN. / MAX. 40 10 10 6.00 x 6.00 2.75 / 3.05 2.75 / 3.05 0.30 / 0.50 SYMBOL A A1 A3 b e MIN. MAX. 0.80 1.00 0 0.05 0.25 Reference 0.18 0.30 0.50 BASIC Source Reference: MLF2TM SE 10-0053 Ordering Information ICS97ULP877AKLF-T Example: ICS XXXX y K LF- T Designation for tape and reel packaging Annealed Lead Free (Optional) Package Type K = MLF Revision Designator (will not correlate with datasheet revision) Device Type Prefix ICS = Standard Device 7116--03/27/07 14 |
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