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SY89228U
1GHz Precision, LVPECL /3, /5 Clock Divider with Fail-Safe Input and Internal Termination
General Description
The SY89228U is a precision, low jitter 1GHz /3, /5 clock divider with an LVPECL output. A unique FailSafe Input (FSI) protection prevents metastable output conditions when the input clock voltage swing drops significantly below 100mV or input is removed. The differential input includes Micrel's unique, 3-pin internal termination architecture that allows the input to interface to any differential signal (AC- or DCcoupled) as small as 100mV (200mVPP) without any level shifting or termination resistor networks in the signal path. The outputs are 800mV, 100Kcompatible LVPECL with fast rise/fall times guaranteed to be less than 270ps. The SY89228U operates from a 2.5V 5% or 3.3V 10% supply and is guaranteed over the full industrial temperature range of -40C to +85C. The SY89228U is part of Micrel's high-speed, Precision Edge(R) product line. All support documentation can be found on Micrel's web site at: www.micrel.com.
Precision Edge(R)
Features
* Accepts a high-speed input and provides a precision /3 and /5 sub-rate, LVPECL output * Fail-Safe Input - Prevents oscillations when input is invalid * Guaranteed AC performance over temperature and supply voltage: - DC-to >1.0GHz throughput - < 1500ps Propagation Delay (In-to-Q) - < 270ps Rise/Fall times * Ultra-low jitter design: - <1psRMS random jitter - <1psRMS cycle-to-cycle jitter - <10psPP total jitter (clock) - <0.7psRMS MUX crosstalk induced jitter * Unique patented internal termination and VT pin accepts DC- and AC-coupled inputs (CML, PECL, LVDS) * Wide input voltage range VCC to GND * 800mV LVPECL output * 46% to 54% Duty Cycle(/ 3) * 47% to 53% Duty Cycle(/ 5) * 2.5V 5% or 3.3V 10% supply voltage * -40C to +85C industrial temperature range * Available in 16-pin (3mm x 3mm) MLF(R) package
Block Diagram
Applications
* Fail-safe clock protection
Markets
* * * * LAN/WAN Enterprise servers ATE Test and measurement
Precision Edge is a registered trademark of Micrel, Inc. MLF and MicroLeadFrame are registered trademarks of Amkor Technology. Micrel Inc. * 2180 Fortune Drive * San Jose, CA 95131 * USA * tel +1 (408) 944-0800 * fax + 1 (408) 474-1000 * http://www.micrel.com
August 2007
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SY89228U
Ordering Information(1)
Part Number SY89228UMG SY89228UMGTR(2)
Notes: 1. Contact factory for die availability. Dice are guaranteed at TA = 25C, DC Electricals Only. 2. Tape and Reel.
Package Type MLF-16 MLF-16
Operating Range Industrial Industrial
Package Marking 228U with Pb-Free bar-line Indicator 228U with Pb-Free bar-line Indicator
Lead Finish NiPdAu Pb-Free NiPdAu Pb-Free
Pin Configuration
16-Pin MLF(R) (MLF-16)
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SY89228U
Pin Description
Pin Number Pin Name Pin Function Differential Input: This input pair is the differential signal input to the device, which accepts AC- or DC-coupled signal as small as 100mV. The input internally terminates to a VT pin through 50 and has level shifting resistors of 3.72 k to VCC. This allows a wide input voltage range from VCC to GND. See Figure 3a, Simplified Differential Input Stage for details. Note that this input will default to a valid (either HIGH or LOW) state if left open. See "Input Interface Applications" subsection. Input Termination Center-Tap: Each side of the differential input pair terminates to the VT pin. The VT pin provides a center-tap for the input (IN, /IN) to a termination network for maximum interface flexibility. See "Input Interface Applications" subsection for more details. Reference Voltage: This output biases to VCC-1.2V. It is used for AC-coupling inputs IN and /IN. Connect VREF-AC directly to the VT pin. Bypass with 0.01F low ESR capacitor to VCC. Due to limited drive capability, the VREF-AC pin is only intended to drive its respective VT pin. Maximum sink/source current is 0.5mA. See "Input Interface Applications" subsection. Single-ended Input: This TTL/CMOS-compatible input disables and enables the output. It is internally connected to a 25k pull-up resistor and will default to a logic HIGH state if left open. When disabled, Q goes LOW and /Q goes HIGH. EN being synchronous, outputs will be enabled/disabled after a rising and a falling edge of the input clock. VTH = VCC/2. Single-ended Input: This TTL/CMOS-compatible input, when pulled LOW, asynchronously sets Q output LOW and /Q output HIGH. Note that this input is internally connected to a 25k pull-up resistor and will default to logic HIGH state if left open. VTH = VCC/2. No Connect Positive Power Supply: Bypass with 0.1F in parallel with 0.01F low ESR capacitors as close to the VCC pins as possible. Differential Output: The LVPECL output swing is typically 800mV and is terminated with 50 to VCC-2V. See the "Truth Table" below for the logic function. Ground: Ground and exposed pad must be connected to a ground plane that is the same potential as the ground pins. Single-ended Input: This TTL/CMOS-compatible input selects divide-by-3 when pulled LOW and divide-by-5 when pulled HIGH. Note that this input is internally connected to a 25k pull-up resistor and will default to logic HIGH state if left open. VTH = VCC/2.
1, 4
IN, /IN
2
VT
3
VREF-AC
5
EN
6 7 8, 13 12, 9 10, 11, 14,15
/MR NC VCC Q, /Q GND, Exposed Pad DIV_SEL
16
Truth Table
Inputs DIV_SEL X 0 1 X EN X 1 1 0 /MR 0 1 1 1 Outputs Q 0 /Q 1
/3 /5
0
/3 /5
1
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SY89228U
Absolute Maximum Ratings(1)
Supply Voltage (VCC) ..........................-0.5V to +4.0V Input Voltage (VIN) ..................................-0.5V to VCC LVPECL Output Current (IOUT).................................... Continuous ................................................. 50mA Surge........................................................ 100mA Current (VT) Source or sink current on VT pin............100mA Input Current Source or sink current on (IN, /IN) ........... 50mA Current (VREF-AC) Source/Sink Current on VREF-AC(4) ............ 0.5mA Maximum Operating Junction Temperature.....125C Lead Temperature (soldering, 20 sec.) ..........+260C Storage Temperature (Ts)..................-65C to 150C
Operating Ratings(2)
Supply Voltage (VCC).................. +2.375V to +2.625V ......................................................+3.0V to +3.6V Ambient Temperature (TA)................ -40C to +85C Package Thermal Resistance (3) MLF(R) ( JA) Still-Air ..................................................... 75C/W MLF(R) ( JB) Junction-to-Board...............................33C/W
DC Electrical Characteristics(5)
TA = -40C to +85C, unless otherwise stated.
Symbol VCC ICC RIN RDIFF_IN VIH VIL VIN VDIFF_IN VIN_FSI VREF-AC VT_IN
Notes: 1. Permanent device damage may occur if absolute maximum ratings are exceeded. This is a stress rating only and functional operation is not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings. 3. Package thermal resistance assumes exposed pad is soldered (or equivalent) to the devices most negative potential on the PCB. JA and JB values are determined for a 4-layer board in still air unless otherwise stated. 4. Due to limited drive capability use for input of the same package only. 5. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. 6. VIN (max) is specified when VT is floating.
Parameter Power Supply Power Supply Current Input Resistance (IN-to-VT) Differential Input Resistance (IN-to-/IN) Input High Voltage (IN, /IN) Input Low Voltage (IN, /IN) Input Voltage Swing (IN, /IN) Differential Input Voltage Swing |IN-/IN| Input Voltage Threshold that Triggers FSI Output Reference Voltage Voltage from Input to VT
Condition
Min 2.375 3.0
Typ 2.5 3.3 40 50 100
Max 2.625 3.6 55 55 110 VCC VIH-0.1 VCC
Units V V mA V V V V
No load, max VCC 45 90 1.2 0 See Figure 2a. Note 6. See Figure 2b. 0.1 0.2
30 VCC-1.3 VCC-1.2
100 VCC-1.1 1.8
mV V V
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SY89228U
LVPECL Outputs DC Electrical Characteristics(7)
VCC = 2.5V 5% or 3.3V 10%; RL = 50 to VCC-2V; TA = -40C to + 85C, unless otherwise stated.
Symbol VOH VOL VOUT VDIFF_OUT Parameter Output HIGH Voltage Q, /Q Output LOW Voltage Q, /Q Output Voltage Swing Q, /Q Differential Output Voltage Swing Q, /Q See Figure 2a. See Figure 2b. Condition Min VCC-1.145 VCC-1.945 550 1100 800 1600 Typ Max VCC-0.895 VCC-1.695 950 Units V V mV mV
LVTTL/CMOS DC Electrical Characteristics(7)
VCC = 2.5V 5% or 3.3V 10%; TA = -40C to + 85C, unless otherwise stated.
Symbol VIH VIL IIH IIL
Note: 7. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
Parameter Input HIGH Voltage Input LOW Voltage Input HIGH Current Input LOW Current
Condition
Min 2.0
Typ
Max 0.8
Units V V A A
-125 -300
30
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SY89228U
AC Electrical Characteristics(8)
VCC = 2.5V 5% or 3.3V 10%; RL = 50 to VCC-2V; TA = -40C to + 85C, unless otherwise stated.
Symbol fMAX tw tpd Parameter Maximum Input Operating Frequency Minimum Pulse Width Differential Propagation Delay In-to-Q In-to-Q /MR(H-L)-to-Q tRR tS EN tH EN tskew tJITTER Reset Recovery Time Set-up Time Hold Time Part-to-Part Skew Clock Random Jitter Cycle-to-Cycle Jitter Total Jitter tr, tf Output Rise/Fall Time (20% to 80%) Output Duty Cycle(/ 3) Output Duty Cycle(/ 5)
Notes: 8. High-frequency AC-parameters are guaranteed by design and characterization. 9. The propagation delay is function of the rise and fall times at IN. Input tr / tf 300ps (20% to 80%). See "Typical Operating Characteristics" for details. 10. Set-up and hold times apply to synchronous applications that intend to enable/disable before the next clock cycle. For asynchronous applications, set-up and hold do not apply. 11. Random Jitter is measured with a K28.7 character pattern, measured at 12
Condition VOUT 200mV IN, /IN 100mV < VIN 200mV, Note 9 200mV < VIN 800mV, Note 9 /MR(L-H)-to-IN EN-to-IN IN-to-EN Note 10 Note 10 Note 10 Note 11 Note 12 Note 13 At full output swing. Duty Cycle(input): 50%; f 1GHz; Note 14 Duty Cycle(input): 50%; f 1GHz; Note 14
Min 1.0 400 900 800 350 300 300 800
Typ 1.5
Max
Units GHz ps
1150 1050 570
1500 1400 850
ps ps ps ps ps ps
450 1 1 10 100 46 47 270 54 53
ps psRMS psRMS psPP ps % %
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SY89228U
Functional Description
Fail-Safe Input (FSI) The input includes a special failsafe circuit to sense the amplitude of the input signal and to latch the outputs when there is no input signal present, or when the amplitude of the input signal drops sufficiently below 100mVPK (200mVPP), typically 30mVPK. Maximum frequency of the SY89228U is limited by the FSI function. Refer to Figure 1b. Input Clock Failure Case If the input clock fails to a floating, static, or extremely low signal swing, the FSI function will eliminate a metastable condition and guarantee a stable output signal. No ringing and no undetermined state will occur at the output under these conditions. Note that the FSI function will not prevent duty cycle distortion in case of a slowly deteriorating (but still toggling) input signal as it nears the FSI threshold (typically, 30mV). Due to the FSI function, the propagation delay will depend on rise and fall time of the input signal and on its amplitude. See "Typical Operating Characteristics" for detailed information. Output Duty Cycle Equation For a non 50% input, derate the spec by: For Divide by 3:
1+
Enable (EN) EN is a synchronous TTL/CMOS-compatible input that enables/disables the outputs based on the input to this pin. Internal 25k pull-up resistor defaults the input to logic HIGH if left open. Input switching threshold is VCC/2. The Enable function operates as follows: 1. The enable/disable function is synchronous so that the clock outputs will be enabled or disabled following a rising and a falling edge of the input clock when switching from EN = LOW to EN = HIGH. However, when switching from EN = HIGH to EN = LOW, the clock outputs will be disabled following an input clock rising edge and an output clock falling edge. 2. The enable/disable function always guarantees the full pulse width at the output before the clock outputs are disabled, non-depending on the divider ratio. Refer to Figure 1c for examples. Divider Operation The divider operation uses both the rising and falling edge of the input clock. For divide by 3, the falling edge of the second input clock cycle will determine the falling edge of the output. For divide by 5, the falling edge of the third input clock cycle. Refer to Figure 1d.
(0.5 For Divide by 5:
X 100 ) x100, in % 3
X 100 ) x100, in % (0.5 5 X = input Duty Cycle, in % 2+
Example: if a 45% input duty cycle is applied or X=45, in divide by 3 mode, the spec would expand by 1.67% to 44.3%-55.7%
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SY89228U
Timing Diagrams
Figure 1a. Propagation Delay
Figure 1b. Fail-Safe Feature
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SY89228U
Figure 1c. Enable Output Timing Diagram Examples (divide by 3)
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SY89228U
Figure 1d. Divider Operation Timing Diagram
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SY89228U
Typical Operating Characteristics
VCC = 3.3V, GND = 0V, VIN = 200mV, tr / tf 300ps, RL = 50 to VCC-2V; TA = 25C, unless otherwise stated.
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SY89228U
Functional Characteristics
VCC = 3.3V, GND = 0V, VIN = 100mV, Q = Divide by 3, tr/tf 300ps, RL = 50 to VCC-2V; TA = 25C, unless otherwise stated.
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SY89228U
Single-Ended and Differential Swings
Figure 2a. Single-Ended Voltage Swing
Figure 2b. Differential Voltage Swing
Input and Output Stages
Figure 3a. Simplified Differential Input Stage
Figure 3b. Simplified Differential Output Stage
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SY89228U
Input Interface Applications
Option: may connect VT to VCC Figure 4a. LVPECL Interface (DC-Coupled) Figure 4b. LVPECL Interface (AC-Coupled) Figure 4c. CML Interface (DC-Coupled)
Figure 4d. CML Interface (AC-Coupled)
Figure 4e. LVDS Interface (DC-Coupled)
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SY89228U
PECL Output Interface Applications
PECL has high input impedance, very low output impedance (open emitter), and a small signal swing which results in low EMI. PECL is ideal for driving 50- and 100-controlled impedance transmission lines. There are several techniques for terminating the PECL output: parallel termination-thevenin equivalent, parallel termination (3-resistor), and ACcoupled termination. Unused output pairs may be left floating. However, single-ended outputs must be terminated, or balanced.
Figure 5b. Parallel Termination (3-Resistor)
Figure 5a. Parallel Termination-Thevenin Equivalent
Related Product and Support Documentation
Part Number SY89229U SY89230U SY89231U Function 1GHz Precision, LVDS /3, /5 Clock Divider with Fail Safe Input and Internal Termination 3.2GHz Precision, LVPECL /3, /5 Clock Divider 3.2GHz Precision, LVDS /3, /5 Clock Divider MLF(R) Application Note Datasheet Link http://www.micrel.com/_PDF/HBW/sy89229u.pdf http://www.micrel.com/_PDF/HBW/SY89230U.pdf http://www.micrel.com/_PDF/HBW/sy89231u.pdf www.amkor.com/products/notes_papers/MLFAppNote.pdf
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SY89228U
Package Information
16-Pin MicroLeadFrame(R) (MLF-16)
Packages Notes: 1. Package meets Level 2 Moisture Sensitivity Classification. 2. All parts are dry-packed before shipment. 3. Exposed pad must be soldered to a ground for proper thermal management.
MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA
TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http:/www.micrel.com
The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer. Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser's use or sale of Micrel Products for use in life support appliances, devices or systems is a Purchaser's own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale. (c) 2007 Micrel, Inc.
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