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ComLinkTM Series CY2DL814
1:4 Clock Fanout Buffer
Features
* Low-voltage operation * VDD = 3.3V * 1:4 Fanout * Single-input configurable for -- LVDS, LVPECL, or LVTTL -- Four differential pairs of LVDS outputs * Drives 50- or 100-ohm load (selectable) * Low input capacitance * 85 ps typical output-to-output skew * <4 ns typical propagation delay * Does not exceed Bellcore 802.3 standards * Operation at 350 MHz - 700 Mbps * Industrial versions available * Packages available include TSSOP/SOIC
Description
The Cypress CY2 series of network circuits is produced using advanced 0.35-micron CMOS technology, achieving the industry's fastest logic. The Cypress CY2DL814 fanout buffer features a single LVDS-, LVPECL-, or LVTTL-compatible input and four LVDS output pairs. Designed for data-communication clock management applications, the fanout from a single input reduces loading on the input clock. The CY2DL814 is ideal for both level translations from single ended to LVDS and/or for the distribution of LVDS-based clock signals. The Cypress CY2DL814 has configurable input and output functions. The input can be selectable for LVPECL/LVTTL or LVDS signals while the output driver's support standard and high drive LVDS. Drive either a 50-ohm or 100-ohm line with a single part number/device.
Block Diagram
Pin Configuration
EN1 EN2 Q1A Q1B Q2A Q2B LVDS / LVPECL / LVTTL CONFIG
EN1 CONFIG CNTRL VDD GND IN+ INEN2
Q3A Q3B Q4A Q4B CNTRL
IN+ IN-
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
Q1A Q1B Q2A Q2B Q3A Q3B Q4A Q4B
16-pin TSSOP/SOIC
OUTPUT
LVDS
Cypress Semiconductor Corporation Document #: 38-07057 Rev. *B
*
3901 North First Street
*
San Jose, CA 95134 * 408-943-2600 Revised June 20, 2005
CY2DL814
ComLinkTM Series CY2DL814
Pin Description
Pin Number 6,7 3 Pin Name IN+, IN- CNTRL Pin Standard Interface Configurable LVTTL/LVCMOS Description Differential input pair or single line. LVPECL default. See config below. Converts into a High drive driver from a standard LVDS. Standard drive (logic = 0) B/High drive/Bus (logic = 1) Converts inputs (IN+/IN-), (EN, EN#) from the default LVPECL/LVDS (logic = 0) To LVTTL/LVCMOS (logic = 1) Enable/disable logic. See Table 1 below for details. Differential outputs.
2
CONFIG
LVTTL/LVCMOS
1,8 16,15,14,13 12,11,10,9
EN1, EN2 Q1A, Q1B, Q2A, Q2B, Q3A, Q3B, Q4A, Q4B VDD
LVTTL/LVCMOS LDVS
4 5
POWER POWER
Positive supply voltage Ground
GND
Maximum Ratings[1, 2]
Storage Temperature: ................................ -65C to + 150C Ambient Temperature:................................... -40C to +85C Supply Voltage to Ground Potential (Inputs and VCC only)....................................... -0.3V to 4.6V Supply Voltage to Ground Potential Table 1. EN1 EN2 Function Table-Differential Input Mode Enable Logic EN1 H H X X L EN2 X X L L H IN+ H L H L X Input IN- L H L H X QnA H L H L Z Outputs QnB L H L H Z (Outputs only) ........................................ -0.3V to VDD + 0.3V DC Input Voltage ................................... -0.3V to VDD + 0.3V DC Output Voltage................................. -0.3V to VDD + 0.9V Power Dissipation........................................................ 0.75W
Table 2. Output Drive Control for Standard and Bus/B/High Drive B CNTRL Pin 3 Binary Value 0 1 Drive STD Standard High Drive/Bus/B Impedance 100 ohm 50 ohm 100 ohm 50 ohm Output Voltage Value V0 = Voutput V = 1/2 * V0 V = 2 * V0 V = V0
Notes: 1. Stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. This is intended to be a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
Document #: 38-07057 Rev. *B
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ComLinkTM Series CY2DL814
Table 3. Input Receiver Configuration for Differential or LVTTL/LVCMOS CONFIG Pin 2 Binary Value 1 0
Input Receiver Family LVTTL in LVCMOS LVDS LVPECL
Input Receiver Type Single-ended, Non-inverting, Inverting, Void of Bias Resistors Low-voltage Differential Signaling Low-voltage Pseudo (Positive) Emitter Coupled Logic
Table 4. Function Control of the TTL Input Logic Used to Accept or Invert the Input Signal LVTTL/LVCMOS Input Logic Input Condition Ground VCC Ground VCC IN- Pin 7 IN+ Pin 6 IN- Pin 7 IN+ Pin 6 IN+ Pin 6 IN- Pin 7 IN+ Pin 6 IN- Pin 7 Table 5. Power Supply Characteristics Parameter ICCD IC Description Dynamic Power Supply Current Test Conditions VDD = Max. Input toggling 50% Duty Cycle, Outputs Open VDD = Max. Input toggling 50% Duty Cycle, Outputs Open fL=100 MHz Min. Typ. 1.5 Max. 2.0 Unit mA/MHz Input Invert Input True Input Invert Input True Input Logic Output Logic Q Pins, Q1A or Q1
Total Power Supply Current
90
100
mA
Table 6. D.C Electrical Characteristics: 3.3V-LVDS Input Parameter VID VIC VIH VIL IIH IIL II Description Magnitude of Differential Input Voltage Common-mode of Differential Input Voltage IVIDI (min. and max.) Input High Voltage Input Low Voltage Input High Current Input Low Current Input High Current Guaranteed Logic High Level Guaranteed Logic Low Level VDD = Max. VDD = Max. VDD = Max., VIN = VDD(max.) VIN = VDD VIN = VSS 10 10 Config/Cntrl Pins Conditions Min. 100 IVIDI/2 2 0.8 20 20 20 Typ. Max. Unit 600 2.4-(IVIDI/2) mV V V V A A A
Table 7. D.C Electrical Characteristics: 3.3V-LVPECL Input Parameter VID VCM IIH IIL II Description Differential Input Voltage p-p Common-mode Voltage Input High Current Input Low Current Input High Current VDD = Max. VDD = Max. VDD = Max., VIN = VDD(Max.) VIN = VDD VIN = VSS Conditions Guaranteed Logic High Level Min. 400 1.65 10 10 Typ. Max. 2600 2.25 20 20 20 Unit mV V A A A
Document #: 38-07057 Rev. *B
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ComLinkTM Series CY2DL814
Table 8. D.C Electrical Characteristics: 3.3V-LVTTL/LVCMOS Input Parameter VIH VIL IIH IIL II VIK VH Parameter I VOD I VOC(SS) Delta VOC(SS) VOC(PP) IOS Voh Vol Parameter Rise Time Description Input High Voltage Input Low Voltage Input High Current Input Low Current Input High Current Clamp Diode Voltage Input Hysteresis Description Steady-state common-mode output voltage Change in VOC(SS) between logic states Peak to peak common mode output voltage Output short circuit Output voltage high Output voltage low Description Conditions RL = 100 ohm QA = 0V or QB = 0V RL = 100 ohm Conditions RL = 100 ohm Conditions Guaranteed Logic High Level Guaranteed Logic Low Level VDD= Max. VDD= Max. VDD = Max., VIN = VDD(Max.) VDD = Min., IIN = -18 mA -0.7 80 Min. 0.25 - -50 - - - 925 Typ. - - 3 - - - - Max. 0.45 226 50 150 -20 1475 - VIN = 2.7V VIN = 0.5V Min. 2 0.8 1 -1 20 -1.2 Typ. Max. Unit V V A A A V mV Unit V mV mV mV mA mV mV
Table 9. D.C Electrical Characteristics: 3.3V-LVDS OUTPUT Differential output voltage p-p VDD = 3.3V, VIN = VIH, or VIL
Table 10.AC Parameters Min. Typ. Max. Unit - - 1.4 ns CL-10 pF Pin control (pin 3) logic is "FALSE" defaulting to 100 ohm output drivers. RL and CL to GND Differential 20% to 80% 3 CL = Cintrinsic and Cexternal Pin control (pin 3) logic is "True" defaulting to 50 ohm output drivers. Differential 20% to 80% CL-10 pF RL and CL to GND 3 CL = Cintrinsic and Cexternal
Fall Time Rise Time RL = 50 ohm Output boost
- -
- 350
1.4 600
ns ps
Fall Time Table 11.AC Switching Characteristics @ 3.3 V (VDD = 3.3V 5%, Temperature = -40C to +85C) Parameter tPLH tPHL Tpd TPe Tpd tSK(0) tSK(p) tSK(t) Description Propagation Delay - Low to High Propagation Delay - High to Low Propagation Delay Enable (EN) to functional operation Functional operation to Disable Output Skew: Skew between outputs of the same package (in phase) Pulse Skew: Skew between opposite transitions of the same output (tPHL-tPLH) Package Skew: Skew between outputs of different VID = 100 mV packages at the same power supply voltage, temperature and package type. Same input signal level and output load. Conditions VOD = 100 mV Min. 3 3 3 - - - - -
-
350
600
ps Unit ns ns ns ns ns ns ns ns
Typ. 4 4 4 - - 0.085 0.2 -
Max. 5 5 5 6 5 0.2 - 1
IN [+,-] to Q[A,B] Data and Clock Speed
IN [1,2] to Q[A,B] Control Speed
Q[A,B] Output Skews
Document #: 38-07057 Rev. *B
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ComLinkTM Series CY2DL814
Table 12.High Frequency Parametrics Parameter Fmax Fmax(20) Description Maximum frequency VDD = 3.3V Maximum frequency VDD = 3.3V Minimum pulse VDD = 3.3V Conditions 50% duty cycle tW(50-50) Standard Load Circuit. 20% duty cycle tW(50-50) LVPECL Input VIN = VIH(Max.)/VIL(Min.) VOUT = VOH(Min.)/VOL (Max.) (Limit) LVPECL Input VIN = VIH(Max.)/VIL(Min.) F= 100 MHz VOUT = VOH(Min.)/VOL(Max.)(Limit)
A
Pulse Generator
TPA
Min. - -
Typ. - -
Max. 400 200
Unit MHz MHz
TW
1
-
-
ns
10pF B
50
TPC
50
TPB
Standard Termination
V1A V1B
1.2 V CM
1.4 V
0V Differential
1.0 V 1.4 V
V0Y
1.2 V CM
0V Differential
V0Z
TPLH TPHL
1.0 V
80% 0V Differential V0Y - V0Z 20% tR tF
Figure 1. Differential Receiver to Driver Propagation Delay and Driver Transition Time[3, 4, 5, 6]
A
Pulse Generator
TPA
50 B
TPC
50
TPB
VOC
VOD
Standard Termination
VI(A) VI(B)
2.0V 1.6V
Next Device
Figure 2. Test Circuit and Voltage Definitions for the Driver Common-mode Output Voltage[3, 4, 5, 6]
Notes: 3. All input pulses are supplied by a frequency generator with the following characteristics: tR and tF 1 ns; pulse rerate = 50 Mpps; pulse width = 10 0.2 ns. 4. RL= 50 ohm 1% Zline = 50 ohm 6". 5. CL includes instrumentation and fixture capacitance within 6 mm of the UT. 6. TPA and B are used for prop delay and Rise/Fall measurements. TPC is used for VOC measurements only and is otherwise connected to VDD- 2.
Document #: 38-07057 Rev. *B
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ComLinkTM Series CY2DL814
A
Pulse Generator
TPA
10pF B
50
TPC
50
TPB
Standard Termination
VI(A) VI(B)
1.4V 1.0V
100% 80%
0.0V
20% 0%
tF
tR
Figure 3. Test Circuit and Voltage Definitions for the Differential Output Signal[3, 4, 5, 6]
IN P U T A
LVCM OS / LVTTL
IN P U T B GND
LVPECL & LVDS
In C o n fig
1
In C o n fig 0 L V D S /L V P E C L
L V T T L /L V C M O S
Figure 4. LVCMOS/LVTTL Single-ended Input Value[7]
Figure 5. LVPECL or LVDS Differential Input Value[8] Product Flow
Industrial, -40C to 85C Industrial, -40C to 85C Industrial, -40C to 85C Industrial, -40C to 85C Commercial, 0C to 70 C Commercial, 0C to 70 C Commercial, 0C to 70 C Commercial, 0C to 70 C Industrial, -40C to 85C Industrial, -40C to 85C Industrial, -40C to 85C Industrial, -40C to 85C Commercial, 0C to 70 C Commercial, 0C to 70 C Commercial, 0C to 70 C Commercial, 0C to 70 C
Ordering Information
Part Number
CY2DL814ZI CY2DL814ZIT CY2DL814SI CY2DL814SIT CY2DL814ZC CY2DL814ZCT CY2DL814SC CY2DL814SCT Lead-free CY2DL814ZXI CY2DL814ZXIT CY2DL814SXI CY2DL814SXIT CY2DL814ZXC CY2DL814ZXCT CY2DL814SXC CY2DL814SXCT 16-pin TSSOP 16-pin TSSOP-Tape and Reel 16-pin SOIC 16-pin SOIC-Tape and Reel 16-pin TSSOP 16-pin TSSOP-Tape and Reel 16-pin SOIC 16-pin SOIC-Tape and Reel
Package Type
16-pin TSSOP 16-pin TSSOP-Tape and Reel 16-pin SOIC 16-pin SOIC-Tape and Reel 16-pin TSSOP 16-pin TSSOP-Tape and Reel 16-pin SOIC 16-pin SOIC-Tape and Reel
Notes: 7. LVCMOS/LVTTL single ended input value. Ground either input: when on the B side then non-inversion takes place. If A side is grounded, the signal becomes the complement of the input on B side. See Table 4. 8. LVPECL or LVDS differential input value.
Document #: 38-07057 Rev. *B
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ComLinkTM Series CY2DL814
Package Drawing and Dimensions 16 Lead (150 Mil) SOIC 16-Lead (150-Mil) SOIC S16.15
PIN 1 ID
8
1 DIMENSIONS IN INCHES[MM] MIN. MAX. REFERENCE JEDEC MS-012
0.150[3.810] 0.157[3.987] 0.230[5.842] 0.244[6.197]
PACKAGE WEIGHT 0.15gms
PART # S16.15 STANDARD PKG. 9 16 SZ16.15 LEAD FREE PKG.
0.386[9.804] 0.393[9.982]
SEATING PLANE
0.010[0.254] 0.016[0.406]
X 45
0.061[1.549] 0.068[1.727] 0.004[0.102] 0.050[1.270] BSC 0.0138[0.350] 0.0192[0.487] 0.004[0.102] 0.0098[0.249]
0~8
0.016[0.406] 0.035[0.889]
0.0075[0.190] 0.0098[0.249]
51-85068-*B
16-lead TSSOP 4.40 mm Body Z16.173
PIN 1 ID
1
DIMENSIONS IN MM[INCHES] MIN. MAX. REFERENCE JEDEC MO-153
6.25[0.246] 6.50[0.256] 4.30[0.169] 4.50[0.177]
PACKAGE WEIGHT 0.05 gms PART # Z16.173 STANDARD PKG. ZZ16.173 LEAD FREE PKG.
16
0.65[0.025] BSC.
0.19[0.007] 0.30[0.012]
1.10[0.043] MAX.
0.25[0.010] BSC GAUGE PLANE 0-8
0.076[0.003] 0.85[0.033] 0.95[0.037] 0.05[0.002] 0.15[0.006] SEATING PLANE 0.50[0.020] 0.70[0.027] 0.09[[0.003] 0.20[0.008]
4.90[0.193] 5.10[0.200]
51-85091-*A
ComLink is a trademark of Cypress Semiconductor Corporation. All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-07057 Rev. *B Page 7 of 8
(c) Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
ComLinkTM Series CY2DL814
Document Title: ComLinkTM Series CY2DL814 1:4 Clock Fanout Buffer Document Number: 38-07057 REV.
** *A *B
ECN NO.
115362 122744 384077
Issue Date
07/10/02 12/14/02 See ECN
Orig. of Change
EHX RBI RGL New Data Sheet
Description of Change
Added power up requirements to maximum ratings information. Added Lead-free devices Added typical values
Document #: 38-07057 Rev. *B
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