 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| FPD1050SOT89 LOW NOISE HIGH LINEARITY PACKAGED PHEMT FEATURES (1.8GHZ): * * * * * * 26 dBm Output Power (P1dB) 17.5 dB Small-Signal Gain (SSG) 1.1 dB Noise Figure 40 dBm Output IP3 50% Power-Added Efficiency FPD1050SOT89E: RoHS compliant (Directive 2002/95/EC) Datasheet v3.0 PACKAGE: GENERAL DESCRIPTION: The FPD1050SOT89 is a packaged depletion mode AlGaAs/InGaAs pseudomorphic High Electron Mobility Transistor (pHEMT). It utilizes a 0.25 m x 1050 m Schottky barrier Gate, defined by high-resolution stepperbased photolithography. The recessed and offset Gate structure minimizes parasitics to optimize performance, with an epitaxial structure designed for improved linearity over a range of bias conditions and i/p power levels. TYPICAL APPLICATIONS: * * * Drivers or output stages in PCS/Cellular base station transmitter amplifiers High intercept-point LNAs WLL and WLAN systems, and other types of wireless infrastructure systems. ELECTRICAL SPECIFICATIONS: PARAMETER Power at 1dB Gain Compression Small-Signal Gain SYMBOL P1dB SSG CONDITIONS VDS = 5 V; IDS = 50% IDSS VDS = 5 V; IDS = 50% IDSS MIN 24.5 16 TYP 26 17.5 MAX UNITS dBm dB Power-Added Efficiency PAE VDS = 5 V; IDS = 50% IDSS; POUT = P1dB 50 % Noise Figure NF VDS = 5 V; IDS = 50% IDSS VDS = 5 V; IDS = 25% IDSS 0.9 1.1 dB Output Third-Order Intercept Point (from 15 to 5 dB below P1dB) IP3 VDS = 5V; IDS = 50% IDSS Matched for optimal power Matched for best IP3 37 39 40 260 320 520 270 1 0.7 12 12 1.0 16 16 76 15 1.3 385 mA mA mS A V V V C/W dBm Saturated Drain-Source Current Maximum Drain-Source Current Transconductance Gate-Source Leakage Current Pinch-Off Voltage Gate-Source Breakdown Voltage Gate-Drain Breakdown Voltage Thermal Resistance IDSS IMAX GM IGSO |VP| |VBDGS| |VBDGD| RJC VDS = 1.3 V; VGS = 0 V VDS = 1.3 V; VGS +1 V VDS = 1.3 V; VGS = 0 V VGS = -5 V VDS = 1.3 V; IDS = 1.05 mA IGS = 1.05 mA IGD = 1.05 mA Note: TAMBIENT = 22; RF specification measured at f = 1850 MHz using CW signal (except as noted) 1 Specifications subject to change without notice Filtronic Compound Semiconductors Ltd Fax: +44 (0) 1325 306177 Email: sales@filcs.com Tel: +44 (0) 1325 301111 Website: www.filtronic.com FPD1050SOT89 Datasheet v3.0 ABSOLUTE MAXIMUM RATING : PARAMETER Drain-Source Voltage Gate-Source Voltage Drain-Source Current Gate Current 2 RF Input Power Channel Operating Temperature Storage Temperature Total Power Dissipation Gain Compression 3 Simultaneous Combination of Limits 2 or more Max. Limits PIN TCH TSTG PTOT Comp. Under any acceptable bias state Under any acceptable bias state Non-Operating Storage See De-Rating Note below Under any bias conditions 260mW 175C -40C to 150C 2.0W 5dB 1 SYMBOL VDS VGS IDS IG TEST CONDITIONS -3V < VGS < +0V 0V < VDS < +8V For VDS > 2V Forward or reverse current ABSOLUTE MAXIMUM 8V -3V IDss 10mA Notes: 1 TAmbient = 22C unless otherwise noted; exceeding any one of these absolute maximum ratings may cause permanent damage to the device 2 Max. RF Input Limit must be further limited if input VSWR > 2.5:1 3 Users should avoid exceeding 80% of 2 or more Limits simultaneously 4 Total Power Dissipation defined as: PTOT (PDC + PIN) - POUT, where PDC: DC Bias Power, PIN: RF Input Power, POUT: RF Output Power Total Power Dissipation to be de-rated as follows above 22C: PTOT= 2.0 - (0.013W/C) x TPACK where TPACK= source tab lead temperature above 22C (coefficient of de-rating formula is the Thermal Conductivity) Example: For a 65C carrier temperature: PTOT = 2.0W - (0.013 x (65 - 22)) = 1.44W BIASING GUIDELINES: * Active bias circuits provide good performance stabilization over variations of operating temperature, but require a larger number of components compared to self-bias or dual-biased. Such circuits should include provisions to ensure that Gate bias is applied before Drain bias, otherwise the pHEMT may be induced to self-oscillate Dual-bias circuits are relatively simple to implement, but will require a regulated negative voltage supply for depletion-mode devices. Self-biased circuits employ an RF-bypassed Source resistor to provide the negative Gate-Source bias voltage, and such circuits provide some temperature stabilization for the device. A nominal value for circuit development is 3.6 for a 50% of IDSS operating point. For standard Class A operation, a 50% of IDSS bias point is recommended. A small amount of RF gain expansion prior to the onset of compression is normal for this operating point. Note that pHEMTs, since they are "quasi- E/D mode" devices, exhibit Class AB traits when operated at 50% of IDSS. To achieve a larger separation between P1dB and IP3, an operating point in the 25% to 33% of IDSS range is suggested. Such Class AB operation will not degrade the IP3 performance. * * * 2 Specifications subject to change without notice Filtronic Compound Semiconductors Ltd Fax: +44 (0) 1325 306177 Email: sales@filcs.com Tel: +44 (0) 1325 301111 Website: www.filtronic.com FPD1050SOT89 Datasheet v3.0 PACKAGE OUTLINE: (dimensions in millimeters - mm) PREFERRED ASSEMBLY INSTRUCTIONS: Available on request. HANDLING PRECAUTIONS: To avoid damage to the devices care should be exercised during handling. Proper Electrostatic Discharge (ESD) precautions should be observed at all stages of storage, handling, assembly, and testing. These devices should be treated as Class (0250 V) as defined in JEDEC Standard No. 22A114. Further information on ESD control measures can be found in MIL-STD-1686 and MIL-HDBK-263. APPLICATION NOTES & DESIGN DATA: PCB Foot Print Application Notes and design data including Sparameters are available on request. DISCLAIMERS: This product is not designed for use in any space based or life sustaining/supporting equipment. ORDERING INFORMATION: PART NUMBER FPD1050SOT89 FPD1050SOT89E DESCRIPTION Packaged pHEMT RoHS compliant Packaged pHEMT Units in inches NOTE: Drawing available on request 3 Specifications subject to change without notice Filtronic Compound Semiconductors Ltd Fax: +44 (0) 1325 306177 Email: sales@filcs.com Tel: +44 (0) 1325 301111 Website: www.filtronic.com |
Price & Availability of FPD1050SOT89
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |