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IDT74SSTU32865 28-BIT 1:2 REGISTERED BUFFER WITH PARITY
COMMERCIAL TEMPERATURE RANGE
28-BIT 1:2 REGISTERED BUFFER WITH PARITY
IDT74SSTU32865
FEATURES:
* * * * * * *
1.8V Operation SSTL_18 style clock and data inputs Differential CLK input Control inputs compatible with LVCMOS levels Flow-through architecture for optimum PCB design Latch-up performance exceeds 100mA ESD >2000V per MIL-STD-883, Method 3015; >200V using machine model (C = 200pF, R = 0) * Available in 160-pin CTBGA package
DESCRIPTION:
APPLICATIONS:
* Along with CSPU877/A/D DDR2 PLL, provides complete solution for DDR2 DIMMs * Optimized for DDR2-400/533 (PC2-3200/4300) JEDEC Raw Card D
The SSTU32865 is a 28-bit 1:2 configurable registered buffer designed for 1.7V to 1.9V VDD operation. All clock and data inputs are compatible with the JEDEC standard for SSTL_18. The control inputs are LVCMOS. All outputs are 1.8V CMOS drivers that have been optimized to drive the DDR2 DIMM load. The SSTU32865 operates from a differential clock (CLK and CLK). Data are registered at the crossing of CLK going high and CLK going low. This device supports low-power standby operation. When the reset input (RESET) is low, the differential input receivers are disabled, and undriven (floating) data, clock, and reference voltage (VREF) inputs are allowed. In addition, when RESET is low all registers are reset, and all outputs are forced low. The LVCMOS RESET and Cx inputs must always be held at a valid logic high or low level. To ensure defined outputs from the register before a stable clock has been supplied, RESET must be held in the low state during power up. In the DDR2 DIMM application, RESET is specified to be completely asynchronous with respect to CLK and CLK. Therefore, no timing relationship can be guaranteed between the two. When entering reset, the register will be cleared and the outputs will be driven low quickly, relative to the time to disable the differential input receivers. However, when coming out of a reset, the register will become active quickly, relative to the time to enable the differential input receivers. As long as the data inputs are low, and the clock is stable during the time from the low-to-high transition of RESET until the input receivers are fully enabled, the design of the SSTU32865 must ensure that the outputs will remain low, thus ensuring no glitches on the outputs. The device monitors both DCS0 and DCS1 inputs and will gate the Qn outputs from changing states when both DCS0 and DCS1 are high. If either DCS0 and DCS1 input is low, the Qn outputs will function normally. The RESET input has priority over the DCS0 and DCS1 control and will force the Qn outputs low and the PYTERR output high. If the DCS-control functionality is not desired, then the CSGateEnable input can be hard-wired to ground, in which case the set-up time requirement for DCS would be the same as for the other D data inputs. The SSTU32865 includes a parity checking function. The SSTU32865 accepts a parity bit from the memory controller at its input pin PARIN, compares it with the data received on the D-inputs, and indicates whether a parity error has occured on its open-drain PYTERR pin (active low).
COMMERCIAL TEMPERATURE RANGE
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c 2005 Integrated Device Technology, Inc.
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
APRIL 2005
DSC-6493/14
IDT74SSTU32865 28-BIT 1:2 REGISTERED BUFFER WITH PARITY
COMMERCIAL TEMPERATURE RANGE
FUNCTIONAL BLOCK DIAGRAM (1:2)
(CS ACTIVE) VREF
PARIN
D
Q 22
PARITY GENERATOR AND CHECKER
PYTERR
R Q0A D0 D Q Q0B R Q21A D21 D Q Q21B R QCS0A DCS0 D Q QCS0B R CSGateEN QCS1A DCS1 D Q QCS1B R QCKE0A, QCKE1A
DCKE0, DCKE1
2
D
Q
2
R
QCKE0B, QCKE1B QODT0A, QODT1A
DODT0, DODT1
2
D
Q
2
R RESET
QODT0B, QODT1B
CLK CLK
2
IDT74SSTU32865 28-BIT 1:2 REGISTERED BUFFER WITH PARITY
COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATION
1 A
VREF
2
NC
3
PARIN
4
NC
5
NC
6
7
8
Q21A
9
Q19A
10
Q18A
11
Q17B
12
Q17A
QCKE1A QCKE0A
B
D1
D2
NC
NC
NC
QCKE1B QCKE0B
Q21B
Q19B
Q18B
QODT0B
QODT0A
C
D3
D4
QODT1B
QODT1A
D
D6
D5
VDDL
GND
NC
NC
GND
GND
Q20B
Q20A
E
D7
D8
VDDL
GND
VDDL
VDDR
GND
GND
Q16B
Q16A
F
D11
D9
VDDL
GND
VDDR
VDDR
Q1B
Q1A
G
D18
D12
VDDL
GND
VDDR
VDDR
Q2B
Q2A
H
CSGate EN CLK
D15
VDDL
GND
GND
GND
Q5B
Q5A
J
DCS0
GND
GND
VDDR
VDDR
QCS0B QCS0A
K
CLK
DCS1
VDDL
VDDL
GND
GND
QCS1B QCS1A
L
RESET
D14
GND
GND
VDDR
VDDR
Q6B
Q6A
M N
D0
D10
GND
GND
GND
GND
Q10B
Q10A
D17
D16
VDDL
VDDL
VDDR
VDDR
Q9B
Q9A
P
D19
D21
GND
VDDL
VDDL
VDDR
VDDR
GND
Q11B
Q11A
R
D13
D20
GND
VDDL
VDDL
GND
GND
GND
Q15B
Q15A
T
DODT1 DODT0
Q14B
Q14A
U
DCKE0 DCKE1
MCL
PYTERR
MCH
Q3B
Q12B
Q7B
Q4B
Q13B
Q0B
Q8B
V
VREF
MCL
MCL
NC
MCH
Q3A
Q12A
Q7A
Q4A
Q13A
Q0A
Q8A
MCL denotes a pin that Must be Connected LOW. MCH denotes a pin that Must be Connected HIGH.
160-BALL CTBGA TOP VIEW
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IDT74SSTU32865 28-BIT 1:2 REGISTERED BUFFER WITH PARITY
COMMERCIAL TEMPERATURE RANGE
160 BALL CTBGA PACKAGE ATTRIBUTES
Top Mark
1
2
3
4
5
6
7
8
9
10 11 12
12 11 10
9
8
7
6
5
4
3
2
1
A B C D E F G H J K L M N P R T U
A B C D E F G H J K L M N P R T U V
V
TOP VIEW
BOTTOM VIEW
SIDE VIEW
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IDT74SSTU32865 28-BIT 1:2 REGISTERED BUFFER WITH PARITY
COMMERCIAL TEMPERATURE RANGE
FUNCTION TABLE (EACH FLIP-FLOP) (1)
Inputs CSGate RESET H H H H H H H H H H H H H H H L DCS0 L L L L L L H H H H H H H H H X or Floating DCS1 L L L H H H L L L H H H H H H X or Floating Enable X X X X X X X X X L L L H H H X or Floating CLK L or H L or H L or H L or H L or H X or Floating CLK L or H L or H L or H L or H L or H X or Floating Dn, DODTn, DCKEn L H X L H X L H X L H X L H X X or Floating Qn L H Q0(2) L H Q0
(2)
Outputs QCS L L Q0(2) L L Q0
(2)
QODT, QCKE L H Q0(2) L H Q0(2) L H Q0(2) L H Q0(2) L H Q0(2) L
L H Q0
(2)
H H Q0
(2)
L H Q0
(2)
H H Q0
(2)
Q0(2) Q0(2) Q0(2) L
H H Q0(2) L
NOTES: 1. H = HIGH Voltage Level L = LOW Voltage Level X = Don't Care = LOW to HIGH = HIGH to LOW 2. Output level before the indicated steady-state conditions were established.
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IDT74SSTU32865 28-BIT 1:2 REGISTERED BUFFER WITH PARITY
COMMERCIAL TEMPERATURE RANGE
PARITY AND STANDBY FUNCTION TABLE(1)
Inputs RESET H H H H H H H H H H L DCS0 L L L L H H H H H X X or Floating DCS1 H H H H L L L L H X X or Floating CLK L or H X or Floating CLK L or H X or Floating of Inputs = H (D0 - D21) Even Odd Even Odd Even Odd Even Odd X X X or Floating PARIN(2) L L H H L L H H X X X or Floating Output PYTERR(3) H L L H H L L H PYTERR0(4) PYTERR0(4) H
NOTES: 1. H = HIGH Voltage Level L = LOW Voltage Level X = Don't Care = LOW to HIGH = HIGH to LOW 2. PARIN arrives one clock cycle after the data to which it applies 3. This transition assumes PTYERR is HIGH at the crossing of CLK going HIGH and CLK going LOW. If PTYERR is LOW, it stays latched LOW for two clock cycles, or until RESET is driven LOW. 4. Output level before the indicated steady-state conditions were established.
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IDT74SSTU32865 28-BIT 1:2 REGISTERED BUFFER WITH PARITY
COMMERCIAL TEMPERATURE RANGE
REGISTER TIMING
n-1 CLK CLK tSU Dn tSU PARIN tPDM, tPDMSS Qn tH tH n n +1 n+2 n+3 n+4 n+5
tPDM PTYERR
tPDH
PARITY LOGIC DIAGRAM
Dn
22 22
D
Q
QnA
QnB
D
D
LATCHING AND (1) RESET FUNCTION
PYTERR
PARIN
D
CLOCK
NOTE: 1. This function holds the error for two cycles. See REGISTER TIMING diagram.
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IDT74SSTU32865 28-BIT 1:2 REGISTERED BUFFER WITH PARITY
COMMERCIAL TEMPERATURE RANGE
ABSOLUTE MAXIMUM RATINGS (1)
Symbol VDD VI
(2,3)
Description Supply Voltage Range Input Voltage Range Output Voltage Range Input Clamp Current VI < 0 VI > VDD
Max. -0.5 to 2.5 -0.5 to 2.5 -0.5 to VDD +0.5 50 50 50 100 -65 to +150
Unit V V V mA mA mA mA C
VO(2,3) IIK IOK IO VDD TSTG
Output Clamp Current VO < 0 VO > VDD Continuous Output Current, VO = 0 to VDD Continuous Current through each VDD or GND Storage Temperature Range
NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. The input and output negative voltage ratings may be exceeded if the ratings of the I/P and O/P clamp current are observed. 3. This value is limited to 2.5V maximum.
TIMING REQUIREMENTS OVER RECOMMENDED OPERATING FREE-AIR TEMPERATURE RANGE
VDD = 1.8V 0.1V Symbol fCLOCK tw tACT(1,2) tINACT(1,3) tSU tH Parameter Clock Frequency Pulse Duration, CLK, CLK HIGH or LOW Differential Inputs Active Time Differential Inputs Inactive Time Setup Time Hold Time DCSn before CLK, CLK Data, PARIN, DODT, and DCKE before CLK, CLK Data, DCSn, PARIN, DCKE, and DODT after CLK, CLK
NOTES: 1. This parameter is not production tested. 2. Data and VREF inputs must be low a minimum time of tACT max, after RESET is taken HIGH. 3. Data, VREF, and clock inputs must be held at valid levels (not floating) a minimum time of tINACT max, after RESET is taken LOW.
Min. -- 1 -- -- 0.7 0.5 0.5
Max. 270 -- 10 15 -- -- --
Unit MHz ns ns ns ns ns
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IDT74SSTU32865 28-BIT 1:2 REGISTERED BUFFER WITH PARITY
COMMERCIAL TEMPERATURE RANGE
TERMINAL FUNCTIONS
Signal Group Terminal Name Type SSTL_18 SSTL_18 SSTL_18 Description DRAM function pins not associated with Chip Select DRAM inputs, re-driven only when Chip Select is LOW DRAM Chip Select signals. These pins initiate DRAM address/command decodes, and as such at least one will be LOW when a valid address/command is present. The register can be programmed to re-drive all D-inputs only (CSGateEN HIGH) when at least one Chip Select input is LOW. Outputs of the register, valid after the specified clock count and immediately following a rising edge of the clock Ungated Inputs Chip Select Gated Inputs Chip Select Inputs DCKE0, DCKE1 DODT0, DODT1 D0:D21 DCS0, DCS1
Re-Driven Outputs
Q0A:Q21A Q0B:Q21B QCS0-1A, B QCKE0-1A, B QODT0-1A, B PARIN PTYERR
SSTL_18
Parity Input Parity Error Output
SSTL_18 Open Drain
Input parity is received on pin PARIN, and should maintain odd parity across the D0:D21 inputs, at the rising edge of the clock When LOW, this output indicates that a parity error was identified associated with the address and/or command inputs. PTYERR will be active for two clock cycles, and delayed by an additional clock cycle for compatibility with final parity out timing on the industry-standard DDR-II register with parity (in JEDEC definition). Chip Select Gate Enable. When HIGH, the D0:D21 inputs will be latched only when at least one Chip Select input is LOW during the rising edge of the clock. When LOW, the D0:D21 inputs will be latched and redriven on every rising edge of the clock. Differential master clock input pair to the register. The register operation is triggered by a rising edge on the positive clock input (CLK). Must be connected to a Logic LOW or HIGH. Asynchronous Reset Input. When LOW, it causes a reset of the internal latches, thereby forcing the outputs LOW. RESET also resets the PTYERR signal. Input reference voltage for SSTL_18 inputs. Two pins (internally tied together) are used for increased reliability.
Program Inputs
CSGateEN
1.8V LVCMOS
Clock Inputs Miscellaneous Inputs
CLK, CLK MCL, MCH RESET VREF
SSTL_18
1.8V LVCMOS 0.9V nominal
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IDT74SSTU32865 28-BIT 1:2 REGISTERED BUFFER WITH PARITY
COMMERCIAL TEMPERATURE RANGE
OPERATING CHARACTERISTICS, TA = 25C (1,2)
Symbol VDD VREF VTT VI VIH VIL VIH VIL VIH VIL VICR VID IOH IOL TA Parameter Supply Voltage Reference Voltage Termination Voltage Input Voltage AC High-Level Input Voltage AC Low-Level Input Voltage DC High-Level Input Voltage DC Low-Level Input Voltage High-Level Input Voltage Low-Level Input Voltage Common Mode Input Voltage Differential Input Voltage High-Level Output Current Low-Level Output Current Operating Free-Air Temperature Data Inputs Data Inputs Data Inputs Data Inputs RESET, Cx RESET, Cx CLK, CLK CLK, CLK Min. 1.7 0.49 * VDD VREF- 40mV 0 VREF+ 250mV -- VREF+ 125mV -- 0.65 * VDD -- 0.675 600 -- -- 0 Typ. -- 0.5 * VDD VREF -- -- -- -- -- -- -- -- -- -- -- -- Max. 1.9 0.51 * VDD VREF+ 40mV VDD -- VREF- 250mV -- VREF- 125mV -- 0.35 * VDD 1.125 -- -8 8 70 Unit V V V V V V V V V V V mV mA mA C
NOTES: 1. The RESET and Cx inputs of the device must be held at valid levels (not floating) to ensure proper device operation. 2. The differential inputs must not be floating unless RESET is LOW.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = 0C to +70C, VDD = 1.8V 0.1V
Symbol VOH VOL II IDD IDDD All Inputs Static Standby Static Operating Dynamic Operating (Clock Only) Dynamic Operating (Per Each Data Input) Dn CI DCSn and CSGateENable CLK and CLK RESET VICR = 0.9V, VID = 600mV, VDD = 1.8V VI = VDD or GND, VDD = 1.8V Parameter Test Conditions VDD = 1.7V to 1.9V, IOH = - 6 mA VDD = 1.7V to 1.9V, IOL = 6 mA VI = VDD or GND IO = 0, VDD = 1.9V, RESET = GND IO = 0, VDD = 1.9V, RESET = VDD, VI = VIH (AC) or VIL (AC) IO = 0, VDD = 1.8V, RESET = VDD, VI = VIH (AC) or VIL (AC), CLK and CLK Switching 50% Duty Cycle. IO = 0, VDD = 1.8V, RESET = VDD, VI = VIH (AC) or VIL (AC), CLK and CLK Switching at 50% Duty Cycle. One Data Input Switching at Half Clock Frequency, 50% Duty Cycle. VI = VREF 250mV, VDD = 1.8V 2.5 4 4 2 -- -- -- -- 3.5 6 6 6 pF 1:2 Mode -- -- -- 1:1 Mode -- -- -- A/Clock MHz/Data Input Min. 1.2 -- -- -- -- -- Typ. -- -- -- -- -- -- Max. -- 0.5 5 200 40 -- Unit V V A A mA A/Clock MHz
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IDT74SSTU32865 28-BIT 1:2 REGISTERED BUFFER WITH PARITY
COMMERCIAL TEMPERATURE RANGE
SWITCHING CHARACTERISTICS OVER RECOMMENDED FREE-AIR OPERATING RANGE (UNLESS OTHERWISE NOTED) (1)
VDD = 1.8V 0.1V Symbol fMAX tPDM(2) tLH tHL tPLH tPDMSS(2,3) tRPHL dV/dt_r dV/dt_f dV/dt_(4) CLK and CLK to Q LOW to HIGH Delay, CLK and CLK to PYTERR HIGH to LOW Delay, CLK and CLK to PYTERR LOW to HIGH Propagation Delay, RESET to PYTERR CLK and CLK to Q (simultaneous switching) RESET to Q Output slew rate from 20% to 80% Output slew rate from 20% to 80% Output slew rate from 20% to 80% Parameter Min 270 1.41 1.2 1 -- -- -- 1 1 -- Max. -- 2.15 3 3 3 2.35 3 4 4 1 Unit MHz ns ns ns ns ns ns V/ns V/ns V/ns
NOTES: 1. See TEST CIRCUITS AND WAVEFORMS. 2. Includes 350ps of test load transmission line delay. 3. This parameter is not production tested. 4. Difference between dV/dt_r (rising edge rate) and dV/dt_f (falling edge rate).
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IDT74SSTU32865 28-BIT 1:2 REGISTERED BUFFER WITH PARITY
COMMERCIAL TEMPERATURE RANGE
TEST CIRCUITS AND WAVEFORMS (VDD = 1.8V 0.1V)
VDD
DUT
TL = 50 CLK Inputs CLK CLK Test Point RL = 100 Test Point LVCMOS RESET Input tINACT IDD 10% VDD VDD/2 VDD/2 0V tACT 90% Output CLK CLK tPLH VTT VICR Out CL = 30 pF TL = 350ps, 50
RL = 1K Test Point RL = 1K
Load Circuit
VICR tPHL
VID
VOH VTT VOL
Voltage and Current Waveforms Inputs Active and Inactive Times
tW Input VICR VICR VID
Voltage Waveforms - Propagation Delay Times
Voltage Waveforms - Pulse Duration
LVCMOS RESET Input
VIH VDD/2 VIL tRPHL VOH
Output CLK VICR CLK tSU Input VREF tH VIH VREF VIL VID
VTT VOL
Voltage Waveforms - Propagation Delay Times
Voltage Waveforms - Setup and Hold Times
NOTES: 1. CL includes probe and jig capacitance. 2. IDD tested with clock and data inputs held at VDD or GND, and IO = 0mA 3. All input pulses are supplied by generators having the following characteristics: PRR 10MHz, ZO = 50, input slew rate = 1 V/ns 20% (unless otherwise specified). 4. The outputs are measured one at a time with one transition per measurement. 5. VTT = VREF = VDD/2 6. VIH = VREF + 250mV (AC voltage levels) for differential inputs. VIH = VDD for LVCMOS input. 7. VIL = VREF - 250mV (AC voltage levels) for differential inputs. VIL = GND for LVCMOS input. 8. VID = 600mV. 9. tPLH and tPHL are the same as tPDM.
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IDT74SSTU32865 28-BIT 1:2 REGISTERED BUFFER WITH PARITY
COMMERCIAL TEMPERATURE RANGE
TEST CIRCUITS AND WAVEFORMS (VDD = 1.8V 0.1V)
VDD
DUT
Out
RL = 50 Test Point
CL = 10 pF
Load Circuit: High-to-Low Slew-Rate
Output 80%
VOH
20% dv_f dt_f VOL
Voltage Waveforms: High-to-Low Slew-Rate
DUT
Out CL = 10 pF Test Point RL = 50
Load Circuit: Low-to-High Slew-Rate
dt_r dv_r 80% VOH
20% Output VOL
Voltage Waveforms: Low-to-High Slew-Rate
NOTES: 1. CL includes probe and jig capacitance. 2. All input pulses are supplied by generators having the following characteristics: PRR 10MHz, ZO = 50, input slew rate = 1 V/ns 20% (unless otherwise specified).
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IDT74SSTU32865 28-BIT 1:2 REGISTERED BUFFER WITH PARITY
COMMERCIAL TEMPERATURE RANGE
TEST CIRCUITS AND WAVEFORMS (VDD = 1.8V 0.1V)
VDD
DUT
Out
RL = 1K Test Point
CL = 10 pF
Load Circuit: High-to-Low Slew-Rate
LVCMOS RESET Input tPLH
VDD VDD/2 0V
VOH Output Waveform 2 0.15V 0V
Voltage Waveforms: Open Drain Output Low-to-High Transition Time (with Respect to RESET Input)
Timing Inputs
VICR tHL
VICR
VI(PP)
Output Waveform 1
VDD VDD/2 VOL
Voltage Waveforms: Open Drain Output High-to-Low Transition Time (with Respect to Clock Inputs)
Timing Inputs
VICR tHL
VICR
VI(PP)
VOH Output Waveform 2 0.15V 0V
Voltage Waveforms: Open Drain Output Low-to-High Transition Time (with Respect to Clock Inputs)
NOTES: 1. CL includes probe and jig capacitance. 2. All input pulses are supplied by generators having the following characteristics: PRR 10MHz, ZO = 50, input slew rate = 1 V/ns 20% (unless otherwise specified).
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IDT74SSTU32865 28-BIT 1:2 REGISTERED BUFFER WITH PARITY
COMMERCIAL TEMPERATURE RANGE
ORDERING INFORMATION
IDT XX XXX XX SSTU32 Temp. Range Device Type Package
BKG Thin Profile, Fine Pitch, Ball Grid Array - Green
865
28-Bit 1:2 Registered Buffer with Parity
74
0C to +70C
CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138
for SALES: 800-345-7015 or 408-284-8200 fax: 408-284-2775 www.idt.com
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