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EM620FV8BS Series
Low Power, 256Kx8 SRAM
Document Title
256K x8 bit Low Power and Low Voltage Full CMOS Static RAM
Revision History
Revision No.
0.0 0.1
History
Initial Draft 0.1 Revision Revised VOH(2.2v to 2.4v),tOH(15ns to 10ns), tOE-55(30ns to 25ns), tWP-55(45ns to 40ns), tWP-70(55ns to 50ns), tWHZ-70(25ns to 20ns), ICC(2mA to 3mA), ICC1(2mA to 3mA) VIH level change from 2.0V to 2.2V Fix typo error
Draft Date
June 28, 2007 July 2, 2007
Remark
0.2 0.3
0.2 Revision 0.3 Revision
Aug. 16, 2007 Nov. 13, 2007
4F Korea Construction Financial Cooperative B/D, 301-1 Yeon-Dong, Jeju-Si, Jeju-Do, Rep.of Korea Tel : +82-64-740-1712 Fax : +82-64-740-1749~1750 / Homepage : www.emlsi.com
Emerging Memory & Logic Solutions Inc.
Zip Code : 690-719
The attached data sheets are provided by EMLSI reserve the right to change the specifications and products. EMLSI will answer to your questions about device. If you have any questions, please contact the EMLSI office. 1
EM620FV8BS Series
Low Power, 256Kx8 SRAM
256K x8 Bit Low Power and Low Voltage CMOS Static RAM
FEATURES - Process Technology : 0.15mm Full CMOS - Organization :256K x8 - Power Supply Voltage => EM620FV8BS Series : 2.7V~3.6V - Low Data Retention Voltage : 1.5V (MIN) - Three state output and TTL Compatible - Packaged product designed for 45/55/70ns - Package Type: 32-sTSOP1 PRODUCT FAMILY
Product Family EM620FV8BS-45LF EM620FV8BS-55LF EM620FV8BS-70LF Operating Temperature Industrial (-40 ~ 85oC) Industrial (-40 ~ 85oC) Industrial (-40 ~ 85oC) Power Dissipation Vcc Range Speed Standby (ISB1, Typ.) 1 A 1 A 1 A Operating (ICC1.Max) 3mA 3mA 3mA PKG Type
GENERAL DESCRIPTION The EM620FV8BS series are fabricated by EMLSI's advanced full CMOS process technology. The families support industrial temperature range and Chip Scale Package for user flexibility of system design. The families also supports low data retention voltage for battery back-up operation with low data retention current. The EM620FV8BS series are available in KGD, JEDEC standard 32 pin 8mm x 13.4mm sTSOP package.
2.7V~3.6V 2.7V~3.6V 2.7V~3.6V
45ns 55ns 70ns
32-sTSOP 32-sTSOP 32-sTSOP
PIN DESCRIPTION
FUNCTIONAL BLOCK DIAGRAM
Pre-charge Circuit
A11 A9 A8 A13 WE CS2 A15 VCC A17 A16 A14 A12 A7 A6 A5 A4
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
EM620FV8BS-45LF
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
OE A10 CS1 I/O 7 I/O 6 I/O 5 I/O 4 I/O 3 VSS I/O 2 I/O 1 I/O 0 A0 A1 A2 A3
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9
VCC VSS
Row Select
Memory Array 1024 x 2048
I/O0 ~ I/O7
Data Cont
I/O Circuit Column Select
A10 A11 A12 A13 A14 A15 A16 A17
Name CS1,CS2 OE WE A0~A17 I/O0~I/O7
Function Chip select inputs Output Enable input Write Enable input Address Inputs Data Inputs/Outputs
Name Vcc Vss NC
Function Power Supply Ground No Connection
WE OE CS1 CS2
Control Logic
2
EM620FV8BS Series
Low Power, 256Kx8 SRAM ABSOLUTE MAXIMUM RATINGS * Parameter
Voltage on Any Pin Relative to Vss Voltage on Vcc supply relative to Vss Power Dissipation Operating Temperature
Symbol
VIN, VOUT VCC PD TA
Minimum
-0.2 to 4.0V -0.2 to 4.0V 1.0 -40 to 85
Unit
V V W
o
C
* Stresses greater than those listed above "Absolute Maximum Ratings" may cause permanent damage to the device. Functional oper-
ation should be restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
FUNCTIONAL DESCRIPTION
CS1 H X L L L CS2 X L H H H OE X X H L X WE X X H H L I/O0-7 High-Z High-Z High-Z Data Out Data In Mode Deselected Deselected Output Disabled Read Write Power Stand by Stand by Active Active Active
Note: X means don't care. (Must be low or high state)
3
EM620FV8BS Series
Low Power, 256Kx8 SRAM RECOMMENDED DC OPERATING CONDITIONS 1)
Parameter Supply voltage Ground Input high voltage Input low voltage
1. 2. 3. 4.
Symbol VCC VSS VIH VIL
Min 2.7 0 2.2 -0.23)
Typ 3.3 0 -
Max 3.6 0 VCC + 0.22) 0.6
Unit V V V V
TA= -40 to 85oC, otherwise specified Overshoot: VCC +2.0 V in case of pulse width < 20ns Undershoot: -2.0 V in case of pulse width < 20ns Overshoot and undershoot are sampled, not 100% tested.
CAPACITANCE1) (f =1MHz, TA=25oC)
Item Input capacitance Input/Ouput capacitance
1. Capacitance is sampled, not 100% tested.
Symbol CIN CIO
Test Condition VIN=0V VIO=0V
Min -
Max 8 10
Unit pF pF
DC AND OPERATING CHARACTERISTICS
Parameter Input leakage current Output leakage current Operating power supply Symbol ILI ILO ICC ICC1 Average operating current ICC2 VOL VOH ISB
VIN=VSS to VCC CS1=VIH or CS2=VIL or OE=VIH or WE=VIL VIO=VSS to VCC IIO=0mA, CS1=VIL, CS2=WE=VIH, VIN=VIH or VIL Cycle time=1s, 100% duty, IIO=0mA, CS1<0.2V, CS2>VCC-0.2V, VIN<0.2V or VIN>VCC-0.2V Cycle time = Min, IIO=0mA, 100% duty, CS1=VIL, CS2=VIH, VIN=VIL or VIH IOL = 2.1mA IOH = -1.0mA CS1=VIH, CS2=VIL, Other inputs=VIH or VIL CS1>VCC-0.2V, CS2>VCC-0.2V (CS1 controlled) or 0VTest Conditions
Min -1 -1 45ns 55ns 70ns 2.4 -
Typ -
Max 1 1 3 3 35 30 25 0.4 0.3
Unit uA uA mA mA
mA
Output low voltage Output high voltage Standby Current (TTL)
V V mA
Standby Current (CMOS)
ISB1
LF
-
11)
10
uA
NOTES
1. Typical values are measured at Vcc=3.3V, TA=25oC and not 100% tested. 4
EM620FV8BS Series
Low Power, 256Kx8 SRAM
VTM3) R12)
AC OPERATING CONDITIONS
Test Conditions (Test Load and Test Input/Output Reference) Input Pulse Level : 0.4 to 2.2V Input Rise and Fall Time : 5ns Input and Output reference Voltage : 1.5V Output Load (See right) : CL1) = 100pF + 1 TTL (70ns) CL1) = 30pF + 1 TTL (45ns/55ns) 1. Including scope and Jig capacitance 2. R1=3070 ohm, R2=3150 ohm 3. VTM=2.8V 4. CL = 5pF + 1 TTL (measurement with tLZ1,2, tHZ1,2, tOLZ, tOHZ, tWHZ)
CL1)
R22)
READ CYCLE (Vcc = 2.7V to 3.6V, Gnd = 0V, TA = -40oC to +85oC)
Parameter
Read cycle time Address access time Chip select to output Output enable to valid output Chip select to low-Z output Output enable to low-Z output Chip disable to high-Z output Output disable to high-Z output Output hold from address change
Symbol
tRC tAA tCO1, tCO2 tOE tLZ1, tLZ2 tOLZ tHZ1, tHZ2 tOHZ tOH
45ns Min 45 10 5 0 0 10 Max 45 45 25 20 15 Min 55 10 5 0 0 10
55ns Max 55 55 25 20 20 Min 70 10 5 0 0 10
70ns Max 70 70 35 25 25 -
Unit
ns ns ns ns ns ns ns ns ns
WRITE CYCLE (Vcc = 2.7V to 3.6V, Gnd = 0V, TA = -40oC to +85oC)
Parameter
Write cycle time Chip select to end of write Address setup time Address valid to end of write Write pulse width Write recovery time Write to ouput high-Z Data to write time overlap Data hold from write time End write to output low-Z
Symbol
tWC tCW1, tCW2 tAS tAW tWP tWR tWHZ tDW tDH tOW
45ns Min 45 45 0 45 35 0 0 25 0 5 Max 15 55 45 0 45 40 0 0 25 0 5
55ns Min Max 20 Min 70 60 0 60 50 0 0 30 0 5
70ns Max 20
Unit
ns ns ns ns ns ns ns ns
-
ns ns
5
EM620FV8BS Series
Low Power, 256Kx8 SRAM
TIMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS1=OE=VIL, CS2=WE=VIH)
tRC Address tAA tOH Data Out
Previous Data Valid Data Valid
TIMING WAVEFORM OF READ CYCLE(2) (WE = VIH)
tRC Address tAA CS1 tCO1,2 tOH
CS2 tOE OE tOLZ
Data Valid
tHZ1,2
tOHZ tWHZ
Data Out
High-Z
tLZ1,2
NOTES (READ CYCLE) 1. tHZ 1,2and tOHZ are defined as the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. At any given temperature and voltage condition, tHZ1,2(Max.) is less than tLZ1,2(Min.) both for a given device and from device to device interconnection.
6
EM620FV8BS Series
Low Power, 256Kx8 SRAM
TIMING WAVEFORM OF WRITE CYCLE(1) (WE CONTROLLED)
tWC Address tCW1,2(2) CS1 tWR(4)
CS2 tAW tWP(1) WE tAS(3) Data in High-Z tWHZ Data out Data Undefined tDW
Data Valid
tDH High-Z tOW
TIMING WAVEFORM OF WRITE CYCLE(2) (CS1 CONTROLLED)
tWC Address tAS(3) CS1 tCW1,2(2) tWR(4)
CS2
tAW tWP(1)
WE tDW Data in High-Z
Data Valid
tDH
Data out
High-Z
7
EM620FV8BS Series
Low Power, 256Kx8 SRAM
TIMING WAVEFORM OF WRITE CYCLE(3) (CS2 CONTROLLED)
tWC Address tCW1,2(2) CS1 tAS(3) CS2 tAW tWP(1) WE tDW Data in Data out High-Z
Data Valid
tWR(4)
tDH
High-Z
NOTES (WRITE CYCLE) 1. A write occurs during the overlap(tWP) of low CS1, a high CS2 and low WE. A write begins at the latest transition among CS1 goes low, CS2 goes high and WE goes low. A write ends at the earliest transition among CS1 goes high, CS2 goes low and WE goes high. The tWP is measured from the beginning of write to the end of write. 2. tCW is measured from the CS1 going low or CS2 going high to end of write. 3. tAS is measured from the address valid to the beginning of write. 4. tWR is measured from the end or write to the address change. tWR applied in case a write ends as CS1 or WE going high or CS2 going low.
8
EM620FV8BS Series
Low Power, 256Kx8 SRAM DATA RETENTION CHARACTERISTICS
Parameter
VCC for Data Retention Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time NOTES
Symbol
VDR IDR tSDR tRDR
Test Condition
ISB1 Test Condition (Chip Disabled) 1) VCC=1.5V, ISB1 Test Condition (Chip Disabled) 1) See data retention wave form
Min
1.5 0 tRC
Typ2)
0.5 -
Max
3.6 5.0 -
Unit
V A ns
1. See the ISB1 measurement condition of data sheet page 4. 2. Typical value is measured at TA=25oC and not 100% tested.
DATA RETENTION WAVE FORM
tSDR Vcc 3.0V
Data Retention Mode
tRDR
2.2V VDR CS1 GND Vcc 3.0V CS2 VDR 0.4V
CS2 < 0.2V CS1 > Vcc-0.2V
Data Retention Mode
tSDR
tRDR
GND
9
EM620FV8BS Series
Low Power, 256Kx8 SRAM PACKAGE DIMENSIONS
32Pin - sTSOP Type1
Unit : millimeters/Inches
+0.10 - 0.05 +0.004 0.008 - 0.002 #1
0.20
13.40 +/-0.20 0.528 +/- 0.008
0.10 0.004 MAX
#32
( 0.25 ) 0.010 8.40 0.331MAX 0.50 0.0197 8.00 0.315
#16
#17
0.25 TYP 0.010
1.00 +/-0.10 0.039 +/- 0.004 11.80 +/-0.10 0.465 +/- 0.004 0.15
+0.10 - 0.05 +0.004 0.006 - 0.002
0.05 0.002 MIN
1.20 MAX 0.047
0~8 0.45~0.75 0.018~0.030 0.50 ( 0.020 )
10
EM620FV8BS Series
Low Power, 256Kx8 SRAM
SRAM PART CODING SYSTEM
EM X XX X X X XX X X - XX XX
1. EMLSI Memory 2. Product Type 3. Density 4. Function 5. Technology 6. Operating Voltage
1. Memory Component EM --------------------- Memory 2. Product Type 6 ------------------------ SRAM 3. Density 1 ------------------------- 1M 2 ------------------------- 2M 4 ------------------------- 4M 8 ------------------------- 8M 4. Function 0 ----------------------- Dual CS 1 ----------------------- Single CS 2 ----------------------- Multiplexed 3 ------------- Single CS / LBB, UBB(tBA=tOE) 4 ------------- Single CS / LBB, UBB(tBA=tCO) 5 ------------- Dual CS / LBB, UBB(tBA=tOE) 6 ------------- Dual CS / LBB, UBB(tBA=tCO) 5. Technology F ------------------------- Full CMOS 6. Operating Voltage T ------------------------- 5.0V V ------------------------- 3.3V U ------------------------- 3.0V S ------------------------- 2.5V R ------------------------- 2.0V P ------------------------- 1.8V
11. Power 10. Speed
9. Package 8. Generation 7. Organization
7. Organization 8 ---------------------- x8 bit 16 ---------------------- x16 bit 8. Generation Blank ----------------- 1st generation A ----------------------- 2nd generation B ----------------------- 3rd generation C ----------------------- 4th generation D ----------------------- 5th generation E ----------------------- 6th generation F ----------------------- 7th generation G ---------------------- 8th generation 9. Package Blank ---------------- KGD, 48&36FpBGA S ---------------------- 32 sTSOP1 T ---------------------- 32 TSOP1 U ---------------------- 44 TSOP2 V ---------------------- 32 SOP 10. Speed 45 ---------------------55 ---------------------70 ---------------------85 ---------------------10 ---------------------12 ---------------------45ns 55ns 70ns 85ns 100ns 120ns
11. Power LL ---------------------- Low Low Power LF ---------------------- Low Low Power(Pb-Free & Green) L ---------------------- Low Power S ---------------------- Standard Power
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