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| Low Gain Drift Precision Instrumentation Amplifier AD8228 FEATURES Easy to use Pin strappable gains of 10 and 100 Wide power supply range: 2.3 V to 18 V DC specifications (B Grade, G = 10) 2 ppm/C gain drift 0.02% gain error 50 V maximum input offset voltage 0.8 V/C maximum input offset drift 0.6 nA maximum input bias current 100 dB CMRR AC specifications 650 kHz, -3 dB bandwidth (G = 10) 2 V/s slew rate Low noise 8 nV/Hz, @ 1 kHz (G = 100) 0.3 V p-p from 0.1 Hz to 10 Hz (G = 100) CONNECTION DIAGRAM -IN 1 G1 2 G2 3 +IN 4 8 +VS 7 VOUT 6 REF TOP VIEW (Not to Scale) Figure 1. APPLICATIONS Weigh scales Industrial process controls Bridge amplifiers Precision data acquisition systems Medical instrumentation Strain gages Transducer interfaces Table 1. Instrumentation Amplifiers by Category General Purpose AD82201 AD8221 AD8222 AD82241 AD8228 1 Zero Drift AD82311 AD85531 AD85551 AD85561 AD85571 Military Grade AD620 AD621 AD524 AD526 AD624 Low Power AD6271 AD6231 07035-001 AD8228 5 -VS High Speed PGA AD8250 AD8251 AD8253 Rail-to-rail output. GENERAL DESCRIPTION The AD8228 is a high performance instrumentation amplifier with very high gain accuracy. Because all gain setting resistors are internal and laser trimmed, gain accuracy and gain drift are better than can be achieved with typical instrumentation amplifiers. Low voltage offset, low offset drift, low gain drift, high gain accuracy, and high CMRR make this part an excellent choice in applications that demand the best dc performance possible, such as bridge signal conditioning. The AD8228 operates on both single and dual supplies. Because the part can operate on supplies up to 18 V, it is well suited for applications where high common-mode input voltages are encountered. The AD8228 is available in 8-lead MSOP and SOIC packages. Performance is specified over the entire industrial temperature range of -40C to +85C for all grades. Furthermore, the AD8228 is operational from -40C to +125C. For a pin-compatible amplifier with similar specifications, but with a gain range of 1 to 1000, see the AD8221. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2008 Analog Devices, Inc. All rights reserved. AD8228 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Connection Diagram ....................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Gain = 10 ....................................................................................... 3 Gain = 100 ..................................................................................... 5 Absolute Maximum Ratings............................................................ 7 Thermal Resistance ...................................................................... 7 ESD Caution.................................................................................. 7 Pin Configuration and Function Descriptions............................. 8 Typical Performance Characteristics ............................................. 9 Theory of Operation ...................................................................... 16 Architecture ................................................................................ 16 Setting the Gain .......................................................................... 16 Common-Mode Input Voltage Range ..................................... 16 Reference Terminal .................................................................... 17 Layout .......................................................................................... 17 Input Protection ......................................................................... 18 Radio Frequency Interference (RFI) ........................................ 18 Applications Information .............................................................. 19 Differential Drive ....................................................................... 19 Precision Strain Gage................................................................. 19 Driving a Differential ADC ...................................................... 19 Outline Dimensions ....................................................................... 20 Ordering Guide .......................................................................... 21 REVISION HISTORY 7/08--Revision 0: Initial Version Rev. 0 | Page 2 of 24 AD8228 SPECIFICATIONS GAIN = 10 VS = 15 V, VREF = 0 V, TA = 25C, RL = 2 k, all specifications referred to input, unless otherwise noted. Table 2. Parameter COMMON-MODE REJECTION RATIO CMRR DC to 60 Hz with 1 k Source Imbalance CMRR at 2 kHz NOISE Voltage Noise Current Noise VOLTAGE OFFSET Offset Over Temperature Average TC Offset vs. Supply (PSR) INPUT CURRENT Input Bias Current Over Temperature Average TC Input Offset Current Over Temperature Average TC REFERENCE INPUT RIN IIN Voltage Range Gain to Output DYNAMIC RESPONSE Small Signal -3 dB Bandwidth Settling Time 0.01% Settling Time 0.001% Slew Rate GAIN Gain Error Gain Nonlinearity RL = 10 k RL = 2 k Gain vs. Temperature INPUT Input Impedance Differential Common Mode Input Operating Voltage Range 1 Over Temperature Input Operating Voltage Range1 Over Temperature Conditions (Gain = 10) VCM = -10 V to +10 V VCM = -10 V to +10 V VIN+ = VIN- = VREF = 0 V f = 1 kHz f = 0.1 Hz to 10 Hz f = 1 kHz f = 0.1 Hz to 10 Hz Referred to input, VS = 5 V to 15 V T = -40C to +85C T = -40C to +85C 104 120 0.5 T = -40C to +85C T = -40C to +85C T = -40C to +85C T = -40C to +85C 1 0.2 1 20 50 -VS 1 0.0001 650 6 9 2.5 0.07 3 3 1 10 10 10 3 3 1 1.5 2.0 0.6 0.8 Min 94 90 15 0.5 40 6 0.5 40 6 A Grade Typ Max Min 100 100 15 B Grade Typ Max Unit dB dB nV/Hz V p-p fA/Hz pA p-p 90 180 1.5 106 120 0.4 1 0.1 1 20 50 -VS 1 0.0001 650 6 9 2.5 50 100 0.8 V V V/C dB nA nA pA/C nA nA pA/C k A V V/V kHz s s V/s 0.6 1 0.4 0.6 VIN+ = VIN- = VREF = 0 V 60 +VS 60 +VS 10 V step 10 V step 2 VOUT = -10 V to +10 V 2 0.02 10 10 2 % ppm ppm ppm/C 100||2 100||2 VS = 2.3 V to 5 V T = -40C to +85C VS = 5 V to 18 V T = -40C to +85C -VS + 1.9 -VS + 2.0 -VS + 1.9 -VS + 2.0 +VS - 1.1 +VS - 1.2 +VS - 1.2 +VS - 1.2 -VS + 1.9 -VS + 2.0 -VS + 1.9 -VS + 2.0 100||2 100||2 +VS - 1.1 +VS - 1.2 +VS - 1.2 +VS - 1.2 G||pF G||pF V V V V Rev. 0 | Page 3 of 24 AD8228 Parameter OUTPUT Output Swing Over Temperature Output Swing Over Temperature Short-Circuit Current POWER SUPPLY Operating Range Quiescent Current Over Temperature TEMPERATURE RANGE Specified Performance Operating Range 2 1 Conditions (Gain = 10) RL = 10 k VS = 2.3 V to 5 V T = -40C to +85C VS = 5 V to 18 V T = -40C to +85C Min -VS + 1.1 -VS + 1.4 -VS + 1.2 -VS + 1.6 A Grade Typ Max +VS - 1.2 +Vs - 1.3 +VS - 1.4 +VS - 1.5 Min -VS + 1.1 -VS + 1.4 -VS + 1.2 -VS + 1.6 B Grade Typ Max +VS - 1.2 +VS - 1.3 +VS - 1.4 +VS - 1.5 Unit V V V V mA V mA mA C C 18 VS = 2.3 V to 18 V T = -40C to +85C -40 -40 2.3 0.85 1 18 1 1.2 +85 +125 2.3 18 18 1 1.2 +85 +125 0.85 1 -40 -40 Operating near the input voltage range limit may reduce the available output range. See Figure 10 and Figure 11 for the input common-mode range vs. output voltage. 2 See the Typical Performance Characteristics section for expected operation between 85C to 125C. Rev. 0 | Page 4 of 24 AD8228 GAIN = 100 VS = 15 V, VREF = 0 V, TA = 25C, RL = 2 k, all specifications referred to input, unless otherwise noted. Table 3. Parameter COMMON-MODE REJECTION RATIO CMRR DC to 60 Hz with 1 k Source Imbalance CMRR at 2 kHz NOISE Voltage Noise Current Noise VOLTAGE OFFSET Offset Over Temperature Average TC Offset vs. Supply (PSR) INPUT CURRENT Input Bias Current Over Temperature Average TC Input Offset Current Over Temperature Average TC REFERENCE INPUT RIN IIN Voltage Range Gain to Output DYNAMIC RESPONSE Small Signal -3 dB Bandwidth Settling Time 0.01% Settling Time 0.001% Slew Rate GAIN Gain Error Gain Nonlinearity RL = 10 k RL = 2 k Gain vs. Temperature INPUT Input Impedance Differential Common Mode Input Operating Voltage Range1 Over Temperature Input Operating Voltage Range1 Over Temperature Conditions (Gain = 100) VCM = -10 V to +10 V VCM = -10 V to +10 V VIN+ = VIN- = VREF = 0 V f = 1 kHz f = 0.1 Hz to 10 Hz f = 1 kHz f = 0.1 Hz to 10 Hz Referred to input, VS = 5 V to 15 V T = -40C to +85C T = -40C to +85C 118 140 0.5 T = -40C to +85C T = -40C to +85C T = -40C to +85C T = -40C to +85C 1 0.2 1 20 50 -VS 1 0.0001 110 13 15 2.5 0.1 5 15 1 15 45 10 5 15 1 1.5 2.0 0.6 0.8 Min 114 100 8 0.3 40 6 0.3 40 6 A Grade Typ Max Min 120 105 8 B Grade Typ Max Unit dB dB nV/Hz V p-p fA/Hz pA p-p 90 140 0.9 124 140 0.4 1 0.1 1 20 50 -VS 1 0.0001 110 13 15 2.5 50 80 0.5 V V V/C dB nA nA pA/C nA nA pA/C k A V V/V kHz s s V/s 0.6 1 0.4 0.6 VIN+ = VIN- = VREF = 0 V 60 +VS 60 +VS 10 V step 10 V step 2 VOUT = -10 V to +10 V 2 0.05 15 45 2 % ppm ppm ppm/C 100||2 100||2 VS = 2.3 V to 5 V T = -40C to +85C VS = 5 V to 18 V T =-40C to +85C -VS + 1.9 -VS + 2.0 -VS + 1.9 -VS + 2.0 +VS - 1.1 +VS - 1.2 +VS - 1.2 +VS - 1.2 -VS + 1.9 -VS + 2.0 -VS + 1.9 -VS + 2.0 100||2 100||2 +VS - 1.1 +VS - 1.2 +VS - 1.2 +VS - 1.2 G||pF G||pF V V V V Rev. 0 | Page 5 of 24 AD8228 Parameter OUTPUT Output Swing Over Temperature Output Swing Over Temperature Short-Circuit Current POWER SUPPLY Operating Range Quiescent Current Over Temperature TEMPERATURE RANGE Specified Performance Operating Range 2 1 Conditions (Gain = 100) RL = 10 k VS = 2.3 V to 5 V T = -40C to +85C VS = 5 V to 18 V T = -40C to +85C Min -VS + 1.1 -VS + 1.4 -VS + 1.2 -VS + 1.6 A Grade Typ Max +VS - 1.2 +Vs - 1.3 +VS - 1.4 +VS - 1.5 Min -VS + 1.1 -VS + 1.4 -VS + 1.2 -VS + 1.6 B Grade Typ Max +VS - 1.2 +VS - 1.3 +VS - 1.4 +VS - 1.5 Unit V V V V mA V mA mA C C 18 VS = 2.3 V to 18 V T = -40C to +85C -40 -40 2.3 0.85 1 18 1 1.2 +85 +125 2.3 18 18 1 1.2 +85 +125 0.85 1 -40 -40 Operating near the input voltage range limit may reduce the available output range. See Figure 12 and Figure 13 for the input common-mode range vs. output voltage. 2 See the Typical Performance Characteristics section for expected operation between 85C to 125C. Rev. 0 | Page 6 of 24 AD8228 ABSOLUTE MAXIMUM RATINGS Table 4. Parameter Supply Voltage Output Short-Circuit Current Input Voltage (Common Mode) Differential Input Voltage Storage Temperature Range Operating Temperature Range1 Maximum Junction Temperature ESD Human Body Model Charge Device Model 1 Rating 18 V Indefinite VS VS -65C to +150C -40C to +125C 140C 2 kV 1 kV THERMAL RESISTANCE JA is specified for a device in free air. Table 5. Package 8-Lead MSOP, 4-Layer JEDEC Board 8-Lead SOIC, 4-Layer JEDEC Board JA 135 121 Unit C/W C/W ESD CAUTION Temperature range for specified performance is -40C to +85C. See the Typical Performance Characteristics section for expected operation from 85C to 125C. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. 0 | Page 7 of 24 AD8228 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS -IN 1 G1 2 G2 3 +IN 4 8 +VS 7 VOUT 6 REF TOP VIEW (Not to Scale) Figure 2. Pin Configuration Table 6. Pin Function Descriptions Pin No. 1 2, 3 4 5 6 7 8 Mnemonic -IN G1, G2 +IN -VS REF VOUT +VS Description Negative Input. Gain Pins. Short together for a gain of 100. Leave unconnected for a gain of 10. Positive Input. Negative Supply. Reference. Output. Positive Supply. Rev. 0 | Page 8 of 24 07035-004 AD8228 5 -VS AD8228 TYPICAL PERFORMANCE CHARACTERISTICS T = 25C, VS = 15 V, RL = 10 k, unless otherwise noted. 70 60 50 MEAN: -5.5 SD: 12.4 100 MEAN: 0.20 SD: 0.12 80 HITS 40 30 20 HITS 60 40 20 10 07035-043 07035-047 0 -100 -50 0 50 G10 SYSTEM VOS RTI @ 15V (V) 100 0 -1.0 -0.5 0 0.5 1.0 G100 SYSTEM VOS DRIFT RTI (V) 1.5 Figure 3. Typical Distribution of Input Offset Voltage (G = 10) Figure 6. Typical Distribution of Input Offset Voltage Drift (G = 100) 60 MEAN: -0.079 SD: 0.27 100 MEAN: 0.29 SD: 0.27 80 50 40 60 HITS 30 HITS 40 20 0 -3 20 10 07035-045 -1.0 -0.5 0 0.5 G10 SYSTEM VOS DRIFT RTI (V) 1.0 1.5 -2 -1 0 1 CMRR G100 RTI (V/V) 2 3 Figure 4. Typical Distribution of Input Offset Voltage Drift (G = 10) Figure 7. Typical Distribution for CMR (G = 100) MEAN: 7.1 SD: 10.1 80 120 100 MEAN: 0.42 SD: 0.08 60 80 HITS HITS 40 60 40 20 20 0 07035-046 -100 -50 0 50 G100 SYSTEM VOS RTI @ 15V (V) 100 -0.5 0 0.5 1.0 NEG IBIAS CURRENTS 15V (nA) 1.5 Figure 5. Typical Distribution of Input Offset Voltage (G = 100) Figure 8. Typical Distribution of Input Bias Current Rev. 0 | Page 9 of 24 07035-049 0 07035-048 0 -1.5 AD8228 MEAN: -0.097 SD: 0.07 80 5 4 VS = 5V INPUT COMMON-MODE VOLTAGE (V) 3 2 1 0 -1 -2 -3 -4 -4 -3 -2 -1 0 1 2 OUTPUT VOLTAGE (V) 3 4 5 07035-035 07035-051 07035-036 60 HITS 40 VS = 2.5V 20 07035-050 0 -0.6 -0.4 -0.2 0 0.2 IOS @ 15V (nA) 0.4 0.6 -5 -5 Figure 9. Typical Distribution of Input Offset Current Figure 12. Input Common-Mode Voltage vs. Output Voltage, VS = 2.5 V, 5 V; G = 100 15 INPUT COMMON-MODE VOLTAGE (V) 5 4 INPUT COMMON-MODE VOLTAGE (V) 3 2 1 0 -1 -2 -3 -4 -4 -3 -2 -1 0 1 2 OUTPUT VOLTAGE (V) VS = 5V 10 VS = 15V 5 0 VS = 2.5V -5 -10 3 4 5 07035-033 -5 -5 -15 -15 -10 -5 0 5 OUTPUT VOLTAGE (V) 10 15 Figure 10. Input Common-Mode Voltage vs. Output Voltage, VS = 2.5 V, 5 V; G =10 15 INPUT COMMON-MODE VOLTAGE (V) Figure 13. Input Common-Mode Voltage vs. Output Voltage, VS = 15 V, G = 100 0.60 0.55 INPUT BIAS CURRENT (nA) 10 VS = 15V 5 +IN IBIAS, 15V SUPPLIES -IN IBIAS, 15V SUPPLIES 0.50 0.45 0.40 0.35 0.30 0.25 -IN IBIAS, 5V SUPPLIES 0 +IN IBIAS, 5V SUPPLIES -5 -10 07035-034 -15 -15 -10 -5 0 5 OUTPUT VOLTAGE (V) 10 15 0.20 -15 -10 -5 0 5 COMMON-MODE VOLTAGE (V) 10 15 Figure 11. Input Common-Mode Voltage vs. Output Voltage, VS = 15 V, G = 10 Figure 14. Input Bias Current vs. Common-Mode Voltage Rev. 0 | Page 10 of 24 AD8228 2.00 CHANGE IN INPUT OFFSET VOLTAGE (V) 160 140 120 G = 10 100 80 60 40 20 0.1 G = 100 1.75 1.50 1.25 1.00 0.75 0.50 0.25 07035-002 0.1 1 WARM-UP TIME (Minutes) 10 1 10 100 1k FREQUENCY (Hz) 10k 100k 1M Figure 15. Change in Input Offset Voltage vs. Warm-Up Time Figure 18. Negative PSRR vs. Frequency 4 3 INPUT BIAS CURRENT (nA) 70 60 50 2 1 +IN IBIAS GAIN (dB) 40 30 20 10 0 G = 100 0 -1 -2 -IN IBIAS IOS G = 10 -10 -3 07035-052 -20 -20 0 20 40 60 80 TEMPERATURE (C) 100 120 140 1k 10k 100k FREQUENCY (Hz) 1M 10M Figure 16. Input Bias Current and Offset Current vs. Temperature Figure 19. Gain vs. Frequency 160 140 G = 100 POSITIVE PSRR (dB) 120 G = 10 100 80 60 40 20 10 150 100 G = 10 GAIN ERROR (V/V) 50 0 G = 100 -50 -100 07035-012 100 1k 10k FREQUENCY (Hz) 100k 1M 0 15 30 45 60 75 TEMPERATURE (C) 90 105 120 135 Figure 17. Positive PSRR vs. Frequency, RTI Figure 20. Gain Error vs. Temperature Rev. 0 | Page 11 of 24 07035-007 -150 -45 -30 -15 07035-019 -4 -40 -30 100 07035-013 0 0.01 NEGATIVE PSRR (dB) AD8228 140 G = 100 120 G = 10 +VS - 0 +VS - 0.4 +VS - 0.8 +VS - 1.2 +VS - 1.6 +VS - 2.0 CMRR (dB) 100 80 INPUT VOLTAGE LIMIT (V) REFERRED TO SUPPLY VOLTAGES 07035-039 -VS + 2.0 -VS + 1.6 -VS + 1.2 -VS + 0.8 -VS + 0.4 -VS + 0 60 0 1 10 100 1k FREQUENCY (Hz) 10k 100k 1M 0 5 10 SUPPLY VOLTAGE (V) 15 20 Figure 21. CMRR vs. Frequency, RTI Figure 24. Input Voltage Limit vs. Supply Voltage 140 G = 100 120 G = 10 +VS - 0 +VS - 0.4 +VS - 0.8 +VS - 1.2 +VS - 1.6 +VS - 2.0 OUTPUT VOLTAGE LIMIT (V) REFERRED TO SUPPLY VOLTAGES RL = 10k RL = 2k CMRR (dB) 100 80 -VS + 2.0 -VS + 1.6 -VS + 1.2 -VS + 0.8 -VS + 0.4 -VS + 0 RL = 10k 07035-015 RL = 2k 60 0 1 10 100 1k FREQUENCY (Hz) 10k 100k 1M 07035-040 40 0 5 10 SUPPLY VOLTAGE (V) 15 20 Figure 22. CMRR vs. Frequency, RTI, 1 k Source Imbalance Figure 25. Output Voltage Swing vs. Supply Voltage 20 15 OUTPUT VOLTAGE (V p-p) 30 VS = 15V 25 10 5 0 -5 -10 -15 07035-008 20 CMR (V/V) 15 10 5 -20 0 20 40 60 80 TEMPERATURE (C) 100 120 140 1 10 100 LOAD RESISTANCE () 1k 10k Figure 23. CMR vs. Temperature Figure 26. Output Voltage Swing vs. Load Resistance Rev. 0 | Page 12 of 24 07035-020 -20 -40 0 07035-014 40 AD8228 +VS -0 -1 1k OUTPUT VOLTAGE SWING (V) REFERRED TO SUPPLY VOLTAGE -2 -3 VOLTAGE NOISE RTI (nV/Hz) 100 G = 10 10 G = 100 +3 +2 +1 07035-021 0 1 2 3 4 5 6 7 8 OUTPUT CURRENT (mA) 9 10 11 12 1 10 100 1k FREQUENCY (Hz) 10k 100k Figure 27. Output Voltage Swing vs. Output Current, G = 1 Figure 30. Voltage Noise Spectral Density vs. Frequency ERROR (10ppm/DIV) 0.2V/DIV -10 -8 -6 -4 -2 0 2 4 OUTPUT VOLTAGE (V) 6 8 10 07035-016 1s/DIV Figure 28. Gain Nonlinearity, G = 10, RL = 10 k 1000 Figure 31. 0.1 Hz to 10 Hz RTI Voltage Noise, G=10 CURRENT NOISE (fA/ Hz) ERROR (10ppm/DIV) 100 10 07035-029 -10 -8 -6 -4 -2 0 2 4 OUTPUT VOLTAGE (V) 6 8 10 1 10 100 FREQUENCY (Hz) 1k 10k Figure 29. Gain Nonlinearity, G = 100, RL = 10 k Figure 32. Current Noise Spectral Density vs. Frequency Rev. 0 | Page 13 of 24 07035-030 1 07035-023 07035-022 -VS +0 1 AD8228 5pA/DIV 5V/DIV 0.002%/DIV 07035-031 1s/DIV 20s/DIV Figure 33. 0.1 Hz to 10 Hz Current Noise Figure 36. Large Signal Pulse Response and Settling Time (G = 100) 30 VS = 15V 25 OUTPUT VOLTAGE (V p-p) 20 15 G = 10, 100 10 20mV/DIV 4s/DIV 10k 100k FREQUENCY (Hz) 1M 07035-024 0 1k Figure 34. Large Signal Frequency Response Figure 37. Small Signal Response, G = 10, RL = 2 k, CL = 100 pF 5V/DIV 0.002%/DIV 20mV/DIV 20s/DIV 4s/DIV Figure 35. Large Signal Pulse Response and Settling Time (G = 10) Figure 38. Small Signal Response, G = 100, RL = 2 k, CL = 100 pF Rev. 0 | Page 14 of 24 07035-028 07035-025 07035-027 5 07035-026 AD8228 15 G = 10 RL = 10k 17.5 20.0 G = 100 RL = 10k SETTLING TIME (s) 10 0.001% SETTLING TIME SETTLING TIME (s) 15.0 0.001% SETTLING TIME 0.01% SETTLING TIME 5 12.5 0.01% SETTLING TIME 0 10.0 07035-041 0 5 10 15 OUTPUT VOLTAGE STEP SIZE (V p-p) 20 0 5 10 15 OUTPUT VOLTAGE STEP SIZE (V p-p) 20 Figure 39. Settling Time vs. Step Size, G = 10 Figure 40. Settling Time vs. Step Size, G = 100 Rev. 0 | Page 15 of 24 07035-042 AD8228 THEORY OF OPERATION I VBIAS I IB COMPENSATION C1 A1 A2 C2 10k 10k +VS -IN 600 Q1 R1 22k +VS V1 -VS -VS R3 4.889k G1 G2 GAIN R4 -VS SET 489 +VS V2 -VS -VS 07035-018 IB COMPENSATION 10k +VS A3 +VS 10k -VS REF OUTPUT R2 22k Q2 600 +VS +IN Figure 41. Simplified Schematic ARCHITECTURE The AD8228 is based on the classic three op amp topology. This topology has two stages: a preamplifier to provide differential amplification, followed by a difference amplifier to remove the common-mode voltage. Figure 41 shows a simplified schematic of the AD8228. The first stage is composed of the A1 and A2 amplifiers, the Q1 and Q2 input transistors, and the R1 through R4 resistors. The feedback loop of A1, R1, and Q1 ensures that the V1 voltage is a constant diode drop below in the negative input voltage. Similarly, V2 is kept a constant diode drop below the positive input. Therefore, a replica of the differential input voltage is placed across either R3 (when the gain pins are left open) or R3||R4 (when the gain pins are shorted). The current that flows across this resistance must also flow through the R1 and R2 resistors, creating a gained differential signal between the A2 and A1 outputs. Note that, in addition to a gained differential signal, the original common-mode signal, shifted a diode drop down, is also still present. The second stage is a difference amplifier, composed of A3 and four 10 k resistors. The purpose of this stage is to remove the common-mode signal from the amplified differential signal. The AD8228 does not depend on external resistors. Much of the dc performance of precision circuits depends on the accuracy and matching of resistors. The resistors on the AD8228 are laid out to be tightly matched. The resistors of each part are laser trimmed and tested for their matching accuracy. Because of this trimming and testing, the AD8228 can guarantee high accuracy for specifications such as gain drift, common-mode rejection (CMRR), and gain error. SETTING THE GAIN The AD8228 can be configured for a gain of 10 or 100 with no external components. Leave Pin 2 and Pin 3 open for a gain of 10; short Pin 2 and Pin 3 together for a gain of 100 (see Figure 42). G = 10 PIN 2 AND PIN 3 OPEN +VS -IN 1 2 3 +IN 4 5 -VS 8 -IN 7 VOUT +IN 1 2 3 4 5 -VS G = 100 PIN 2 AND PIN 3 SHORTED +VS 8 AD8228 6 REF AD8228 6 REF 7 VOUT Figure 42. Setting the Gain The transfer function with Pin 2 and Pin 3 open is VOUT = 10 x (VIN+ - VIN-) + VREF The transfer function with Pin 2 and Pin 3 shorted is VOUT = 100 x (VIN+ - VIN-) + VREF COMMON-MODE INPUT VOLTAGE RANGE The three op amp architecture of the AD8228 applies gain and then removes the common-mode voltage. Therefore, internal nodes in the AD8228 experience a combination of both the gained signal and the common-mode signal. This combined signal can be limited by the voltage supplies even when the individual input and output signals are not. Figure 10 through Figure 13 show the allowable common-mode input voltage ranges for various output voltages and supply voltages. Rev. 0 | Page 16 of 24 07035-003 AD8228 REFERENCE TERMINAL The output voltage of the AD8228 is developed with respect to the potential on the reference terminal. This is useful when the output signal needs to be offset to a precise midsupply level. For example, a voltage source can be tied to the REF pin to level-shift the output so that the AD8228 can drive a single-supply ADC. The REF pin is protected with ESD diodes and should not exceed either +VS or -VS by more than 0.3 V. For best performance, source impedance to the REF terminal should be kept below 1 . As shown in Figure 41, the reference terminal, REF, is at one end of a 10 k resistor. Additional impedance at the REF terminal adds to this 10 k resistor and results in amplification of the signal connected to the positive input. The amplification from the additional RREF can be computed by Common-Mode Rejection Ratio over Frequency The AD8228 has a higher CMRR over frequency than typical in-amps, which gives it greater immunity to disturbances such as line noise and its associated harmonics. The AD8228 pinout was designed so that the board designer can take full advantage of this performance with a well-implemented layout. Poor layout can cause some of the common-mode signal to be converted to a differential signal before it reaches the in-amp. Such conversions occur when one input path has a frequency response that is different from the other. To keep CMRR across frequency high, input source impedance and capacitance of each path should be closely matched. Additional source resistance in the input path (for example, for input protection) should be placed close to the in-amp inputs, which minimizes their interaction with parasitic capacitance from the PCB traces. Parasitic capacitance at the gain setting pins can also affect CMRR over frequency. If the board design has a component at the gain setting pins (for example, a switch or jumper), the part should be chosen so that the parasitic capacitance is as small as possible. 2 x (10 k + RREF ) 20 k + RREF Only the positive signal path is amplified; the negative path is unaffected. This uneven amplification degrades the CMRR of the amplifier. INCORRECT CORRECT Power Supplies A stable dc voltage should be used to power the instrumentation amplifier. Noise on the supply pins can adversely affect performance. See the PSRR performance curves in Figure 17 and Figure 18 for more information. A 0.1 F capacitor should be placed as close as possible to each supply pin. As shown in Figure 45, a 10 F tantalum capacitor can be used farther away from the part. In most cases, it can be shared by other precision integrated circuits. +VS AD8228 REF V + V AD8228 REF OP1177 07035-005 - Figure 43. Driving the Reference LAYOUT The AD8228 is a high precision device. To ensure optimum performance at the PCB level, care must be taken in the design of the board layout. The AD8228 pins are arranged in a logical manner to aid in this task. -IN 1 G1 2 G2 3 +IN 4 8 7 6 0.1F +IN 10F AD8228 -IN REF VOUT LOAD +VS VOUT 07035-006 REF -VS 07035-044 0.1F -VS 10F AD8228 TOP VIEW (Not to Scale) 5 Figure 45. Supply Decoupling, REF, and Output Referred to Local Ground Figure 44. Pinout Diagram Rev. 0 | Page 17 of 24 AD8228 References The output voltage of the AD8228 is developed with respect to the potential on the reference terminal. Care should be taken to tie REF to the appropriate local ground. For applications where the AD8228 encounters extreme overload voltages, such as cardiac defibrillators, external series resistors and low leakage diode clamps such as the BAV199L, the FJH1100s, or the SP720 should be used. Input Bias Current Return Path The input bias current of the AD8228 must have a return path to common. When the source, such as a thermocouple, cannot provide a return current path, one should be created, as shown in Figure 46. INCORRECT +VS Large Differential Voltages When G = 100 When operating at a gain of 100, large differential input voltages can cause more than 6 mA of current to flow into the inputs. This condition occurs when the voltage between +IN and -IN exceeds 5 V. This is true for differential voltages of either polarity. The maximum allowed differential voltage can be increased by adding an input protection resistor in series with each input. The value of each protection resistor should be RPROTECT = (VDIFF_MAX - 5 V)/6 mA CORRECT +VS AD8228 REF AD8228 REF RADIO FREQUENCY INTERFERENCE (RFI) RF rectification is often a problem when amplifiers are used in applications having strong RF signals. The disturbance can appear as a small dc offset voltage. High frequency signals can be filtered with a low-pass RC network placed at the input of the instrumentation amplifier, as shown in Figure 47. The filter limits the input signal bandwidth, according to the following relationship: FilterFrequencyDIFF = -VS TRANSFORMER +VS -VS TRANSFORMER +VS 1 2R(2CD + CC ) 1 2 RCC +15V 0.1F 10F AD8228 REF 10M -VS THERMOCOUPLE +VS C 1 fHIGH-PASS = 2RC REF C R C AD8228 REF FilterFrequencyCM = where CD 10 CC. -VS THERMOCOUPLE +VS CC R R 1nF +IN AD8228 C AD8228 REF 4.02k CD R 4.02k 07035-009 10nF AD8228 REF -IN VOUT -VS CAPACITIVELY COUPLED -VS CAPACITIVELY COUPLED CC 1nF 0.1F -15V 10F INPUT PROTECTION All terminals of the AD8228 are protected against ESD (1 kV, human body model). In addition, the input structure allows for dc overload conditions of about 3.5 V beyond the supplies. Figure 47. RFI Suppression Input Voltages Beyond the Rails For larger input voltages, an external resistor should be used in series with each input to limit current during overload conditions. The AD8228 can safely handle a continuous 6 mA current. The limiting resistor can be computed from R LIMIT V IN - V SUPPLY 6 mA - 600 CD affects the difference signal, and CC affects the common-mode signal. Values of R and CC should be chosen to minimize RFI. Mismatch between the R x CC at the positive input and the R x CC at the negative input degrades the CMRR of the AD8228. By using a value of CD one magnitude larger than CC, the effect of the mismatch is reduced, and performance is improved. Rev. 0 | Page 18 of 24 07035-010 Figure 46. Creating an IBIAS Path AD8228 APPLICATIONS INFORMATION DIFFERENTIAL DRIVE Figure 48 shows how to configure the AD8228 for differential output. The advantage of this circuit is that the dc differential accuracy depends on the AD8228 and not on the op amp or the resistors. This circuit takes advantage of the precise control the AD8228 has of its output voltage relative to the reference voltage. The ideal equation for the differential output is as follows: VDIFF_OUT = VOUT+ - VOUT- = Gain x (VIN+ - VIN-) Op amp dc performance and resistor matching determine the dc common-mode output accuracy. However, because commonmode errors are likely to be rejected by the next device in the signal chain, these errors typically have little effect on overall system accuracy. The ideal equation for the common-mode output is as follows: VCM_OUT = PRECISION STRAIN GAGE The low offset and high CMRR over frequency of the AD8228 make it an excellent candidate for bridge measurements. As shown in Figure 49, the bridge can be connected directly to the inputs of the amplifier. 5V 10F 350 350 +IN 350 350 -IN + 0.1F AD8228 - 07035-011 2.5V Figure 49. Precision Strain Gage VOUT + + VOUT - 2 = VREF DRIVING A DIFFERENTIAL ADC Figure 50 shows how the AD8228 can be used to drive a differential ADC. The AD8228 is configured with an op amp and two resistors for differential drive. The 510 resistors and 2200 pF capacitors isolate the instrumentation amplifier from the switching transients produced by the switched capacitor front end of a typical SAR converter. These components between the ADC and the amplifier also create a filter at 142 kHz, which provides antialiasing and noise filtering. The advantage of this configuration is that it uses less power than a dedicated ADC driver: the AD8641 typically consumes 200 A, and the current through the two 10 k resistors is 250 A at full output voltage. With the AD7688, this configuration gives excellent dc performance and a THD of 71 dB (10 kHz input). For applications that need better distortion performance, a dedicated ADC driver, such as the ADA4941-1 or ADA4922-1, is recommended. For best ac performance, an op amp with at least 3 MHz gain bandwidth product and 2 V/s slew rate is recommended. +IN AD8228 -IN REF 10k VREF +OUT 10k + - AD8641 -OUT Figure 48. Differential Output Using an Op Amp +8V 0.1F VIN VOUT 0.1F 07035-017 +8V 0.1F +IN ADR435 GND 10F X5R 10k +5V 10k 0.1F 510 REF VDD AD8228 -IN REF 10k 0.1F -8V 10k -8V 0.1F IN+ 0.1F AD7688 IN- AD8641 0.1F +8V 0.1F GND Figure 50. Driving a Differential ADC Rev. 0 | Page 19 of 24 07035-032 510 AD8228 OUTLINE DIMENSIONS 3.20 3.00 2.80 3.20 3.00 2.80 PIN 1 8 5 1 5.15 4.90 4.65 4 0.65 BSC 0.95 0.85 0.75 0.15 0.00 0.38 0.22 SEATING PLANE 1.10 MAX 8 0 0.80 0.60 0.40 0.23 0.08 COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-187-AA Figure 51. 8-Lead Mini Small Outline Package [MSOP] (RM-8) Dimensions shown in millimeters 5.00 (0.1968) 4.80 (0.1890) 4.00 (0.1574) 3.80 (0.1497) 8 1 5 4 6.20 (0.2441) 5.80 (0.2284) 1.27 (0.0500) BSC 0.25 (0.0098) 0.10 (0.0040) COPLANARITY 0.10 SEATING PLANE 1.75 (0.0688) 1.35 (0.0532) 0.50 (0.0196) 0.25 (0.0099) 8 0 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.0157) 45 0.51 (0.0201) 0.31 (0.0122) COMPLIANT TO JEDEC STANDARDS MS-012-A A CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 52. 8-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-8) Dimensions shown in millimeters and (inches) Rev. 0 | Page 20 of 24 012407-A AD8228 ORDERING GUIDE Model AD8228ARMZ 1 AD8228ARMZ-RL1 AD8228ARMZ-R71 AD8228ARZ1 AD8228ARZ-RL1 AD8228ARZ-R71 AD8228BRMZ1 AD8228BRMZ-RL1 AD8228BRMZ-R71 AD8228BRZ1 AD8228BRZ-RL1 AD8228ARZ-R71 1 Temperature Range -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C Package Description 8-Lead MSOP 8-Lead MSOP, 13" Tape and Reel 8-Lead MSOP, 7" Tape and Reel 8-Lead SOIC_N 8-Lead SOIC_N, 13" Tape and Reel 8-Lead SOIC_N, 7" Tape and Reel 8-Lead MSOP 8-Lead MSOP, 13" Tape and Reel 8-Lead MSOP, 7" Tape and Reel 8-Lead SOIC_N 8-Lead SOIC_N, 13" Tape and Reel 8-Lead SOIC_N, 7" Tape and Reel PackageOption RM-8 RM-8 RM-8 R-8 R-8 R-8 RM-8 RM-8 RM-8 R-8 R-8 R-8 Branding Y16 Y16 Y16 Y1M Y1M Y1M Z = RoHS Compliant Part. Rev. 0 | Page 21 of 24 AD8228 NOTES Rev. 0 | Page 22 of 24 AD8228 NOTES Rev. 0 | Page 23 of 24 AD8228 NOTES (c)2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07035-0-7/08(0) Rev. 0 | Page 24 of 24 |
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