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MDT10P7212
1. General Description
This EPROM-Based 8-bit micro-controller uses a fully static CMOS technology process to achieve higher speed and smaller size with the low power consumption and high noise immunity. On chip memory includes 4K words of ROM, and 192 bytes of static RAM. -8 analog inputs multiplexed into one A/D converter -10-bit resolution TMR0: 8-bit real time clock/counter TMR1: 16-bit real time clock/count TMR2: 8-bit clock/counter (internal) 5 types of oscillator can be selected by programming option:
2. Features
The followings are some of the features on the hardware and software: Fully CMOS static design 8-bit data bus On chip EPROM size: 4.0 K words Internal RAM size: 192 bytes 37 single word instructions 14-bit instructions 8-level stacks Operating voltage: 2.5 V ~ 5.5 V (PRD Disable) 4.5 V ~ 5.5 V (PRD Enable) Operating frequency: DC ~ 20 MHz The most fast execution time is 200 ns under 20 MHz in all single cycle instructions except the branch instruction Addressing modes include direct, indirect and relative addressing modes Power-on Reset Power edge-detector Reset Power range-detector Reset Sleep Mode for power saving Capture, Compare, PWM module 7 interrupt sources: -External INT pin -TMR0 timer, TMR1 timer, TMR2 timer -A/D conversion completion -Port B<7:4> interrupt on change -CCP1 A/D converter module:
RCLow cost RC oscillator LFXTLow frequency crystal oscillator XTALStandard crystal oscillator HFXTHigh frequency crystal oscillator IRCInternal 8MHz RC oscillator On-chip RC oscillator based Watchdog Timer (WDT) 18/20 I/O pins with their own independent direction control
3. Applications
The application areas of this MDT10P7212 range from appliance motor control and high speed auto-motive to low power remote transmitters/receivers, pointing
devices, and telecommunications processors, such as Remote controller, small instruments, chargers, toy, automobile and PC peripheral ... etc.
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P. 1
2007/11 VER1.2
MDT10P7212
4. Pin Assignment PE2/AIC7 1 PA0/AIC0 2 PA1/AIC1 3 PA2/AIC2 4 PA3/AIC3 5 PA5/AIC4 6 PA4/T0CKI/VPP 7 VSS 8 PB0 9 PB1 10 PB2 11 PB3 12 24 23 22 21 20 19 18 17 16 15 14 13 PE1/AIC6 PE0/AIC5 PC2/CCP1 PC1/T1OSC1 PC0/T1OSC2 PC4 PC3 VDD PB7 PB6 PB5 PB4 PE2/AIC7 1 PA0/AIC0 2 PA1/AIC1 3 PA2/AIC2 4 PA3/AIC3 5 PA5/AIC4 6 PA4/T0CKI/VPP 7 VSS 8 PB0 9 PB1 10 PB2 11 PB3 12 24 23 22 21 20 19 18 17 16 15 14 13 PE1/AIC6 PE0/AIC5 PC2/CCP1 PC1/T1OSC1 PC0/T1OSC2 OSC1 OSC2 VDD PB7 PB6 PB5 PB4
MDT10P7212K11 (SKINNY) MDT10P7212S11 (SOP) 5. Order information
Device ROM (words) MDT10P7212K11 MDT10P7212S11 MDT10P7212K12 MDT10P7212S12 4K 4K 4K 4K RAM (bytes) 192 192 192 192 22 22 20 20 I/O A/D (10 bits) 8-channel 8-channel 8-channel 8-channel
MDT10P7212K12 (SKINNY) MDT10P7212S12 (SOP)
Timer (8/16) 2/1 2/1 2/1 2/1
CCP
INRC (8Mhz)
Package
1 1 1 1
Yes Yes No No
SKINNY SOP SKINNY SOP
6. Pin Function Description
Pin Name PA0~PA3, PA5 I/O I/O Function Description Port A, TTL input level Analog input channel PA4/T0CKI/VPP I/O Real Time Clock/Counter, Schmitt Trigger input levels Open drain output, Vpp input when programming PB0~PB7 I/O Port B, TTL input level/PB0: External interrupt input, PB4~PB7: Interrupt on pin change PC0~PC2 OSC1/PC4 I/O I, I/O Port C, Schmitt Trigger input levels Oscillator Input/external clock input PC4 in IRC mode This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw
P. 2
2007/11 VER1.2
MDT10P7212
Pin Name OSC2/PC3 I/O O, I/O Function Description Oscillator Output/in RC mode, the CLKOUT pin has 1/4 frequency of CLKIN PC3 in IRC mode PE0~PE2 I/O Port E, Schmitt Trigger input levels Analog input channel VDD VSS Power supply Ground
7. Memory Map
(A) Register Map
Address BANK0 00 01 02 03 04 05 06 07 09 0A 0B 0C 0E 0F 10 11 12 15 16
Description
Indirect Addressing Register RTCC PCL STATUS MSR Port A Port B Port C Port E PCHLAT INTS PIFB1 TMR1L TMR1H T1STA TMR2 T2STA CCP1L CCP1H
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P. 3
2007/11 VER1.2
MDT10P7212
Address 17 1E 1F 20~7F BANK1 01 05 06 07 09 0C 0D 0E 12 1E 1F A0~FF TMR CPIO A CPIO B CPIO C CPIO E PIEB1 PIEB2 PSTA T2PER ADRESL, The ADRESL register is not a writable register. ADS1 General purpose register CCP1CTL ADRESH, The ADRESH register is not a writable register. ADS0 General purpose register Description
(1) IAR (Indirect Address Register): R00 (2) RTCC (Real Time Counter/Counter Register): R01 (3) PC (Program Counter): R02, R0A Write PC --- from PCHLAT Write PC --- from PCHLAT LJUMP, LCALL --- from instruction word RTWI, RET --- from STACK A11 A10~A8 A7~A0
Write PC --- from ALU LJUMP, LCALL --- from instruction word RTWI, RET, RTFI --- from STACK
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P. 4
2007/11 VER1.2
MDT10P7212
(4) STATUS (Status register): R03 Bit 0 1 2 3 4 5 Symbol C HC Z /PF /TF RBS0 Carry bit Half Carry bit Zero bit Power down Flag bit WDT Timer overflow Flag bit Register Bank Select bit 0: 00h~7Fh (Bank0) 1: 80h~FFh (Bank1) 7-6 -General purpose bit Function
(5) MSR (Memory Bank Select Register): R04 Memory Bank Select Register: 0: 00h~7Fh (Bank0) 1: 80h~FFh (Bank1)
b7
b6
b5
b4
b3
b2
b1
b0
Indirect Addressing Mode (6) PORT A: R05 PA5~PA0, I/O Register (7) PORT B: R06 PB7~PB0, I/O Register (8) PORT C: R07 PC4~PC0, I/O Register (9) PORT E: R09 PE2~PE0, I/O Register (10) PCHLAT: R0A
(11) INTS (Interrupt Status Register): R0B Bit 0 1 2 Symbol RBIF INTF TIF Function PORT B change interrupt flag, Set when PB <7:4> inputs change Set when INT interrupt occurs Set when TMR0 overflows
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P. 5
2007/11 VER1.2
MDT10P7212
Bit 3 Symbol RBIE 0: Disable PB change interrupt 1: Enable PB change interrupt 4 INTS 0: Disable INT interrupt 1: Enable INT interrupt 5 TIS 0: Disable TMR0 interrupt 1: Enable TMR0 interrupt 6 PEIE 0: Disable all peripheral interrupt 1: Enable all peripheral interrupt 7 GIS 0: Disable global interrupt 1: Enable global interrupt (12) PIFB1 (Peripheral Interrupt Flag Bit): R0C Bit 0 Symbol TMR1IF TMR1 interrupt flag 0: TMR1 did not overflow 1: TMR1 overflowed 1 TMR2IF TMR2 interrupt flag 0: No TMR2 to T2PER match occurred 1: TMR2 to T2PER match occurred 2 CCP1IF CCP1 interrupt flag 0: No TMR1 capture/compare occurred 1: A TMR1 capture/compare occurred 5~3 6 -ADIF Unimplemented, read as `0' A/D interrupt flag 0: A/D conversion is not complete 1: A/D conversion completed 7 -Unimplemented, read as `0' Function Function
(13) TMR1L: R0E The LSB of the 16-bit TMR1 (14) TMR1H: R0F The MSB of the 16-bit TMR1
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P. 6
2007/11 VER1.2
MDT10P7212
(15) T1STA: R10 Bit 0 Symbol TMR1ON 0: Stop TMR1 1: Enable TMR1 1 TMR1CLK 0: Internal clock (Fosc/4) 1: External clock from pin PC0 2 /T1SYNC TMR1CLK = 1 0: Synchronize external clock 1: Do not synchronize external clock TMR1CLK = 0 This bit is ignored 3 T1OSCEN 0: TMR1 Oscillator is shut off 1: TMR1 Oscillator is enable 5~4 T1CKPS1 ~ T1CKPS0 1 1 = 1:8 Prescale value 1 0 = 1:4 Prescale value 0 1 = 1:2 Prescale value 0 0 = 1:1 Prescale value 7~6 -Unimplemented, read as `0' Function
(16) TMR2: R11 TMR2 register
(17) T2STA: R12 Bit 1~0 Symbol T2CKPS1 ~ T2CKPS0 2 TMR2ON 0 0 = Prescaler is 1 0 1 = Prescaler is 4 1 x = Prescaler is 16 0: TMR2 is off 1: TMR2 is on 7~3 -Unimplemented, read as `0' Function
(18) CCP1L: R15 Capture/Compare/PWM LSB
(19) CCP1H: R16 Capture/Compare/PWM MSB
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P. 7
2007/11 VER1.2
MDT10P7212
(20) CCP1CTL: R17 Bit 3~0 Symbol CCP1M3 ~ CCP1M0 0 0 0 0: CCP1 off 0 1 0 0: Capture1 mode, every falling edge 0 1 0 1: Capture1 mode, every rising edge 0 1 1 0: Capture1 mode, every 4th rising edge 0 1 1 1: Capture1 mode, every 16th rising edge 1 0 0 0: Compare1 mode, set output on match 1 0 0 1: Compare1 mode, clear output on match 1 0 1 0: Compare1 mode, generate software interrupt on match 1 0 1 1: Compare1 mode, trigger special event 1 1 x x: PWM1 mode 5~4 7~6 PWM1LSB These bits are the two LSBs of the PWM1 duty cycle -Unimplemented, read as `0' Function
(21) ADRESH: R1E A/D result register high byte, The ADRESH register is not a writable register. (22) ADS0 ( A/D Status Register ): R1F Bit 0 Symbol ADRUN Function 0: A/D converter module is shut off and consumes no operating current 1: A/D converter module is operating 1 2 -Unimplemented, read as `0'
GO/DONEB 0: A/D conversion not in progress 1: A/D conversion in progress
5~3
CHS2~0
000: AIC0 001: AIC1 010: AIC2 011: AIC3 100: AIC4 101: AIC5 110: AIC6 111: AIC7
7~6
ASCS1~0
00: fosc/2 01: fosc/8 10: fosc/32 11: f RC (*Note)
*Note: determined by OSC mode, HF: fosc/32, XT: fosc/8, RC: fosc/2, LF: fosc/2
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P. 8
2007/11 VER1.2
MDT10P7212
(23) TMR (Time Mode Register): R81 Bit Symbol Prescaler Value Function RTCC rate WDT rate 1:1 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128
2~0
PS2~0
3
PSC
4
TCE
5
TCS
6
IES
7
PBPH
000 1:2 001 1:4 010 1:8 011 1 : 16 100 1 : 32 101 1 : 64 110 1 : 128 111 1 : 256 Prescaler assignment bit 0: RTCC 1: Watchdog Timer RTCC signal edge 0: Increment on low-to-high transition on RTCC pin 1: Increment on high-to-low transition on RTCC pin RTCC signal set 0: Internal instruction cycle clock 1: Transition on RTCC pin Interrupt edge select 0: Interrupt on falling edge on PB0 1: Interrupt on rising edge on PB0 PORTB7~0 pull-hi 0: PORTB7~0 pull-hi are enable 1: PORTB7~0 pull-hi are disable
(24) CPIO A (Control Port I/O Mode Register): R85 "0", I/O pin in output mode "1", I/O pin in input mode (25) CPIO B (Control Port I/O Mode Register): R86 "0", I/O pin in output mode "1", I/O pin in input mode (26) CPIO C (Control Port I/O Mode Register): R87 "0", I/O pin in output mode "1", I/O pin in input mode
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P. 9
2007/11 VER1.2
MDT10P7212
(27) PIEB1: R8C Bit 0 Symbol TMR1IE TMR1 interrupt enable bit 0: Disable TMR1 interrupt 1: Enable TMR1 interrupt 1 TMR2IE TMR2 interrupt enable bit 0: Disable TMR2 interrupt 1: Enable TMR2 interrupt 2 CCP1IE CCP1 interrupt enable bit 0: Disable CCP1 interrupt 1: Enable CCP1 interrupt 5~3 6 -ADIE Unimplemented, read as `0' A/D interrupt enable bit 0: Disable A/D interrupt 1: Enable A/D interrupt 7 -Unimplemented, read as `0' Function
(28) PSTA: R8E Bit 0 1 7~2 Symbol PRDB PORB -Function 0: Power range-detector Reset occurred 1: No Power range-detector Reset Occurred 0: Power on Reset occurred 1: No Power on Reset occurred Unimplemented, read as `0'
(29) T2PER: R92 Timer2 period
(30) ADRESL: R9E A/D result register low byte, The ADRESL register is not a writable register. (31) ADS1 ( A/D Status Register ): R9F Bit Symbol Function 0 0 0: PA0~3, PA5, PE0~2 = analog input, VREF = VDD 0 0 1: PA0~2, PA5, PE0~2 = analog input, VREF = PA3 0 1 0: PA0~3, PA5 = analog input, PE0~2 = digital I/O, VREF = VDD 0 1 1: PA0~2, PA5 = analog input, PE0~2 = digital I/O, VREF = PA3 1 0 0: PA0, 1, 3 = analog input, PA2, 5, PE0~2 = digital I/O, VREF = VDD 1 0 1: PA0, 1 = analog input, PA2, 5, PE0~2 = digital I/O, VREF = PA3 1 1 x: PA0~3, 5, PE0~2 = digital I/O 6~3 -Unimplemented, read as `0'
2~0
PAVM2~0
This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw
P. 10
2007/11 VER1.2
MDT10P7212
Bit 7 Symbol ADFM Function A/D result format select 0: Left justified, bit 5~0 of ADRESL are read as "0" 1: Right justified, bit 7~2 of ADRESH are read as "0" (32) Configurable options for EPROM (Set by writer) Oscillator Type RC Oscillator
HFXT Oscillator XTAL Oscillator LFXT Oscillator
Watchdog Timer control Watchdog timer disable all the time Watchdog timer enable all the time
Power-range control Power-range disable Power-range enable
Oscillator-start Timer control 0ms 75ms
Power-edge Detect PED Disable PED Enable (B) Program Memory Address 000-FFF 000 004 Program memory
Security state Security Disable Security Enable
Description
The starting address of power on, external reset or WDT time-out reset Interrupt vector
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P. 11
2007/11 VER1.2
MDT10P7212
8. Reset Condition for all Registers
Register Address Power-On Reset, Power range detector Reset N/A xxxx xxxx 0000 0000 0000 0001 1xxx xxxx xxxx --xx xxxx xxxx xxxx xxxx xxxx ---0 0000 0000 000x -000 0000 xxxx xxxx xxxx xxxx --00 0000 0000 0000 ---- -000 xxxx xxxx xxxx xxxx --00 0000 xxxx xxxx 0000 00-0 1111 1111 --11 1111 1111 1111 1111 1111 -000 0000 ---- --0u 1111 1111 xxxx xxxx 0--- -000 WDT Reset Wake-up from SLEEP
IAR RTCC PC STATUS MSR PORT A PORT B PORT C PCHLAT INTS PIFB1 TMR1L TMR1H T1STA TMR2 T2STA CCP1L CCP1H CCP1CTL ADRESH ADS0 TMR CPIOA CPIOB CPIOC PIEB1 PSTA T2PER ADRESL ADS1
00h 01h 0Ah,02h 03h 04h 05h 06h 07h 0Ah 0Bh 0Ch 0Eh 0Fh 10h 11h 12h 15h 16h 17h 1Eh 1Fh 81h 85h 86h 87h 8Ch 8Eh 92h 9Eh 9Fh
N/A uuuu uuuu 0000 0000 0000 000# #uuu uuuu uuuu --uu uuuu uuuu uuuu uuuu uuuu ---0 0000 0000 000u -000 0000 uuuu uuuu uuuu uuuu --uu uuuu 0000 0000 ---- -uuu uuuu uuuu uuuu uuuu --00 0000 uuuu uuuu 0000 00-0 1111 1111 --11 1111 1111 1111 1111 1111 -000 0000 ---- --uu 1111 1111 uuuu uuuu 0--- -000
N/A uuuu uuuu PC+1 000# #uuu uuuu uuuu --uu uuuu uuuu uuuu uuuu uuuu ---u uuuu uuuu uuuu -uuu uuuu uuuu uuuu uuuu uuuu --uu uuuu uuuu uuuu ---- -uuu uuuu uuuu uuuu uuuu --uu uuuu uuuu uuuu uuuu uu-u uuuu uuuu --uu uuuu uuuu uuuu uuuu uuuu -uuu uuuu ---- --uu 1111 1111 uuuu uuuu u--- -uuu
Note : uunchanged, xunknown, - unimplemented, read as "0" This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw
P. 12
2007/11 VER1.2
MDT10P7212
#value depends on the condition of the following table
Condition WDT reset (not during SLEEP) WDT reset during SLEEP Power-on reset Power-range reset
Status: bit 4 0 0 1 1
Status: bit 3 1 0 1 1
PSTA: bit 1 u u 0 u
PSTA: bit 0 u u x 0
Note : uunchanged, xunknown, - unimplemented, read as "0"
9. Instruction Set
Instruction Code 010000 00000000 010000 00000001 010000 00000010 010000 00000011 010000 00000100 010000 00000rrr 010001 1rrrrrrr 011000 trrrrrrr 111010 iiiiiiii 010111 trrrrrrr 011001 trrrrrrr 011010 trrrrrrr 011011 trrrrrrr 011100 trrrrrrr 011101 trrrrrrr 011110 trrrrrrr 010010 trrrrrrr 110100 iiiiiiii 010011 trrrrrrr 110101 iiiiiiii 010100 trrrrrrr 110110 iiiiiiii 011111 trrrrrrr 010110 trrrrrrr Mnemonic Operands NOP CLRWT SLEEP TMODE RET CPIO R STWR R LDR R, t LDWI I SWAPR R, t INCR R, t INCRSZ R, t ADDWR R, t SUBWR R, t DECR R, t DECRSZ R, t ANDWR R, t ANDWI i IORWR R, t IORWI i XORWR R, t XORWI i COMR R, t RRR R, t Function No operation Clear Watchdog timer Sleep mode Load W to TMODE register Return from subroutine Control I/O port register Store W to register Load register Load immediate to W Swap halves register Increment register None 0WT 0WT, stop OSC WTMODE StackPC WCPIO r WR Rt IW [R(0~3) R(4~7)]t R + 1t TF, PF TF, PF None None None None Z None None Z None C, HC, Z Operating Status
Increment register, skip if zero R + 1t Add W and register Subtract W from register Decrement register W + Rt
R Wt or (R+/W+1 C, HC, Z t) R 1t Z None Z Z Z Z Z Z Z C
Decrement register, skip if zero R 1t AND W and register AND W and immediate Inclu. OR W and register Inclu. OR W and immediate Exclu. OR W and register Exclu. OR W and immediate Complement register Rotate right register R Wt i WW R Wt i WW R Wt i WW /Rt R(n) R(n-1), CR(7), R(0)C
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P. 13
2007/11 VER1.2
MDT10P7212
Instruction Code 010101 trrrrrrr 010000 1xxxxxxx 010001 0rrrrrrr 0000bb brrrrrrr 0010bb brrrrrrr 0001bb brrrrrrr 0011bb brrrrrrr 100nnn nnnnnnnn 101nnn nnnnnnnn 110111 iiiiiiii 110001 iiiiiiii 111000 iiiiiiii 010000 00001001 Note : W WT TMODE CPIO TF PF PC OSC Inclu. Exclu. AND : : : : : : : : : : : Working register Watchdog timer TMODE mode register Control I/O port register Timer overflow flag Power loss flag Program Counter Oscillator Inclusive `' Exclusive `' Logic AND `' b t : : 0 1 R : C : HC : Z : / : x : i : n : Bit position Target : Working register : General register General register address Carry flag Half carry Zero flag Complement Don't care Immediate data ( 8 bits ) Immediate address Mnemonic Operands RLR CLRW CLRR BCR BSR R R, b R, b R, t Function Rotate left register Clear working register Clear register Bit clear Bit set Bit Test, skip if clear Bit Test, skip if set Long CALL subroutine Long JUMP to address Add immediate to W Operating R(n)r(n+1), CR(0), R(7)C 0W 0R 0R(b) 1R(b) Skip if R(b)=0 Skip if R(b)=1 nPC, PC+1Stack nPC W+iW Status C Z Z None None None None None None C,HC,Z None C,HC,Z None
BTSC R, b BTSS R, b LCALL n LJUMP n ADDWI i RTWI i
Return, place immediate to W StackPC,iW Subtract W from immediate Reture from interrupt i-WW StackPC,1GIS
SUBWI i RTFI
This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw
P. 14
2007/11 VER1.2

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