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DVIULC6-2x6
Ultra low capacitance ESD protection
Features

2-line ESD protection (at 15 kV air and contact discharge, exceeds IEC 61000-4-2) Protects VBUS when applicable Ultra low capacitance: 0.6 pF at F = 825 MHz Fast response time compared with varistors Low leakage current: 0.5 A max RoHS compliant
QFN (pin view) DVIULC6-2M6 SOT-666 DVIULC6-2P6
Applications
ESD standards compliance guaranteed at device level, hence greater immunity at system level ESD protection of VBUS when applicable. Large bandwidth to minimize impact on data signal quality Consistent D+ / D- signal balance: - Ultra low impact on intra- and inter-pair skew - Matching high bit rate DVI, and IEEE 1394 requirements Low PCB space consumption - 1.45 mm2 for QFN Low leakage current for longer operation of battery powered devices Higher reliability offered by monolithic integration 500 m pitch for QFN 6 leads

Benefits
DVI ports up to 1.65 Gb/s IEEE 1394a, b, and c up to 3.2 Gb/s USB2.0 ports up to 480 Mb/s (high speed), backwards compatible with USB1.1 low and full speed Ethernet port: 10/100/1000 Mb/s SIM card protection Video line protection

Description
The DVIULC6-2x6 is a monolithic, application specific discrete device dedicated to ESD protection of high speed interfaces, such as DVI, IEEE 1394a, b and c, USB2.0, Ethernet links and video lines. Its ultra low line capacitance secures a high level of signal integrity without compromising in protecting sensitive chips against the most stringently characterized ESD strikes.

Complies with these standards
IEC 61000-4-2 level 4 - 15 kV air discharge - 8 kV contact discharge MIL STD883G-Method 3015-7
May 2008
Rev 1
1/17
www.st.com
Characteristics
DVIULC6-2x6
1
Characteristics
Figure 1. Functional diagram
I/O1
1
6
I/O1
I/O1
1
6
I/O1
GND
2
5
VBUS
GND
2
5
VBUS
I/O2
3
4
I/O2
I/O2
3
4
I/O2
QFN 6 leads
SOT666
When used with a DVI application, Pin 5 should not be connected to protect against backdrive current flow on data lines.
Table 1.
Symbol VPP Tstg Tj TL
Absolute ratings
Parameter Peak pulse voltage Storage temperature range Maximum junction temperature Lead solder temperature (10 seconds duration) IEC61000-4-2 air discharge IEC61000-4-2 contact discharge MIL STD883G-Method 3015-7 Value 15 15 25 -55 to +150 125 260 Unit kV C C C
Table 2.
Symbol IRM VBR
Electrical characteristics (Tamb = 25 C)
Value Parameter Leakage current Breakdown voltage between VBUS and GND Test Conditions Min. Typ. VRM = 5 V IR = 1 mA IPP = 1 A, tp = 8/20 s Any I/O pin to GND IPP = 5 A, tp = 8/20 s Any I/O pin to GND VR = 0 V, F= 825 MHz VR = 0 V, F= 1 MHz VR = 0 V, F= 825 MHz 0.02 0.5 6 12 17 0.85 Max 0.5 A V V V pF pF pF Unit
VCL
Clamping voltage
Ci/o-GND
Capacitance between I/O and GND
Capacitance variation between I/O Ci/o-GND and GND Ci/o-i/o Capacitance between I/O
2/17
DVIULC6-2x6
Characteristics
Figure 2.
Line capacitance versus line voltage (typical values)
C(pF)
Figure 3.
Line capacitance versus frequency (typical values) DVIULC6-2M6
C(pF)
1.0
F=825MHz Vosc=500mVRMS VBUS OPEN Tj =25 C
1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 CI/O - GND
0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2
Vosc=30mVRMS Tj =25C VI-O/GND = 0V VBUS OPEN
CI/O - GND
Data line voltage (v)
0.1
0
CI/O - CI/O
F(MHz)
1 10 100 1000 10000
Figure 4.
Line capacitance versus frequency Figure 5. (typical values) DVIULC6-2P6
0.00
Frequency response (typical values) DVIULC6-2M6
S21(db)
C(pF)
1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 1 10 100 1000 10000
- 16.00 300.0k 1.0M 3.0M 10.0M 30.0M 100.0M 300.0M 1.0G 3.0G
Vosc=30mVrms Tj = 25 C VI-O/GND = 0V VBUS OPEN
Fc=5.9GHz
- 4.00
C I/O - GND
- 8.00
C I/O - I/O
- 12.00
F(MHz)
F(Hz)
Figure 6.
Frequency response (typical values) DVIULC6-2P6
Figure 7.
Relative variation of leakage current versus junction temperature (typical values)
S21(db)
0.00
IRM[Tj] / IRM[Tj=25C]
Fc=5.3GHz
- 4.00
5 4
3
- 8.00
2
- 12.00
F(Hz)
- 16.00 300.0k 1.0M 3.0M Ligne 2 10.0M 30.0M 100.0M 300.0M 1.0G 3.0G
Tj(C)
1 25 50 75 100 125
3/17
Characteristics
DVIULC6-2x6
Figure 8.
Eye diagram at 1.65 Gbps amplitude 500 mV PCB + DVIULC6-2M6
Figure 9.
Eye diagram at 3.2 Gbps amplitude 500 mV PCB + DVIULC6-2M6
Horizontal: 100 ps/div Vertical: 200 mV/div
Horizontal: 50 ps/div Vertical: 200 mV/div
Figure 10. Eye diagram at 1.65 Gbps amplitude 500 mV PCB + DVIULC6-2P6
Horizontal: 100 ps/div Vertical: 200 mV/div
Figure 11. Eye diagram at 3.2 Gbps amplitude 500 mV PCB + DVIULC6-2P6
Horizontal: 50 ps/div Vertical: 200 mV/div
4/17
DVIULC6-2x6
Application examples
2
Application examples
Figure 12. DVI single link application
DVI
Host (Desktop, Notebook) Tx0Tx0+
TMDS transmitter video
1 6 1 6
Rx0Rx0+
TMDS receiver
2
5
2
5
3
4
3
4
Display (flat panel, monitor, projector)
DVI connectors
1 6 1 6 2 5 2 5
Tx1Tx1+
Rx1Rx1+
video
3
4
3
4
Multimedia controller
audio
audio DVIULC6-2M6
controller
1 6
Ctrl / status
Tx2Tx2+
1
6
Rx2Rx2+
2
5
2
5
Ctrl / status
3
4
3
4
TCTC+ CEC SCL Vcc 5V SDA HPD
1
6
1
6
RCRC+ CEC SCL Vcc 5V
2
5
2
5
3
4
3
4
TMDS links
DVIULC6-4SC6
SDA HPD
Control links
Figure 13. T1/E1/Ethernet protection
+VCC
Tx
SMP75-8
100nF
D A TA TRANSCEIVER
+VCC
Rx
SMP75-8
100nF
5/17
Application examples
DVIULC6-2x6
2.1
PCB layout considerations
Figure 14. PCB layout example
Width=100 m Space=400 m
All dimensions in m
3160
3160
Width=215 m PCB Characteristics Space=100 m Substrate: H = 730 m, Er =3.9 Z0diff=100 Tracks: H = 35 m copper Coatinbg: H = 35 m above substrate: H = 10 m above tracks, Er = 3.4 GND plane on the bottom layer
Figure 15. TDR results for DVIULC6-2M6 with PCB layout example
6/17
DVIULC6-2x6
Technical information
3
3.1
Technical information
Surge protection
The DVIULC6-2x6 is particularly optimized to perform ESD surge protection based on the rail to rail topology. The clamping voltage VCL can be calculated as follows: VCL+ = VTRANSIL + VF for positive surges VCL- = - VF with: VF = VT + Rd.Ip (VF forward drop voltage) / (VT forward drop threshold voltage) and VTRANSIL = VBR + Rd_TRANSIL . IP for negative surges
Calculation example
We assume that the value of the dynamic resistance of the clamping diode is typically: Rd = 0.5 and VT = 1.1 V. We assume that the value of the dynamic resistance of the transil diode is typically Rd_TRANSIL = 0.5 and VBR = 6.1 V For an IEC 61000-4-2 surge Level 4 (Contact Discharge: Vg= 8 kV, Rg= 330 ), VBUS = +5 V, and, in first approximation, we assume that: Ip = Vg / Rg = 24 A. We find: VCL+ = +31.2 V VCL- = -13.1 V Note: The calculations do not take into account phenomena due to parasitic inductances.
3.2
Surge protection application example
If we consider that the connections from the pin VBUS to VCC, from I/O to data line, and from GND to PCB GND plane are two tracks 10 mm long and 0.5 mm wide, we can assume that the parasitic inductances, LVBUS, LI/O, and LGND, of these tracks are about 6 nH. So when an IEC 61000-4-2 surge occurs on the data line, due to the rise time of this spike (tr = 1 ns), the voltage VCL has an extra value equal to LI/O.dI/dt + LGND.dI/dt. The dI/dt is calculated as: dI/dt = Ip/tr = 24 A/ns for an IEC 61000-4-2 surge level 4 (contact discharge Vg = 8 kV, Rg = 330 ) The over voltage due to the parasitic inductances is: LI/O.dI/dt = LGND.dI/dt = 6 x 24 = 144 V By taking into account the effect of these parasitic inductances due to unsuitable layout, the clamping voltage will be: VCL+ = +31.2 + 144 +144 = 319.2 V VCL- = -13.1 - 144 -144 = -301.1 V We can reduce as much as possible these phenomena with simple layout optimization.
7/17
Technical information
DVIULC6-2x6
Figure 16. IESD behavior: parasitic phenomena due to unsuitable layout
ESD surge on data line VBUS Data line LI/O VCL+
LI/O
di L VBUS dt
Vcc pin
L I/O
di di + L GND dt dt
POSITIVE SURGE
VF VTRANSIL
I/O pin
VCL
VTRANSIL +VF t
tr=1ns
GND pin
LGND
LGND
di dt
-VF
tr=1ns
t
VCL + = VTRANSIL + VF + L I/O VCL - = - VF - L I/O
di di + L GND dt dt di di - L GND dt dt
surge > 0
- L I/O
surge < 0
di di - L GND dt dt
NEGATIVE SURGE
VTRANSIL = VBR + Rd.Ip
VCL-
Figure 17. ESD behavior - measurement conditions
ESD SURGE TEST BOARD IN OUT
Figure 18. Remaining voltage after the DVIULC6-2M6 during positive ESD surge
10V/Div
Figure 19. Remaining voltage after the DVIULC6-2M6 during negative ESD surge
10V/Div
100ns/Div
100ns/Div
8/17
DVIULC6-2x6
Technical information
Figure 20. Remaining voltage after the DVIULC6-2P6 during positive ESD surge
10V/Div
Figure 21. Remaining voltage after the DVIULC6-26 during negative ESD surge
10V/Div
100ns/Div
100ns/Div
Important
An important precaution to take is to put the protection device as close as possible to the disturbance source (generally the connector).
3.3
Crosstalk behavior
Figure 22. Crosstalk phenomena
RG1 Line 1 1 VG1 + 12VG2
VG1 RG2 Line 2
RL1
VG2
RL2
2VG2 + 21VG1
DRIVERS
RECEIVERS
The crosstalk phenomena is due to the coupling between 2 lines. The coupling factor (12 or 21) increases when the gap across lines decreases, particularly in silicon dice. In the example above the expected signal on load RL2 is 2VG2, in fact the real voltage at this point has got an extra value 21VG1. This part of the VG1 signal represents the effect of the crosstalk phenomenon of the line 1 on the line 2. This phenomenon has to be taken into account when the drivers impose fast digital data or high frequency analog signals in the disturbing line. The perturbed line will be more affected if it works with low voltage signal or high load impedance (few k).
9/17
Technical information Figure 23. Analog crosstalk measurements
TEST BOARD NETWORK ANALYSER PORT 1 NETWORK ANALYSER PORT 2
DVIULC6-2x6
Figure 23 gives the measurement circuit for the analog application. In usual frequency range of analog signals (up to 240 MHz) the effect on disturbed line is less than -40 dB (see Figure 24, and Figure 25). Figure 24. Analog crosstalk results (typical values) for DVIULC6-2M6
dB
0.00
-7.6dB@7GHz
- 30.00
- 60.00
- 90.00
F (Hz)
- 120.00 300.0k 1.0M 3.0M 10.0M 30.0M 100.0M 300.0M 1.0G 3.0G
Figure 25. Analog crosstalk results (typical values) for DVIULC6-2P6
dB
0.00
7.2dB@7GHz
- 30.00
- 60.00
- 90.00
F (Hz)
- 120.00 300.0k 1.0M 3.0M 10.0M 30.0M 100.0M 300.0M 1.0G 3.0G
10/17
DVIULC6-2x6
Recommendation on PCB assembly
4
4.1
Recommendation on PCB assembly
Stencil opening design
1. General recommendation on stencil opening design a) Stencil opening dimensions: L (Length), W (Width), T (Thickness)
Figure 26. Stencil opening dimensions.
L
T
W
b)
General Design Rule Stencil thickness (T) = 75 ~ 125 m W Aspect Ratio = ---- 1.5 T LxW Aspect Area = --------------------------- 0.66 2T ( L + W )
2.
Reference design a) b) Stencil opening thickness: 100 m Stencil opening for leads: Opening to footprint ratio is 90%.
Figure 27. Recommended stencil window position (QFN only)
7 m
7 m 15 m
650 m
620 m 236 m 15 m 250 m
Footprint
Stencil window Footprint
11/17
Recommendation on PCB assembly
DVIULC6-2x6
4.2
Solder paste
1. 2. 3. 4. Halide-free flux qualification ROL0 according to ANSI/J-STD-004. "No clean" solder paste is recommended. Offers a high tack force to resist component movement during high speed. Solder paste with fine particles: powder particle size is 20-45 m.
4.3
Placement
1. 2. 3. 4. Manual positioning is not recommended. It is recommended to use the lead recognition capabilities of the placement system, not the outline centering. Standard tolerance of 0.05 mm is recommended. 3.5 N placement force is recommended. Too much placement force can lead to squeezed out solder paste and cause solder joints to short. Too low placement force can lead to insufficient contact between package and solder paste that could cause open solder joints or badly centered packages. To improve the package placement accuracy, a bottom side optical control should be performed with a high resolution tool. For assembly, a perfect supporting of the PCB (all the more on flexible PCB) is recommended during solder paste printing, pick and place and reflow soldering by using optimized tools.
5. 6.
4.4
PCB design preference
1. 2. To control the solder paste amount, the closed via is recommended instead of open vias. The position of tracks and open vias in the solder area should be well balanced. The symmetrical layout is recommended, in case any tilt phenomena caused by asymmetrical solder paste amount due to the solder flow away.
12/17
DVIULC6-2x6
Recommendation on PCB assembly
4.5
Reflow profile
Figure 28. ST ECOPACK(R) recommended soldering reflow profile for PCB mounting
Temperature (C)
260C max 255C 220C 180C 125 C
2C/s recommended 2C/s recommended 6C/s max 6C/s max
3C/s max 3C/s max
0 0 1 2 3 4 5
10-30 sec 90 to 150 sec 90 sec max
6
7
Time (min)
Note:
Minimize air convection currents in the reflow oven to avoid component movement.
13/17
Package information
DVIULC6-2x6
5
Package information
Epoxy meets UL94, V0
In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a lead-free second level interconnect. The category of second level interconnect is marked on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at www.st.com. Table 3. Micro QFN 1.45x1.00 6L dimensions
Dimensions
D
N
Ref.
E
Millimeters Min. Typ. 0.55 0.02 0.25 1.45 1.00 0.50 0.20 0.30 0.35 0.40 0.008 Max. 0.60 0.05 0.30 Min.
Inches Typ. Max.
1
2
A A1
0.50 0.00 0.18
0.020 0.022 0.024 0.000 0.001 0.002 0.007 0.010 0.012 0.057 0.039 0.020
A A1
1 2
b D
L k b e
E e K L
0.012 0.014 0.016
Figure 29. QFN 6 leads footprint dimensions in mm [inches]
0.50 [0.020]
0.25 [0.010]
0.65 [0.026] 0.30 1.60 [0.012] [0.063]
Note:
Product marking may be rotated by 90 for assembly plant differentiation. In no case should this product marking be used to orient the component for its placement on a PCB. Only pin 1 mark is to be used for this purpose.
14/17
DVIULC6-2x6 Table 4. SOT-666 dimensions
Package information
Dimensions
b1 L1
Ref.
Millimeters Min. Typ. Max. Min.
Inches Typ. Max. 0.024 0.007 0.013
L3 b
A A3 b
D E1
0.45 0.08 0.17 0.19 1.50 1.50 1.10 0.50 0.19 0.10 0.10 0.27
0.60 0.018 0.18 0.003 0.34 0.007
b1 D
0.34 0.007 0.011 0.013 1.70 0.059 1.70 0.059 1.30 0.043 0.020 0.007 0.30 0.004 0.004 0.012 0.067 0.067 0.051
A
E
L2 E A3
E1 e L1 L2
e
L3
Figure 30. Footprint (dimensions in mm)
0.50
0.62
2.60
0.99
0.30
15/17
Ordering information
DVIULC6-2x6
6
Ordering information
Table 5. Ordering information
Marking T(1) R Package QFN 6 leads SOT-666 Weight 2.2 mg 2.9 mg Base qty 3000 3000 Delivery mode Tape and reel Tape and reel
Order code DVIULC6-2M6 DVIULC6-2P6
1. The marking can be rotated by 90 to diferentiate assembly location
7
Revision history
Table 6. Document revision history
Date 06-May-2008 Revision 1 First issue. Description of changes
16/17
DVIULC6-2x6
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