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| Agilent HMMC-3102 DC - 16 GHz Packaged Divide-by-2 Prescaler HMMC-3102-TR1 - 7" diameter reel/500 each HMMC-3102-BLK - Bubble strip/10 each Data Sheet Features * Wide Frequency Range: 0.2-16 GHz * High Input Power Sensitivity: On-chip pre- and post-amps t -20 to +10 dBm (1-10 GHz) len i Ag -15 to +10 dBm (10-12 GHz) -10 to +5 dBm (12-15 GHz) * Pout: +6 dBm (0.99 Vp-p) will drive ECL * Low Phase Noise: -153 dBc/Hz @ 100 kHz Offset Package Type: 8-lead SSOP Plastic * (+) or (-) Single Supply Bias Package Dimensions: 4.9 x 3.9 mm Typ. with wide range: Package Thickness: 1.55 mm Typ. 4.5 to 6.5 V Lead Pitch: 1.25 mm Nom. * Differential I/0 with on-chip Lead Width: 0.42 mm Nom. 50 matching [1] Absolute Maximum Ratings (@ TA=25C, unless otherwise indicated) Description The HMMC-3102 is a packaged GaAs HBT MMIC prescaler which offers DC to 16 GHz frequency translation for use in communications and EW systems incorporating high-frequency PLL oscillator circuits and signal-path down conversion applications. The prescaler provides a large input power sensitivity window and low phase noise. Symbol VCC VEE |VCC VEE| VLogic Pin(CW) VRFin TBS[2] Tst Tmax Parameters/Conditions Bias Supply Voltage Bias Supply Voltage Bias Supply Delta Logic Threshold Voltage CW RF Input Power DC Input Voltage (@ RFin or RFin Ports) Backside Operating Temp. Storage Temperature Maximum Assembly Temp. (60 seconds max.) Min. Max. +7 Units volts volts -7 +7 VCC-1.5 VCC-1.2 +10 VCC 0.5 -40 -65 +85 +165 310 volts volts dBm volts C C C BS) may cause permanent damage to the device. [2] MTTF >5x105 hours @ TBS <85C. Operation in excess of maximum operating temperature (TBS) will degrade MTTF. [1]Operation in excess of any parameter limit (except T 6-53 DC Specifications/Physical Properties Symbol Parameters/Conditions [1] (TA = 25C, VCC - VEE = 5.0 volts, unless otherwise listed) Min. 4.5 68 Typ. 5.0 80 VCC VCC - 1.45 VCC -1.35 VCC -1.25 Max. 6.5 92 Units volts mA volts volts VCC - VEE Operating bias supply difference |ICC| or |IEE| Bias supply current VRFin(q) Quiescent DC voltage appearing at all RF ports VRFout(q) Nominal ECL Logic Level VLogic (VLogic contact self-bias voltage, generated on-chip) [1] Prescaler will operate over full specified supply voltage range. V CC or VEE not to exceed limits specified in Absolute Maximum Ratings section. RF Specifications (TA = 25C, Z0 = 50, VCC - VEE = 5.0 volts) Symbol in(max) in(min) Self-Osc. Parameters/Conditions Maximum input frequency of operation Minimum input frequency of (Pin = -10 dBm) Output Self-Oscillation Frequency[2] @ DC, (Square-wave input) @ in = 500 MHz, (Sine-wave input) in = 1 to 10 GHz in = 10 to 12 GHz in = 12 to 15 GHz Small-Signal Input/Output Return Loss (@in< 12 GHz) Small-Signal Reverse Isolation (@in< 12 GHz) SSB Phase noise (@ Pin = 0 dBm, 100kHz offset from a out = 1.2 GHz Carrier) Input signal time variation @ zero-crossing (in = 10 GHz, Pin = -10 dBm) Output transition time (10% to 90% rise/fall time) @ out < 1 GHz @ out = 2.5 GHz @ out = 3.5 GHz @ out <1 GHz @ out = 2.5 GHz @ out = 3.5 GHz out power level appearing at RFin or RFin (@ in 12 GHz, Unused RFout or RFout unterminated) out power level appearing at RFin or RFin (@ in = 12 GHz, Both RFout & RFout terminated) Power level of in appearing at RFout or RFout (@ in = 12 GHz, Pin = 0 dBm, Referred to Pin(in)) Second harmonic distortion output level (@ out = 3.0 GHz, Referred to Pout(out)) operation[1] Min. 16 Typ. 18 0.2 -15 -15 -15 -10 -4 3.4 >-25 >-20 >-25 >-15 >-10 15 30 -153 1 4 3.5 0 70 6 5.5 2.0 0.99 0.94 0.63 -40 0.5 +10 +10 +10 +10 +4 Max. Units GHz GHz GHz dBm dBm dBm dBm dBm dB dB dBc/Hz ps ps dBm dBm dBm volts volts volts dBm Pin RL S12 N Jitter r or f Pout[3] |Vout(p-p)|[4] PSpitback -47 dBm Pfeedthru H2 -23 -25 dBc dBc [1]For sine-wave input signal. Prescaler will operate down to D.C. for square-wave input signal. Minimum divide frequency limited by input slew-rate. Prescaler can exhibit this output signal under bias in the absence of an RF input signal. This condition can be eliminated by use of the Input DC offset technique described on page 3. [3] Fundamental of output square wave's Fourier Series. [4] Square wave amplitude calculated from Pout. [2] 6-54 HMMC-3102/rev.3.3 Applications The HMMC-3102 is designed for use in high frequency communications, microwave instrumentation, and EW radar systems where low phase-noise PLL control circuitry or broad-band frequency translation is required. For positive supply operation, VCC pins are nominally biased at any voltage in the +4.5 to +6.5 volt range with pin 8 (VEE) grounded. For negative bias operation VCC pins are typically grounded and a negative voltage between -4.5 to 6.5 volts is applied to pin 8 (VEE). Operation The device is designed to operate when driven with either a singleended or differential sinusoidal input signal over a 200 MHz to 16 GHz bandwidth. Below 200 MHz the prescaler input is "slew-rate" limited, requiring fast rising and falling edge speeds to properly divide. The device will operate at frequencies down to DC when driven with a square-wave. Due to the presence of an off-chip RF-bypass capacitor inside the package (connected to the VCC contact on the device), and the unique design of the device itself, the component may be biased from either a single positive or single negative supply bias. The backside of the package is not DC connected to any DC bias point on the device. AC-Coupling and DCBlocking All RF ports are DC connected on-chip to the VCC contact through on-chip 50 resistors. Under any bias conditions where VCC is not DC grounded the RF ports should be AC coupled via series capacitors mounted on the PC-board at each RF port. Only under bias conditions where VCC is DC grounded (as is typical for negative bias supply operation) may the RF ports be direct coupled to adjacent circuitry or in some cases, such as level shifting to subsequent stages. In the latter case the package heat sink may be "floated" and bias applied as the difference between VCC and VEE. nal to noise ratio is present at the RF input lead, the prescaler will operate and provide a divided output equal the input frequency divided by the divide modulus. Under certain "ideal" conditions where the input is well matched at the right input frequency, the component may "self-oscillate", especially under small signal input powers or with only noise present at the input This "self-oscillation" will produce a undesired output signal also known as a false trigger. To prevent false triggers or self-oscillation conditions, apply a 20 to 100 mV DC offset voltage between the RFin and RFin ports. This prevents noise or spurious low level signals from triggering the divider. Adding a 10K resistor between the unused RF input to a contact point at the VEE potential will result in an offset of 25mV between the RF inputs. Note however, that the input sensitivity will be reduced slightly due to the presence of this offset. Input DC Offset If an RF signal with sufficient sig- Assembly Notes Independent of the bias applied to the package, the backside of VCC VCC VCC IN IN / OUT OUT SOIC8 w/Backside GND VEE Figure 1. Simplified Schematic HMMC-3102/rev.3.3 6-55 the package should always be connected to both a good RF ground plane and a good thermal heat sinking region on the PCboard to optimize performance. For single-ended output operation the unused RF output lead should be terminated into 50 to a contact point at the VCC potential or to RF ground through a DC blocking capacitor. A minimum RF and thermal PC VCC RFin VCC board contact area equal to or greater than 2.67 x 1.65 mm (0.105" x 0.065") with eight 0.020" diameter plated-wall thermal vias is recommended. .GaAs MMICs are ESD sensitive. ESD preventive measures must be employed in all aspects of storage, handling, and assembly. tors in successful GaAs MMIC performance and reliability. Agilent application note #54, "GaAs MMIC ESD, Die Attach and Bonding Guidelines" provides basic information on these subjects. Additional References: PN #18, "HBT Prescaler Evaluation Board." MMIC ESD precautions, handling Notes: considerations, die attach and bonding methods are critical fac- *All dimensions in millimeters. RFin *Refer to JEDEC Outline MS-012 for additional tolerances SYMBOL MIN. MAX. Agilent VCC RFin VEE HMMC-3102 9618 Exposed heat sink on package bottom must be soldered to PCB rf ground plane. VEE RFout A 1.35 1.75 A1 0.0 .25 B 0.33 0.51 C 0.19 .025 D 4.80 5.00 E 3.80 4.00 e 1.27 BSC H 5.80 6.20 L 0.40 1.27 a 0 8 *Exposed heat slug area on pkg bottom = 2.67 x 1.65. *Exposed heat sink on package bottom must be soldered to PCB rf ground plane. VCC RFout Figure 2. Package & Dimensions VCC (+4.5 to +6.5 volts) ~ 1 mf Monoblock Capacitor To operate component from a negative supply, ground each VCC connection and supply VEE with a negative voltage (-4.5 to -6.5v) bypassed to ground with ~ 1 f capacitor. RFin VCC RFout VCC RFout RFout should be terminated in 50 to ground. (DC blocking capacitor required for positive bias configuration.) Figure 3. Assembly Diagram (Single-Supply, positive-bias configuration shown) 6-56 HMMC-3102/rev.3.3 Supplemental Data: (VCC-VEE=+5 volts, TA=25C) (TA=25C) 20 20 100 100 90 90 80 80 70 70 0.0 0.0 -0.2 -0.2 -0.4 -0.4 -0.6 -0.6 -0.8 -0.8 -1.0 -1.0 -1.2 -1.2 -1.4 -1.4 -1.6 -1.6 10 10 Input Power, Pin (dBm) ISupply (mA) 0 0 60 60 50 50 40 40 30 30 20 20 -10 -10 -20 -20 -30 -30 -40 -40 0 0 2 2 4 4 6 6 8 8 10 10 12 12 14 14 16 16 18 18 20 20 10 10 00 Input Frequency, in (GHz) 0 0 1 1 2 2 3 3 VCC - VEE (volts) 4 4 5 5 6 6 7 7 8 8 9 9 -1.8 -1.8 -2.0 -2.0 Figure 4. Typical Input Sensitivity Window Figure 5. Typical Supply Current & VLogic vs. Supply Voltage (VCC - VEE = +5 volts, TA=25C) (Low Pout Mode, Tr=~70 pS, Output Freq:882 MHz, TA = 25C) Output Voltage (80 mV / div.) Pout (@ Pin=0dBm), dBm 8 8 6 6 4 4 2 2 0 0 -2 -2 -4 -4 -6 -6 -8 -8 Period (200 pS / div.) 0 0 1 1 2 2 Output Frequency (GHz) 3 3 4 4 5 5 6 6 7 7 8 8 Figure 6. Typical Output Voltage Waveform Figure 7. Typical Output Power vs. Output Frequency, out (GHz) 0 0 -10 -10 -20 -20 -30 -30 -40 -40 -50 -50 -60 -60 -70 -70 -80 -80 -90 -90 -100 -3 Pin=0 dBm, Fcarrier=6.0 GHz (VCC -VEE+5 volts, Pin=0 dBm,TA=25C) SSB Phase Noise (dBc/Hz) -23 -43 -63 -83 -103 -123 -143 -163 10 100 1K 10K 100K 1M 10M PSpitback (dBm) Unterminated RFout Port Both RFout Ports Terminated Offset From Carrier (Hz) -100 0 0 2 2 4 4 Input Frequency, in (GHz) 6 6 8 8 10 10 12 12 14 14 16 16 18 18 20 20 Figure 8. Typical Phase Noise Performance Figure 9. Typical HMMC-3102 "Spitback" Power HMMC-3102/rev.3.3 VLogic - VCC (volts) 6-57 Device Orientation Reel Tape User Feed Direction Cover Tape Tape Dimensions and Product Orientation 2.0 0.05 See Note 6 See Note 1 0.30 0.05 4.0 1.5+0.1/-0.0 A 1.75 R0.3 MAX. Bo 5.5 0.05 See Note 6 12.0 0.3 Ko SECTION A-A 1.5 MIN Ao A R0.5 Typical Ao = 6.4mm Bo = 5.2 mm Ko = 2.1 mm 8.0 Notes: 1. 10 sprocket hole pitch cumulative tolerance: 0.2mm. 2. Camber not to exceed 1mm in 100mm. 3. Material: Black Conductive Advantek Polystyrene. 4. Ao and Bo measured on a plane 0.3mm above the bottom of the pocket. 5. Ko measured from a plane on the inside bottom of the pocket to the top surface of the carrier. 6. Pocket position relative to sprocket hole measured as true position of pocket, not pocket hole. This data sheet contains a variety of typical and guaranteed performance data. The information supplied should not be interpreted as a complete list of circuit specifications. In this data sheet the term typical refers to the 50th percentile performance. For additional information contact your local Agilent Technologies sales representative. 6-58 HMMC-3102/rev.3.3 |
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