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TDA7309
DIGITAL CONTROLLED STEREO AUDIO PROCESSOR WITH LOUDNESS
1
FEATURES
INPUT MULTIPLEXER: 3 STEREO INPUTS RECORD OUTPUT FUNCTION LOUDNESS FUNCTION VOLUME CONTROL IN 1dB STEPS INDEPENDENT LEFT AND RIGHT VOLUME CONTROL SOFT MUTE FUNCTION ALL FUNCTIONS PROGRAMMABLE VIA SERIAL I2C BUS
Figure 1. Packages

DIP20
SO20
Table 1. Order Codes
Part Number TDA7309 TDA7309D TDA7309D013TR Package DIP20 SO20 Tape & Reel

2
DESCRIPTION
The TDA7309 is a control processor with independent left and right volume control for quality audio applications. Selectable external loudness and soft mute functions are provided. Control is accomplished by serial I2C bus microprocessor interface. Figure 2. Block Diagram
The AC signal setting is obtained by resistor networks and switches combined with operational amplifiers. Thanks to the used BIPOLAR/CMOS Technology, Low Distortion, Low Noise and Low DC stepping are obtained.
100nF Recout(L) 3x 2.2F 17 18 LEFT INPUTS 20 VOLUME + LOUDNESS MUTE 2 1 LOUD(L) 19
OUT LEFT
INPUT SELECTOR 3x 2.2F 14 13 RIGHT INPUTS 11 VOLUME + LOUDNESS SOFT MUTE SERIAL BUS DECODER + LATCHES
6 4 5 8
DIGGND SDA SCL ADDR CSM BUS
3
SUPPLY
TDA7309
MUTE 15 CREF 10 Recout(R) 22F 12 LOUD(R)
9
OUT RIGHT
16 VS
7 AGND
D93AU045A
100nF
March 2006
Rev. 6 1/14
TDA7309
Figure 3. Pin Description
RecoutL OUTL CSM SDA SCL DGND GND ADD OUTR RecoutR 1 2 3 4 5 6 7 8 9 10
D94AU058A
20 19 18 17 16 15 14 13 12 11
IN3L LOUDL IN2L IN1L VS CREF IN1R IN2R LOUDR IN3R
Table 2. Absolute Maximum Ratings
Symbol VS Tamb Tstg Parameter Operating Supply Voltage Operating Ambient Temperature Storage Temperature Range Value 10.5 -40 to 85 -55 to +150 Unit V C C
Table 3. QUICK REFERENCE DATA
Symbol VS VCL THD S/N Sc Parameter Operating Supply Voltage Max. Input Signal Handling Total Harmonic Distortion Signal to Noise Ratio Channel Separation f = 1KHz Volume Control 1.0dB step Soft Mute Attenuation Direct Mute Attenuation -95 60 100 V = 1Vrms, f = 1KHz Test Condition Min. 6 2 0.01 106 100 0 0.1 Typ. Max. 10 Unit V Vrms % dB dB dB dB dB
Table 4. Thermal Data
Symbol Rth j-pins Parameter Thermal resistance Junction to Pins SO20 150 DIP20 100 Unit C/W
Figure 4. Test Circuit
IN1L IN2L IN3L RecoutL 17 18 20 1 2 16 OUTL VS CREF AGND OUTR ADD 3 CSM
IN1R IN2R IN3R RecoutR
TDA7309
14 13 11 10 LL 19 LR 12 5 SCL 4 SDA 6 DIGGND
15 7 9 8
D94AU057A
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Table 5. Electrical Characteristcs (Refer to the test circuit, Tamb = 25C, VS = 9V, RL = 10K, RG = 50, all controls flat (G = 0), f = 1KHz unless otherwise specified.)
Symbol SUPPLY VS IS SVR RI Sin CRANGE AVMAX ASTEP EA ET VDC Amute Td Supply Voltage Supply Current Ripple Rejection Input Resistance Input Separation Control Range Max. Attenuation Step resolution Attenuation Set Error Tracking Error DC Steps Output Mute Attenuation Delay Time Csmute = 22nF; 0 to -20dB Fast Mode Slow Mode AUDIO OUTPUTS VCLIP RL Rout VDC GENERAL eNO Output Noise BW = 20-20KHz, flat; output muted all gains = 0dB A curve all gains = 0dB Et S/N d SC
VIL
Parameter
Test Condition
Min. 5 (*) 60 35 80
Typ. 9 7 85 50 90 92
Max. 10 10
Unit V mA dB
INPUT SELECTORS 65 K dB dB 95 1.5 1.2 2 2 adjacent attenuation steps from 0dB to AV max 80 SOFT MUTE 1 20 2 2 100 200 3.8 2.5 5 3 0 0 95 80 106 0.01 100 1 3 Vin = 0.4V IO = 1.6mA -5 0.4 +5 0.8 0.1 1 2 15 300 2.6 ms ms Vrms K V V V V dB dB dB % dB V V A V 0 0.5 100 3 5 dB dB dB dB dB mV mV dB
VOLUME CONTROL 87 0.5 AV = 0 to -24dB AV = -24 to -56dB -1.2 -3 92 1
Clipping Level Output Load Resistance Output Impedance DC Voltage Level
d = 0.3%
Total Tracking Error Signal to Noise Ratio Distortion Channel Separation Input Low Voltage Input High Voltage Input Current Output Voltage SDA Acknowledge
AV = 0 to -24dB AV = -24 to -56dB all gains = 0dB; VO = 1Vrms
BUS INPUTS VIH IIN VO
(*) Hedevice work until 5V but no guarantee about SVR
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TDA7309
Figure 5. Noise vs. Volume Setting. Figure 8. THD vs. RLOAD.
Figure 6. SVRR vs. Frequency.
Figure 9. Channel Separation vs. Frequency.
Figure 7. THD vs. frequency
Figure 10. Output Clip Level vs. Supply Voltage.
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TDA7309
Figure 11. Quiescen Current vs. Supply Voltage Figure 13. Loudness vs. Frequency (CLOAD = 100nF) vs. Volume
Figure 12. Loudness vs. Volume Attenuation
Figure 14. Loudness vs. External Capacitors
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TDA7309
3
I2C BUS INTERFACE
Data transmission from microprocessor to the TDA7313 and viceversa takes place thru the 2 wires I2C BUS interface, consisting of the two lines SDA and SCL (pull-up resistors to positive supply voltage must be connected). 3.1 Data Validity As shown in fig. 11, the data on the SDA line must be stable during the high period of the clock. The HIGH and LOW state of the data line can only change when the clock signal on the SCL line is LOW. 3.2 Start and Stop Conditions As shown in fig. 16 a start condition is a HIGH to LOW transition of the SDA line while SCL is HIGH. The stop condition is a LOW to HIGH transition of the SDA line while SCL is HIGH. 3.3 Byte Format Every byte transferred on the SDA line must contain 8 bits. Each byte must be followed by an acknowledge bit. The MSB is transferred first. 3.4 Acknowledge The master (P) puts a resistive HIGH level on the SDA line during the acknowledge clock pulse (see fig. 17). The peripheral (audioprocessor) that acknowledges has to pull-down (LOW) the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during this clock pulse. The audioprocessor which has been addressed has to generate an acknowledge after the reception of each byte, otherwise the SDA line remains at the HIGH level during the ninth clock pulse time. In this case the master transmitter can generate the STOP information in order to abort the transfer. 3.5 Transmission without Acknowledge Avoiding to detect the acknowledge of the audioprocessor, the P can use a simplier transmission: simply it waits one clock without checking the slave acknowledging, and sends the new data. This approach of course is less protected from misworking and decreases the noise immunity. Figure 15. Data Validity on the I2CBUS
SDA
SCL DATA LINE STABLE, DATA VALID CHANGE DATA ALLOWED
D99AU1031
Figure 16. Timing Diagram of I2CBUS
SCL I2CBUS SDA
D99AU1032
START
STOP
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TDA7309
Figure 17. Acknowledge on the I2CBUS
SCL
1
2
3
7
8
9
SDA MSB START
D99AU1033
ACKNOWLEDGMENT FROM RECEIVER
Table 6. SDA, SCL I2CBUS Timing
Symbol fSCL tBUF tHD:STA tLOW tHIGH tSU:STA tHD:DA tSU:DAT tR tF tSU:STO SCL clock frequency Bus free time between a STOP and START condition Hold time (repeated) START condition. After this period, the first clock pulse is generated LOW period of the SCL clock HIGH period of the SCL clock Set-up time for a repeated START condition Data hold time Data set-up time Rise time of both SDA and SCL signals Fall time of both SDA and SCL signals Set-up time for STOP condition Parameter Min. 0 1.3 0.6 1.3 0.6 0.6 0.300 100 20 20 0.6 300 300 Typ. Max. 400 Unit kHz s s s s s s ns ns (*) ns (*) s
All values referred to VIH min. and VIL max. levels (*) Must be guaranteed by the I2C BUS master.
Figure 18. Definition of Timing on the I2C-bus
SDA tBUF tR tF tHIGH tHD;STA tSP tSU;STO
SCL tLOW P S tHD;STA tF tSU;STA tSU;DAT Sr P
tHD;DAT
D95AU314
P = STOP S = START
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TDA7309
4
SOFTWARE SPECIFICATION
4.1 Interface Protocol The interface protocol comprises:

A start condition (s) A chip address byte, containing the TDA7309 address (the 8th bit of the byte must be 0). The TDA7309 must always acknowledge at the end of each transmitted byte. A sequence of data (N-bytes + acknowledge) A stop condition (P)

Figure 19.
ACK = Acknowledge S = Start P = Stop MAX CLOCK SPEED 400kbits/s Table 7. Chip address
MSB 0 0 0 0 1 1 1 1 0 0 0 0 1 0 LSB 0 0 pin address open pin address close to ground
Table 8. Function Codes
MSB VOLUME MUTE/LOUD INPUTS CHANNEL 0 1 1 1 F6 X 0 0 1 F5 X 0 1 0 F4 X X X X F3 X X X X F2 X X X X F1 X X X X LSB X X X X
Table 9. Channel Abilitation Codec
MSB 1 F6 1 F5 0 X X X X X X X X X X X X 0 0 1 1 0 1 0 1 F4 F3 F2 F1 LSB FUNCTION channel RIGHT LEFT BOTH BOTH
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4.2 Power on reset condition 11111110 Table 10. Volume Codes
MSB 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 0 0 1 1 0 0 1 1 0 0 1 1 X 0 1 0 1 0 1 0 1 0 1 0 1 X 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 F6 F5 F4 F3 F2 F1 LSB FUNCTION step 1dB 0dB -1dB -2dB -3dB -4dB -5dB -6dB -7dB step 8dB 0dB -8dB -16dB -24dB -32dB -40dB -48dB -56dB -64dB -72dB -80dB -88dB MUTE
Table 11. Mute Loudness Codes
MSB 1 F6 0 F5 0 X X 1 X X 0 1 0 0 0 0 1 0 1 F4 F3 F2 F1 LSB FUNCTION mute/loud slow soft mute on fast soft mute on soft mute off LOUD OFF loud on (10dB) loud on (20dB)
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TDA7309
Table 12. Input Multiplexer Codes
MSB 1 F6 0 F5 1 X X X X X X X X X X X X 0 0 1 1 0 1 0 1 F4 F3 F2 F1 LSB FUNCTION inputs MUTE IN2 IN3 IN1
Purchase of I2C Components of STMicrolectronics, conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specifications as defined by Philips.
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TDA7309
Figure 20. DIP20 Mechanical Data & Package Dimensions
DIM. MIN. a1 B b b1 D E e e3 F I L Z 0.254 1.39
mm TYP. MAX. MIN. 0.010 1.65 0.45 0.25 25.4 8.5 2.54 22.86 7.1 3.93 3.3 1.34 0.055
inch TYP. MAX.
OUTLINE AND MECHANICAL DATA
0.065 0.018 0.010 1.000 0.335 0.100 0.900 0.280 0.155 0.130
DIP20
0.053
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TDA7309
Figure 21. SO20 Mechanical Data & Package Dimensions
mm DIM. MIN. A A1 B C D (1) E e H h L k ddd 10.0 0.25 0.40 2.35 0.10 0.33 0.23 12.60 7.40 1.27 10.65 0.75 1.27 0.394 0.010 0.016 TYP. MAX. 2.65 0.30 0.51 0.32 13.00 7.60 MIN. 0.093 0.004 0.013 0.009 0.496 0.291 0.050 0.419 0.030 0.050 TYP. MAX. 0.104 0.012 0.200 0.013 0.512 0.299 inch
OUTLINE AND MECHANICAL DATA
0 (min.), 8 (max.) 0.10 0.004
(1) "D" dimension does not include mold flash, protusions or gate burrs. Mold flash, protusions or gate burrs shall not exceed 0.15mm per side.
SO20
0016022 D
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TDA7309
Table 13. Revision History
Date January 2004 March 2006 Revision 5 6 Description of Changes First Issue in EDOCS DMS Modified on the page 8/14 the "MAX CLOCK SPEED" to 400kbits/s.
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TDA7309
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