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 DG2307
Vishay Siliconix
High-Speed, Low rON, SPDT Analog Switch
(2:1 Multiplexer)
DESCRIPTION
The DG2307 is a single-pole-double-throw switch/2:1 mux designed for 2 to 5.5 V applications. Using Vishay Siliconix proprietary sub-micro CMOS process, the DG2307 achieves low on-resistance, low power consumption. It is 1.6 V TTL logic compatible across the operation voltage range. With its low rON and low parasitic capacitance character, it is ideal for clock signal and high speed data stream switching. It has low insertion lost and negligible propagation delay. The DG2307 can handle both analog and digital signals and permits signals to be transmitted in either direction. When Bn pin is at off status, the path will have a high impedance with respect to the output. Break before make is guaranteed. As a committed partner to the community and the environment, Vishay Siliconix manufactures this product with the lead (Pb)-free device terminations. For analog switching products manufactured with 100 % matte tin device terminations, the lead (Pb)-free "-E3" suffix is being used as a designator.
FEATURES
* * * * * * Operates From Single 2 ~ 5.5 V SC70-6 Package 5 Switch Connection Between Ports Minimal Propagation Delay TTL Compatible Input Level RoHS Compliant
RoHS
COMPLIANT
APPLICATIONS
* * * * * Cellular Phones PDAs GPS MP3 Data Acquisition
FUNCTIONAL BLOCK DIAGRAM AND PIN CONFIGURATION
SC-70
6- Pin B1 GND B0 1 2 3 Top View Device Marking: G1 6 5 4 S V+ A
TRUTH TABLE
Logic Input (S) 0 1 Function B0 Connected to A B1 Connected to A
ORDERING INFORMATION
Temp Range - 40 to 85 C Package SC70-6 Part Number DG2307DL-T1-E3
Document Number: 73361 S-70852-Rev. B, 30-Apr-07
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DG2307
Vishay Siliconix
ABSOLUTE MAXIMUM RATINGS
Parameter Reference V+ to GND S, A, Ba Continuous Current (Any terminal) Peak Current (Pulsed at 1 ms, 10 % duty cycle) Storage Temperature Power Dissipation (Packages)b (D Suffix) 6-Pin SC70c Limit - 0.3 to + 6 - 0.3 to (V+ + 0.3 V) 50 200 - 65 to 150 250 Unit V mA C mW
Notes: a. Signals on A, or B or S exceeding V+ will be clamped by internal diodes. Limit forward diode current to maximum current ratings. b. All leads welded or soldered to PC Board. c. Derate 3.1 mW/C above 70 C.
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
SPECIFICATIONS
Test Conditions Otherwise Unless Specified Parameter DC Characteristics High Level Input Voltage Low Level Input Voltage VSH VSL V+ = 4.5 V On Resistance RON V+ = 3.0 V On Resistance Matching Between Channels Input Leakage Current Off Stage Switch Leakage On State Switch Leakage Power Supply Power Supply Range Quiescent Supply Current V+ I+ V+ = 5.5 V, VA = VB = V+ or GND Full Room Full 2 5.5 1 10 A RON IS IBN(off) IBN(on) V+ = 2.3 to 5.5 V V+ = 2.3 to 5.5 V VBN = 0 V, IA = - 30 mA VBN = 2.3 V, IA = - 30 mA VBN = 0 V, IA = - 24 mA VBN = 1.5 V, IA = - 24 mA Full Full Full Full Full Full Room Room Room Full Room Full Room Full - 0.1 - 1.0 - 0.1 - 1.0 - 0.1 - 1.0 4 9 6 13.5 0.32 0.31 0.1 - 1.0 0.1 - 1.0 0.1 - 1.0 A 0.7 V+ 0.3 V+ 6 12 9 20 V Symbol V+ = 3.0 V, VS = 0.25 V to 0.7 V+e Tempa Minb Limits - 40 to 85 C Typc Maxb Unit
V+ = 4.5 V, VBN = 0 V, IA = - 30 mA V+ = 3.0 V, VBN = 0 V, IA = - 24 mA V+ = 5.5 V, VA = 5.5 V V+ = 5.5 V, VA/VB = 0 V/5.5 V V+ = 5.5 V, VA/VB = 0 V/5.5 V
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Document Number: 73361 S-70852-Rev. B, 30-Apr-07
DG2307
Vishay Siliconix
SPECIFICATIONS
Test Conditions Otherwise Unless Specified Parameter AC Electrical Characteristics V+ = 2.3 to 2.7 V Prop Delay Timef tPHL/tPLH VA = 0 V V+ = 3.0 to 3.6 V V+ = 4.5 to 5.5 V V+ = 2.3 to 2.7 V Output Enable Timef tPZL/tPZH VLOAD = 2 x V+ for tPZL VLOAD = 0 V for tPZH V+ = 3.0 to 3.6 V V+ = 4.5 to 5.5 V V+ = 2.3 to 2.7 V Output Disable Timef tPLZ/tPHZ VLOAD = 2 x V+ for tPLZ VLOAD = 0 V for tPHZ V+ = 3.0 to 3.6 V V+ = 4.5 to 5.5 V V+ = 2.3 to 2.7 V Break-Before-Make Timed tBBM V+ = 3.0 to 3.65 V V+ = 4.5 to 5.5 V Charge Injectiond Analog Switch Characteristics Off Isolationd Crosstalkd - 3 db Bandwidthd Capacitance Control Pin Capacitanced B Port Off Capacitance Switch Enabled
d
Limits - 40 to 85 C Tempa Full Full Full Room Full Room Full Room Full Room Full Room Full Room Full Full Full Full Room Room Room Room Room Room Room 0.5 0.5 0.5 7 3 - 57.6 - 58.7 250 4.9 6.5 18.5 pF pC Minb Typc 1.2 0.8 0.3 5.9 6.2 4.1 4.5 2.6 2.9 5.9 6.2 4.1 4.5 2.6 2.9 Maxb Unit
Symbol
V+ = 3.0 V, VS = 0.25 V to 0.7 V+e
ns
Q
CL = 0.1 nF, VGEN = 0 V RGEN = 0
V+ = 5 V V+ = 3.3 V
OIRR XTALK BW CIN CIO-B CIO-A(on)
V+ = 5 V, RL = 50 , f = 10 MHz RL = 50 V+ = 0 V V+ = 5 V
dB MHz
A Port Capacitance When
Room
Notes: a. Room = 25 C, Full = as determined by the operating suffix. b. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. c. Typical values are for design aid only, not guaranteed nor subject to production testing. d. Guarantee by design, nor subjected to production test. e. VIN = input voltage to perform proper function. f. Guaranteed by design and not production tested. The bus switch propagation delay is a function of the RC time constant contributed by the on-resistance and the specified load capacitance with an ideal voltage source (zero output impedance) driving the switch.
Document Number: 73361 S-70852-Rev. B, 30-Apr-07
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DG2307
Vishay Siliconix
LOGIC DIAGRAM (POSITIVE LOGIC)
1 B 6 S 3 B 4 A
Figure 1.
TYPICAL CHARACTERISTICS 25 C, unless otherwise noted
14
40 20 V+ = 3.0 V, IB = - 24 mA Loss, OIRR, XTALK (dB) 0 - 20 - 40 - 60 - 80 OIRR XTALK LOSS
rDS(on) - On Resistance ()
12
10
8
6 V+ = 4.5 V, IB = - 30 mA
4
- 100 - 120 10 K
2 0.0
0.5
1.0
1.5
2.0
2.5
100 K
1M
10 M
100 M
1G
VA - Analog Voltage (V)
F - Frequency (Hz)
rDS(on) vs. VA vs. VSUPPLY
Insertion Loss, Off-Isolation, Crosstalk vs. Frequency
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Document Number: 73361 S-70852-Rev. B, 30-Apr-07
DG2307
Vishay Siliconix
AC LOADING AND WAVEFORMS
VLD RL 500 From Output Under Test CL 50 pF RL 500 SW Open GND
TEST
tPLH/tPHL tPLZ/tPZL tPHZ/tPZH
SW
Open
VLD
GND
Load Circuit
Figure 2. AC Test Circuit
tf = 2.5 ns tr = 2.5 ns 90 % Switch Input 10 % tw tPLH tPHL VOH 1.5 V 1.5 V Output Waveform 1 SW at V LD tPZH VOL Output Waveform 2 SW at GND 1.5 V 1.5 V 1.5 V 90 % 1.5 V 10 % tf = 2.5 ns 3.0 V Logic Input 90 % 1.5 V 10 % GND tPZL 10 %
tr = 2.5 ns 90 % 1.5 V GND tPLZ VLD 2 3.0 V
VOL + 0.3 V VOL tPHZ VOH VOH - 0.3 V
Output
0V
Propagation Delay Times
Enable and Disable Time - Low- and High-Level Enabling
Figure 3. AC Waveforms
Notes: a. CL includes probe and jig capacitance. b. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. c. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. d. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 . e. The outputs are measured one at a time with one transition per measurement. f. tPLZ and tPHZ are the same as tdis. g. tPZL and tPZH are the same as tdis. h. tPLH and tPHL are the same as tdis. i. VLD = 2 V+.
Document Number: 73361 S-70852-Rev. B, 30-Apr-07
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DG2307
Vishay Siliconix
TEST CIRCUITS
V+ Logic Input COM VO RL 50 CL 35 pF VIN
H
V+ VNO VNC NO NC IN GND
tr < 5 ns tf < 5 ns
VINL
VNC = VNO VO Switch 0V Output
90 %
tD
tD
CL (includes fixture and stray capacitance)
Figure 4. Break-Before-Make Interval
V+
Rgen + Vgen VIN = 0 - V+
V+ NC or NO IN GND COM VOUT VOUT CL = 0.01 nF IN On
VOUT
Off Q = VOUT x CL
On
IN depends on switch configuration: input polarity determined by sense of switch.
Figure 5. Charge Injection
V+ 10 nF 10 nF V+ NC or NO IN COM COM 0 V, 2.4 V RL GND GND Analyzer V COM Off Isolation = 20 log V NO/ NC NC or NO 0 V, 2.4 V V+ COM Meter IN HP4192A Impedance Analyzer or Equivalent f = 1 MHz V+
Figure 6. Off-Isolation
Figure 7. Channel Off/On Capacitance
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see http://www.vishay.com/ppg?73361.
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Document Number: 73361 S-70852-Rev. B, 30-Apr-07
Legal Disclaimer Notice
Vishay
Disclaimer
All product specifications and data are subject to change without notice. Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively, "Vishay"), disclaim any and all liability for any errors, inaccuracies or incompleteness contained herein or in any other disclosure relating to any product. Vishay disclaims any and all liability arising out of the use or application of any product described herein or of any information provided herein to the maximum extent permitted by law. The product specifications do not expand or otherwise modify Vishay's terms and conditions of purchase, including but not limited to the warranty expressed therein, which apply to these products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document or by any conduct of Vishay. The products shown herein are not designed for use in medical, life-saving, or life-sustaining applications unless otherwise expressly indicated. Customers using or selling Vishay products not expressly indicated for use in such applications do so entirely at their own risk and agree to fully indemnify Vishay for any damages arising or resulting from such use or sale. Please contact authorized Vishay personnel to obtain written terms and conditions regarding products designed for such applications. Product names and markings noted herein may be trademarks of their respective owners.
Document Number: 91000 Revision: 18-Jul-08
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