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Freescale Semiconductor Technical Data
Document Number: MC34119 Rev. 3.0, 12/2006
Low Power Audio Amplifier
The 34119 is a low power audio amplifier integrated circuit intended for telephone applications, such as in speakerphones. It provides differential speaker outputs to maximize output swing at low supply voltages (2.0 V minimum). Coupling capacitors to the speaker are not required. Open loop gain is 80 dB, and the closed loop gain is set with two external resistors. A Chip Disable pin permits powering down and/or muting the input signal. Features * Wide Operating Supply Voltage Range (2.0 V to 16 V), Allows Telephone Line Powered Applications * Low Quiescent Supply Current (2.7 mA Typ) for Battery Powered Applications * Chip Disable Input to Power Down the IC * Low Power--Down Quiescent Current (65 A Typ) * Drives a Wide Range of Speaker Loads (8.0 and Up) * Output Power Exceeds 250 mW with 32 Speaker * Low Total Harmonic Distortion (0.5% Typ) * Gain Adjustable from <0 dB to >46 dB for Voice Band * Requires Few External Components * Pb-Free Packaging Designated by Suffix Code EF
34119
LOW POWER AUDIO AMPLIFIER
D SUFFIX EF SUFFIX (PB-FREE) 98ASB42564B 8-PIN SOICN
ORDERING INFORMATION
Device MC34119D/R2 MCZ34119EF/R2 Temperature Range (TA) -20C to 70C Package
8 SOICN
34199
Audio Input VIN FC1 4 3 6 5
CC
V01
V02 8 2 FC2 1 7 GND CD Chip Disable
Figure 1. 34119 Simplified Application Diagram
Freescale Semiconductor, Inc. reserves the right to change the detail specifications, as may be required, to permit improvements in the design of its products.
(c) Freescale Semiconductor, Inc., 2007. All rights reserved.
INTERNAL BLOCK DIAGRAM
INTERNAL BLOCK DIAGRAM
VCC 7
VIN 4 FC1 3
-+
#1 4.0 k 4.0 k
5
V01
FC2 2
50 k 125 k 50 k
-+
#2 Bias Circuit
8
V02
1 CD
7 GND
Figure 2. 34119 Simplified Internal Block Diagram
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Analog Integrated Circuit Device Data Freescale Semiconductor
PIN CONNECTIONS
PIN CONNECTIONS
CD
1 2 3 4
8 7 6 5
V02
FC2
GND
FC1
VCC
VIN
V01
Figure 3. 34119 Pin Connections Table 1. 34119 Pin Definitions
Pin Number 1 2 3
Pin Name CD FC2 FC1
Definition Chip Disable -- Digital input. A Logic "0" (<0.8 V) sets normal operation. A logic "1" (2.0 V) sets the power down mode. Input impedance is nominally 90 k. A capacitor at this pin increases power supply rejection, and affects turn--on time. This pin can be left open if the capacitor at FC1 is sufficient. Analog ground for the amplifiers. A 1.0 F capacitor at this pin (with a 5.0 F capacitor at Pin 2) provides (typically) 52 dB of power supply rejection. Turn--on time of the circuit is affected by the capacitor on this pin. This pin can be used as an alternate input. Amplifier input. The input capacitor and resistor set low frequency rolloff and input impedance. The feedback resistor is connected to this pin and VO1. Amplifier Output #1. The dc level is (VCC - 0.7 V)/2. DC supply voltage (+2.0 V to +16 V) is applied to this pin. Ground pin for the entire circuit. Amplifier Output #2. This signal is equal in amplitude, but 180 out--of--phase with that at VO1. The dc level is (VCC -- 0.7 V)/2.
4 5 6 7 8
VIN V01 VCC GND V02
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ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
Table 2. Maximum Ratings All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage to the device.
Ratings ELECTRICAL RATINGS Supply Voltage Voltage @ CD (Pin 1) Load Impedance (at VIN) Peak Load Current Differential Gain (5.0 kHz Bandwidth) THERMAL RATINGS Ambient Temperature THERMAL RESISTANCE Peak Package Reflow Temperature During Reflow (1), (2) TPPRT Note 2 C TA -20 70 C VCC VCD RL IL AVD 2.0 0.0 8.0 0.0 16 VCC 200 46 VDC VDC mA dB Symbol Min Max Unit
Notes 1. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause malfunction or permanent damage to the device. 2. Freescale's Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow Temperature and Moisture Sensitivity Levels (MSL), Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes and enter the core ID to view all orderable parts. (i.e. MC33xxxD enter 33xxx), and review parametrics.
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Analog Integrated Circuit Device Data Freescale Semiconductor
ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics Characteristics noted under conditions -1.0 V VCC 18 V, - 20C TA 70C, GND = 0 V unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25C under nominal conditions unless otherwise noted.
Characteristic AMPLIFIERS Output DC Level @ VO1, VO2, VCC = 3.0 V, RL = 16 (RF = 75 k) VCC = 6.0 V VCC = 12 V Output Level High (IOUT = -75 mA, 2.0 V VCC 16 V) Low (IOUT = 75 mA, 2.0 V VCC 16 V) Output DC Offset Voltage (VO1 - VO2) (VCC = 6.0 V, RF = 75 k, RL = 32) Input Bias Current @ VIN (VCC = 6.0 V) Equivalent Resistance @ FC1 (VCC = 6.0 V) @ FC2 (VCC = 6.0 V) CHIP DISABLE Input Voltage Low High Input Resistance (VCC = VCD = 16 V) POWER SUPPLY Power Supply Current (VCC = 3.0 V, RL = , CD = 0.8 V) (VCC= 16 V, RL = , CD = 0.8 V) (VCC = 3.0 V, RL = , CD = 2.0 V) TYPICAL TEMPERATURE PERFORMANCE (-20C < TA < 70C) Input Bias Current @ VIN Total Harmonic Distortion (VCC = 6.0 V, RL = 32, POUT = 125 mW, f = 1.0 kHz) Power Supply Current (VCC = 3.0 V, RL = , CD = 0 V (VCC = 3.0 V, RL = , CD = 2.0 V) ICC -2.5 -0.03 A/C IIN THD 40 0.003 pA/C %/C ICC3 ICC16 ICCD 2.7 3.3 65 4.0 5.0 100 mA mA A VIL VIH RCD 2.0 50 90 0.8 175 k V RFC1 RFC2 100 18 150 25 220 40 IIB VOH VOL VO -30 0.0 -100 30 -200 nA k VCC - 1.0 0.16 mV VO(3) VO(6) VO(12) 1.0 1.15 2.65 5.65 1.25 V V Symbol Min Typ Max Unit
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ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics Characteristics noted under conditions -1.0 V VCC 18 V, - 20C TA 70C, GND = 0 V unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25C under nominal conditions unless otherwise noted.
Characteristic AMPLIFIERS AC Input Resistance (@ VIN) Open Loop Gain (Amplifier #1, f < 100 Hz) Closed Loop Gain (Amplifier #2, VCC = 6.0 V, f = 1.0 kHz, RL = 32) Gain Bandwidth Product Output Power VCC = 3.0 V, RL = 16, THD 10% VCC = 6.0 V, RL = 32, THD 10% VCC = 12 V, RL = 100, THD 10%% Total Harmonic Distortion (f = 1.0 kHz) (VCC = 6.0 V, RL = 32, POUT = 125 mW) (VCC 3.0 V, RL = 8.0, POUT = 20 mW) (VCC 12 V, RL = 32, POUT = 200 mW) Power Supply Rejection (VCC = 6.0 V, VCC = 3.0 V) (C1 = , C2 = 0.01 F) (C1 = 0.1 F, C2 = 0, f = 1.0 kHz) (C1 = 1.0 F, C2 = 5.0 F, f = 1.0 kHz) Differential Muting (VCC = 6.0 V, 1.0 kHz f 20 kHz, CD = 2.0 V) GMT PSRR 50 12 52 > 70 dB POUT3 POUT6 POUT12 THD 0.5 0.5 0.6 1.0 dB 55 240 400 % RI AVOL1 AV2 GBW 80 -0.35 > 30 0.0 1.5 0.35 M dB dB MHz mW Symbol Min Typ Max Unit
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Analog Integrated Circuit Device Data Freescale Semiconductor
ELECTRICAL CHARACTERISTICS ELECTRICAL PERFORMANCE CURVES
ELECTRICAL PERFORMANCE CURVES
PSRR, POWER SUPPLY REJECTION (dB)
60 50 40 30 20 10 0 200
100 80 60 40 20 0 Gain Phase
0 72 108 144 180
EXCESS PHASE (DEGREES) ,
C1 1.0 F
36
C1 = 0.1 F
AVOL (dB)
C1 = 0
100
1.0 k
10 k f, FREQUENCY (Hz)
100 k
1.0 M
1.0 k f, FREQUENCY (Hz) (C2= 5.0F)
10 k
20 k
Figure 4. Amplifier #1 Open Loop Gain and Phase
36 Rf = 150 k, RI = 6.0 k DIFFERENTIAL GAIN (dB) 32 24 16 8 0 100 Rf = 75 k, RI = 3.0 k
Rf 0.1 Input RI -#1 + #2 VO1 VO2 VO
Figure 7. Power Supply Rejection versus Frequency
PSRR, POWER SUPPLY REJECTION (dB) 60 50 40 30 20 10 C1 = 0 0 200 1.0 k f, FREQUENCY (Hz) (C2= 1.0 F) 10 k 20 k C1 = 0.1 F C1 = 5.0 F C1 = 1.0 F
1.0 k 10 k f, FREQUENCY (Hz)
20 k
Figure 5. Differential Gain versus Frequency
PSRR, POWER SUPPLY REJECTION (dB) 60 50 C1 = 0.1 F 40 30 20 10 0 200 C1 = 0 C1 1. F 0
Figure 8. Power Supply Rejection versus Frequency
PSRR, POWER SUPPLY REJECTION (dB) 60 50 C1 = 5.0 F 40 30 20 10 0 200 C1 = 1.0 F C1 = 0.1 F
1.0 k f, FREQUENCY (Hz) (C2= 10 F)
10 k
20 k
1.0 k f, FREQUENCY (Hz) (C2= 0)
10 k
20 k
Figure 6. Power Supply Rejection versus Frequency
Figure 9. Power Supply Rejection versus Frequency
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ELECTRICAL CHARACTERISTICS ELECTRICAL PERFORMANCE CURVES
1000 DEVICE DISSIPATION (mW) 800 600 400 VCC = 3.0 V 200 0
THD, TOTAL HARMONIC DISTORTION (%)
10 8.0 VCC = 3.0 V, RL = 16 6.0 4.0 VCC = 16 V, RL = 32 2.0 0 0 100 200 300 400 500 POUT, OUTPUT POWER (mW) (f 1.0kHz,AVD = 34 dB) = VCC = 6.0 V, RL = 16 VCC = 12 V, RL = 32 VCC = 3.0 V, RL = 8.0 VCC = 6.0 V, RL = 32
VCC = 12 V VCC = 6.0 V
0
30
60
90
120
150
LOAD POWER (mW)
Figure 10. Device Dissipation, 8.0 Load
1200 VCC = 16 V DEVICE DISSIPATION (mW) 1000 800 600 400 200 0 VCC = 3.0 V VCC = 6.0 V VCC = 12 V THD, TOTAL HARMONIC DISTORTION (%) 10
Figure 13. Distortion versus Power
8.0 VCC = 3.0 V, RL = 16 6.0 4.0 2.0 0 0
VCC = 3.0 V, RL = 8.0 VCC = 6.0 V, RL = 32 VCC = 16 V, RL = 32 Limit
0
100
200 LOAD POWER (mW)
300
400
VCC = 12 V, RL = 32 VCC = 6.0 V, RL = 16 100 200 300 400 500 POUT , OUTPUT POWER (mW) (f 3.0kHz,AVD = 34 dB) =
Figure 11. Device Dissipation, 16 Load
1200 DEVICE DISSIPATION (mW) 1000 800 600 400 200 0 0 100 200 300 400 500 LOAD POWER (mW) VCC = 6.0 V VCC = 3.0 V VCC = 16 V VCC = 12 V THD, TOTAL HARMONIC DISTORTION (%) 10 8.0 6.0 4.0 2.0 0 0
Figure 14. Distortion versus Power
VCC = 3.0 V, RL = 16 VCC = 3.0 V, RL = 8.0
VCC = 6.0 V, RL = 32
VCC = 16 V, RL = 32 Limit VCC = 6.0 V, RL = 16 Limit VCC = 12 V, RL = 32
100
200 300 400 POUT , OUTPUT POWER (mW) (f 1,3.0kHz,AVD = 12 dB) =
500
Figure 12. Device Dissipation, 32 Load
Figure 15. Distortion versus Power
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Analog Integrated Circuit Device Data Freescale Semiconductor
ELECTRICAL CHARACTERISTICS ELECTRICAL PERFORMANCE CURVES
500 400 LOAD POWER (mW)
RL = 32
RL = 16 300 200
RL = 8.0
100 0 0 TA = 25C--Derate at higher temperatures 2.0 4.0 6.0 8.0 10 12 14 16 VCC, SUPPLY VOLTAGE (V)
INPUT 80 mV/DIV
OUTPUT 1.0 V/DIV
20 s/DIV
Figure 16. Maximum Allowable Load Power
4.0 I CC , POWER SUPPLY CURRENT (mA) 1.5 CD = 0 3.0 VCC --VOH (V) 1.4 1.3 1.2 1.1 1.0 CD = VCC 0 0 2.0 4.0 6.0 8.0 10 12 14 16 VCC, SUPPLY VOLTAGE (V) 0.9 0.8 0
Figure 19. Large Signal Response
RL =
2.0
2.0 VCC 16 V TA = 25C 40 80 120 160 200
1.0
ILOAD, LOAD CURRENT (mA)
Figure 17. Power Supply Current
Figure 20. VCC-VOH @ V01, V02 versus load Current
1.4
OUTPUT 20 mV/DIV
VOL, OUTPUT LOW LEVEL (V)
1.2 1.0 0.8 0.6 0.4 0.2 0 0
TA = 25C
VCC = 2.0 V
VCC = 3.0 V
INPUT 1.0 mV/DIV
VCC
6.0 V
20 s/DIV
40
80
120
160
200
ILOAD, LOAD CURRENT (mA)
Figure 18. Small Signal Response
Figure 21. VOL @ V01, V02 versus Load Current
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Analog Integrated Circuit Device Data Freescale Semiconductor
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ELECTRICAL CHARACTERISTICS ELECTRICAL PERFORMANCE CURVES
200 AVD, DIFFERENTIAL GAIN (dB) Valid for VCD VCC 0 0 4.0 8.0 12 16 0 100 1.0 k 10 k f, FREQUENCY (Hz) 20 k VCD, CHIP DISABLE VOLTAGE (V) 36 32 24 16 8.0 160 120 80 40
ICD , ( A)
Figure 22. Input Characteristics @ CD (Pin 1)
6 VCC 0.1 3.0 k 0.1 Input 5.0 F 2 50 k 125 k 50 k -+ 4 3
Figure 25. Frequency Response of Figure 24
1000 pF 100 k 100 k 1000 pF
-#1 +
5 4.0 k Speaker 4.0 k 8
0.05 0.05 5.1 k 5.1 k
6 VCC 4 3
#2 Bias Circuit
0.1 Input
-#1 + 50 k 125 k 50 k
5 4.0 k -+ Speaker 4.0 k 8 Bias Circuit 7 GND 1
1
Disable
5.0 F 2
#2
7
Differential Gain = 34 dB Frequency Response: See figure 5 Input Impedance 125 k PSRR 50 dB
GND
Disable
Figure 26. Audio Amplifier with Bandpass
Figure 23. Small Signal Response
75 k 0.05 0.05 5.1 k 5.1 k AVD, DIFFERENTIAL GAIN (dB) 6 VCC 4 3 0.1 Input 5.0 F 2 50 k 125 k 50 k 7 GND -+
36 32 24 16 8.0 0 100
-#1 +
5 4.0 k Speaker 4.0 k 8 Bias Circuit 1
#2
Disable
1.0 k 10 k f, FREQUENCY (Hz)
20 k
Figure 27. Frequency Response of Figure 26 Figure 24. Audio Amplifier with Bass Suppression
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Analog Integrated Circuit Device Data Freescale Semiconductor
ELECTRICAL CHARACTERISTICS ELECTRICAL PERFORMANCE CURVES
Rf 75 k 6 VCC (+1.0 V to +8.0 V) CI RI 0.1 3.0 k Audio Input VIN FC1
4 3
-#1 + 50 k 125 k 50 k
5 4.0 k -+ 4.0 k 8 Bias 1 Circuit 7 VEE (--1.0 V to --8.0 V)
VO1 Speaker
FC2
2
#2
VO2 CD
4700 20 k 20 k Chip Disable
10 k
VCC
NOTE:
If VCC and VEE are not symmetrical about ground then FC1 must be connected through a capacitor to ground as shown on the front page.
VEE
Figure 28. Split Supply Operation
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Analog Integrated Circuit Device Data Freescale Semiconductor
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FUNCTIONAL DESCRIPTION INTRODUCTION
FUNCTIONAL DESCRIPTION
INTRODUCTION
The 34119 is a low power audio amplifier capable of low voltage operation (VCC = 2.0 V minimum), such as that encountered in line-powered speakerphones. The circuit provides a differential output (VO1-VO2) to the speaker to maximize the available voltage swing at low voltages. The differential gain is set by two external resistors. Pins FC1 and FC2 allow control of the amount of power supply and noise rejection, as well as providing alternate inputs to the amplifiers. The CD pin permits power down of the IC for muting purposes and to conserve power.
FUNCTIONAL INTERNAL BLOCK DESCRIPTION AMPLIFIERS
Referring to the Internal Block Diagram on page 2, the internal configuration consists of two identical operational amplifiers. Amplifier #1 has an open loop gain of 80 dB (at f 100 Hz), and the closed loop gain is set by external resistor RF and RI. The amplifier is unity gain stable, and has a unity gain frequency of approximately 1.5 MHz. In order to adequately cover the telephone voice band (300 Hz to 3400 Hz), a maximum closed loop gain of 46 is recommended. Amplifier #2 is internally set to a gain of - 1.0 (0 dB). The outputs of both amplifiers are capable of sourcing and sinking a peak current of 200 mA. The outputs can typically swing to within 0.4 V above ground, and to within 1.3 V below VCC, at the maximum current. See Figures 20 and 21 for VOH and VOL curves. The output dc offset voltage (VO1 - VO2) is primarily a function of the feedback resistor (RF), and secondarily due to the amplifiers' input offset voltages. The input offset voltage of the two amplifiers will generally be similar for a particular IC, and therefore nearly cancel each other at the outputs. Amplifier #1's bias current, however, flows out of VIN (Pin 4) and through RF, forcing VO1 to shift negative by an amount equal to [RF IIB]. VO2 is shifted positive an equal amount. The output offset voltage, specified in the Electrical Characteristics, is measured with the feedback resistor shown in the Typical Applications Circuit, and therefore takes into account the bias current as well as internal offset voltages of the amplifiers. The bias current is constant with respect to VCC. capacitors must charge up through the internal 50 k and 125 k. resistors. The graph of Figure 29 indicates the turn-on time upon application of VCC of +6.0 V. The turn-on time is 60% longer for VCC = 3.0 V, and 20% less for VCC = 9.0 V. Turn-off time is <10 s upon removal of VCC.
360 300 t, TURN--ON TIME (ms) 240 180 120 60 0 0 2.0 4.0 6.0 C1 = 1.0 F VCC switching from 0 V to 6.0 V 8.0 10 C2, CAPACITANCE (F) C1 = 5.0 F
Figure 29. Turn-On Time versus C1 and C2 at Power-On
CHIP DISABLE
The Chip Disable (Pin 1) can be used to power down the IC to conserve power, or for muting, or both. When at a Logic "0" (0 V to 0.8 V), the 34119 is enabled for normal operation. When Pin 1 is at a Logic "1" (2.0 V to VCC V), the IC is disabled. If Pin 1 is open, that is equivalent to a Logic "0," although good design practice dictates that an input should never be left open. Input impedance at Pin 1 is a nominal 90 k. The power supply current (when disabled) is shown in Figure 17. Muting, defined as the change in differential gain from normal operation to muted operation, is in excess of 70 dB. The turn-off time of the audio output, from the application of the CD signal, is <2.0 s, and turn-on time is 12 ms-15 ms. Both times are independent of C1, C2, and VCC. When the 34119 is disabled, the voltages at FC1 and FC2 do not change as they are powered from VCC. The outputs, VO1 and VO2, change to a high impedance condition, removing the signal from the speaker. If signals from other sources are to be applied to the outputs (while disabled), they must be within the range of VCC and Ground.
FC1 AND FC2
Power supply rejection is provided by the capacitors (C1 and C2 in the Typical Applications Circuit) at FC1 and FC2. C2 is somewhat dominant at low frequencies, while C1 is dominant at high frequencies, as shown in the graphs of Figures 6 to 9. The required values of C1 and C2 depend on the conditions of each application. A line powered speakerphone, for example, will require more filtering than a circuit powered by a well regulated power supply. The amount of rejection is a function of the capacitors, and the equivalent impedance looking into FC1 and FC2 (listed in the Electrical Characteristics as RFC1 and RFC2). In addition to providing filtering, C1 and C2 also affect the turn-on time of the circuit at power-up, since the two
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Analog Integrated Circuit Device Data Freescale Semiconductor
FUNCTIONAL DESCRIPTION FUNCTIONAL INTERNAL BLOCK DESCRIPTION
POWER DISSIPATION
Figures 10 to 12 indicate the device dissipation (within the IC) for various combinations of VCC, RL, and load power. The maximum power which can safely be dissipated within the MC34119 is found from the following equation: PD = (140C - TA)/JA where TA is the ambient temperature; and JA is the package thermal resistance (100C/W for the standard DIP package, and 180C/W for the surface mount package.) The power dissipated within the 34119, in a given application, is found from the following equation: PD = (VCC x ICC) + (IRMS x VCC) - (RL x IRMS2) where ICC is obtained from Figure 17; and IRMS is the RMS current at the load; and RL is the load resistance.
Figures 10 to 12, along with Figures 13 to 15 (distortion curves), and a peak working load current of 200 mA, define the operating range for the 34119. The operating range is further defined in terms of allowable load power in Figure 16 for loads of 8.0, 16 and 32. The left (ascending) portion which 10% distortion occurs. The center flat portion of each curve is defined by the maximum output current capability of the 34119. The right (descending) portion of each curve is defined by the maximum internal power dissipation of the IC at 25C. At higher ambient temperatures, the maximum load power must be reduced according to the above equations. Operating the device beyond the current and junction temperature limits will degrade long term reliability.
LAYOUT CONSIDERATIONS
Normally a snubber is not needed at the output of the 34119, unlike many other audio amplifiers. However, the PC board layout, stray capacitances, and the manner in which the speaker wires are configured, may dictate otherwise. Generally, the speaker wires should be twisted tightly, and not more than a few inches in length.
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Analog Integrated Circuit Device Data Freescale Semiconductor
13
TYPICAL APPLICATIONS
TYPICAL APPLICATIONS
RF 75 k 6 CI 0.1 RI 3.0 k VCC
Audio Input
VIN FC1
4 3
-+
#1 4.0 k 4.0 k
5
VO1 Speaker
C1 1.0 F
C2* 5.0F FC2
2
50 k 125 k 50 k
-+
#2 Bias Circuit
8
VO2
1
CD
Chip Disable
7
* = Optional Differential Gain = 2 x
GND
RF RI
This device contains 45 active transistors.
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Analog Integrated Circuit Device Data Freescale Semiconductor
PACKAGING PACKAGE DIMENSIONS
PACKAGING
PACKAGE DIMENSIONS
For the most current package revision, visit www.freescale.com and perform a keyword search using the "98A" listed below.
D SUFFIX EF SUFFIX (PB-FREE) PLASTIC PACKAGE 98ASB42564B ISSUE U
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Analog Integrated Circuit Device Data Freescale Semiconductor
15
REVISION HISTORY
REVISION HISTORY
REVISION 2.0
DATE 11/2006
DESCRIPTION OF CHANGES * * * * Converted to the current Freescale format Implemented Revision History page Removed Peak Package Reflow Temperature During Reflow (solder reflow) parameter from Maximum Ratings on page 4. Added note with instructions from www.freescale.com Updated the Package drawing to the current revision Restated note Freescale's Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow Temperature and Moisture Sensitivity Levels (MSL), Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes and enter the core ID to view all orderable parts. (i.e. MC33xxxD enter 33xxx), and review parametrics. on page 4
3.0
12/2006
*
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Analog Integrated Circuit Device Data Freescale Semiconductor
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MC34119 Rev. 3.0 12/2006

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