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HA16174P/FP
Power Factor Correction Controller IC
REJ03D0789-0100 Rev.1.00 Jan 06, 2006
Description
The HA16174P/FP is a power-factor correction (PFC) controller IC. This IC adopts continuous conduction mode as PFC operation. Various functions such as over voltage detection, over current detection, soft start, feedback-loop disconnection detection, Power Good signal output, and holding function of PFC operation through momentary outage (PFC hold function) are incorporated in a single chip. This eliminates a significant amount of external circuitry. The PFC function enables the continuation of PFC operation for a specified period when a momentary outage occurs, so that quick recovery after a sufficiently momentary outage is achieved*. The continuance time can be adjusted by an external capacitance. The PFC output voltage is monitored by checking the Power Good signal. When the power-factor correction is "good," the Power Good signal is output after a delay time to secure stabilization of the PFC output voltage; when the power factor correction is not good, the output is stopped immediately. The delay time and power good stop level are adjustable by using an external circuit. PFC operation can be turned on and off by an external control signal. By using this function, PFC operation can be disabled at low input voltage, allowing remote control from the secondary side. A soft-start control pin provides for the easy adjustment of soft-start operation, and can be used to prevent overshooting of the output voltage. *: For details on the PFC hold function, refer to page 19.
Features
* Maximum ratings Power-supply voltage Vcc: 24 V Operating junction temperature Tjopr: -40 to 125C * Electrical characteristics VREF output voltage VREF: 5.0 V 3% UVLO operation start voltage VH: 10.5 0.7 V UVLO operation stop voltage VL: 9.0 0.5 V PFC output maximum ON duty Dmax-out: 95% (typ.) * Functions Continuous conduction mode Hold function of PFC operation on momentary outage (PFC hold function) Over voltage detection Over current detection Soft start Feedback loop disconnection detection Power Good signal output (open-drain output) PFC function on/off control Package lineup: SOP-16 and DILP-16
Rev.1.00 Jan 06, 2006 page 1 of 36
HA16174P/FP
Pin Arrangement
OUT GND DELAY PGADJ PFC-ON VREF CAO CS 1 2 3 4 5 6 7 8 (Top view) 16 15 14 13 12 11 10 9 VCC SS EO FB IAC PG CT RT
Pin Description
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Pin Name OUT GND DELAY PGADJ PFC-ON VREF CAO CS RT CT PG IAC FB EO SS VCC I/O Output -- Input/Output Input Input Output Output Input/Output Input/Output Output Output Input Input Output Output Input Function Power MOS FET gate driver output Ground PG start up delay time and hold time adjust and IC shut down PG off threshold voltage input PFC function on/off signal input Reference voltage output Current control error amplifier output Current sense signal input Timing resistor for operational frequency adjust Timing capacitor for operational frequency adjust Power good signal output (open drain output) Multiplier reference current input Voltage control error amplifier input Voltage control error amplifier output Timing capacitor for soft start time adjust Power supply voltage input
Rev.1.00 Jan 06, 2006 page 2 of 36
HA16174P/FP
Block Diagram
VCC
16
5 V Internal Bias
H
10.5 V
VREF
5 V VREF Generator
27.5 V
L
UVLO
9.0 V
6
VREF In GOOD Out
RT 9 CT 10
CAO
770 ns 15.4 s 0.65 V 3.6 V
PFC-DT RAMP
Reset: Vcc<5 V Shut down
R S R S
Q Q
UVL
VREF GOOD
65 kHz
Gate Driver +/- 1.0 A (PEAK)
Q Q
1
VREF
Oscillator 7
VREF
SS
OUT
R S
Q Q
10 A
IMO = K x {IAC x (VEO - 1V)}
DELAY
PFC DELAY
IAC
CAMP
3
1.25 V
12
IAC
O
IMO
VE
VREF
K
55 k 3.3 k
DELAY RESET PG DELAY
CS
CLIMIT
8
Gain Select
K = 0.20
2.50 V
-0.30 V
100 A
EO
Gain Selector
K = 0.05
Shut down
4.0 V
14
2.5 V
2.688 V 2.638 V
B+OVP
VREF
FB
13
VAMP
3.0 V 2.638 V
B+PG RESET
25 A
15 SS
0.50 V
S R
Q
FB LOW
GND
0.95 V
Q
2
PFC-OFF
PFC-ON 5
0.1
Circuit Ground
1.75 V 1.60 V
VREF GOOD
IN OUT PFC DELAY
S R S
Q Q Q Q
B+GOOD
B+PG RESET
PG
DELAY RESET
11
2.40 V
PGADJ 4
S R
Q Q
IN OUT
PG DELAY
R
Rev.1.00 Jan 06, 2006 page 3 of 36
HA16174P/FP
Absolute Maximum Ratings
(Ta = 25C)
Item Supply voltage OUT peak current OUT DC current Terminal voltage CAO voltage EO voltage DELAY voltage PFC-ON voltage PFC-ON clamp current RT current CT current IAC current CS voltage VREF current PG current PGADJ voltage Symbol VCC Ipk-out Idc-out Vi-group1 Vi-group2 Vcao Veo Vdelay Vpfc-on Ipfc-on-clamp Irt Ict Iiac Vi-cs Io-ref Io-pg Vpgadj Ratings 24 1.0 0.1 -0.3 to Vcc -0.3 to Vref -0.3 to Vcaoh -0.3 to Veoh -0.3 to +6.5 -0.3 to +6.5 300 -200 800 1 -1.5 to 0.3 -5 5 2.3 Unit V A A V V V V V V A A A mA V mA mA V Note 3 4 5
Power dissipation Pt 1 W Operating junction temperature Tj-opr -40 to 125 C Storage temperature Tstg -55 to 150 C Notes 1. Rated voltages are with reference to the GND pin. 2. For rated currents, inflow to the IC is indicated by (+), and outflow by (-). 3. The transient current when driving a capacitive load. 4. This is the rated voltage for the following pins: OUT, PG 5. This is the rated voltage for the following pins: VREF, FB, IAC, SS, RT, CT 6. HA16174P (DILP) type: ja = 120C/W 7. HA16174FP (SOP) type: ja = 120C/W This is value mounted on glass epoxy board of 10% wiring density and 40 mm x 40 mm x 1.6 mm.
6, 7
Rev.1.00 Jan 06, 2006 page 4 of 36
HA16174P/FP
Electrical Characteristics
(Ta = 25C, VCC = 12 V, RT = 27 k, CT = 1000 pF)
Supply Item Start threshold Shutdown threshold UVLO hysteresis Start-up current Is temperature stability Operating current Output voltage Line regulation Load regulation Temperature stability Oscillator Initial accuracy fout temperature stability fout voltage stability CT peak voltage Ramp valley voltage RT voltage Sink current Threshold voltage1 Symbol VH VL dVUVL Is dIs/dTa Icc Vref Vref-line Vref-load dVref fout dfout/dTa fout-line Vct-H Vct-L Vrt Iss VCL1 td-CL Vfb Ifb Av-v Veoh Veol Isrc-eo Isnk-eo Gm-v Vio-ca Av-ca Vcaoh Vcaol Isrc-ca Isnk-ca Gm-c Min 9.8 8.5 1.0 140 -- 3.45 4.85 -- -- -- 58.5 -- -1.5 -- -- 1.07 15.0 -0.33 -- 2.40 -0.3 -- 5.2 -- -- -- 150 -- -- 5.2 -- -- -- 150 Typ 10.5 9.0 1.5 200 -0.3 4.5 5.00 5 5 80 65 0.1 0.5 3.6 0.65 1.25 25.0 -0.30 280 2.50 0 60 5.7 0.1 -120 120 200 (-10) 60 5.7 0.1 -90 90 200 Max 11.2 9.5 2.0 260 -- 6.45 5.15 20 20 -- 71.5 -- 1.5 4.0 -- 1.43 35.0 -0.27 500 2.60 0.3 -- 6.2 0.3 -- -- 290 0 -- 6.2 0.3 -- -- 290 Unit V V V A %/C mA V mV mV ppm/C kHz %/C % V V V A V ns V A dB V V A A A/V mV dB V V A A A/V Test Conditions
VREF
VCC = 9.5 V *1 IAC = 0 A, CL = 0 F Isource = 1 mA Isource = 1 mA, VCC = 12 V to 23 V Isource = 1 mA to 5 mA Ta = -40 to 125C *1 Measured pin: OUT Ta = -40 to 125C *1 VCC = 12 V to 18 V *1 *1 SS = 2 V PFC-ON = 2 V CS = 0 to -1 V FB-EO Short Measured pin: FB *1 FB = 2.3 V, EO: Open FB = 2.7 V, EO: Open FB = 1.0 V, EO = 2.5 V FB = 4.0 V, EO = 2.5 V FB = 2.5 V, EO = 2.5 V *1 *1
Soft start Current limit VAMP
CAMP
Note
Delay to output Feedback voltage Input bias current Open loop gain High voltage Low voltage Source current Sink current Transconductance Input offset voltage Open loop gain High voltage Low voltage Source current Sink current Transconductance 1: Design spec.
CAO = 2.5 V *1 CAO = 2.5 V *1 *1
Rev.1.00 Jan 06, 2006 page 5 of 36
HA16174P/FP (Ta = 25C, VCC = 12 V, RT = 27 k, CT = 1000 pF)
IAC/ Multiplier Item IAC PIN voltage Terminal offset current Output current (PFC-ON = 2.5 V) Output current (PFC-ON = 5.5 V) PFC-CS resistance OUT Gain voltage Minimum duty cycle Maximum duty cycle Rise time Fall time Low voltage Symbol Viac Imo-offset Imo1 Imo2 Imo3 Imo4 Rmo Vpfc-gain Dmin-out Dmax-out tr-out tf-out Vol1-out Vol2-out Vol3-out Voh1-out Voh2-out Vshut Vres Ishut Min 1.6 -136 -- -- -- -- -- (3.4) -- 90 -- -- -- -- -- 11.5 10.0 3.30 -- 120 Typ 2.3 -90 -20 -60 -5 -15 3.3 (4.1) -- 95 30 30 0.05 0.5 0.03 11.9 11.0 4.00 -- 190 Max 3.0 -73 -- -- -- -- -- (4.7) 0 98 100 100 0.2 2.0 0.7 -- -- 4.70 4.0 260 Unit V A A A A A k V % % ns ns V V V V V V V A Test Conditions IAC = 100 A IAC = 0 A, CS = 0 V EO = 2 V, IAC = 100 A *1,2 EO = 4 V, IAC = 100 A * EO = 2 V, IAC = 100 A *1,2
1,2
EO = 4 V, IAC = 100 A * *1
1
1,2
High voltage Shutdown Shutdown voltage Reset voltage Shutdown current
Gain = 0.125* CAO = 4.0 V CAO = 0 V CL = 1000 pF CL = 1000 pF Iout = 20 mA Iout = 200 mA (Pulse Test) Iout = 10 mA, VCC = 5 V Iout = -20 mA Iout = -200 mA (Pulse Test) Input: DELAY Input: Vcc VCC = 9 V
Notes 1. Design spec. 2. Imo1 to Imo4 defined as, Imo = (CS Terminal Current) - (Imo-offset)
CAO
IMO = K x {IAC x (VEO - 1 V)}
IAC
K VE O
CAMP
IAC
Oscillator
VREF
3.3 k Imo 55 k
-0.3 V CLIMIT
Terminal Current
Imo-offset
CS
Rev.1.00 Jan 06, 2006 page 6 of 36
HA16174P/FP (Ta = 25C, VCC = 12 V, RT = 27 k, CT = 1000 pF)
Supervisor/ PG Item PFC enable voltage PFC disable voltage PFC shutdown voltage PFC disable delay threshold voltage Input current B+ good voltage PGADJ voltage PGADJ minimum voltage B+ OVP set voltage B+ OVP reset voltage B+ OVP PG OFF voltage FB low set voltage PG leakage current PG shunt current PG start-up delay threshold voltage Delay to PG OFF DELAY source current DELAY sink current Note Symbol Von-pfc Voff-pfc Vshut-pfc Vd-pfc Ipfc-on dVbgood Vpgadj Vpgadjmin dVovps dVovpr dVovp_pg Vfbls Ioff-pg Ion-pg Vd-pgon td-pgoff Isrc-delay Isnk-delay Min 1.62 1.48 0.5 1.15 -- -0.175 1.42 -- 0.125 0.075 0.275 0.45 -- 2 2.3 -- -14.5 70 Typ 1.75 1.6 0.95 1.25 0.1 -0.1 1.50 -- 0.188 0.138 0.500 0.50 0.001 -- 2.5 0.2 -10 100 Max 1.87 1.72 1.2 1.35 1.0 -0.025 1.58 0.55 0.250 0.200 0.725 0.55 1.0 -- 2.7 1 -7 145 Unit V V V V A V V V V V V V A mA V s A A Test Conditions Input pin: PFC-ON Input pin: PFC-ON Input pin: PFC-ON Input pin: DELAY PFC-ON = 2 V Input pin: FB *1 Input pin: FB, PGADJ = 1.5 V Input pin: FB Input pin: FB *1 Input pin: FB *1 Input pin: FB Input pin: FB PG = 2 V PG = 2 V Input pin: DELAY Input pin: FB DELAY = 1 V DELAY = 1 V
1. dVbgood = Vbgood - Vref x 0.5 dVovps = Vovps - Vref x 0.5 dVovpr = Vovpr - Vref x 0.5 dVovp_pg = Vovp_pg - Vref x 0.5
Vovp_pg Vovps Vbgood Vfbls
FB
Vovpr
Vref x 0.5 Vpgadj
PG OUT
Rev.1.00 Jan 06, 2006 page 7 of 36
HA16174P/FP
Timing Chart
1. Start-up Timing
VCC
10.5 V (VH) 5V 4.0 V
VREF
VREF GOOD
PFC-ON
1.75 V (Von-pfc)
PFC-OFF (Internal signal)
SS CAO
Soft start
CAO SS
OUT
Normal operation
FB
2.4 V (Vbgood)
B+GOOD (Internal signal)
2.5 V (Vd-pgon) DELAY
PG
td-pgon
Power good period (System enable)
Rev.1.00 Jan 06, 2006 page 8 of 36
HA16174P/FP 2. Stop Timing
1.6 V (Voff-pfc) PFC-ON
1.25 V (Vd-pfc) DELAY
PFC-OFF (Internal signal)
PFC operation hold time
td-pfcoff
SS
OUT
Normal operation PGADJ
FB
PG
Power good period (System enable)
Rev.1.00 Jan 06, 2006 page 9 of 36
HA16174P/FP 3. Oscillator, Gate Driver Output
CT
CAO
Dead time (Internal signal)
OUT (Leading edge control)
4. PFC Operation ON/OFF
1.75 V (Von-pfc) 1.6 V (Voff-pfc)
PFC-ON
0.95 V (Vshut-pfc)
PFC-OFF (Internal signal)
1.25 V (Vd-pfc)
DELAY
OUT
Rev.1.00 Jan 06, 2006 page 10 of 36
HA16174P/FP 5. FB Supervisor
Vovp_pg FB
Vovpr
Vovps
Vovpr PGADJ 0.5 V (FB LOW)
2.4 V (Vb-good)
B+GOOD (Internal signal) B+OVP (Internal signal)
FB LOW (Internal signal)
SS
OUT
2.5 V (Vd-pgon)
DELAY
PG
td-pgon
td-pgon td-pgon
td-pgon
Rev.1.00 Jan 06, 2006 page 11 of 36
HA16174P/FP 6. PFC ON/OFF Function
Em R1 720 k R2 20 k C1 2.2 4 PFC-ON 1.75 V 1.60 V PFC ON/OFF control
Rec+
Rec-
VPFC-ON (DC) =
2 * Em R2 * R1 + R2 2 * 2 * Vac R2 = * R1 + R2 VPFC-ON (DC) * R1 + R2 Vac = * 2 * 2 R2
Vac 71.9 V 65.8 V
PFC-ON 1.75 V 1.60 V
PFC-OFF (Internal signal)
PFC ON status
Rev.1.00 Jan 06, 2006 page 12 of 36
HA16174P/FP
Description of Pin Functions
OUT Pin: The power MOS FET gate-drive signal is output from this pin, and takes the form of a rectangular waveform with an amplitude of VCC-GND. GND Pin: The ground terminal. DELAY Pin: This pin has three functions; (1) delay-time setting for output of the Power Good signal, (2) setting the PFC function hold time for cases of momentary outage, and (3) IC shutdown. Normal operation is as a 100 A constant-current sink. (1) Power Good signal output delay When the PFC output voltage is within the range from 96% (typ.) to 105.5% (typ.), this pin functions as a 10 A source current. When the capacitor is charged until the voltage reaches 2.5 V (typ.), the Power Good signal is output and the delay-pin function becomes a 100 A sink current. The delay time for Power Good signal output is set by the values of the external capacitor. (2) Setting the PFC function hold time for momentary outage When the PFC-ON pin is driven below 1.6 V (typ.) due to a momentary outage, the delay pin functions as a 10 A source current. PFC operation continues until the capacitor is charged to 1.25 V (typ.). After the voltage on the delay pin reaches 1.25 V (typ.) the pin functions as a 100 A sink current, and PFC operation terminates. The PFC function hold time can be set by the value of the external capacitor. (3) Shutdown When this pin is pulled up to 4 V (typ.) or higher, the IC enters the shutdown state. Accordingly, the VREF signal becomes low and the operating current becomes several hundred A. The IC does not resume operation until Vcc falls to 4 V (max.) or below. Note: (1) and (2) cannot be set independently. PGADJ Pin: This pin sets the stop level of power good signal. If the FB pin voltage falls below this pin voltage, the Power Good signal stops immediately. Do not set this pin voltage to 2.3 V or higher. When this pin is open-circuit, the Power Good signal stops when the voltage on the FB pin becomes lower than 0.55 V (max.). PFC-ON Pin: This pin is applied smoothing voltage of rectified AC voltage. When 1.75 V (typ.) or more is applied to this pin, PFC operation starts. When the voltage is 1.6 V (typ.) or lower, the PFC operation stops after the PFC operation hold time (refer to the description of DELAY pin operation). When the voltage is forcibly lower than 0.95 V (typ.), PFC operation stops even if the PFC operation hold time has not elapsed. VREF Pin: Temperature-compensated voltage with an accuracy of 5 V 3% is output from this pin. The pin should supply no more than 5 mA (max.) source current. This pin has no sink capabilities. CAO Pin: This pin is the current-error amplifier output, and is connected to the phase-compensation circuit of the current-error amp. The result of comparison of the voltage on this pin and the CT pin produces the pulse output from the OUT pin. CS Pin: Current detection pin. The current is controlled to be proportional to the AC voltage and the power factor is corrected. When the voltage on this pin drops to -0.3 V (typ.) or below, over current detection circuit operates, and OUT pin is stopped.
Rev.1.00 Jan 06, 2006 page 13 of 36
HA16174P/FP RT Pin: A pin for frequency adjustment of the oscillator. CT Pin: A pin for frequency adjustment of the oscillator. PG Pin: Open-drain pin for output of the Power Good signal. The internal MOS FET is in the ON state when the output voltage of the PFC power supply is started up or in case of abnormality. When the output voltage becomes normal, the MOS FET is switched to the OFF state after the delay time. IAC Pin: This pin is for detecting the input AC voltage waveform. For processing within the IC, the AC voltage waveform is converted to current information. FB Pin: This pin is the input to the voltage error amp. This pin is applied to voltage divided PFC output with resistors. The feedback loop is intended to keep 2.5 V (typ.). EO Pin: This pin is the output of the voltage error amp. This pin is connected to the phase-compensation circuit of the voltage error amp. The voltage on this pin is the input signal to the internal multiplier. SS Pin: This pin is connected to GND or VREF via a capacitor. This pin is pulled up to the VREF pin voltage until PFC operation starts. When the voltage on the PFC-ON pin has reached 1.75 V (typ.) PFC operation is start and this pin flows 25 A source current. Operation of the CAO pin is affected by that of the SS pin, the pulse width of the OUT pin is limited, and this prevents overshooting when start up. VCC Pin: IC power-supply pin. The IC starts up at 10.5 V (typ.), and stops at 9 V (typ.).
Rev.1.00 Jan 06, 2006 page 14 of 36
HA16174P/FP
Description of Functions
1. UVL Circuit The UVL circuit monitors the Vcc voltage. When the voltage is lower than 9.0 V, the IC is stopped. When the voltage is higher than 10.5 V, IC is started. When operation of the IC is stopped by the UVL circuit, the driver circuit output is fixed low, output of VREF is stopped, and the oscillator is stopped.
VCC
10.5 V (VH)
9 V (VL)
5V VREF 4.0 V CAO
CT
OUT
Figure 1 UVL Operation
Rev.1.00 Jan 06, 2006 page 15 of 36
HA16174P/FP 2. Operating Frequency The HA16174 operating frequency fosc is determined by adjusting the timing resistor Rt (the RT pin, pin 9) and the timing capacitance Ct (the CT pin, pin 10). The operating frequency is approximated by the following expression:
fosc = 1.7 x 106 (kHz) Rt x Ct (pF)
(k)
When the IC is operated at high frequencies, the expression becomes less accurate due to IC internal delay time, etc. Please confirm operation the value with the actually mounted IC. The maximum operating frequency is 400 kHz. As a reference, the operating frequency data when the timing resistor and the timing capacitance are changed is shown in the below figure.
1000
Operating Frequency (kHz)
100
Timing capacitance Ct 470 pF 1000 pF 2200 pF
10
4700 pF
1 1 10 Timing Resistance (k) 100
Figure 2 Operating Frequency Characteristics
Rev.1.00 Jan 06, 2006 page 16 of 36
HA16174P/FP 3. Soft Start This function prevents applying excessive stress on external components and overshooting of the PFC output voltage (B + voltage) when start up. The pulse width is gradually widening from 0% duty cycle. During soft-start operation, the SS and CAO signals lower with link.. The duty cycle is controlled by the CAO signal. The soft-start time can be set by an external capacity.
1.75 V CAO SS SS
PFC-ON
CAO
CT
OUT
PFC output voltage
Figure 3 Soft-Start Operation Waveform
Rev.1.00 Jan 06, 2006 page 17 of 36
HA16174P/FP 4. PFC-ON Pin Function Several functions are assigned to the PFC-ON pin, and which is operational depends on the power-supply state. Details of their operation are given below. Note, however, that the functions do not operate when VREF voltage is lower than 4 V as UVL operation and shut down.
Full-wave rectified AC 0.95 V 720 k
Gain selector
PFC-ON
2.2 20 k
Gate Driver +/- 1.0 A (PEAK) 5
0.1
PFC ON/OFF control
VREF 1.75 V 1.60 V
To Power MOSFET gate
1
OUT
VREF
4.7
SS
15 25 A
VREF
10 A
1.25 V
DELAY
2.2
3
100 A
Figure 4 Internal Circuits Connected to the PFC-ON Pin 4-1. Power-Supply Startup Operation When the AC voltage is applied, the voltage on the PFC-ON pin rises. After it exceeds 1.75 V, the voltage on the SS pin starts to be discharged and PFC operation starts up. The PFC output voltage is initially charged to a voltage of about 2 x AC voltage; after PFC operation starts, it is boosted to the prescribed voltage.
Full-wave rectified AC
1.75 V PFC-ON
SS CAO CAO SS
PFC output voltage
Figure 5 Waveforms in Operations at Startup
Rev.1.00 Jan 06, 2006 page 18 of 36
HA16174P/FP 4-2. Operation on a Momentary Outage (PFC operation hold on momentary outage: PFC hold function) (1) When the Momentary Outage is Short During a momentary outage, the voltage on the PFC-ON pin is discharged. When it reaches 1.6 V, charging of the capacitor on the DELAY pin starts. The voltage on the PFC-ON pin continues to fall and, when it reaches 1.4 V, source current begins to flow through the pin. The lower the PFC-ON voltage, the greater the amount of current, so the PFC-ON pin voltage does not fall below the level determined by the external resistor and the source current. AC-voltage input is resumed, if the DELAY pin voltage doesn't reach 1.25 V before the PFC-On pin voltage rises above 1.75 V, the PFC output voltage resumes quickly. In this case, the soft-start function does not operate.
Full-wave rectified AC
PFC-ON
1.6 V
1.75 V
Ipfc-on
1.25 V
DELAY
OUT
PF output voltage
Figure 6 PFC Hold Function Operation Waveform 1 The hold time for PFC operation is adjusted by the value of the capacitance on the DELAY pin. Note, however, that if VCC voltage of IC is not normally supplied during a momentary outage, the PFC-ON hold function does not operate.
Rev.1.00 Jan 06, 2006 page 19 of 36
HA16174P/FP (2) When the Momentary Outage is Long When the momentary outage is long enough that the DELAY pin voltage reaches 1.25 V, Output on the OUT is stopped, SS is reset, and PFC operation stops. When the supply of AC voltage resumes, the IC is restarted in a softstart operation.
Full-wave rectified AC
PFC-ON
1.6 V
1.75 V
Ipfc-on 1.25 V DELAY
SS
OUT
Soft start
PF output voltage
Figure 7 PFC Hold Function Operation Waveform 2 Note: When the PFC output voltage is driving a heavy load, the PFC output voltage falls rapidly, and the FB pin may fall below 0.5 V before the DELAY pin reaches 1.25 V. Here, the OUT pin is stopped, and the SS pin is reset by the FB pin low-voltage detection circuit.
Rev.1.00 Jan 06, 2006 page 20 of 36
HA16174P/FP (3) PFC Shutdown By forcibly lowering the PFC-ON pin to 0.95 V, the PFC operation can be stopped even during the hold period. Output on the OUT pin is stopped, the SS pin is reset, and the PFC operation stops. When the PFC-ON pin is driven higher than 1.75 V, the IC is restarted in a soft-start operation.
Full-wave rectified AC
PFC-ON
0.95 V
1.75 V
SS
OUT
Soft start
PFC output voltage
Figure 8 PFC Shutdown Function Operation Waveform
Rev.1.00 Jan 06, 2006 page 21 of 36
HA16174P/FP 5. FB Pin Function The FB pin is a feedback input for the PFC output voltage. This pin is applied to voltage divided PFC output with resistors. The PFC output voltage is controlled so that the applied voltage on FB is 2.5 V. The FB pin function provides protection against abnormal PFC output voltages. The protective functions are over voltage detection, lowvoltage detection, and Power Good (PG) signal control. These functions do not operate when VREF voltage is lower than 4 V as UVL operation and shut down.
820 k
EO
14
2.5 V 2.688 V 2.638 V
Gate Driver +/- 1.0 A (PEAK) 1
33 n
To Power MOSFET gate
PFC Output voltage
720 k
B+OVP 3.0 V 2.638 V 5 B+PG RESET
OUT
FB
20 k
VREF
FB control
0.50 V
5.1 k
11
VREF 56 k 2.40 V
PG
SQ RQ
PGADJ
24 k
4
VREF
4.7
VREF
SS
15 25 A
VREF
10 A
2.5 V DELAY
2.2
100 A
3
Figure 9 Internal Circuits Connected to the FB Pin
Rev.1.00 Jan 06, 2006 page 22 of 36
HA16174P/FP 5-1. Power-Supply Startup Operation When the AC voltage is applied, the PFC-ON pin voltage starts to rise; after it has reached 1.75 V, PFC operation starts. When PFC operation starts, the voltage on the FB pin starts to rise. When it has reached 2.4 V (equivalent to 96% of the PFC output voltage), the capacitor attached to the DELAY pin starts to charge up. When the voltage on the DELAY pin reaches 2.5 V, the internal MOS FET of the PG pin is turned off. Delaying the output of the PG signal avoids an unstable state of PFC output voltage, and assists in achieving correct on-and-off control in the back stages of the system.
Full-wave rectified AC
1.75 V PFC-ON SS CAO CAO SS 2.4 V
FB
96% of the output voltage
PFC output voltage
100 A
DELAY pin current
-10 A 2.5 V
DELAY pin voltage
PG pin voltage (pulled up by a resistor to the VREF voltage)
Figure 10 Waveforms in Operation to Delay PG Assertion
Rev.1.00 Jan 06, 2006 page 23 of 36
HA16174P/FP 5-2. Operation when the Power-Supply Stops When the supply of AC voltage stops the voltage on the FB pin falls. When the voltage on the FB pin is the same voltage on the PGADJ pin, the internal MOS FET of the PG pin is immediately turned on. When the FB pin voltage is lower than 0.5 V, PFC operation stops, and the SS pin is reset.
Full-wave rectified AC
PGADJ
FB
0.5 V
PG pin voltage (pulled up by a resistor to the VREF pin)
OUT
SS
Figure 11 Waveforms in Operation to Stop PG Output Note: When the load on the PFC output voltage is light, the PFC output voltage falls slowly, so the PFC-hold function may be activated before the voltage on the FB pin falls to 0.5 V. In this case, the PFC hold function takes over, stopping output on the OUT pin and resetting the SS pin.
Rev.1.00 Jan 06, 2006 page 24 of 36
HA16174P/FP 5-3. Over Voltage Operation When the PFC output voltage is larger than 7.5% of the prescribed voltage due to an abnormality in the system or a sudden change of AC voltage or load, operation of the OUT pin is terminated. When the PFC output voltage returns to within 5.5% of the prescribed voltage, operation of the OUT pin is restarted. If the PFC output voltage rises to 20% above the prescribed voltage, the condition is considered definitely abnormal, and output of the PG signal is also stopped. In this case, too, when the voltage returning to within 5.5% of the prescribed voltage is considered a return to normal conditions, operation of the OUT pin is restarted and the PG signal is output after the delay time due to operation of the DELAY pin.
120% of the prescribed output voltage 107.5% of the prescribed output voltage
PFC output voltage
105.5% of the prescribed output voltage
3.0 V 2.688 V
FB
2.668 V
OUT 100 A DELAY pin current
-10 A 2.5 V
DELAY pin voltage
PG pin voltage (pulled up by a resistor to the VREF voltage)
Figure 12 Waveforms of Operations after Over Voltage Detection by the FB Pin
Rev.1.00 Jan 06, 2006 page 25 of 36
HA16174P/FP 6. IC Shutdown Function When the DELAY pin is pulled up to 4 V, the IC shutdown function operates. During shutdown, the IC enters the standby state. To reset the circuit from the shutdown state, the voltage on VCC must be lowered to 4 V or less. After this reset, when the VCC pin voltage reaches 10.5 V, the IC is restarted.
VCC
9V 4.0 V
10.5 V
4V DELAY
Internal latch
Latched state
VREF
Figure 13 Waveform of Operations in IC Shutdown
Rev.1.00 Jan 06, 2006 page 26 of 36
HA16174P/FP
Main Characteristics
Standby Current vs. Power Supply Voltage Characteristics 250 Ta = 25C 200
Is (A)
150
100
50
0 0 1 2 3 4 5 6 Vcc (V) 7 8 9 10 11
Power Dissipation vs. Power Supply Voltage Characteristics 8 7.5 7 6.5
Icc (mA)
Ta = 25C CL = 1000 pF
6 5.5 5 4.5 4 3.5 10 12 14 16 Vcc (V) 18 20 22 24
Rev.1.00 Jan 06, 2006 page 27 of 36
HA16174P/FP
Reference Voltage Temperature Characteristics 5.2 5.15 5.1 Vcc = 12 V Iref = -1 mA
VREF (V)
5.05 5 4.95 4.9 4.85 4.8 -40
-20
0
20
40 Ta (C)
60
80
100
120
Operating Frequency Temperature Characteristics 75 73 71 Vcc = 12 V RT= 27 k CT = 1000 pF
Frequency (kHz)
69 67 65 63 61 59 57 55 -40 -20 0 20 40 Ta (C) 60 80 100 120
Rev.1.00 Jan 06, 2006 page 28 of 36
HA16174P/FP
Start-up Voltage Temperature Characteristics 11.5 11.3 11.1 10.9
VH (V)
10.7 10.5 10.3 10.1 9.9 9.7 9.5 -40 -20 0 20 40 Ta (C) 60 80 100 120
Shutdown Voltage Temperature Characteristics 9.6
9.4
9.2
VL (V)
9
8.8
8.6
8.4 -40
-20
0
20
40 Ta (C)
60
80
100
120
Rev.1.00 Jan 06, 2006 page 29 of 36
HA16174P/FP
Standby Current Temperature Characteristics 280 Vcc = 9.5 V 260 240 220
Is (A)
200 180 160 140 120 -40
-20
0
20
40 Ta (C)
60
80
100
120
Operating Current Temperature Characteristics 7 6.5 6 5.5 5 4.5 4 3.5 3 -40 Vcc = 12 V CL = 0 pF
Icc (mA)
-20
0
20
40 Ta (C)
60
80
100
120
Rev.1.00 Jan 06, 2006 page 30 of 36
HA16174P/FP
VAMP Feedback Voltage Temperature Characteristics 2.7 2.65 2.6 2.55
Vfb (V)
Vcc = 12 V FB-EO Short
2.5 2.45 2.4 2.35 2.3 -40
-20
0
20
40 Ta (C)
60
80
100
120
EO Pin Voltage vs. CS Pin Current Characteristics 100 90 80 70
-Imo (A)
Ta = 25C Vcc = 12 V Iac = 100 A
60 50 40 30 20 10 0 0 1 2 Veo (V) 3 4 5 PFC-ON = 5.5 V PFC-ON = 2.5 V
Rev.1.00 Jan 06, 2006 page 31 of 36
HA16174P/FP
Vamp Frequency Characteristics 80 60 40 Ta = 25C Vcc = 12 V 200 150 100 50 0 -50 -100 -150 -200 10E+6
Gain (dB)
20 0 -20 -40 -60 -80 10E+0
100E+0
1E+3
10E+3 100E+3 Frequency f (Hz)
1E+6
Camp Frequency Characteristics 80 60 40 Ta = 25C Vcc = 12 V 200 150 100 50 0 -50 -100 -150 -200 10E+6
Gain (dB)
20 0 -20 -40 -60 -80 10E+0
100E+0
1E+3
10E+3 100E+3 Frequency f (Hz)
1E+6
Rev.1.00 Jan 06, 2006 page 32 of 36
Phase (deg.)
Phase (deg.)
HA16174P/FP
Precautions on Usage
1. DELAY Pin The value of the external capacitor connected to the DELAY pin determines the PFC hold function hold time and the PG signal output delay time. However, since the above functions are achieved by the same pin, the times are related as follows. PG delay time = 2 x PFC hold time 2. CS Pin The CS pin is used to for detection in PFC control led current. When power supply is started up, the voltage drop of inrush current must not exceed the maximum rated value of the CS pin. 3. VREF Pin For stabilization, be sure to connect a capacitor between the pin and ground. It possible to occur overshoot of VREF by connected capacitance. The degree of the overshoot will depend on the value of the connected capacitor. Pay particular attention to this point if you intend to use the VREF pin voltage as reference voltage for an external circuit.
Vref overshoot
Vref Peak Voltage (V)
7 6.5 6 5.5 5 0.01
0.1 Cref (F)
1
Figure 14 Overshoot on the VREF Pin vs. Capacitance 4. PFC-ON Pin In design of worldwide power supply, it is possible that calculated voltage exceed maximum rated voltage of PFC-ON pin. Actually, as a clamp circuit is included in the PFC-ON pin, the voltage is clamped however, clamp current must not exceed 300 A. 5. OUT Pin Undershooting or overshooting may occur due to the wiring of the OUT pin. These may bring to malfunctions of the IC. In such a case, prevent the undershooting or overshooting by using a Schottky barrier diode, etc.
Rev.1.00 Jan 06, 2006 page 33 of 36
HA16174P/FP 6. Pattern Layout In designing the pattern layout, pay as much attention as is possible to the following points. (1) Place the stabilizing capacitor for the VREF pin as close to the IC as possible, and keep the wiring short. (2) Place the timing resistor of the RT pin as close to the IC as possible, and keep the wiring short. (3) Place the phase compensation circuit for the CAO pin as close to the IC as possible, and keep the wiring short. (4) Place the timing capacitor for the CT pin as close to the IC as possible, and keep the wiring short. (5) Place the stabilizing capacitor for the VCC pin as close to the IC as possible, and keep the wiring short. (6) Place the resistor for the PGADJ pin as close to the IC as possible, and keep the wiring short. (7) Place the IC pins and their wiring as far from high-voltage switching lines (particularly the drain voltage for the power MOS FET) as possible and in general design the wiring to minimize switching noise. (8) It is probable that stability of operation is achieved by inputting signals via filters to pins with input functions. Note, however, that such filter circuits can affect the bias conditions for pins that have both input and output functions.
Rev.1.00 Jan 06, 2006 page 34 of 36
HA16174P/FP
System Diagram
Rec+ B+
B+ OUT (385 V dc)
T1 Q1
470 (450 V)
680 k To FB
680 k
Rec-
From OUT
from auxiliary
24 V 4.7
VRB1
GND
VCC
16
5 V Internal Bias
H
10.5 V
VREF
5 V VREF Generator
27.5 V
L
UVLO
9.0 V
6
VREF In GOOD Out
0.1
27 k
RT 9 CT 10
770 ns 15.4 s 0.65 V 3.6 V
PFC-DT RAMP
Reset: Vcc<5 V Shut down
R S R S
Q Q
UVL
VREF GOOD
1000 p
65 kHz
Gate Driver +/- 1.0 A (PEAK)
Q Q
To Q1 gate
1
VREF
VREF CAO 3.3 n 30 k
Oscillator 7
OUT
R S
Q Q
10 A
470 p 3M
IMO = K x {IAC x (VEO - 1V)}
VREF
SS
PFC DELAY
DELAY
3
2.2
IAC
CAMP
12
1.75 M
1000 p
IAC
O
IMO
VE
VREF
K
55 k 3.3 k
DELAY RESET PG DELAY
1.25 V
100
CS
CLIMIT
8
0.016 (5 W) 0.01
Gain Select
K = 0.20
2.50 V
-0.30 V
100 A
820 k
EO
Gain Selector
K = 0.05
Shut down
4.0 V
14
2.5 V
2.688 V 2.638 V
B+OVP
VREF
33 n
VREF
FB
13
From VRB1 (B+ monitor1)
VAMP
3.0 V 2.638 V
B+PG RESET
25 A
15 SS
4.7
0.50 V
720 k
S R
Q
FB LOW
GND
0.95 V
Q
2
PFC-OFF
PFC-ON 5
2.2 20 k
0.1
VREF
Circuit Ground
5.1 k
1.75 V 1.60 V
VREF GOOD
IN OUT PFC DELAY
S R S
Q Q Q Q
B+GOOD
VREF
56 k
2.40 V
B+PG RESET
PG
DELAY RESET
11
PGADJ 4
24 k
S R
Q Q
IN OUT
PG DELAY
R
Rev.1.00 Jan 06, 2006 page 35 of 36
HA16174P/FP
Package Dimensions
JEITA Package Code P-DIP16-6.3x19.2-2.54 RENESAS Code PRDP0016AE-B Previous Code DP-16FV MASS[Typ.] 1.05g
D
16
9
1 0.89 b3
8
Z
A1
A
E
Reference Symbol
Dimension in Millimeters
Min
e
bp
e1
c
( Ni/Pd/Au plating )
e1 D E A A1 bp b3 c e Z L
Nom Max 7.62 19.2 20.32 6.3 7.4 5.06
L
0.51 0.40 0.48 0.56 1.30 0.19 0.25 0.31 0 15 2.29 2.54 2.79 1.12 2.54
JEITA Package Code P-SOP16-5.5x10.06-1.27
RENESAS Code PRSP0016DH-B
Previous Code FP-16DAV
MASS[Typ.] 0.24g
*1
D F 9
16
NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET.
bp
HE
E
Index mark
*2
Terminal cross section ( Ni/Pd/Au plating )
1 Z e
*3
8 bp x M L1
Reference Dimension in Millimeters Symbol
c
A1
y
L
Detail F
D E A2 A1 A bp b1 c c1 HE e x y Z L L1
Min Nom Max 10.06 10.5 5.50
0.00 0.10 0.20 2.20 0.34 0.40 0.46 0.15 0.20 0.25 0 8 7.50 7.80 8.00 1.27 0.12 0.15 0.80 0.50 0.70 0.90 1.15
Rev.1.00 Jan 06, 2006 page 36 of 36
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Keep safety first in your circuit designs!
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