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Features
* Single Chip All-in-one Design
- MIDI Control Processor, Serial and Parallel Interface - Synthesis, General MIDI Wavetable Implementation - General MIDI Compatible Effects: Reverb + Chorus - Spatial Effect - 4-band Stereo Equalizer - Stereo DAC. DR: 86 dB min, THD+N: -80 dB max State of the art Synthesis for Products Providing Best Quality for Price - 64-voice Polyphony (without effects) - 38-voice Polyphony + Effects - On-chip CleanWaveTM Wavetable Data, Firmware, RAM Delay Lines Audio Stereo Line Output Typical Applications: Battery Operated Musical Keyboards, Portable Phones, Karaokes QFN44 (7mm x 7mm) Package: Small Footprint, Small Pin Count Low Power - 75 mW typ. Operating - Single 3.3V or Single 1.8V Power Supply - Built-in Power Switch and 3.3V to 1.8V Regulator
*
Audio Processing ATSAM2195 Low-power Single Chip Synthesizer with Effects
* * * *
1. Typical Hardware Configuration
Figure 1-1. Typical Hardware Configuration
MIDI In ATSAM2195 Parallel MIDI Audio OUT
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2. Pin Description
2.1 Pins By Function - 44-lead QFN Package
Power Supply Group
Pin # 20, 31, 33 Type PWR Function DIGITAL GROUND All pins should be connected to a ground plane DIGITAL GROUND Ground supply; down bonded to the exposed die pad (heatsink). It is recommended, but not obligatory, to connect this pad to a ground plane during PCB layout I/O POWER SUPPLY This pin should be connected to a nominal 3.3V power for 3.3V single supply applications. This pin should be connected to a nominal 1.8V power for 1.8V single supply applications CORE POWER SUPPLY These pins should be connected to nominal 1.8V. 3.3V single supply application: If the built-in regulator is used, then these pins should be connected to the output of the regulator OUTVC18 (pin 35). 1.8V single supply application: If the built-in power switch is used for minimum power down consumption, then all these pins should be connected to the output of the power switch PWROUT (pin 39). ANALOG GROUND These pins should be connected to an analog ground plane DAC PERIPHERY ANALOG SUPPLY 3.3V single supply application: This pin should be connected to a nominal 3.3V power through a serial inductor filter (better result) or a 10 ohm resistor. 1.8V single supply application: This pin should be connected to a nominal 1.8V power through a serial inductor filter (better result) or a 10 ohm resistor. DAC 1.8V ANALOG SUPPLY This pin should be connected to a clean 1.8V. 3.3V single supply application: If the built-in regulator is used, then this pin should be connected to the output of the regulator OUTVC18 (pin 35) through a serial inductor filter (better result) or a 10 ohm resistor. 1.8V single supply application: If the built-in power switch is used, then this pin should be connected to the output of the power switch PWROUT (pin 39) through a serial inductor filter (better result) or a 10 ohm resistor. Regulator input This pin should be connected to a nominal 3.3V power for 3.3V single supply applications. This pin should be grounded for 1.8V single supply applications Power switch input. This pin should be left not connected for 3.3V single supply applications. This pin should connected to a 1.8V nominal power for 1.8V single supply applications
Table 2-1.
Pin Name GND
GND
exposed die pad
PWR
VD33
21
PWR
VD18
19, 30
PWR
AGND
43, 44
PWR
VA33
4
PWR
VA18
2
PWR
REGIN
34
PWR
PWRIN
38
PWR
2
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Table 2-2.
Pin Name MIDI IN
Serial MIDI, parallel MIDI (MPU-401)
Pin # 10 15, 16, 17, 18, 22, 23, 24, 25 11 12 Type IN Function Serial TTL MIDI IN. Connected to the built-in synthesizer at power-up or after MPU reset. Connected to the D0-D7 bus (read mode) when MPU switched to UART mode. This pin should be tied HIGH if not used. 8 bit bi-directional bus, under control of CS, RD, WR. These pins have a built-in pull down. They should be left unconnected if not used Select data(0) or control(1) for write, data(0) or status(1) for read. This pin has a built-in pull-down. It should be left unconnected if not used. Chip select, active low. This pin has a built-in pull up. It should be left unconnected if not used. Read, active low. When CS and RD are low, data(A0=0) or status(A0=1) is read on D0-D7. Read data is acknowledged on the rising edge of RD. This pin has a built-in pull up. It should be left unconnected if not used. Write, active low. When CS and WR are low, data (A0=0) or control (A0=1) is written from the D0-D7 bus to the ATSAM2195 on the rising edge of WR. This pin has a built-in pull up. It should be left unconnected if not used. A rising edge indicates that a MIDI byte is available for read on D0-D7. Acknowledged by reading the byte.
D0-D7 A0 CS
I/O IN IN
RD
13
IN
WR
14
IN
IRQ
26
OUT
Table 2-3.
Pin Name AGNDREF VREF VCM VBG AOUTL AOUTR
Analog audio group
Pin # 42 41 40 3 1 5 Type IN OUT OUT OUT OUT OUT Function These pin is used as a reference by the internal DAC. It should be connected to a clean analog ground plane Reference voltage. Generated on-chip. Should be stabilized by external capacitors 10 F // 100 nF to AGND. On-chip output stage common-mode voltage. Should be stabilized by external capacitors 10 F // 100 nF to AGND. Bandgap voltage. Can be stabilized by capacitors 1F // 100 nF to AGND. Can be left unconnected for low-cost application. Left channel audio output Right channel audio output
Table 2-4.
Pin Name
Digital audio group
Pin # Type Function Selects the full scale output level for AOUTL and AOUTR. OUTLEV = 0 for 1.1Vpp OUTLEV = 1 for 2.2Vpp If 1.8V single supply (VA33 = 1.8V), OUTLEV should be tied to 0. Activate a dither signal to reduce eventual noise tones at the output. See Dither Modes Description.
OUTLEV
6
IN
DITH0-DITH1
7, 8
IN
3
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Table 2-5.
Pin Name X1-X2
Miscellaneous group
Pin # 29, 28 Type Function 9.6 MHz crystal connection. An external 9.6 MHz clock can also be used on X1 (1.95Vpp max through 47 pF capacitor). X2 cannot be used to drive external circuits. Reset input, active low. This is a Schmitt trigger input, allowing direct connection to an RC network 3.3V to 1.8 V regulator output. When 3.3V single supply application this pin can be used to power VD18 pins, and VA18 pin through a serial inductor filter (better result) or a 10 ohm resistor. Decoupling capacitors 470 pF in parallel with 2.2 or 4.7 F must be connected between OUTVC18 and GND. Power switch output. When 1.8V single supply application this pin can be used to power VD18 pins, and VA18 pin through a serial inductor filter (better result) or a 10 ohm resistor. Power down, active low. When power down is active, all digital outputs are set to logic level 0, D0-D7 bus is set in high Z, analog outputs decrease to 0V, the PLL and crystal oscillator are stopped. 3.3V single supply application: If the built-in regulator is used then 1.8V supply is removed from the core. To exit from power down, PDWN must be set to VD33, then RESET applied. When unused this pin must be connected to VD33. 1.8V single supply application: If the built-in power switch is used then 1.8V supply is removed from the core. To exit from power down, PDWN must be set to VD18, then RESET applied. When unused this pin must be connected to VD18 Test pins. Should be grounded
RESET
9
IN
OUTVC18
35
PWR
PWROUT
39
PWR
PDWN
37
IN
TEST0-TEST1TEST2
36, 27, 32
IN
4
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2.2 Pinout By Pin Number - 44-lead QFN Package
Pinout
Pin# 12 13 14 15 16 17 18 19 20 21 22 Pin Name CS RD WR D0 D1 D2 D3 VD18 GND VD33 D4 Pin# 23 24 25 26 27 28 29 30 31 32 33 Pin Name D5 D6 D7 IRQ TEST1 X2 X1 VD18 GND TEST2 GND Pin# 34 35 36 37 38 39 40 41 42 43 44 Pin Name REGIN OUTVC18 TEST0 PDWN PWRIN PWROUT VCM VREF AGNDREF AGND AGND
Table 2-6.
Pin# 1 2 3 4 5 6 7 8 9 10 11
Pin Name AOUTL VA18 VBG VA33 AOUTR OUTLEV DITH0 DITH1 RESET MIDI IN A0
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3. Mechanical Dimensions - 44-lead QFN Package
Notes:
1. All package dimensions are in mm. 2. R-QFN044_D - QFN
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4. Marking
FRANCE
SAM2195
YYWW 58A60B XXXXXXXXX
Pin 1
7
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5. Absolute Maximum Ratings
All voltages with respect to 0V, GND=0V. Table 5-1. Absolute Maximum Ratings*
*NOTICE: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Temperature under bias.......................... -55 C to +125 C Storage Temperature ............................... -65C to +150C Voltage on any Input Pins except X1......................................... -0.3V to +VD33+0.3V Voltage on X1 .................................... -0.3V to VD18+0.3V Supply voltage (I/O) (VD33)........................ -0.3V to +3.6V Supply voltage (core) (VD18) ................... -0.3V to +1.95V Supply voltage (DAC analog 3.3V) (VA33)......................................................... -0.3V to +3.6V Supply voltage (DAC analog 1.8V) (VA18)....................................................... -0.3V to +1.95V Maximum IOL per I/O pin........................................... 4 mA Maximun IOH per I/O pin ........................................... 4 mA Maximum Output current from PWROUT pin (max duration = 1sec) (IPWRO) ............................ 650 mA Maximum Output current from OUTVC18 pin (max duration = 1sec) (IREGO) ............................. 100 mA
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Table 5-2.
Parameter
Recommended Operating Conditions
Symbol VD33 VD33 VD18 VA33 VA33 VA18 PWRIN REGIN IPWRO IREGO tA Min 3 1.65 1.65 3 1.65 1.65 1.75 2.7 0 Typ 3.3 1.8 1.8 3.3 1.8 1.8 1.80 3.3 60 Max 3.6 1.95 1.95 3.6 1.95 1.95 1.95 3.6 217 +70 Unit V V V V V V V V mA mA C
Digital supply voltage: - OUTLEV = 1 - OUTLEV = 0 Digital supply voltage Analog supply voltage: - OUTLEV = 1 - OUTLEV = 0 Analog supply voltage Power switch supply Regulator supply Power Switch output current OUTVC18 output current Operating ambient temperature
Table 5-3.
Parameter
Digital Characteristics (TA=25C, VD33=3.3V10%, 1.65 V< VD18 < 1.95V)
Symbol VIL VIH VIL VIH VOL VOH VREGO 1.65 1.8 Min -0.3 2 -0.3 1.2 VD33-0.4 Typ 75 <1 0.1 1.95 Max 0.8 3.6 0.3 VD18+0.3 0.4 Unit V V V V V V mW A V V
Low level input voltage (Except X1) High level input voltage (Except X1) Low level input voltage for X1 High level input voltage for X1 Low level output voltage IOL=-2mA High level output voltage IOH=2mA Power consumption (crystal freq.=9.6MHz) Power down supply current (using power switch) Drop down from PWRIN to PWROUT (at IPWRO = 180mA) Voltage on OUTVC18 (at IREGO = 60mA)
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Table 5-4.
Parameter
Analog Characteristics (TA=25C)
Symbol THD + N THD + N DR DR Min 86 80 83 80 -0.1 2.04 1.02 1.38 0.74 3 Typ 100 2.2 1.1 1.5 0.80 4.7 10 100 Max -80 -76 +01 2.36 1.18 0.1 1.58 0.84 Unit dB dB dB dB
Total Harmonic Distortion + Noise (at 0 dB, full scale) VA33 = 3.3V, OUTLEV = 1 VA33 = 1.8V, OUTLEV = 0 Dynamic Range (A-Weighted) VA33 = 3.3V, OUTLEV = 1 VA33 = 1.8V, OUTLEV = 0 Inter-channel isolation (1kHz) VA33 = 3.3V, OUTLEV = 1 VA33 = 1.8V, OUTLEV = 0 Inter-channel gain mismatch Gain drift Full-scale output voltage VA33 = 3.3V, OUTLEV = 1 VA33 = 1.8V or 3.3V, OUTLEV = 0 VCM Maximum allowable DC current source VCM Nominal voltage VA33 = 3.3V, OUTLEV = 1 VA33 = 1.8V or 3.3V, OUTLEV = 0 AC-Load resistance Load capacitance
RL CL
dB dB ppm/ C Vpp Vpp mA V V k pF
Table 5-5.
Parameter
Filter Characteristics (TA=25C)
Symbol PB PB SB SA GD 65 Min -0.05 0 0 Typ 20.49 1.12 100 Max +0.05 17 18.74 Unit dB kHz kHz kHz dB ms ppm/ C
Frequency response (10Hz - 17kHz) Passband to -0.1dB corner to -6 dB corner Stopband Stopband attenuation (20.49kHz - 112.5kHz) Group delay Gain drift
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6. Timings
6.1 Slave 8-bit Parallel Interface
This interface is typically used to connect the chip to an host processor. Figure 6-1. 8-bit Parallel Interface Read Cycle
A0 tAVCS CS
tCSLRDL RD
tPRD
tRDHCSH
tRDLDV D0 - D7
tDRH
IRQ
Figure 6-2.
8-bit Parallel Interface Write Cycle
tWRCYC A0 tAVCS CS
tCSLWRL WR
tPWR
tWRHCSH
tDWS D0 - D7
tDWH
Table 6-1.
Parameter
Timings
Symbol tAVCS tCSLRDL tRDHCSH tPRD tRDLDV tDRH Min 0 5 5 50 5 Typ Max 20 10 Unit ns ns ns ns ns ns
Address valid to chip select low Chip select low to RD low RD high to CS high RD pulse width Data out valid from RD Data out hold from RD
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Table 6-1.
Timings
tCSLRWRL tWRHCSH tPWR tDWS tDWH tWRCYC 5 5 50 10 0 3.5 ns ns ns ns ns s
Chip select low to WR low WR high to CS high WR pulse width Write data setup time Write data hold time Write cycle Notes:
1. When data is pending on parallel port, the host should read it within 1 ms. If not, the parallel port is deactivated. Reactivating the port can be done with the following control sequence: 0FFh (Closed port), 03FFh (Open port). 2. For safe operation, write cycle time should not be lower than 3.5 s.
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7. Reset and Power Down
During power-up, the RESET input should be held low until the crystal oscillator and PLL are stabilized, which can take about 20 ms. A typical RC/diode power-up network can be used. After RESET, the ATSAM2195 enters an initialization routine. It takes around 50 ms before a MIDI IN or MPU message can be processed. Audio begins after 500 ms, maximum. To enter power-down, Reset should be held low 500 ms min and then PDWN asserted low. In Power-down mode, the crystal oscillator and PLL are stopped. The chip enters a deep power down sleep mode. To exit power down, PDWN has to be asserted high, then RESET applied.
7.1
3.3V Single Supply Application
Power down mode is managed by the internal regulator. The equivalent schematic and standard connection is shown on the diagram below.
ATSAM2195
13
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7.2
1.8V Single Supply Application
Power down mode is managed by the internal power switch. The equivalent schematic and standard connection is shown on the diagram below.
ATSAM2195
14
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8. Dither Modes Description (Dithering Signal Programmability)
Dithering is used to attenuate the so-called idle tones caused by correlation between DAC input signal and truncation noise. This correlation manifests as spurious signals in the audio band and hence can be perceived by the user. The addition of a random digital signal to the truncator input in the digital modulator has been proven to be very effective to reduce the presence of idle tones. However, this is actually a noisy signal so that its power must be traded-off with the required dynamic range. For better control, the ATSAM2195 allows programmability of the dithering signal power as shown below.
dith[1:0] 00 01 10 11 Mode description No dither Dither signal power = -30dBFS Dither signal power = -27dBFS Dither signal power = -24dBFS Minimum recommended dither. Typical value Maximum recommended value. Above it dither noise may become dominant. Comments
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9. System Design
The schematics of this section are the reference designs for applications with ATSAM2195. The conformity with these schematics ensures the best performance.
9.1
3.3V Single Supply Application
ATSAM2195
16
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9.2 1.8V Single Supply Application
ATSAM2195
17
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10. Recommended Board Layout
Like all HCMOS high integration ICs, following simple rules of board layout is mandatory for reliable operations: * GND, VD33, VD18, VA33, VA18 distribution and decoupling All GND, VD33, VD18, VA33, VA18 pins should be connected. A GND plane is strongly recommended below the ATSAM2195. The board GND, VD33, VD18 distribution should be in grid form. Recommended decoupling is 0.1 F at each VD33, VD18, VA33, VA18 pin of the IC with an additional 1F-T between pins 30 and 31. Decoupling capacitors should be implemented close to the IC. * Crystal The paths between the crystal and the ATSAM2195 should be short and shielded. The ground return from the crystal compensation capacitors should be pin 31. * Analog section A specific AGND ground plane should be provided, which connects by a single trace to the GND ground. No digital signals should cross the AGND plane.
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