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PCA2125
SPI Real time clock / calendar
Rev. 00.11 -- 30 January 2007 Preliminary data sheet
1. Product profile
1.1 General description
The PCA2125 is a CMOS real time clock/calendar optimized for low power consumption and 125 C operation. Data is transferred serially via an SPI bus with a maximum data rate of 8.0 Mbits/s. An alarm and timer function are also available with possibility to generate a wake-up signal on an interrupt pin.
1.2 Features
Provides year, month, day, weekday, hours, minutes and seconds based on 32.768 kHz quartz crystal Resolution: seconds - years Clock operating voltage: 1.2 to 5.5 V Low backup current; typical 0.55 A at VDD = 3.0 V and Tamb = 25 C 3 line SPI with separate combinable data input and output Serial interface (at VDD = 1.8 to 5.5 V) 1 second or 1 minute interrupt output Freely programmable timer with interrupt capability Freely programmable alarm function with interrupt capability Integrated oscillator capacitor Internal power-on reset Open-drain interrupt pin
1.3 Applications
Automotive time keeping application Metering
1.4 Quick reference data
Table 1. Symbol VDD Quick reference data Parameter supply voltage Conditions SPI bus inactive; Tamb = 25 C SPI bus active; Tamb = -40 to +125 C Min 1.2 1.6 Typ Max 5.5 5.5 Unit V V
NXP Semiconductors
PCA2125
SPI Real time clock / calendar
Table 1. Symbol IDD
Quick reference data ...continued Parameter supply current Conditions fSCL = 7.0 MHz fSCL = 1.0 MHz SPI bus inactive and CLKOUT disabled; fSCL = 0 kHz; Tamb = 25 C VDD = 5 V VDD = 2 V -40 -65 550 550 725 725 +125 +150 nA nA C C Min Typ Max 800 200 Unit A A
Tamb Tstg
ambient temperature storage temperature
operating
2. Pinning information
2.1 Pinning
OSCI OSCO n.c. n.c. INT CE VSS
1 2 3 4 5 6 7
001aaf892
14 VDD 13 CLKOUT 12 n.c.
PCA2125
11 n.c. 10 SCL 9 8 SDI SDO
Fig 1. Pin configuration TSSOP14
2.2 Pin description
Table 2. Symbol OSCI OSCO nc nc INT CE VSS SDO SDI SCL nc Pin description PCA2125 Pin 1 2 3 4 5 6 7 8 9 10 11 Description oscillator input oscillator output Do not connect and do not use as feed through. Connect to VDD if floating pins not allowed. Do not connect and do not use as feed through. Connect to VDD if floating pins not allowed. interrupt output (open-drain; active LOW). When not used, must be connected to VSS or pulled high via a resistor. chip enable input (active HIGH) with 200 k pull down. ground serial data output, push-pull serial data input. May float when CE inactive. serial clock input. May float when CE inactive. Do not connect and do not use as feed through. Connect to VDD if floating pins not allowed.
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SPI Real time clock / calendar
Pin description PCA2125 Pin 12 13 14 Description Do not connect and do not use as feed through. Connect to VDD if floating pins not allowed. clock output (open drain) positive supply voltage
Table 2. Symbol nc CLKOUT VDD
3. Ordering information
Table 3. Ordering information Package Name Description Version SOT402-1 TSSOP14 plastic thin shrink small outline package; 14 leads; body width 4.4mm Type number Topside mark PCA2125TS PCA2125
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4. Block diagram
INT 5 OSCI OSCO 1 2 OSCILLATOR 32.768 kHz CONTROL 1 DIVIDER AND TIMER CONTROL 2 1 Hz SECONDS MINUTES 13 7 14 HOURS DAYS WEEKDAYS MONTHS OSCILLATOR MONITOR POR CONTROL LOGIC YEARS MINUTE ALARM HOUR ALARM SCL SDO SDI CE 10 8 9 6
200 k
0 1 2 3 4 5 6 7 8 9 A B C D E F
CLKOUT VSS VDD
DAY ALARM SERIAL BUS INTERFACE ADDRESS REGISTER WEEKDAY ALARM CLOCKOUT CONTROL TIMER CONTROL COUNTDOWN TIMER
001aaf894
Fig 2. Block diagram of PCA2125
5. Device protection diagram
VDD OSCI
CLKOUT OSCO SCL INT SDI CE SDO VSS
PCA2125
001aaf895
Fig 3. Device diode protection diagram PCA2125
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6. Functional description
The PCA2125 contains sixteen 8-bit registers with an auto-incrementing address register, and on-chip 32.768 kHz oscillator with one integrated capacitor, a frequency divider which provides the source clock for the Real Time Clock (RTC), a programmable clock output, and an 8 MHz SPI. All sixteen registers are designed as addressable 8-bit parallel registers although not all bits are implemented. The first two registers (memory address 00H and 01H) are used as control registers. The memory addresses 02H through 08H are used as counters for the clock function (seconds up to years). Addresses 09H through 0CH define the alarm condition, whilst address 0DH defines the clock out mode. The seconds, minutes, hours, days, weekdays, months and years registers are all coded in BCD format. When one of the RTC registers is read the contents of all counters are frozen. Therefore, faulty reading of the clock/calendar during a carry condition is prevented. Address registers 0EH and 0FH are used for the countdown timer function. The countdown timer has four selectable source clocks allowing for countdown periods in the range from less than 1ms to more than 4hours. There are also two pre-defined timers which can be used to generate an interrupt once per second or once per minute, but these are defined at address 01H.
Table 4: 4096 Hz 64 Hz 1 Hz 160 Hz Countdown timer durations minimum timer duration 244 s 15.625 ms 1s 60 s maximum timer duration 62.256 ms 3.984 s 255 s 4 hrs 15 minutes
Timer source clock
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6.1 Register overview
16 registers are available. The time registers are encoded in the binary coded decimal format (BCD) to simplify application use. Other registers are either bit-wise or standard binary.
Table 5: Registers overview Bit positions labelled as x are not implemented and will return a 0 when read. Bit positions labelled with 0 should always be written with logic 0. Address 00HEX 01HEX 02HEX 03HEX 04HEX 05HEX 06HEX 07HEX 08HEX 09HEX 0AHEX 0BHEX 0CHEX 0DHEX 0EHEX 0FHEX Register name control 1 control 2 seconds minutes hours days weekdays months years minute alarm hour alarm day alarm weekday alarm CLKOUT control timer control countdown timer AEn AEn AEn AEn x TE x x x x x Bit 7 ext test MI RF x x x x x x x x x 10 years 10 minute alarm AMPM / 10 hour alarm 10 day alarm x x x x x x x x x COF2 x x x Bit 6 0 SI Bit 5 stop MSF 10 seconds 10 minutes AMPM / 10 hours 10 days x 10months x Bit 4 0 TI/TP Bit 3 POR ovrd AF Bit 2 12/24 TF seconds minutes hours days weekdays months years minute alarm hour alarm day alarm weekday alarm COF1 CTD1 COF0 CTD0 Bit 1 0 AIE Bit 0 0 TIE
countdown timer value, n
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6.2 Reset
The PCA2125 includes an internal reset circuit (see Figure 4) which is active whenever the oscillator is stopped. The oscillator may be stopped, for example, by grounding one of the oscillator pins, OSCI or OSCO. The oscillator is also considered to be stopped during the time between power-up and stable crystal resonance. This time may be in the range of 200ms to 2s depending on crystal type, temperature and supply voltage. Whenever an internal reset occurs, the RF flag is set.
chip in reset
chip not in reset
VDD
oscillation
internal reset t
001aaf897
Fig 4. Power on reset
The SPI interface is initialized whenever the chip enable line CE is inactive.
Table 6: Address 00HEX 01HEX 02HEX 03HEX 04HEX 05HEX 06HEX 07HEX 08HEX 09HEX 0AHEX 0BHEX 0CHEX 0DHEX 0EHEX 0FHEX
[1] [2]
Register reset value Register name control 1 control 2 seconds minutes hours days weekdays months years minute alarm hour alarm day alarm weekday alarm CLKOUT control timer control countdown timer Bit 7 0 0 1 x 1 1 1 1 0 x Bit 6 0 0 x x x x x Bit 5 0 0 x x x x x x x x x Bit 4 0 x x x x x x x x x x Bit 3 1 0 x x x x x x x x x x Bit 2 0 0 x x x x x x x x x x x 0 x Bit 1 0 0 x x x x x x x x x x x 0 1 x Bit 0 0 0 x x x x x x x x x x x 0 1 x
registers marked `x' are undefined at power up and unchanged by subsequent resets. registers marked `-' are not implemented.
After reset, the following mode is entered: 32768Hz CLKOUT active
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Power on reset override available to be set 24 hour mode is selected
6.2.1 Power-On Reset (POR) override
The power on reset duration is directly related to the crystal oscillator start-up time. Due to the long start-up times experienced by these types of circuits, a mechanism has been built in to disable the POR and hence speed up on-board test of the device (see Figure 5).
OSCILLATOR
osc stopped 0 = stopped, 1 = running
reset
SDI
POR OVERRIDE CLEAR POR_OVRD REGISTER
0 = override inactive 1 = override active
CE
0 = clear override mode 1 = override possible
001aaf898
Fig 5. Reset system.
The setting of this mode requires that the `POR ovrd' register be set to `1' and that the SPI bus pins, SDI and CE, be toggled in a specific order as shown in Figure 6. All timings are required minimums. Once the override mode has been entered, the device immediately stops being reset and set-up operation may commence i.e. entry into the external clock test mode via the SPI bus access. The override mode may be cleared by writing a logic 0 to `POR ovrd'. `POR ovrd' must be set to logic 1 before re-entry into the override mode is possible. Setting `POR ovrd' to logic 0 during normal operation has no effect except to prevent accidental entry into the POR override mode. This is the recommended setting.
minimum 500 ns SDI
CE reset override minimum 500 ns minimum 2000 ns
POR override set at this time
001aaf900
Fig 6. POR override sequence.
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6.3 Control registers
6.3.1 Control 1 register
Table 7. Bit 7 6 5 stop Control 1 (address 00HEX) bits description Symbol ext test Value 0 1 0 0 1 Description normal mode external clock test mode Reserved for future use. RTC source clock runs RTC divider chain flip-flops are asynchronously set to logic 0; the RTC clock is stopped (CLKOUT at 32.768, 16.384 or 8.192 kHz is still available) Reserved for future use. Power-on reset override facility is disabled; set to logic 0 for normal operation Power-on reset override may be enabled 24 hour mode is selected 12 hour mode is selected Reserved for future use. Table 15 Section 6.2.1 Section 6.10 Section Section 6.9
4 3 POR ovrd 12/24
0 0 1
2 1 to 0
0 1 00
6.3.2 Control 2 register
Table 8. Bit 7 6 5 Control 2 (address 01HEX) bits description Symbol MI SI MSF Value 0 1 0 1 0 1 2 TF 0 1 4 3 TI/TP AF 0 1 0 1 1 0 AIE TIE 0 1 0 1 Description Minute interrupt is disabled Minute interrupt is enabled Second interrupt is disabled Second interrupt is enabled No minute or second interrupt generated Flag set when minute or second interrupt generated. Flag must be cleared to clear interrupt. No countdown timer interrupt generated Flag set when countdown timer interrupt generated. Flag must be cleared to clear interrupt. Interrupt pin follows timer flags Interrupt pin generates a pulse No alarm interrupt generated Flag set when alarm triggered. Flag must be cleared to clear interrupt. No interrupt generated from the alarm flag Interrupt generated when alarm flag set No interrupt generated from the countdown timer flag Interrupt generated when countdown timer flag set Section 6.7 Section 6.7.3 Section 6.5.1 Section 6.7.2 Section 6.6 Section Section 6.6.1
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6.4 Time and date function
The majority of these registers are coded in the Binary Coded Decimal format. BCD is used to simplify application use. An example is shown for the minutes register:
Table 9: Minutes value in decimal 00 01 02 : 09 10 : 58 59 Table 10. Bit 7 0 0 1 1 0 0 1 1 1 1 0 0 0 0 0 1 0 0 0 0 0 0 0 1 1 0 0 0 0 0 1 0 BCD example Bit 7 23 0 0 0 Bit 6 22 0 0 0 Bit 5 21 0 0 0 Bit 4 20 0 0 0 Bit 3 23 0 0 0 Bit 2 22 0 0 0 Bit 1 21 0 0 1 Bit 0 20 0 1 0
Seconds / RF (address 02HEX) bits description Symbol RF Value 0 1 Description clock integrity is guaranteed clock integrity is not guaranteed. Chip reset has occurred since flag was last cleared this register holds the current seconds coded in BCD format;
6 to 0
seconds
00 to 59
Table 11. Bit 6 to 0
Minutes (address 03HEX) bits description Symbol minutes Value 00 to 59 Description this register holds the current minutes coded in BCD format
Table 12. Bit 5 4 to 0
Hours (address 04HEX) bits description Symbol AMPM hours Value
[1]
Description Indicates AM Indicates PM this register holds the current hours coded in BCD format for 12 hour mode
[1]
12 hour mode 0 1 00 to012
24 hour mode 5 to 0
[1]
hours
00 to 23
this register holds the current hours coded in BCD format for 24 hour mode
Hour mode is set by the 12 / 24 bit in control register 2.
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Days (address 05HEX) bits description Symbol days Value 01 to 31
[1]
Table 13. Bit 5 to 0
[1]
Description this register holds the current day coded in BCD format
The RTC compensates for leap years by adding a 29th day to February if the year counter contains a value which is exactly divisible by 4, including the year 00.
Table 14. Bit 2 to 0
[1]
Weekdays (address 06HEX) bits description Symbol weekdays Value 0 to 6
[1]
Description this register holds the current weekday, see Table 15
These bits may be re-assigned by the user.
Although the association of the weekdays counter to the actual weekday is arbitrary, the PCA2125 will assume `Sunday' is 000 and `Monday' is 001 for the purposes of determining the increment for calendar weeks.
Table 15: Day Sunday Monday Tuesday Wednesday Thursday Friday Saturday Table 16. Bit 4 to 0 Weekday assignments Bit 7 x x x x x x x Bit 6 x x x x x x x Bit 5 x x x x x x x Bit 4 x x x x x x x Bit 3 x x x x x x x Bit 2 0 0 0 0 1 1 1 Bit 1 0 0 1 1 0 0 1 Bit 0 0 1 0 1 0 1 0
Months (address 07HEX) bits description Symbol month Value 01 to 12 Description this register holds the current month coded in BCD format, see Table 17
Table 17: Month January February March April May June July August September October November December
Month assignments Bit 7 x x x x x x x x x x x x Bit 6 x x x x x x x x x x x x Bit 5 x x x x x x x x x x x x Bit 4 0 0 0 0 0 0 0 0 0 1 1 1 Bit 3 0 0 0 0 0 0 0 1 1 0 0 0 Bit 2 0 0 0 1 1 1 1 0 0 0 0 0 Bit 1 0 1 1 0 0 1 1 0 0 0 0 1 Bit 0 1 0 1 0 1 0 1 0 1 0 1 0
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Years (address 08HEX) bits description Symbol years Value 00 to 99 Description this register holds the current year coded in BCD format
Table 18. Bit 7 to 0
6.4.1 Data flow
Figure 7 shows the data flow and data dependencies starting from the 1 Hz clock tick.
1 Hz tick
SECONDS
MINUTES
12/24 hour mode
HOURS
DAYS
WEEK DAY
MONTHS
YEARS
001aaf901
Fig 7. Data flow for the time function
6.5 Alarm function
When one or more of these registers are loaded with a valid minute, hour, day or weekday and its corresponding bit Alarm Enable not (AEn) is logic 0, then that information will be compared with the current minute, hour, day and weekday.
Table 19. Bit 7 6 to 0 Minute alarm (address 09HEX) bits description Symbol AEn minute alarm Value 0 1 00 to 59 Description minute alarm is enabled minute alarm is disabled this register holds the minute alarm information coded in BCD format
Table 20. Bit 7
Hour alarm (address 0AHEX) bits description Symbol AEn Value 0 1 Description hour alarm is enabled hour alarm is disabled
24 hour mode
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Hour alarm (address 0AHEX) bits description Symbol hour alarm am/pm alarm hour alarm Value 00 to 23 Description this register holds the hour alarm information coded in BCD format when in 24 hour mode. this register holds the hour alarm information coded in BCD format when in 12 hour mode
Table 20. Bit 5 to 0
12 hour mode 5 4 to 0 0 to 1 00 to 11
Table 21. Bit 7 5 to 0
Day alarm (address 0BHEX) bits description Symbol AEn day alarm Value 0 1 01 to 31 Description day alarm is enabled day alarm is disabled this register holds the day alarm information coded in BCD format
Table 22. Bit 7 2 to 0
Weekday alarm (address 0CHEX) bits description Symbol AEn Value 0 1 weekday 0 to 6 alarm Description weekday alarm is enabled weekday alarm is disabled this register holds the weekday alarm information
check now signal MINUTE AEN MINUTE ALARM = MINUTE TIME 1 0 E.G. MINUTE AEN1
HOUR AEN HOUR ALARM = HOUR TIME set alarm flag, AF DAY AEN DAY ALARM = DAY TIME
WEEKDAY AEN WEEKDAY ALARM = WEEKDAY TIME
001aaf902
Fig 8. Alarm function block diagram
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Generation of interrupts from the alarm function is described under the interrupt section, Section 6.7.3.
6.5.1 Alarm flag
When all enabled comparisons first match, the Alarm Flag (AF) is set. AF will remain set until cleared by software. Once AF has been cleared it will only be set again when the time increments to match the alarm condition once more. Alarm registers which have their bit AEn at logic 1 are ignored. Figure 9 shows an example for clearing AF but leaving MSF and TF unaffected. Clearing the flags is made by a write command, therefore bits 7,6,4,1 and 0 must be written with their previous values. Repeatedly re-writing these bits has no influence on the functional behavior.
minutes counter
44
45
46
minute alarm
45
AF
INT when AIE = 1
001aaf903
Example where only the minute alarm is used and no other interrupts are enabled.
Fig 9. AF timing
To prevent the timer flags being overwritten while clearing AF, a logic AND is performed during a write access. Writing a `1' will cause the flag to maintain it's value, whilst writing a `0' will cause the flag to be reset.
Table 23: Register Control 2 Flag location in control 2 Bit 7 Bit 6 Bit 5 MSF Bit 4 Bit 3 AF Bit 2 TF Bit 1 Bit 0 -
The following tables show what instruction must be sent to clear the AF. In this example, MSF and TF are unaffected.
Table 24: Register Control 2 Example to clear only TF (bit 2) Bit 7 Bit 6 Bit 5 1 Bit 4 Bit 3 0 Bit 2 1 Bit 1 Bit 0 -
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6.6 Timer functions
The countdown timer has four selectable source clocks allowing for countdown periods in the range from less than 1ms to more than 4hours. There are also two pre-defined timers which can be used to generate an interrupt once per second or once per minute. Address registers 01HEX, 0EHEX and 0FHEX are used to control the timer function and output.
Table 25. Bit 7 6 5 Control 2 (address 01HEX) bits description Symbol MI SI MSF Value 0 1 0 1 0 1 4 2 TI/TP TF 0 1 0 1 0 3 1 Table 26. Bit 6:2 7 1 to 0 0 TE CDT 0 1 0 0 1 1 Table 27. Bit 7 to 0 0 1 0 1 TIE AF AIE 0 1 Description Minute interrupt is disabled Minute interrupt is enabled Second interrupt is disabled Second interrupt is enabled No minute or second interrupt generated Flag set when minute or second interrupt generated. Flag must be cleared to release INT. Interrupt pin follows timer flags Interrupt pin generates a pulse No countdown timer interrupt generated Flag set when countdown timer interrupt generated. Flag must be cleared to release INT. No interrupt generated from the countdown timer flag Interrupt generated when countdown timer flag set See Table 8. See Table 8.
Timer control (address 0EHEX) bits description Symbol Value Description Reserved for future use. Countdown timer is disabled Countdown timer is enabled 4096 Hz countdown timer source clock 64 Hz countdown timer source clock 1 Hz countdown timer source clock 160 Hz countdown timer source clock Section 6.6.2 Section
Countdown timer (address 0AHEX) bits description Symbol n Value 00 to FF Description countdown value = n; n CountdownPeriod = -------------------------------------------------------------SourceClockFrequency Section Section 6.6.2
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6.6.1 Second and minute interrupt; SI, MI
The minute and second interrupt are pre-defined timers for generating periodic interrupts. The timers can be enabled independently from one another, however a minute interrupt enabled on top of a second interrupt will not be distinguishable since it will occur at the same time; see Figure 10.
seconds counter
58
59
59
00
00
01
minutes counter
11
12
INT when SI enabled
MSF when SI enabled
INT when only MI enabled
MSF when only MI enabled
001aaf905
In this example, TI/TP is set to 1 resulting in 1/64 Hz wide interrupt pulse and the MSF flag is not cleared after an interrupt.
Fig 10. INT example for SI and MI Table 28. disabled enabled disabled enabled Effect of MI and SI on INT generation Second interrupt, SI disabled disabled enabled enabled Result No interrupt generated An interrupt once per minute An interrupt once per second An interrupt once per second
Minute interrupt, MI
The minute/second flag, MSF, is set to `1' when either the seconds or the minutes counter increments according to the currently enabled interrupt. The flag can be read and cleared by the interface. The status of the MSF does not affect INT pulse generation. If the MSF flag is not cleared prior to the next coming interrupt period, an INT pulse will still be generated. The purpose of the flag is to allow the controlling system to interrogate the PCA2125 and identify the source of the interrupt i.e. minute/second or countdown timer.
Table 29: disabled enabled disabled enabled Effect of MI and SI on MSF Second interrupt, SI disabled disabled enabled enabled Result MSF never set. MSF set when minutes counter increments MSF set when seconds counter increments MSF set when seconds counter increments
Minute interrupt, MI
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6.6.2 Countdown timer function
The 8-bit countdown timer at address 0FHEX is controlled by the timer control register at address 0EHEX. The timer control register determines one of 4 source clock frequencies for the timer (4096 Hz, 64 Hz, 1 Hz, or 160 Hz), and enables or disables the timer.
Table 30. CDT1 0 0 1 1
[1]
CDT1 and CDTD: Timer frequency selection CDT0 0 1 0 1 TIMER Source clock frequency 4096 Hz 64 Hz 1 Hz 160 Hz
[1]
delay for n=1 244 s 15.625 ms 1s 60 s
delay for n = 255 62.256 ms 3.984 s 255 s 4 hrs 15 min
When not in use, CDT must be set to 160 Hz for power saving.
Remark: Note that all timings which are generated from the 32.768kHz oscillator are based on the assumption that there is 0 ppm deviation. Deviation in oscillator frequency will result in deviation in timings. This is not applicable to interface timing. The timer counts down from a software-loaded 8-bit binary value, n. Loading the counter with 0 effectively stops the timer. Values from 1 to 255 are valid. When the counter reaches 1, the countdown Timer Flag (TF) will be set and the counter automatically re-loads and starts the next timer period. Reading the timer will return the current value of the countdown counter (see Figure 11)..
countdown value, n
xx
03
timer source clock
countdown counter
xx
03
02
01
03
02
01
03
02
01
03
TE
TF
INT n duration of first timer period after enable may range from n - 1 to n + 1 n
001aaf906
In the example it is assumed that the timer flag is cleared before the next countdown period expires and that the INT is set to pulsed mode.
Fig 11. General countdown timer behavior
If a new value of n is written before the end of the current timer period, then this value will take immediate effect. NXP does not recommend to changing n without first disabling the counter (by setting TE = 0). The update of n is asynchronous to the timer clock, therefore changing it without setting TE = 0 will result in a corrupted value loaded into the
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countdown counter which results an undetermined countdown period for the first period. The countdown value n will however be correctly stored and correctly loaded on subsequent timer periods. When the countdown timer flag is set, an interrupt signal on INT will be generated provided that this mode is enabled. See Section 6.7.2 for details on how the interrupt can be controlled. When starting the timer for the first time, the first period will have an uncertainty which is a result of the enable instruction being generated from the interface clock which is asynchronous from the timer source clock. Subsequent timer periods will have no such delay. The amount of delay for the first timer period will depend on the chosen source clock, see Table 31.
Table 31: 4096 Hz 64 Hz 1 Hz 1/60 Hz First period delay for timer counter value, n. minimum timer period n n (n-1) + 1/64Hz (n-1) + 1/64Hz maximum timer period n+1 n+1 n + 1/64Hz n + 1/64Hz
Timer source clock
At the end of every countdown, the timer sets the countdown Timer Flag (TF). The TF may only be cleared by software. The asserted TF can be used to generate an interrupt (INT). The interrupt may be generated as a pulsed signal every countdown period or as a permanently active signal which follows the condition of TF. Bit TI/TP is used to control this mode selection and the interrupt output may be disabled with the TIE bit, see Table 25. When reading the timer, the current countdown value is returned and not the initial value, n. For accurate read back of the countdown value, the SPI bus clock (SCL) must be operating at a frequency of at least twice the selected timer clock. Since it is not possible to freeze the countdown timer counter during read back, it is recommended to read the register twice and check for consistent results.
6.6.3 Timer flags
When a minute or second interrupt occurs, MSF is set to 1. Similarly, at the end of a timer countdown, TF is set to 1. These bits maintain their value until overwritten by software. If both countdown timer and minute/second interrupts are required in the application, the source of the interrupt can be determined by reading these bits. To prevent one flag being overwritten while clearing another a logic AND is performed during a write access. Writing a `1' will cause the flag to maintain it's value, whilst writing a `0' will cause the flag to be reset. Three examples are given for clearing the flags. Clearing the flags is made by a write command, therefore bits 7,6,4,1 and 0 must be written with their previous values. Repeatedly re-writing these bits has no influence on the functional behavior.
Table 32: Register Control 2 Flag location in control 2 Bit 7 Bit 6 Bit 5 MSF Bit 4 Bit 3 AF Bit 2 TF Bit 1 Bit 0 -
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The following tables show what instruction must be sent to clear the appropriate flag.
Table 33: Register Control 2 Table 34: Register Control 2 Table 35: Register Control 2 Example to clear only TF (bit 2) Bit 7 Bit 6 Bit 5 1 Bit 4 Bit 3 1 Bit 2 0 Bit 1 Bit 0 -
Example to clear only MSF (bit 5) Bit 7 Bit 6 Bit 5 0 Bit 4 Bit 3 1 Bit 2 1 Bit 1 Bit 0 -
Example to clear both TF and MSF Bit 7 Bit 6 Bit 5 0 Bit 4 Bit 3 1 Bit 2 0 Bit 1 Bit 0 -
Clearing the alarm flag (AF) operates in exactly the same way, but is described in Section 6.5.1.
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SPI Real time clock / calendar
6.7 Interrupt output, INT
An active low interrupt signal is available at pin INT. Operation is controlled via the bits of control register 2. Interrupts may be sourced from three places; Second/minute timer, countdown timer or alarm function. With the TI/TP bit, the timer generated interrupts can be configured to either generate a pulse or to follow the status of the interrupt flags; TF and MSF. Remark: Note that the interrupts from the three groups are wire-OR'd, meaning they will mask one another (see Figure 12).
SI MSF: MINUTE SECOND FLAG SET CLEAR MI to interface: read MSF 0 PULSE GENERATOR 1 TRIGGER CLEAR from interface: clear MSF TE TF: TIMER SET CLEAR PULSE GENERATOR 2 TRIGGER CLEAR from interface: clear TF AF: ALARM FLAG SET CLEAR from interface: clear AF to interface: read AF AIE to interface: read TF 0 1 TI/TP INT 1 SI MI
SECONDS COUNTER
MINUTES COUNTER
TIE
COUNTDOWN COUNTER
set alarm flag, AF
001aaf907
When SI, MI, TIE and AIE are all disabled, INT will remain high impedance.
Fig 12. Interrupt scheme
6.7.1 Minute/Second interrupts
The pulse generator for the minute/second interrupt operates from an internal 64 Hz clock and consequently generates a pulse of 164 seconds in duration. If the MSF flag is clear before the end of the INT pulse, then the INT pulse is shortened. This allows the source of a system interrupt to be cleared immediately it is serviced i.e. the system does not have to wait for the completion of the pulse before continuing; see Figure 13. Instructions for clearing MSF can be found in Section 6.6.3.
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seconds counter
58
59
MSF
INT
(1)
SCL 8th clock instruction CLEAR INSTRUCTION
001aaf908
Fig 13. Example of shortening the INT pulse by clearing the MSF flag.
The timing shown for clearing MSF in Figure 13 is also valid for the non-pulsed interrupt mode i.e. when TI/TP = 0, where the pulse may be shortened by setting both MI and SI to `0'.
6.7.2 Countdown timer interrupts
Generation of interrupts from the countdown timer is controlled via the TIE bit (see Table 25). The pulse generator for the countdown timer interrupt also uses an internal clock, but this time it is dependent on the selected source clock for the countdown timer and on the countdown value, n. As a consequence, the width of the interrupt pulse varies (see Table 36).
Table 36. INT operation (bit TI / TP = 1) INT period (s) n=1 4096 64 1 160
[1]
[1]
Source clock (Hz)
n>1 14096 164 164 164
18192 1128 164 164
n = loaded countdown value. Timer stopped when n = 0.
If the TF flag is clear before the end of the INT pulse, then the INT pulse is shortened. This allows the source of a system interrupt to be cleared immediately it is serviced i.e. the system does not have to wait for the completion of the pulse before continuing (see Figure 14). Instructions for clearing MSF can be found in Section 6.6.3.
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countdown counter
01
n
TF
INT
(1)
SCL 8th clock instruction CLEAR INSTRUCTION
001aaf909
Fig 14. Example of shortening the INT pulse by clearing the TF flag.
The timing shown for clearing TF in Figure 14 is also valid for the non-pulsed interrupt mode i.e. when TI/TP = 0, where the pulse may be shortened by setting TIE to `0'.
6.7.3 Alarm interrupts
Generation of interrupts from the alarm function is controlled via the AIE bit (see Table 8). If AIE is enabled, the INT pin follows the status of AF. Clearing AF will immediately clear INT. No pulse generation is possible for alarm interrupts (see Figure 15).
minute counter
44
45
minute alarm
45
AF
INT
SCL 8th clock instruction CLEAR INSTRUCTION
001aaf910
Example where only the minute alarm is used and no other interrupts are enabled.
Fig 15. AF timing
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6.8 Clock output
A programmable square wave is available at pin CLKOUT. Operation is controlled by the COF control bits in the control register. Frequencies of 32.768 kHz (default) down to 1Hz can be generated for use as a system clock, micro-controller clock, input to a charge pump, or for calibration of the oscillator. CLKOUT is an open drain output and enabled at power-on. When disabled the output is high impedance (Hi-Z). The duty cycle of the selected clock is not controlled however, due to the nature of the clock generation, all but the 32.768kHz frequencies will be 50:50. The `stop' function can also affect the CLKOUT signal, depending on the selected frequency. When `stop' is active, the CLKOUT pin will generate a continuous 0 for those frequencies that can be stopped. For more details see Section 6.10.
Table 37: COF[2:0] 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 CLKOUT frequency selection CLKOUT FREQUENCY, Hz 32768 16384 8192 4096 2048 1024 1 CLKOUT = 0 Typical duty cycle High% : Low% 60:40 to 40:60 50:50 50:50 50:50 50:50 50:50 50:50 Effect of `stop' No effect No effect No effect CLKOUT = 0 CLKOUT = 0 CLKOUT = 0 CLKOUT = 0
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6.9 External clock test mode
A test mode is available which allows for on-board testing. In such a mode it is possible to set up test conditions and control the operation of the RTC. The test mode is entered by setting bit `ext test' in control/status1 register. Then pin CLKOUT becomes an input. The test mode replaces the internal signal with the signal applied to pin CLKOUT. Every 64 positive edges applied to pin CLKOUT generates an increment of one second. The signal applied to pin CLKOUT should have a minimum pulse width of 300 ns and a minimum period of 1000 ns. The internal clock, now sourced from CLKOUT, is divided down to 1 Hz by a 26 divide chain called a pre-scaler. The pre-scaler can be set into a known state by using bit `stop'. When bit `stop' is set, the pre-scaler is reset to 0 (stop must be cleared before the pre-scaler can operate again). From a stop condition, the first 1 second increment will take place after 32 positive edges on CLKOUT. Thereafter, every 64 positive edges will cause a 1 second increment. Remark: Entry into EXT_CLK test mode is not synchronized to the internal 64 Hz clock. When entering the test mode, no assumption as to the state of the pre-scaler can be made. Operation example: 1. Set `ext test' test mode (control/status 1, bit `ext test' = 1) 2. Set stop (control/status 1, bit stop = 1) 3. Clear stop (control/status 1, bit stop = 0) 4. Set time registers to desired value 5. Apply 32 clock pulses to CLKOUT 6. Read time registers to see the first change 7. Apply 64 clock pulses to CLKOUT 8. Read time registers to see the second change. Repeat 7 and 8 for additional increments.
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6.10 'stop' bit function
The function of the stop bit is to allow for accurate starting of the time circuits. The stop function will cause the upper part of the pre-scaler, F2 to F14, to be held in reset and thus no 1Hz ticks will be generated. The time circuits can then be set and will not increment until the stop is released. (see Figure 16). Stop will not affect the output of 32768 Hz, 16384 Hz or 8192 Hz (see Section 6.8).
OSC STOP DETECTOR 32768 Hz 16384 Hz 8192 Hz
reset
4096 Hz
F0
F1
F2 RES
F13 RES
2 Hz
F14 1 Hz tick RES stop
OSC
512 Hz
CLKOUT source 8192 Hz 16384 Hz
001aaf911
Fig 16. stop bit
The lower two stages of the pre-scaler, F0 and F1, are not reset and because the SPI interface is asynchronous to the crystal oscillator, the accuracy of re-starting the time circuits will be between 0 and one 8192Hz cycle (see Figure 17).
8192 Hz
stop released 0-122 s
001aaf912
Fig 17. stop bit release timing
The first increment of the time circuits is between 0.499888 s and 0.500000 s after stop is released. The uncertainty is caused by the pre-scaler bits F0 and F1 not being reset (see Table 38).
Table 38. Stop First increment of time circuits after stop release
[1]
Pre-scaler F0F1, F2 to F14
1Hz tick
Time Comment HH:MM:SS Pre-scaler counting normally
Clock is running normally. 0
01-0000111010100 xx-0000000000000
12:45:12
Stop is activated by user. F0F1 are not reset and values can not be predicted externally. 1
PCA2125_00
Pre-scaler is reset. Time circuits are frozen.
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First increment of time circuits after stop release
[1]
Table 38. Stop
Pre-scaler F0F1, F2 to F14
1Hz tick
Time Comment HH:MM:SS 08:00:00 Pre-scaler is reset. Time circuits are frozen. Pre-scaler is now running.
New time is set by user. 1
xx-0000000000000
Stop is released by user. 0 0 0 0 : 0 0 0 : 0 0 : 0 0
xx-0000000000000
001aaf913
08:00:00 08:00:00 08:00:00 08:00:00 : 08:00:00
1s
xx-1000000000000 xx-0100000000000 xx-1100000000000
:
11-1111111111110 00-0000000000001 10-0000000000001
:
08:00:01 08:00:01 : 08:00:01
0 to 1 transition of F14 increments the time circuits.
11-1111111111111
0.499888 - 0.500000 s
00-0000000000000
:
08:00:01 : 08:00:01 08:00:02 0 to 1 transition of F14 increments the time circuits.
11-1111111111110 00-0000000000001
[1]
F0 is clocked at 32768 Hz.
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6.11 3-line Serial Interface
Data transfer to and from the device is made via a 3 wire SPI interface. The data lines for input and output are split to allow for alternative system wiring. The data input and output line can be connected together to facilitate a bi-directional databus. The chip enable signal is used to identify the transmitted data. Each data transfer is a byte, with the MSB sent first (see Figure 18).
Table 39. Symbol CE Serial interface Function chip enable input; active high
[1]
Description When inactive, the interface is reset. Pull-down resistor included. Input may be higher than VDD. When CE is inactive, input may float. Input may be higher than VDD. When CE is inactive, input may float. Input may be higher than VDD. Input data is sampled on the rising edge of SCL. Push-pull output. Drives from VSS to VDD. Output data is changed on the falling edge of SCL.
SCL SDI
serial clock input serial data input
SDO
serial data output
[1]
Chip enable may not be wired permanently high.
The transmission is controlled by the active high chip enable signal CE. The first byte transmitted is the command byte. Subsequent bytes will be either data to be written or data to be read. Date is captured on the rising edge of the clock and transferred internally on the falling edge.
data bus
COMMAND
DATA
DATA
DATA
chip enable
001aaf914
Fig 18. Data transfer overview
The command byte defines the address of the first register to be accessed and the read/write mode. The address counter will auto increment after every access and will reset to zero after the last valid register is accessed. The read/write bit (R/W) defines if the following bytes will be read or write information.
Table 40: Bit 7 6..4 3..0 Command byte definition Symbol R/W Sub Address, SA Value 0 1 001 Description Data will be write data Data will be read data Other codes will cause the device to ignore data transfer. Valid address range.
Register Address, RA 00HEX to 0FHEX
In the following example, the seconds register is set to 45 seconds and the minutes register to 10 minutes (see Figure 19).
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R/W b7 0 b6 0 b5 0 b4 1 b3 0
addr 02HEX b2 0 b1 1 b0 0 b7 0 b6 1
seconds data 45BCD b5 0 b4 0 b3 0 b2 1 b1 0 b0 1 b7 0 b6 0
minutes data 10BCD b5 0 b4 1 b3 0 b2 0 b1 0 b0 0
SCL
SDI
CE
address counter
xx
02
03
04
001aaf915
Fig 19. Serial bus write example
In the following example, the months and years registers are read (see Figure 20). In this example, SDI and SDO are not connected together. In this configuration, it is important that SDI is never left floating, it must always be driven either high or low. If SDI is left open, high IDD currents may result.
R/W b7 1 b6 0 b5 0 b4 1 b3 0
addr 07HEX b2 1 b1 1 b0 1 b7 0 b6 0
months data 11BCD b5 0 b4 1 b3 0 b2 0 b1 0 b0 1 b7 0 b6 0
years data 06BCD b5 0 b4 0 b3 0 b2 1 b1 1 b0 0
SCL
SDI
SDO
CE
address counter
xx
07
08
09
001aaf916
Fig 20. Serial bus read example
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7. Limiting values
Table 41: Symbol VDD IDD VI VO II IO Ptot Tamb Tstg Limiting valuesIn accordance with the Absolute Maximum Rating System (IEC 60134). Parameter supply voltage supply current input voltage output voltage input current output current total power dissipation ambient temperature storage temperature Min -0.5 -50 -0.5 -0.5 -10 -10 -40 -65 Max +6.5 +50 +6.5 +6.5 +10 +10 300 +125 +150 Unit V mA V V mA mA mW C C
7.1 ESD values * Electrostatic Discharge (ESD) protection exceeds 2000 V Human Body model (HBM)
per JESD22-A114, 200 V Machine Model (MM) per JESD22-A115 and 2000 V CHarged Device Model (CDM) per JESD22-C101.
* Latch-up testing is done to JEDEC standard JESD78 which exceeds 100 mA.
8. Static characteristics
Table 42. Static characteristics VDD = 1.2 to 5.5 V; VSS = 0 V; Tamb = -40 to +125C; fosc = 32.768 kHz; quartz Rs = 60 k; CL = 12 pF; unless otherwise specified. Symbol Supplies VDD supply voltage SPI bus inactive; Tamb = 25 C SPI bus active; Tamb = -40 to 125 C VDDminclock IDD1 minimum supply voltage for clock data integrity supply current 1 Tamb = 25 C SPI bus active fSCL = 7.0 MHz fSCL = 1.0 MHz 800 200 A A
[1] [1]
Parameter
Conditions
Min 1.2 1.6 -
Typ 1.1
Max 5.5 5.5 -
Unit V V V
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Table 42. Static characteristics VDD = 1.2 to 5.5 V; VSS = 0 V; Tamb = -40 to +125C; fosc = 32.768 kHz; quartz Rs = 60 k; CL = 12 pF; unless otherwise specified. Symbol IDD2 Parameter supply current 2 Conditions SPI bus inactive; CLKOUT disabled; (fSCL = 0 Hz); Tamb = 25 C VDD = 5.0 V VDD = 3.0 V VDD = 2.0 V SPI bus inactive (fSCL = 0 Hz); CLKOUT disabled; Tamb = -40 to +125 C VDD = 5.0 V VDD = 3.0 V VDD = 2.0 V IDD3 supply current 3 SPI bus inactive (fSCL = 0 Hz); CLKOUT enabled at 32 kHz; Tamb = 25 C VDD = 5.0 V VDD = 3.0 V VDD = 2.0 V SPI bus inactive (fSCL = 0 Hz); CLKOUT enabled at 32 kHz; Tamb = -40 to +125 C VDD = 5.0 V VDD = 3.0 V VDD = 2.0 V Inputs VIL VI VI VIH ILI Ci Outputs VO VO IOH IOL IOL ILO COSCO
[1]
[2] [2]
Min
Typ
Max
Unit
-
550 550 550
725 725 725
nA nA nA
-
680 -
1000 -
nA nA nA
-
-
-
nA nA nA
VSS
0 0 25
0.3VDD VDD+0.5 5.5 VDD +1 7 VDD+0.5 5.5 1.5 +1 -
nA nA nA V V V V A pF V V mA mA mA A pF
LOW-level input voltage Input voltage Input voltage HIGH-level input voltage input leakage current input capacitance Output voltage Output voltage HIGH-level output current LOW-level output current LOW-level output current output leakage current Capacitance on OSCO for pins OSCO and SDO for CLKOUT and INT (refers to external pull-up voltage) VOH = 4.6 V; VDD = 5 V VOL = 0.4 V; VDD = 5 V (INT and CLKOUT) VOL = 0.4 V; VDD = 5 V VO = VDD or VSS VI = VDD or VSS
[3]
for OSCI pin for pins CE, SDI, SCL
-0.5 -0.5 0.7VDD -1 0.7VDD 0.7VDD -1.5 -1 -1 -
For reliable oscillator start at power-up: VDD = VDD(min) + 0.3 V.
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[2] [3]
Timer source clock = 160 Hz, level of pins SCE, SDI and SCL is VDD or VSS. Tested on sample basis.
9. Dynamic characteristics
Table 43. Dynamic characteristics VDD1 = 1.6 to 5.5V; VSS = 0 V; Tamb = -40 to +125 C, fCLKOUT = 32.768 kHz unless otherwise specified. All timing values are valid within the operating supply voltage at ambient temperature and referenced to VIL and VIH with an input voltage swing of VSS to VDD. Symbol Parameter Conditions VDD = 1.6V Min fSCLK tSCLK tw(SCLKH) tw(SCLKL) tRF tCES tCEH tCER tWCE tDS tDH tRD tRZ SCL clock frequency SCLK time SCLK HIGH pulse width SCLK LOW pulse width SCLK rise and fall time CE setup time CE hold time CE recovery time Pulse width CE SDI setup time SDI hold time SDO read delay time SDO disable time No load value. Bus will be help up by bus capacitance. Use RC time constant with application values. 530 200 200 30 100 100 20 100 Max 1.89 100 0.99 216 50 VDD = 2.7V Min 210 100 100 30 60 100 10 60 Max 4.76 100 0.99 100 30 VDD = 4.5V Min 160 100 100 30 40 100 10 40 Max 6.25 100 0.99 75 30 VDD = 5.5V Min 125 62.5 62.5 30 30 100 5 30 Max 8.0 100 0.99 60 25 MHz ns ns ns ns ns ns ns s ns ns ns ns Unit
Serial interface timing characteristics (SPI and serial interface, see Figure 21)
tZZ
Bus conflict avoidance time
0
-
0
-
0
-
0
-
ns
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tWCE CE tCES tRF tRF SCL 20% 80% tCYC tWH tWL tCEH tCER
WRITE
tDS tDH
SDI
R/W
SA2
RA0
b7
b6
b0
SDO
Hi Z
READ
SDI
b7
b6
b0 tRD tZZ tRZ b7 b6 b0
001aaf917
SDO
Hi Z
Fig 21. SPI interface timing
10. Application information
1F supercap
OSCI
VDD
CLKOUT
CE SCL
OSCO
PCA2125
VSS
SDI SDO
INT
001aaf918
The 1 Farad capacitor is used as a standby/back-up supply. With the RTC in its minimum power configuration i.e. timer off and CLKOUT off, the RTC may operate for weeks.
Fig 22. Application diagram.
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10.1 Quartz frequency adjustment
10.1.1 Method 1: fixed OSCI capacitor
By evaluating the average capacitance necessary for the application layout, a fixed capacitor can be used (see Figure 22). The frequency is best measured via the 32.768 kHz signal available after power-on at pin CLKOUT. The frequency tolerance depends on the quartz crystal tolerance, the capacitor tolerance and the device-to-device tolerance (on average 5 x 10-6). Average deviations of 5 minutes per year can be easily achieved.
10.1.2 Method 2: OSCI trimmer
Using the 32.768 kHz signal available after power-on at pin CLKOUT, fast setting of a trimmer is possible.
10.1.3 Method 3: OSCO output
Direct measurement of OSCO out (accounting for test probe capacitance).
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11. Package outline
TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm
SOT402-1
D
E
A
X
c y HE vMA
Z
14
8
Q A2 pin 1 index A1 Lp L (A 3) A
1
e bp
7
wM detail X
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.1 A1 0.15 0.05 A2 0.95 0.80 A3 0.25 bp 0.30 0.19 c 0.2 0.1 D (1) 5.1 4.9 E (2) 4.5 4.3 e 0.65 HE 6.6 6.2 L 1 Lp 0.75 0.50 Q 0.4 0.3 v 0.2 w 0.13 y 0.1 Z (1) 0.72 0.38 8 0o
o
Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT402-1 REFERENCES IEC JEDEC MO-153 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18
Fig 23. Package outline SOT402-1
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12. Handling information
Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be completely safe you must take normal precautions appropriate to handling MOS devices; see JESD625-A and/or IEC61340-5.
13. Soldering
This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 "Surface mount reflow soldering description".
13.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization.
13.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following:
* Through-hole components * Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are:
* * * * * *
Board specifications, including the board finish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus PbSn soldering
13.3 Wave soldering
Key characteristics in wave soldering are:
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* Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are exposed to the wave
* Solder bath specifications, including temperature and impurities 13.4 Reflow soldering
Key characteristics in reflow soldering are:
* Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 24) than a PbSn process, thus reducing the process window
* Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
* Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 44 and 45
Table 44. SnPb eutectic process (from J-STD-020C) Package reflow temperature (C) Volume (mm3) < 350 < 2.5 2.5 Table 45. 235 220 Lead-free process (from J-STD-020C) Package reflow temperature (C) Volume (mm3) < 350 < 1.6 1.6 to 2.5 > 2.5 260 260 250 350 to 2000 260 250 245 > 2000 260 245 245 350 220 220
Package thickness (mm)
Package thickness (mm)
Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 24.
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temperature
maximum peak temperature = MSL limit, damage level
minimum peak temperature = minimum soldering temperature
peak temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 24. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365 "Surface mount reflow soldering description".
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14. Revision history
Table 46. Revision history Release date tbd Data sheet status Product data sheet Change notice Supersedes PCA2125_00.11 Document ID PCA2125_1 Modifications:
* * * * *
The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Legal texts have been adapted to the new company name where appropriate. Figure 11 and Figure 13: update SPI diagrams for readout data, last bit during read. Figure 4: POR ovrd diagram corrected. Section 6.6: update SPI timing. Objective data sheet -
PC212x_08
20061218
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15. Legal information
15.1 Data sheet status
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]
Product status[3] Development Qualification Production
Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification.
Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
15.2 Definitions
Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.
malfunction of a NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights.
15.3 Disclaimers
General -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners.
16. Contact information
For additional information, please visit: http://www.nxp.com For sales office addresses, send an email to: salesaddresses@nxp.com
PCA2125_00
(c) NXP B.V. 2007. All rights reserved.
Preliminary data sheet
Rev. 00.11 -- 30 January 2007
39 of 40
NXP Semiconductors
PCA2125
SPI Real time clock / calendar
17. Contents
1 1.1 1.2 1.3 1.4 2 2.1 2.2 3 4 5 6 6.1 6.2 6.2.1 6.3 6.3.1 6.3.2 6.4 6.4.1 6.5 6.5.1 6.6 6.6.1 6.6.2 6.6.3 6.7 6.7.1 6.7.2 6.7.3 6.8 6.9 6.10 6.11 7 7.1 8 9 10 10.1 10.1.1 10.1.2 10.1.3 11 12 Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . 1 General description . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Quick reference data . . . . . . . . . . . . . . . . . . . . 1 Pinning information . . . . . . . . . . . . . . . . . . . . . . 2 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Device protection diagram . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 5 Register overview . . . . . . . . . . . . . . . . . . . . . . . 6 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Power-On Reset (POR) override . . . . . . . . . . . 8 Control registers . . . . . . . . . . . . . . . . . . . . . . . . 9 Control 1 register . . . . . . . . . . . . . . . . . . . . . . . 9 Control 2 register . . . . . . . . . . . . . . . . . . . . . . . 9 Time and date function . . . . . . . . . . . . . . . . . . 10 Data flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Alarm function. . . . . . . . . . . . . . . . . . . . . . . . . 12 Alarm flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Timer functions . . . . . . . . . . . . . . . . . . . . . . . . 15 Second and minute interrupt; SI, MI . . . . . . . . 16 Countdown timer function . . . . . . . . . . . . . . . . 17 Timer flags . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Interrupt output, INT . . . . . . . . . . . . . . . . . . . . 20 Minute/Second interrupts . . . . . . . . . . . . . . . . 20 Countdown timer interrupts. . . . . . . . . . . . . . . 21 Alarm interrupts . . . . . . . . . . . . . . . . . . . . . . . 22 Clock output . . . . . . . . . . . . . . . . . . . . . . . . . . 23 External clock test mode . . . . . . . . . . . . . . . . 24 'stop' bit function . . . . . . . . . . . . . . . . . . . . . . . 25 3-line Serial Interface . . . . . . . . . . . . . . . . . . . 27 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 29 ESD values . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Static characteristics. . . . . . . . . . . . . . . . . . . . 29 Dynamic characteristics . . . . . . . . . . . . . . . . . 31 Application information. . . . . . . . . . . . . . . . . . 32 Quartz frequency adjustment . . . . . . . . . . . . . 33 Method 1: fixed OSCI capacitor . . . . . . . . . . . 33 Method 2: OSCI trimmer. . . . . . . . . . . . . . . . . 33 Method 3: OSCO output . . . . . . . . . . . . . . . . . 33 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 34 Handling information. . . . . . . . . . . . . . . . . . . . 35 13 13.1 13.2 13.3 13.4 14 15 15.1 15.2 15.3 15.4 16 17 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction to soldering. . . . . . . . . . . . . . . . . Wave and reflow soldering. . . . . . . . . . . . . . . Wave soldering . . . . . . . . . . . . . . . . . . . . . . . Reflow soldering . . . . . . . . . . . . . . . . . . . . . . Revision history . . . . . . . . . . . . . . . . . . . . . . . Legal information . . . . . . . . . . . . . . . . . . . . . . Data sheet status . . . . . . . . . . . . . . . . . . . . . . Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . Contact information . . . . . . . . . . . . . . . . . . . . Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 35 35 35 36 38 39 39 39 39 39 39 40
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'.
(c) NXP B.V. 2007.
All rights reserved.
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 30 January 2007 Document identifier: PCA2125_00

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