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R8C/1A Group, R8C/1B Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
REJ03B0144-0140 Rev.1.40 Dec 08, 2006
1.
Overview
These MCUs are fabricated using the high-performance silicon gate CMOS process, embedding the R8C/ Tiny Series CPU core, and is packaged in a 20-pin molded-plastic LSSOP, SDIP or a 28-pin plastic moldedHWQFN. It implements sophisticated instructions for a high level of instruction efficiency. With 1 Mbyte of address space, they are capable of executing instructions at high speed. Furthermore, the R8C/1B Group has on-chip data flash ROM (1 KB x 2 blocks). The difference between the R8C/1A Group and R8C/1B Group is only the presence or absence of data flash ROM. Their peripheral functions are the same.
1.1
Applications
Electric household appliances, office equipment, housing equipment (sensors, security systems), portable equipment, general industrial equipment, audio equipment, etc.
Rev.1.40 Dec 08, 2006 REJ03B0144-0140
Page 1 of 45
R8C/1A Group, R8C/1B Group
1. Overview
1.2
Performance Overview
Table 1.1 outlines the Functions and Specifications for R8C/1A Group and Table 1.2 outlines the Functions and Specifications for R8C/1B Group. Table 1.1
CPU
Functions and Specifications for R8C/1A Group
Item Number of fundamental instructions Minimum instruction execution time Operating mode Address space Memory capacity Ports Specification 89 instructions
50 ns (f(XIN) = 20 MHz, VCC = 3.0 to 5.5 V) 100 ns (f(XIN) = 10 MHz, VCC = 2.7 to 5.5 V) Single-chip 1 Mbyte See Table 1.3 Product Information for R8C/1A Group Peripheral I/O ports: 13 pins (including LED drive port) Functions Input port: 3 pins LED drive ports I/O ports: 4 pins Timers Timer X: 8 bits x 1 channel, timer Z: 8 bits x 1 channel (Each timer equipped with 8-bit prescaler) Timer C: 16 bits x 1 channel (Input capture and output compare circuits) Serial interfaces 1 channel Clock synchronous serial I/O, UART 1 channel UART Clock synchronous serial interface 1 channel I2C bus Interface(1) Clock synchronous serial I/O with chip select (SSU) A/D converter 10-bit A/D converter: 1 circuit, 4 channels Watchdog timer 15 bits x 1 channel (with prescaler) Reset start selectable, count source protection mode Internal: 11 sources, External: 4 sources, Software: 4 sources, Interrupts Priority levels: 7 levels Clock generation circuits 2 circuits * Main clock oscillation circuit (with on-chip feedback resistor) * On-chip oscillator (high speed, low speed) High-speed on-chip oscillator has a frequency adjustment function Oscillation stop detection function Main clock oscillation stop detection function Voltage detection circuit On-chip Power-on reset circuit On-chip Electric Supply voltage VCC = 3.0 to 5.5 V (f(XIN) = 20 MHz) Characteristics VCC = 2.7 to 5.5 V (f(XIN) = 10 MHz) Current consumption Typ. 9 mA (VCC = 5.0 V, f(XIN) = 20 MHz, A/D converter stopped) Typ. 5 mA (VCC = 3.0 V, f(XIN) = 10 MHz, A/D converter stopped) Typ. 35 A (VCC = 3.0 V, wait mode, peripheral clock off) Typ. 0.7 A (VCC = 3.0 V, stop mode) Flash Memory Programming and erasure voltage VCC = 2.7 to 5.5 V Programming and erasure 100 times endurance Operating Ambient Temperature -20 to 85C -40 to 85C (D version) -20 to 105C (Y version) (2) Package 20-pin molded-plastic LSSOP 20-pin molded-plastic SDIP 28-pin molded-plastic HWQFN NOTE: 1. I2C bus is a trademark of Koninklijke Philips Electronics N. V. 2. Please contact Renesas Technology sales offices for the Y version.
Rev.1.40 Dec 08, 2006 REJ03B0144-0140
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R8C/1A Group, R8C/1B Group
1. Overview
Table 1.2
CPU
Functions and Specifications for R8C/1B Group
Item Number of fundamental instructions Minimum instruction execution time Operating mode Address space Memory capacity Ports Specification 89 instructions
50 ns (f(XIN) = 20 MHz, VCC = 3.0 to 5.5 V) 100 ns (f(XIN) = 10 MHz, VCC = 2.7 to 5.5 V) Single-chip 1 Mbyte See Table 1.4 Product Information for R8C/1B Group Peripheral I/O ports: 13 pins (including LED drive port) Functions Input port: 3 pins LED drive ports I/O ports: 4 pins Timers Timer X: 8 bits x 1 channel, timer Z: 8 bits x 1 channel (Each timer equipped with 8-bit prescaler) Timer C: 16 bits x 1 channel (Input capture and output compare circuits) Serial interfaces 1 channel Clock synchronous serial I/O, UART 1 channel UART Clock synchronous serial interface 1 channel I2C bus Interface(1) Clock synchronous serial I/O with chip select (SSU) A/D converter 10-bit A/D converter: 1 circuit, 4 channels Watchdog timer 15 bits x 1 channel (with prescaler) Reset start selectable, count source protection mode Internal: 11 sources, External: 4 sources, Software: 4 sources, Interrupts Priority levels: 7 levels Clock generation circuits 2 circuits * Main clock generation circuit (with on-chip feedback resistor) * On-chip oscillator (high speed, low speed) High-speed on-chip oscillator has a frequency adjustment function Oscillation stop detection function Main clock oscillation stop detection function Voltage detection circuit On-chip Power on reset circuit On-chip Electric Supply voltage VCC = 3.0 to 5.5 V (f(XIN) = 20 MHz) Characteristics VCC = 2.7 to 5.5 V (f(XIN) = 10 MHz) Current consumption Typ. 9 mA (VCC = 5.0 V, f(XIN) = 20 MHz, A/D converter stopped) Typ. 5 mA (VCC = 3.0 V, f(XIN) = 10 MHz, A/D converter stopped) Typ. 35 A (VCC = 3.0 V, wait mode, peripheral clock off) Typ. 0.7 A (VCC = 3.0 V, stop mode) Flash Memory Programming and erasure voltage VCC = 2.7 to 5.5 V Programming and erasure 10,000 times (data flash) endurance 1,000 times (program ROM) Operating Ambient Temperature -20 to 85C -40 to 85C (D version) -20 to 105C (Y version) (2) Package 20-pin molded-plastic LSSOP 20-pin molded-plastic SDIP 28-pin molded-plastic HWQFN NOTE: 1. I2C bus is a trademark of Koninklijke Philips Electronics N. V. 2. Please contact Renesas Technology sales offices for the Y version.
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R8C/1A Group, R8C/1B Group
1. Overview
1.3
Block Diagram
Figure 1.1 shows a Block Diagram.
8
4
1
3
I/O ports
Peripheral Functions
Timers
Port P1
Port P3
Port P4
A/D converter (10 bits x 4 channels)
Timer X (8 bits) Timer Z (8 bits) Timer C (16 bits)
UART or clock synchronous serial I/O (8 bits x 1 channel)
System clock generator XIN-XOUT High-speed on-chip oscillator Low-speed on-chip oscillator
UART (8 bits x 1 channel)
SSU (8 bits x 1 channel) or I2C bus
Watchdog timer (15 bits)
R8C/Tiny Series CPU core
R0H R1H R2 R3 A0 A1 FB R0L R1L SB USP ISP INTB PC FLG
Memory
ROM(1)
RAM(2)
Multiplier
NOTES: 1. ROM size varies with MCU type. 2. RAM size varies with MCU type.
Figure 1.1
Block Diagram
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R8C/1A Group, R8C/1B Group
1. Overview
1.4
Product Information
Table 1.3 lists Product Information for R8C/1A Group and Table 1.4 lists Product Information for R8C/1B Group. Table 1.3 Product Information for R8C/1A Group ROM Capacity 4 Kbytes 8 Kbytes 12 Kbytes 16 Kbytes 4 Kbytes 8 Kbytes 12 Kbytes 16 Kbytes 4 Kbytes 8 Kbytes 12 Kbytes 16 Kbytes 8 Kbytes 12 Kbytes 16 Kbytes 4 Kbytes 8 Kbytes 12 Kbytes 16 Kbytes 4 Kbytes 8 Kbytes 12 Kbytes 16 Kbytes 4 Kbytes 8 Kbytes 12 Kbytes 16 Kbytes 8 Kbytes 12 Kbytes 16 Kbytes RAM Capacity 384 bytes 512 bytes 768 bytes 1 Kbyte 384 bytes 512 bytes 768 bytes 1 Kbyte 384 bytes 512 bytes 768 bytes 1 Kbyte 512 bytes 768 bytes 1 Kbyte 384 bytes 512 bytes 768 bytes 1 Kbyte 384 bytes 512 bytes 768 bytes 1 Kbyte 384 bytes 512 bytes 768 bytes 1 Kbyte 512 bytes 768 bytes 1 Kbyte Current of October 2006
Type No. R5F211A1SP R5F211A2SP R5F211A3SP R5F211A4SP R5F211A1DSP R5F211A2DSP R5F211A3DSP R5F211A4DSP R5F211A1DD R5F211A2DD R5F211A3DD R5F211A4DD R5F211A2NP R5F211A3NP R5F211A4NP R5F211A1XXXSP R5F211A2XXXSP R5F211A3XXXSP R5F211A4XXXSP R5F211A1DXXXSP R5F211A2DXXXSP R5F211A3DXXXSP R5F211A4DXXXSP R5F211A1XXXDD R5F211A2XXXDD R5F211A3XXXDD R5F211A4XXXDD R5F211A2XXXNP R5F211A3XXXNP R5F211A4XXXNP
NOTE:
Package Type Remarks PLSP0020JB-A PLSP0020JB-A PLSP0020JB-A PLSP0020JB-A PLSP0020JB-A D version PLSP0020JB-A PLSP0020JB-A PLSP0020JB-A PRDP0020BA-A PRDP0020BA-A PRDP0020BA-A PRDP0020BA-A PWQN0028KA-B PWQN0028KA-B PWQN0028KA-B PLSP0020JB-A Factory programming product (1) PLSP0020JB-A PLSP0020JB-A PLSP0020JB-A PLSP0020JB-A D version PLSP0020JB-A PLSP0020JB-A PLSP0020JB-A PRDP0020BA-A Factory programming product (1) PRDP0020BA-A PRDP0020BA-A PRDP0020BA-A PWQN0028KA-B PWQN0028KA-B PWQN0028KA-B
1. The user ROM is programmed before shipment.
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R8C/1A Group, R8C/1B Group
1. Overview
Type No.
R 5 F 21 1A 4 D XXX SP
Package type: SP: PLSP0020JB-A DD: PRDP0020BA-A NP: PWQN0028KA-B ROM number Classification D: Operating ambient temperature -40C to 85C No Symbol: Operating ambient temperature -20C to 85C Y: Operating ambient temperature -20C to 105C (Note) ROM capacity 1: 4 KB 2: 8 KB 3: 12 KB 4: 16 KB R8C/1A Group R8C/Tiny Series Memory type F: Flash memory version Renesas MCU Renesas semiconductors
NOTE: Please contact Renesas Technology sales offices for the Y version.
Figure 1.2
Type Number, Memory Size, and Package of R8C/1A Group
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R8C/1A Group, R8C/1B Group
1. Overview
Table 1.4
Product Information for R8C/1B Group ROM Capacity Program ROM Data Flash 4 Kbytes 1 Kbyte x 2 8 Kbytes 1 Kbyte x 2 12 Kbytes 1 Kbyte x 2 16 Kbytes 1 Kbyte x 2 4 Kbytes 1 Kbyte x 2 8 Kbytes 1 Kbyte x 2 12 Kbytes 1 Kbyte x 2 16 Kbytes 1 Kbyte x 2 4 Kbytes 1 Kbyte x 2 8 Kbytes 1 Kbyte x 2 12 Kbytes 1 Kbyte x 2 16 Kbytes 1 Kbyte x 2 8 Kbytes 1 Kbyte x 2 12 Kbytes 1 Kbyte x 2 16 Kbytes 1 Kbyte x 2 4 Kbytes 1 Kbyte x 2 8 Kbytes 1 Kbyte x 2 12 Kbytes 1 Kbyte x 2 16 Kbytes 1 Kbyte x 2 4 Kbytes 1 Kbyte x 2 8 Kbytes 1 Kbyte x 2 12 Kbytes 1 Kbyte x 2 16 Kbytes 1 Kbyte x 2 4 Kbytes 1 Kbyte x 2 8 Kbytes 1 Kbyte x 2 12 Kbytes 1 Kbyte x 2 16 Kbytes 1 Kbyte x 2 8 Kbytes 1 Kbyte x 2 12 Kbytes 1 Kbyte x 2 16 Kbytes 1 Kbyte x 2 RAM Capacity 384 bytes 512 bytes 768 bytes 1 Kbyte 384 bytes 512 bytes 768 bytes 1 Kbyte 384 bytes 512 bytes 768 bytes 1 Kbyte 512 bytes 768 bytes 1 Kbyte 384 bytes 512 bytes 768 bytes 1 Kbyte 384 bytes 512 bytes 768 bytes 1 Kbyte 384 bytes 512 bytes 768 bytes 1 Kbyte 512 bytes 768 bytes 1 Kbyte
Current of October 2006 Package Type PLSP0020JB-A PLSP0020JB-A PLSP0020JB-A PLSP0020JB-A PLSP0020JB-A PLSP0020JB-A PLSP0020JB-A PLSP0020JB-A PRDP0020BA-A PRDP0020BA-A PRDP0020BA-A PRDP0020BA-A PWQN0028KA-B PWQN0028KA-B PWQN0028KA-B PLSP0020JB-A PLSP0020JB-A PLSP0020JB-A PLSP0020JB-A PLSP0020JB-A PLSP0020JB-A PLSP0020JB-A PLSP0020JB-A PRDP0020BA-A PRDP0020BA-A PRDP0020BA-A PRDP0020BA-A PWQN0028KA-B PWQN0028KA-B PWQN0028KA-B Remarks
Type No. R5F211B1SP R5F211B2SP R5F211B3SP R5F211B4SP R5F211B1DSP R5F211B2DSP R5F211B3DSP R5F211B4DSP R5F211B1DD R5F211B2DD R5F211B3DD R5F211B4DD R5F211B2NP R5F211B3NP R5F211B4NP R5F211B1XXXSP R5F211B2XXXSP R5F211B3XXXSP R5F211B4XXXSP R5F211B1DXXXSP R5F211B2DXXXSP R5F211B3DXXXSP R5F211B4DXXXSP R5F211B1XXXDD R5F211B2XXXDD R5F211B3XXXDD R5F211B4XXXDD R5F211B2XXXNP R5F211B3XXXNP R5F211B4XXXNP
NOTE:
D version
Factory programming product (1)
D version
Factory programming product (1)
1. The user ROM is programmed before shipment.
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R8C/1A Group, R8C/1B Group
1. Overview
Type No.
R 5 F 21 1B 4 D XXX SP
Package type: SP: PLSP0020JB-A DD: PRDP0020BA-A NP: PWQN0028KA-B ROM number Classification D: Operating ambient temperature -40C to 85C No Symbol: Operating ambient temperature -20C to 85C Y: Operating ambient temperature -20C to 105C (Note) ROM capacity 1: 4 KB 2: 8 KB 3: 12 KB 4: 16 KB R8C/1B Group R8C/Tiny Series Memory Type F: Flash memory version Renesas MCU Renesas semiconductors
NOTE: Please contact Renesas Technology sales offices for the Y version.
Figure 1.3
Type Number, Memory Size, and Package of R8C/1B Group
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R8C/1A Group, R8C/1B Group
1. Overview
1.5
Pin Assignments
Figure 1.4 shows Pin Assignments for PLSP0020JB-A Package (Top View), Figure 1.5 shows Pin Assignments for PRDP0020BA-A Package (Top View) and Figure 1.6 shows Pin Assignments for PWQN0028KA-B Package (Top View).
PIN assignments (top view)
P3_5/SSCK/SCL/CMP1_2
P3_7/CNTR0/SSO/TXD1
RESET XOUT/P4_7(1) VSS/AVSS XIN/P4_6 VCC/AVCC MODE
P4_5/INT0/RXD1
P1_7/CNTR00/INT10
1
2
3
20
19
18
P3_4/SCS/SDA/CMP1_1
P3_3/TCIN/INT3/SSI00/CMP1_0
P1_0/KI0/AN8/CMP0_0
P1_1/KI1/AN9/CMP0_1
P4_2/VREF
P1_2/KI2/AN10/CMP0_2
P1_3/KI3/AN11/TZOUT
P1_4/TXD0
P1_5/RXD0/CNTR01/INT11
P1_6/CLK0/SSI01
R8C/1A Group R8C/1B Group
4
5
6
7
8
9
10
17
16
15
14
13
12
11
NOTE: 1. P4_7 is an input-only port.
Package: PLSP0020JB-A (20P2F-A)
Figure 1.4
Pin Assignments for PLSP0020JB-A Package (Top View)
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R8C/1A Group, R8C/1B Group
1. Overview
PIN assignments (top view)
P3_5/SSCK/SCL/CMP1_2
P3_7/CNTR0/SSO/TXD1
RESET XOUT/P4_7(1) VSS/AVSS XIN/P4_6 VCC/AVCC MODE
P4_5/INT0/RXD1
P1_7/CNTR00/INT10
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
P3_4/SCS/SDA/CMP1_1
P3_3/TCIN/INT3/SSI00/CMP1_0
P1_0/KI0/AN8/CMP0_0
P1_1/KI1/AN9/CMP0_1
P4_2/VREF
P1_2/KI2/AN10/CMP0_2
P1_3/KI3/AN11/TZOUT
P1_4/TXD0
P1_5/RXD0/CNTR01/INT11
P1_6/CLK0/SSI01
NOTE: 1. P4_7 is an input-only port. Package: PRDP0020BA-A (20P4B)
R8C/1A Group R8C/1B Group
Figure 1.5
Pin Assignments for PRDP0020BA-A Package (Top View)
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R8C/1A Group, R8C/1B Group
1. Overview
PIN Assignment (top view)
P1_2/AN10/KI2/CMP0_2
P1_3/AN11/KI3/TZOUT
P4_2/VREF
NC
NC
NC
21 20 19 18 17 16 15
P1_1/AN9/KI1/CMP0_1
22
NC
14
P1_4/TXD0 P1_5/RXD0/CNTR01/INT11 P1_6/CLK0/SSI01
P1_0/AN8/KI0/CMP0_0
23
13
P3_3/TCIN/INT3/SSI00/CMP1_0
24
P3_4/SCS/SDA/CMP1_1
25
R8C/1A Group R8C/1B Group
12
11
P1_7/CNTR00/INT10
P3_5/SSCK/SCL/CMP1_2
26
10
P4_5/INT0/RXD1 MODE VCC/AVCC
P3_7/CNTR0/SSO/TXD1
27
9
RESET
28
8
1
2
3
4
5
6
7
(1)
VSS/AVSS
XIN/P4_6
NC
NC
NC
NOTES: 1. P4_7 is a port for the input.
Package: PWQN0028KA-B(28PJW-B)
Figure 1.6
Pin Assignments for PWQN0028KA-B Package (Top View)
Rev.1.40 Dec 08, 2006 REJ03B0144-0140
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XOUT/P4_7
NC
R8C/1A Group, R8C/1B Group
1. Overview
1.6
Pin Functions
Table 1.5 lists Pin Functions, Table 1.6 lists Pin Name Information by Pin Number of PLSP0020JB-A, PRDP0020BA-A Packages and Table 1.7 lists Pin Name Information by Pin Number of PWQN0028KAB Package. Table 1.5 Type Pin Functions Symbol I/O Type I I I I I O Description Apply 2.7 V to 5.5 V to the VCC pin. Apply 0 V to the VSS pin. Power supply for the A/D converter Connect a capacitor between AVCC and AVSS. Input "L" on this pin resets the MCU. Connect this pin to VCC via a resistor. These pins are provided for main clock generation circuit I/O. Connect a ceramic resonator or a crystal oscillator between the XIN and XOUT pins. To use an external clock, input it to the XIN pin and leave the XOUT pin open. INT interrupt input pins Key input interrupt input pins Timer X I/O pin Timer X output pin Timer Z output pin Timer C input pin Timer C output pins Transfer clock I/O pin Serial data input pins Serial data output pins Data I/O pin. Chip-select signal I/O pin Clock I/O pin Data I/O pin Clock I/O pin Data I/O pin Reference voltage input pin to A/D converter Analog input pins to A/D converter CMOS I/O ports. Each port has an I/O select direction register, allowing each pin in the port to be directed for input or output individually. Any port set to input can be set to use a pull-up resistor or not by a program. P1_0 to P1_3 also function as LED drive ports. Input-only ports
Power Supply Input VCC, VSS Analog Power Supply Input Reset Input MODE Main Clock Input Main Clock Output AVCC, AVSS RESET MODE XIN XOUT
INT Interrupt Key Input Interrupt Timer X Timer Z Timer C
INT0, INT1, INT3 KI0 to KI3 CNTR0 CNTR0 TZOUT TCIN CMP0_0 to CMP0_2, CMP1_0 to CMP1_2
I I I/O O O I O I/O I O I/O I/O I/O I/O I/O I/O I I I/O
Serial Interface
CLK0 RXD0, RXD1 TXD0, TXD1
Clock synchronous SSI00, SSI01 serial I/O with chip SCS select (SSU) SSCK SSO I2C bus Interface SCL SDA Reference Voltage Input A/D Converter I/O Port VREF AN8 to AN11 P1_0 to P1_7, P3_3 to P3_5, P3_7, P4_5
Input Port I: Input
P4_2, P4_6, P4_7 O: Output
I
I/O: Input and output
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R8C/1A Group, R8C/1B Group
1. Overview
Table 1.6
Pin Name Information by Pin Number of PLSP0020JB-A, PRDP0020BA-A Packages I/O Pin Functions for Peripheral Modules Clock Synchronous I2C bus Serial A/D Timer Interface Serial I/O with Interface Converter Chip Select CMP1_2 SSCK SCL TXD1 SSO CNTR0
Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
Control Pin
Port
Interrupt
P3_5 P3_7 RESET XOUT VSS/AVSS XIN VCC/AVCC MODE P4_7 P4_6
P4_5 P1_7 P1_6 P1_5 P1_4 P1_3 P1_2 VREF P4_2 P1_1 P1_0 P3_3 P3_4
INT0 INT10 INT11 KI3 KI2 KI1 KI0 INT3 CNTR00 CNTR01 TZOUT CMP0_2 CMP0_1 CMP0_0 TCIN/ CMP1_0 CMP1_1
RXD1 CLK0 RXD0 TXD0 AN11 AN10 AN9 AN8 SSI00 SCS SDA SSI01
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R8C/1A Group, R8C/1B Group
1. Overview
Table 1.7
Pin Name Information by Pin Number of PWQN0028KA-B Package I/O Pin Functions for Peripheral Modules Clock Serial Synchronous I2C bus A/D Timer Interface Serial I/O with Interface Converter Chip Select
Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
Control Pin NC XOUT VSS/AVSS NC NC XIN NC VCC/AVCC MODE
Port
Interrupt
P4_7
P4_6
P4_5 P1_7 P1_6 P1_5 P1_4 NC P1_3 P1_2 NC NC VREF NC
INT0 INT10 INT11 CNTR00 CNTR01
RXD1 CLK0 RXD0 TXD0 SSI01
KI3 KI2
TZOUT CMP0_2
AN11 AN10
P4_2 P1_1 P1_0 P3_3 P3_4 P3_5 P3_7 KI1 KI0 INT3 CMP0_1 CMP0_0 TCIN/CMP1_0 CMP1_1 CMP1_2 CNTR0 TXD1 SSI00 SCS SSCK SSO SDA SCL AN9 AN8
RESET
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R8C/1A Group, R8C/1B Group
2. Central Processing Unit (CPU)
2.
Central Processing Unit (CPU)
Figure 2.1 shows the CPU Registers. The CPU contains 13 registers. R0, R1, R2, R3, A0, A1, and FB configure a register bank. There are two sets of register bank.
b31
b15
b8b7
b0
R2 R3
R0H (high-order of R0)
R1H (high-order of R1)
R0L (low-order of R0) R1L (low-order of R1)
R2 R3 A0 A1 FB
b19 b15 b0
Data registers (1)
Address registers (1)
Frame base register (1)
INTBH
INTBL
Interrupt table register
The 4 high order bits of INTB are INTBH and the 16 low bits of INTB are INTBL.
b19 b0
PC
Program counter
b15
b0
USP ISP SB
b15 b0
User stack pointer Interrupt stack pointer Static base register
FLG
b15 b8 b7 b0
Flag register
IPL
U I OBSZDC
Carry flag Debug flag Zero flag Sign flag Register bank select flag Overflow flag Interrupt enable flag Stack pointer select flag Reserved bit Processor interrupt priority level Reserved bit
NOTE: 1. These registers comprise a register bank. There are two register banks.
Figure 2.1
CPU Register
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R8C/1A Group, R8C/1B Group
2. Central Processing Unit (CPU)
2.1
Data Registers (R0, R1, R2, and R3)
R0 is a 16-bit register for transfer, arithmetic, and logic operations. The same applies to R1 to R3. R0 can be split into high-order bits (R0H) and low-order bits (R0L) to be used separately as 8-bit data registers. R1H and R1L are analogous to R0H and R0L. R2 can be combined with R0 and used as a 32bit data register (R2R0). R3R1 is analogous to R2R0.
2.2
Address Registers (A0 and A1)
A0 is a 16-bit register for address register indirect addressing and address register relative addressing. It is also used for transfer and arithmetic and logic operations. A1 is analogous to A0. A1 can be combined with A0 and used as a 32-bit address register (A1A0).
2.3
Frame Base Register (FB)
FB is a 16-bit register for FB relative addressing.
2.4
Interrupt Table Register (INTB)
INTB is a 20-bit register that indicates the start address of an interrupt vector table.
2.5
Program Counter (PC)
PC is 20 bits wide indicates the address of the next instruction to be executed.
2.6
User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)
The stack pointer (SP), USP, and ISP, are each 16 bits wide. The U flag of FLG is used to switch between USP and ISP.
2.7
Static Base Register (SB)
SB is a 16-bit register for SB relative addressing.
2.8
Flag Register (FLG)
FLG is an 11-bit register indicating the CPU state.
2.8.1
Carry Flag (C)
The C flag retains a carry, borrow, or shift-out bits that have been generated by the arithmetic and logic unit.
2.8.2
Debug Flag (D)
The D flag is for debugging only. Set it to 0.
2.8.3
Zero Flag (Z)
The Z flag is set to 1 when an arithmetic operation results in 0; otherwise to 0.
2.8.4
Sign Flag (S)
The S flag is set to 1 when an arithmetic operation results in a negative value; otherwise to 0.
2.8.5
Register Bank Select Flag (B)
Register bank 0 is selected when the B flag is 0. Register bank 1 is selected when this flag is set to 1.
2.8.6
Overflow Flag (O)
The O flag is set to 1 when the operation results in an overflow; otherwise to 0.
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R8C/1A Group, R8C/1B Group
2. Central Processing Unit (CPU)
2.8.7
Interrupt Enable Flag (I)
The I flag enables maskable interrupts. Interrupts are disabled when the I flag is set to 0, and are enabled when the I flag is set to 1. The I flag is set to 0 when an interrupt request is acknowledged.
2.8.8
Stack Pointer Select Flag (U)
ISP is selected when the U flag is set to 0; USP is selected when the U flag is set to 1. The U flag is set to 0 when a hardware interrupt request is acknowledged or the INT instruction of software interrupt numbers 0 to 31 is executed.
2.8.9
Processor Interrupt Priority Level (IPL)
IPL is 3 bits wide, assigns processor interrupt priority levels from level 0 to level 7. If a requested interrupt has higher priority than IPL, the interrupt is enabled.
2.8.10
Reserved Bit
If necessary, set to 0. When read, the content is undefined.
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R8C/1A Group, R8C/1B Group
3. Memory
3.
3.1
Memory
R8C/1A Group
Figure 3.1 is a Memory Map of R8C/1A Group. The R8C/1A Group has 1 Mbyte of address space from addresses 00000h to FFFFFh. The internal ROM is allocated lower addresses, beginning with address 0FFFFh. For example, a 16Kbyte internal ROM area is allocated addresses 0C000h to 0FFFFh. The fixed interrupt vector table is allocated addresses 0FFDCh to 0FFFFh. They store the starting address of each interrupt routine. The internal RAM is allocated higher addresses, beginning with address 00400h. For example, a 1Kbyte internal RAM area is allocated addresses 00400h to 007FFh. The internal RAM is used not only for storing data but also for calling subroutines and as stacks when interrupt requests are acknowledged. Special function registers (SFRs) are allocated addresses 00000h to 002FFh. The peripheral function control registers are allocated here. All addresses within the SFR, which have nothing allocated are reserved for future use and cannot be accessed by users.
00000h
SFR
(See 4. Special Function Registers (SFRs)) 002FFh
00400h
Internal RAM
0XXXXh 0FFDCh
Undefined instruction Overflow BRK instruction Address match Single step
Watchdog timer*oscillation stop detection*voltage monitor 2
0YYYYh
Internal ROM
0FFFFh 0FFFFh
Address break (Reserved) Reset
Expanded area
FFFFFh
NOTE: 1. The blank regions are reserved. Do not access locations in these regions. Internal ROM Part Number Size Address 0YYYYh 0C000h Internal RAM Size Address 0XXXXh 007FFh
R5F211A4SP, R5F211A4DSP, R5F211A4DD, R5F211A4NP, R5F211A4XXXSP, R5F211A4DXXXSP, R5F211A4XXXDD, R5F211A4XXXNP R5F211A3SP, R5F211A3DSP, R5F211A3DD, R5F211A3NP, R5F211A3XXXSP, R5F211A3DXXXSP, R5F211A3XXXDD, R5F211A3XXXNP R5F211A2SP, R5F211A2DSP, R5F211A2DD, R5F211A2NP, R5F211A2XXXSP, R5F211A2DXXXSP, R5F211A2XXXDD, R5F211A2XXXNP R5F211A1SP, R5F211A1DSP, R5F211A1DD, R5F211A1XXXSP, R5F211A1DXXXSP, R5F211A1XXXDD 8 Kbytes 0E000h 512 bytes 005FFh 12 Kbytes 0D000h 768 bytes 006FFh 16 Kbytes 1 Kbyte
4 Kbytes
0F000h
384 bytes
0057Fh
Figure 3.1
Memory Map of R8C/1A Group Page 18 of 45
Rev.1.40 Dec 08, 2006 REJ03B0144-0140
R8C/1A Group, R8C/1B Group
3. Memory
3.2
R8C/1B Group
Figure 3.2 is a Memory Map of R8C/1B Group. The R8C/1B Group has 1 Mbyte of address space from addresses 00000h to FFFFFh. The internal ROM (program ROM) is allocated lower addresses, beginning with address 0FFFFh. For example, a 16-Kbyte internal ROM area is allocated addresses 0C000h to 0FFFFh. The fixed interrupt vector table is allocated addresses 0FFDCh to 0FFFFh. They store the starting address of each interrupt routine. The internal ROM (data flash) is allocated addresses 02400h to 02BFFh. The internal RAM is allocated higher addresses beginning with address 00400h. For example, a 1Kbyte internal RAM area is allocated addresses 00400h to 007FFh. The internal RAM is used not only for storing data but also for calling subroutines and as stacks when interrupt requests are acknowledged. Special function registers (SFRs) are allocated addresses 00000h to 002FFh. The peripheral function control registers are allocated here. All addresses within the SFR, which have nothing allocated are reserved for future use and cannot be accessed by users.
00000h
SFR
(See 4. Special Function Registers (SFRs)) 002FFh 00400h
Internal RAM
0XXXXh
02400h 02BFFh
Internal ROM (data Flash)(1)
0FFDCh
Undefined instruction Overflow BRK instruction Address match Single step
Watchdog timer * oscillation stop detection * voltage monitor 2
0YYYYh
Internal ROM (program ROM)
0FFFFh 0FFFFh
Address break (Reserved) Reset
Expanded area
FFFFFh
NOTES: 1. Data flash block A (1 Kbyte) and B (1 Kbyte) are shown. 2. The blank regions are reserved. Do not access locations in these regions. Internal ROM Part Number R5F211B4SP, R5F211B4DSP, R5F211B4DD, R5F211B4NP, R5F211B4XXXSP, R5F211B4DXXXSP, R5F211B4XXXDD, R5F211B4XXXNP R5F211B3SP, R5F211B3DSP, R5F211B3DD, R5F211B3NP, R5F211B3XXXSP, R5F211B3DXXXSP, R5F211B3XXXDD, R5F211B3XXXNP R5F211B2SP, R5F211B2DSP, R5F211B2DD, R5F211B2NP, R5F211B2XXXSP, R5F211B2DXXXSP, R5F211B2XXXDD, R5F211B2XXXNP R5F211B1SP, R5F211B1DSP, R5F211B1DD, R5F211B1XXXSP, R5F211B1DXXXSP, R5F211B1XXXDD 8 Kbytes 0E000h 512 bytes 005FFh 12 Kbytes 0D000h 768 bytes 006FFh 16 Kbytes 0C000h 1 Kbyte 007FFh Size Address 0YYYYh Internal RAM Size Address 0XXXXh
4 Kbytes
0F000h
384 bytes
0057Fh
Figure 3.2
Memory Map of R8C/1B Group
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R8C/1A Group, R8C/1B Group
4. Special Function Registers (SFRs)
4.
Special Function Registers (SFRs)
An SFR (special function register) is a control register for a peripheral function. Tables 4.1 to 4.4 list the special function registers. Table 4.1 SFR Information (1)(1)
Address 0000h 0001h 0002h 0003h 0004h 0005h 0006h 0007h 0008h 0009h 000Ah 000Bh 000Ch 000Dh 000Eh 000Fh 0010h 0011h 0012h 0013h 0014h 0015h 0016h 0017h 0018h 0019h 001Ah 001Bh 001Ch 001Dh 001Eh 001Fh 0020h 0021h 0022h 0023h 002Ah 002Bh 002Ch 002Dh 002Eh 002Fh 0030h 0031h 0032h 0033h 0034h 0035h 0036h 0037h 0038h 0039h 003Ah 003Bh 003Ch 003Dh 003Eh 003Fh Register Symbol After reset
Processor Mode Register 0 Processor Mode Register 1 System Clock Control Register 0 System Clock Control Register 1 Address Match Interrupt Enable Register Protect Register Oscillation Stop Detection Register Watchdog Timer Reset Register Watchdog Timer Start Register Watchdog Timer Control Register Address Match Interrupt Register 0
PM0 PM1 CM0 CM1 AIER PRCR OCD WDTR WDTS WDC RMAD0
00h 00h 01101000b 00100000b 00h 00h 00000100b XXh XXh 00X11111b 00h 00h X0h 00h 00h X0h
Address Match Interrupt Register 1
RMAD1
Count Source Protection Mode Register INT0 Input Filter Select Register High-Speed On-Chip Oscillator Control Register 0 High-Speed On-Chip Oscillator Control Register 1 High-Speed On-Chip Oscillator Control Register 2
CSPR INT0F HRA0 HRA1 HRA2
00h 00h 00h When shipping 00h
Voltage Detection Register 1(2) Voltage Detection Register 2(2)
VCA1 VCA2
00001000b 00h(3) 01000000b(4)
Voltage Monitor 1 Circuit Control Register (2) Voltage Monitor 2 Circuit Control Register (5)
VW1C VW2C
0000X000b(3) 0100X001b(4) 00h
X: Undefined NOTES: 1. The blank regions are reserved. Do not access locations in these regions. 2. Software reset, watchdog timer reset, and voltage monitor 2 reset do not affect this register. 3. After hardware reset. 4. After power-on reset or voltage monitor 1 reset. 5. Software reset, watchdog timer reset, and voltage monitor 2 reset do not affect b2 and b3.
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R8C/1A Group, R8C/1B Group Table 4.2
Address 0040h 0041h 0042h 0043h 0044h 0045h 0046h 0047h 0048h 0049h 004Ah 004Bh 004Ch 004Dh 004Eh 004Fh 0050h 0051h 0052h 0053h 0054h 0055h 0056h 0057h 0058h 0059h 005Ah 005Bh 005Ch 005Dh 005Eh 005Fh 0060h 0061h 0062h 0063h 0064h 0065h 0066h 0067h 0068h 0069h 006Ah 006Bh 006Ch 006Dh 006Eh 006Fh 0070h 0071h 0072h 0073h 0074h 0075h 0076h 0077h 0078h 0079h 007Ah 007Bh 007Ch 007Dh 007Eh 007Fh
4. Special Function Registers (SFRs)
SFR Information (2)(1)
Register Symbol After reset
Key Input Interrupt Control Register A/D Conversion Interrupt Control Register SSU/IIC Interrupt Control Register(2) Compare 1 Interrupt Control Register UART0 Transmit Interrupt Control Register UART0 Receive Interrupt Control Register UART1 Transmit Interrupt Control Register UART1 Receive Interrupt Control Register Timer X Interrupt Control Register Timer Z Interrupt Control Register INT1 Interrupt Control Register INT3 Interrupt Control Register Timer C Interrupt Control Register Compare 0 Interrupt Control Register INT0 Interrupt Control Register
KUPIC ADIC SSUAIC/IIC2AIC CMP1IC S0TIC S0RIC S1TIC S1RIC TXIC TZIC INT1IC INT3IC TCIC CMP0IC INT0IC
XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XX00X000b
X: Undefined NOTES: 1. The blank regions are reserved. Do not access locations in these regions. 2. Selected by the IICSEL bit in the PMR register.
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R8C/1A Group, R8C/1B Group Table 4.3
Address 0080h 0081h 0082h 0083h 0084h 0085h 0086h 0087h 0088h 0089h 008Ah 008Bh 008Ch 008Dh 008Eh 008Fh 0090h 0091h 0092h 0093h 0094h 0095h 0096h 0097h 0098h 0099h 009Ah 009Bh 009Ch 009Dh 009Eh 009Fh 00A0h 00A1h 00A2h 00A3h 00A4h 00A5h 00A6h 00A7h 00A8h 00A9h 00AAh 00ABh 00ACh 00ADh 00AEh 00AFh 00B0h 00B1h 00B2h 00B3h 00B4h 00B5h 00B6h 00B7h 00B8h 00B9h 00BAh 00BBh 00BCh 00BDh 00BEh 00BFh
4. Special Function Registers (SFRs)
SFR Information (3)(1)
Register Timer Z Mode Register Symbol TZMR After reset 00h
Timer Z Waveform Output Control Register Prescaler Z Register Timer Z Secondary Register Timer Z Primary Register
PUM PREZ TZSC TZPR
00h FFh FFh FFh
Timer Z Output Control Register Timer X Mode Register Prescaler X Register Timer X Register Timer Count Source Setting Register Timer C Register
TZOC TXMR PREX TX TCSS TC
00h 00h FFh FFh 00h 00h 00h
External Input Enable Register Key Input Enable Register Timer C Control Register 0 Timer C Control Register 1 Capture, Compare 0 Register Compare 1 Register UART0 Transmit/Receive Mode Register UART0 Bit Rate Generator UART0 Transmit Buffer Register UART0 Transmit/Receive Control Register 0 UART0 Transmit/Receive Control Register 1 UART0 Receive Buffer Register UART1 Transmit/Receive Mode Register UART1 Bit Rate Generator UART1 Transmit Buffer Register UART1 Transmit/Receive Control Register 0 UART1 Transmit/Receive Control Register 1 UART1 Receive Buffer Register UART Transmit/Receive Control Register 2
INTEN KIEN TCC0 TCC1 TM0 TM1 U0MR U0BRG U0TB U0C0 U0C1 U0RB U1MR U1BRG U1TB U1C0 U1C1 U1RB UCON
00h 00h 00h 00h 0000h(2) FFFFh(3) FFh FFh 00h XXh XXh XXh 00001000b 00000010b XXh XXh 00h XXh XXh XXh 00001000b 00000010b XXh XXh 00h
SS Control Register H / IIC bus Control Register 1(4) SS Control Register L / IIC bus Control Register 2(4) SS Mode Register / IIC bus Mode Register(4) SS Enable Register / IIC bus Interrupt Enable Register(4) SS Status Register / IIC bus Status Register(4) SS Mode Register 2 / Slave Address Register(4) SS Transmit Data Register / IIC bus Transmit Data Register(4) SS Receive Data Register / IIC bus Receive Data Register(4)
SSCRH / ICCR1 SSCRL / ICCR2 SSMR / ICMR SSER / ICIER SSSR / ICSR SSMR2 / SAR SSTDR / ICDRT SSRDR / ICDRR
00h 01111101b 00011000b 00h 00h / 0000X000b 00h FFh FFh
X: Undefined NOTES: 1. The blank regions are reserved. Do not access locations in these regions. 2. In input capture mode. 3. In output compare mode. 4. Selected by the IICSEL bit in the PMR register.
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R8C/1A Group, R8C/1B Group Table 4.4
Address 00C0h 00C1h 00C2h 00C3h 00C4h 00C5h 00C6h 00C7h 00C8h 00C9h 00CAh 00CBh 00CCh 00CDh 00CEh 00CFh 00D0h 00D1h 00D2h 00D3h 00D4h 00D5h 00D6h 00D7h 00D8h 00D9h 00DAh 00DBh 00DCh 00DDh 00DEh 00DFh 00E0h 00E1h 00E2h 00E3h 00E4h 00E5h 00E6h 00E7h 00E8h 00E9h 00EAh 00EBh 00ECh 00EDh 00EEh 00EFh 00F0h 00F1h 00F2h 00F3h 00F4h 00F5h 00F6h 00F7h 00F8h 00F9h 00FAh 00FBh 00FCh 00FDh 00FEh 00FFh 01B3h 01B4h 01B5h 01B6h 01B7h 0FFFFh
4. Special Function Registers (SFRs)
SFR Information (4)(1)
Register A/D Register Symbol AD After reset XXh XXh
A/D Control Register 2 A/D Control Register 0 A/D Control Register 1
ADCON2 ADCON0 ADCON1
00h 00000XXXb 00h
Port P1 Register Port P1 Direction Register Port P3 Register Port P3 Direction Register Port P4 Register Port P4 Direction Register
P1 PD1 P3 PD3 P4 PD4
XXh 00h XXh 00h XXh 00h
Port Mode Register
PMR
00h
Pull-Up Control Register 0 Pull-Up Control Register 1 Port P1 Drive Capacity Control Register Timer C Output Control Register Flash Memory Control Register 4 Flash Memory Control Register 1 Flash Memory Control Register 0 Optional Function Select Register
PUR0 PUR1 DRR TCOUT FMR4 FMR1 FMR0 OFS
00XX0000b XXXXXX0Xb 00h 00h 01000000b 1000000Xb 00000001b (2)
X: Undefined NOTES: 1. Blank regions, 0100h to 01B2h and 01B8h to 02FFh are all reserved. Do not access locations in these regions. 2. The OFS register cannot be changed by a user program. Use a flash programmer to write to it.
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R8C/1A Group, R8C/1B Group
5. Electrical Characteristics
5.
Electrical Characteristics
Please contact Renesas Technology sales offices for the electrical characteristics in the Y version (Topr = -20C to 105C ). Table 5.1
Symbol VCC AVCC VI VO Pd Topr Tstg Supply voltage Analog supply voltage Input voltage Output voltage Power dissipation Operating ambient temperature Storage temperature Topr = 25C
Absolute Maximum Ratings
Parameter Condition VCC = AVCC VCC = AVCC Rated Value -0.3 to 6.5 -0.3 to 6.5 -0.3 to VCC+0.3 -0.3 to VCC+0.3 300 -20 to 85 / -40 to 85 (D version) -65 to 150 Unit V V V V mW C C
Table 5.2
Symbol VCC AVCC VSS AVSS VIH VIL IOH(sum) IOH(peak) IOH(avg) IOL(sum) IOL(peak)
Recommended Operating Conditions
Parameter Supply voltage Analog supply voltage Supply voltage Analog supply voltage Input "H" voltage Input "L" voltage Peak sum output "H" current Sum of all pins IOH (peak) Conditions Standard Min. 2.7 - - - 0.8VCC 0 - - - - - Drive capacity HIGH Drive capacity LOW - - - Drive capacity HIGH Drive capacity LOW 3.0 V VCC 5.5 V 2.7 V VCC < 3.0 V 3.0 V VCC 5.5 V 2.7 V VCC < 3.0 V HRA01 = 0 Low-speed on-chip oscillator clock selected HRA01 = 1 High-speed on-chip oscillator clock selected - - 0 0 0 0 - Typ. - VCC 0 0 - - - - - - - - - - - - - - - - 125 Max. 5.5 - - - VCC 0.2VCC -60 -10 -5 60 10 30 10 5 15 5 20 10 20 10 - Unit V V V V V V mA mA mA mA mA mA mA mA mA mA MHz MHz MHz MHz kHz
Peak output "H" current Average output "H" current Peak sum output "L" currents Peak output "L" currents Average output "L" current Sum of all pins IOL (peak) Except P1_0 to P1_3 P1_0 to P1_3 Except P1_0 to P1_3 P1_0 to P1_3
IOL(avg)
f(XIN) -
Main clock input oscillation frequency System clock OCD2 = 0 Main clock selected OCD2 = 1 On-chip oscillator clock selected
-
8
-
MHz
NOTES: 1. VCC = 2.7 to 5.5 V at Topr = -20 to 85 C / -40 to 85 C, unless otherwise specified. 2. Typical values when average output current is 100 ms.
Rev.1.40 Dec 08, 2006 REJ03B0144-0140
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R8C/1A Group, R8C/1B Group
5. Electrical Characteristics
Table 5.3
Symbol - -
A/D Converter Characteristics
Parameter Resolution Absolute accuracy 10-bit mode 8-bit mode 10-bit mode 8-bit mode Vref = VCC AD = 10 MHz, Vref = VCC = 5.0 V AD = 10 MHz, Vref = VCC = 5.0 V AD = 10 MHz, Vref = VCC = 3.3 V(3) AD = 10 MHz, Vref = VCC = 3.3 V(3) Vref = VCC 10-bit mode 8-bit mode AD = 10 MHz, Vref = VCC = 5.0 V AD = 10 MHz, Vref = VCC = 5.0 V Conditions Standard Min. - - - - - 10 3.3 2.8 2.7 0 0.25 1 Without sample and hold With sample and hold Typ. - - - - - - - - - - - - Max. 10 3 2 5 2 40 - - Vcc AVcc 10 10 Unit Bits LSB LSB LSB LSB k s s V V MHz MHz
Rladder tconv Vref VIA -
Resistor ladder Conversion time Reference voltage Analog input voltage(4) A/D operating clock frequency(2)
NOTES: 1. VCC = AVCC = 2.7 to 5.5 V at Topr = -20 to 85 C / -40 to 85 C, unless otherwise specified. 2. If f1 exceeds 10 MHz, divide f1 and ensure the A/D operating clock frequency (AD) is 10 MHz or below. 3. If AVcc is less than 4.2 V, divide f1 and ensure the A/D operating clock frequency (AD) is f1/2 or below. 4. When the analog input voltage is over the reference voltage, the A/D conversion result will be 3FFh in 10-bit mode and FFh in 8-bit mode.
P1 P3 P4
30pF
Figure 5.1
Port P1, P3, and P4 Measurement Circuit
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R8C/1A Group, R8C/1B Group
5. Electrical Characteristics
Table 5.4
Symbol - - - td(SR-SUS) - - - - - - -
Flash Memory (Program ROM) Electrical Characteristics
Parameter Program/erase endurance(2) Byte program time Block erase time Time delay from suspend request until suspend Interval from erase start/restart until following suspend request Interval from program start/restart until following suspend request Time from suspend until program/erase restart Program, erase voltage Read voltage Program, erase temperature Data hold time(8) Ambient temperature = 55 C Conditions R8C/1A Group R8C/1B Group Standard Min. 100(3) 1,000(3) - - - 650 0 - 2.7 2.7 0 20 Typ. - - 50 0.4 - - - - - - - - Max. - - 400 9 97+CPU clock x 6 cycles - - 3+CPU clock x 4 cycles 5.5 5.5 60 - Unit times times s s s s ns s V V C year
NOTES: 1. VCC = 2.7 to 5.5 V at Topr = 0 to 60 C, unless otherwise specified. 2. Definition of programming/erasure endurance The programming and erasure endurance is defined on a per-block basis. If the programming and erasure endurance is n (n = 100 or 10,000), each block can be erased n times. For example, if 1,024 1-byte writes are performed to block A, a 1 Kbyte block, and then the block is erased, the programming/erasure endurance still stands at one. However, the same address must not be programmed more than once per erase operation (overwriting prohibited). 3. Endurance to guarantee all electrical characteristics after program and erase. (1 to Min. value can be guaranteed). 4. If emergency processing is required, a suspend request can be generated independent of this characteristic. In that case the normal time delay to suspend can be applied to the request. However, we recommend that a suspend request with an interval of less than 650 s is only used once because, if the suspend state continues, erasure cannot operate and the incidence of erasure error rises. 5. In a system that executes multiple programming operations, the actual erasure count can be reduced by writing to sequential addresses in turn so that as much of the block as possible is used up before performing an erase operation. For example, when programming groups of 16 bytes, the effective number of rewrites can be minimized by programming up to 128 groups before erasing them all in one operation. In addition, averaging the number of erase operations between block A and block B can further reduce the effective number of rewrites. It is also advisable to retain data on the erase count of each block and limit the number of erase operations to a certain number. 6. If an error occurs during block erase, attempt to execute the clear status register command, then execute the block erase command at least three times until the erase error does not occur. 7. Customers desiring programming/erasure failure rate information should contact their Renesas technical support representative. 8. The data hold time includes time that the power supply is off or the clock is not supplied.
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R8C/1A Group, R8C/1B Group
5. Electrical Characteristics
Table 5.5
Symbol - - - - - td(SR-SUS) - - - - - - -
Flash Memory (Data flash Block A, Block B) Electrical Characteristics
Parameter Program/erase endurance(2) Byte program time (Program/erase endurance 1,000 times) Byte program time (Program/erase endurance > 1,000 times) Block erase time (Program/erase endurance 1,000 times) Block erase time (Program/erase endurance > 1,000 times) Time Delay from suspend request until suspend Interval from erase start/restart until following suspend request Interval from program start/restart until following suspend request Time from suspend until program/erase restart Program, erase voltage Read voltage Program, erase temperature Data hold time(9) Ambient temperature = 55 C Conditions Standard Min. 10,000(3) - - - - - 650 0 - 2.7 2.7 -20(8) 20 Typ. - 50 65 0.2 0.3 - - - - - - - - Max. - 400 - 9 - 97+CPU clock x 6 cycles - - 3+CPU clock x 4 cycles 5.5 5.5 85 - Unit times s s s s s s ns s V V C year
NOTES: 1. VCC = 2.7 to 5.5 V at Topr = -20 to 85 C / -40 to 85 C, unless otherwise specified. 2. Definition of programming/erasure endurance The programming and erasure endurance is defined on a per-block basis. If the programming and erasure endurance is n (n = 100 or 10,000), each block can be erased n times. For example, if 1,024 1-byte writes are performed to block A, a 1 Kbyte block, and then the block is erased, the programming/erasure endurance still stands at one. However, the same address must not be programmed more than once per erase operation (overwriting prohibited). 3. Endurance to guarantee all electrical characteristics after program and erase. (1 to Min. value can be guaranteed). 4. If emergency processing is required, a suspend request can be generated independent of this characteristic. In that case the normal time delay to suspend can be applied to the request. However, we recommend that a suspend request with an interval of less than 650 s is only used once because, if the suspend state continues, erasure cannot operate and the incidence of erasure error rises. 5. In a system that executes multiple programming operations, the actual erasure count can be reduced by writing to sequential addresses in turn so that as much of the block as possible is used up before performing an erase operation. For example, when programming groups of 16 bytes, the effective number of rewrites can be minimized by programming up to 128 groups before erasing them all in one operation. It is also advisable to retain data on the erase count of each block and limit the number of erase operations to a certain number. 6. If an error occurs during block erase, attempt to execute the clear status register command, then execute the block erase command at least three times until the erase error does not occur. 7. Customers desiring programming/erasure failure rate information should contact their Renesas technical support representative. 8. -40 C for D version. 9. The data hold time includes time that the power supply is off or the clock is not supplied.
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R8C/1A Group, R8C/1B Group
5. Electrical Characteristics
Suspend request (maskable interrupt request)
FMR46
Fixed time (97 s)
Clockdependent time Access restart
td(SR-SUS)
Figure 5.2
Transition Time to Suspend
Table 5.6
Symbol Vdet1 - td(E-A) Vccmin
Voltage Detection 1 Circuit Electrical Characteristics
Parameter Voltage detection level(3) Voltage detection circuit self power consumption Waiting time until voltage detection circuit operation starts(2) MCU operating voltage minimum value VCA26 = 1, VCC = 5.0 V Condition Standard Min. 2.70 - - 2.7 Typ. 2.85 600 - - Max. 3.00 - 100 - Unit V nA s V
NOTES: 1. The measurement condition is VCC = 2.7 V to 5.5 V and Topr = -40C to 85 C. 2. Necessary time until the voltage detection circuit operates when setting to 1 again after setting the VCA26 bit in the VCA2 register to 0. 3. Ensure that Vdet2 > Vdet1.
Table 5.7
Symbol Vdet2 - - td(E-A)
Voltage Detection 2 Circuit Electrical Characteristics
Parameter Voltage detection level(4) Voltage monitor 2 interrupt request generation time(2) Voltage detection circuit self power consumption Waiting time until voltage detection circuit operation starts(3) VCA27 = 1, VCC = 5.0 V Condition Standard Min. 3.00 - - - Typ. 3.30 40 600 - Max. 3.60 - - 100 Unit V s nA s
NOTES: 1. The measurement condition is VCC = 2.7 V to 5.5 V and Topr = -40C to 85 C. 2. Time until the voltage monitor 2 interrupt request is generated after the voltage passes Vdet2. 3. Necessary time until the voltage detection circuit operates when setting to 1 again after setting the VCA27 bit in the VCA2 register to 0. 4. Ensure that Vdet2 > Vdet1.
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R8C/1A Group, R8C/1B Group
5. Electrical Characteristics
Table 5.8
Symbol Vpor2
Reset Circuit Electrical Characteristics (When Using Voltage Monitor 1 Reset)
Parameter Power-on reset valid voltage Condition Min. -20C Topr 85C -20C Topr 85C, tw(por2) 0s(3) - - Standard Typ. - - Max. Vdet1 100 V ms Unit
tw(Vpor2-Vdet1) Supply voltage rising time when power-on reset is deasserted(1)
NOTES: 1. This condition is not applicable when using with Vcc 1.0 V. 2. When turning power on after the time to hold the external power below effective voltage (Vpor1) exceeds10 s, refer to Table 5.9 Reset Circuit Electrical Characteristics (When Not Using Voltage Monitor 1 Reset). 3. tw(por2) is the time to hold the external power below effective voltage (Vpor2).
Table 5.9
Symbol Vpor1 tw(Vpor1-Vdet1) tw(Vpor1-Vdet1) tw(Vpor1-Vdet1) tw(Vpor1-Vdet1)
Reset Circuit Electrical Characteristics (When Not Using Voltage Monitor 1 Reset)
Parameter Power-on reset valid voltage Supply voltage rising time when power-on reset is deasserted Supply voltage rising time when power-on reset is deasserted Supply voltage rising time when power-on reset is deasserted Supply voltage rising time when power-on reset is deasserted Condition Min. -20C Topr 85C 0C Topr 85C, tw(por1) 10 s(2) -20C Topr < 0C, tw(por1) 30 s(2) -20C Topr < 0C, tw(por1) 10 s(2) 0C Topr 85C, tw(por1) 1 s(2) - - - - - Standard Typ. - - - - - Max. 0.1 100 100 1 0.5 V ms ms ms ms Unit
NOTES: 1. When not using voltage monitor 1, use with Vcc 2.7 V. 2. tw(por1) is the time to hold the external power below effective voltage (Vpor1).
Vdet1(3)
Vccmin Vpor2
Vdet1(3)
Vpor1 tw(por1) tw(Vpor1-Vdet1) Sampling time(1, 2)
tw(por2) tw(Vpor2-Vdet1)
Internal reset signal ("L" valid) 1 x 32 fRING-S
1 x 32 fRING-S
NOTES: 1. Hold the voltage inside the MCU operation voltage range (Vccmin or above) within the sampling time. 2. The sampling clock can be selected. Refer to 7. Voltage Detection Circuit for details. 3. Vdet1 indicates the voltage detection level of the voltage detection 1 circuit. Refer to 7. Voltage Detection Circuit for details.
Figure 5.3
Reset Circuit Electrical Characteristics
Rev.1.40 Dec 08, 2006 REJ03B0144-0140
Page 29 of 45
R8C/1A Group, R8C/1B Group
5. Electrical Characteristics
Table 5.10
Symbol - -
High-Speed On-Chip Oscillator Circuit Electrical Characteristics
Parameter High-speed on-chip oscillator frequency when the reset is deasserted High-speed on-chip oscillator frequency temperature * supply voltage dependence(2) Condition VCC = 5.0 V, Topr = 25 C 0 to +60 C/5 V 5 %(3) -20 to +85 C/2.7 to 5.5 V(3) -40 to +85 C/2.7 to 5.5 V(3) Standard Min. - 7.76 7.68 7.44 Typ. 8 - - - Max. - 8.24 8.32 8.32 Unit MHz MHz MHz MHz
NOTES: 1. The measurement condition is VCC = 5.0 V and Topr = 25 C. 2. Refer to 10.6.4 High-Speed On-Chip Oscillator Clock for notes on high-speed on-chip oscillator clock. 3. The standard value shows when the HRA1 register is assumed as the value in shipping and the HRA2 register value is set to 00h.
Table 5.11
Symbol td(P-R) td(R-S)
Power Supply Circuit Timing Characteristics
Parameter Time for internal power supply stabilization during power-on(2) STOP exit time(3) Condition Standard Min. 1 - Typ. - - Max. 2000 150 Unit s s
NOTES: 1. The measurement condition is VCC = 2.7 to 5.5 V and Topr = 25 C. 2. Waiting time until the internal power supply generation circuit stabilizes during power-on. 3. Time until CPU clock supply starts after the interrupt is acknowledged to exit stop mode.
Rev.1.40 Dec 08, 2006 REJ03B0144-0140
Page 30 of 45
R8C/1A Group, R8C/1B Group
5. Electrical Characteristics
Table 5.12
Symbol tSUCYC tHI tLO tRISE tFALL tSU tH tLEAD tLAG tOD tSA tOR
Timing Requirements of Clock Synchronous Serial I/O with Chip Select(1)
Parameter SSCK clock cycle time SSCK clock "H" width SSCK clock "L" width SSCK clock rising time SSCK clock falling time SSO, SSI data input setup time SSO, SSI data input hold time SCS setup time SCS hold time SSO, SSI data output delay time SSI slave access time SSI slave out open time Slave Slave Master Slave Master Slave Conditions Standard Min. 4 0.4 0.4 - - - - 100 1 1tCYC+50 1tCYC+50 - - - Typ. - - - - - - - - - - - - - - Max. - 0.6 0.6 1 1 1 1 - - - - 1 1.5tCYC+100 1.5tCYC+100 Unit tCYC(2) tSUCYC tSUCYC tCYC(2) s tCYC(2) s ns tCYC(2) ns ns tCYC(2) ns ns
NOTES: 1. VCC = 2.7 to 5.5V, VSS = 0V at Ta = -20 to 85 C / -40 to 85 C, unless otherwise specified. 2. 1tCYC = 1/f1(s)
Rev.1.40 Dec 08, 2006 REJ03B0144-0140
Page 31 of 45
R8C/1A Group, R8C/1B Group
5. Electrical Characteristics
4-Wire Bus Communication Mode, Master, CPHS = 1
VIH or VOH
SCS (output)
VIH or VOH
tHI
tFALL
tRISE
SSCK (output) (CPOS = 1)
tLO
tHI
SSCK (output) (CPOS = 0)
tLO
tSUCYC
SSO (output)
tOD
SSI (input)
tSU
tH
4-Wire Bus Communication Mode, Master, CPHS = 0
VIH or VOH
SCS (output)
VIH or VOH
tHI
tFALL
tRISE
SSCK (output) (CPOS = 1)
tLO
tHI
SSCK (output) (CPOS = 0)
tLO
tSUCYC
SSO (output)
tOD
SSI (input)
tSU
tH
CPHS, CPOS: Bits in SSMR register
Figure 5.4
I/O Timing of Clock Synchronous Serial I/O with Chip Select (Master)
Rev.1.40 Dec 08, 2006 REJ03B0144-0140
Page 32 of 45
R8C/1A Group, R8C/1B Group
5. Electrical Characteristics
4-Wire Bus Communication Mode, Slave, CPHS = 1
VIH or VOH
SCS (input)
VIH or VOH
tLEAD
tHI
tFALL
tRISE
tLAG
SSCK (input) (CPOS = 1)
tLO
tHI
SSCK (input) (CPOS = 0)
tLO
tSUCYC
SSO (input)
tSU
tH
SSI (output)
tSA
tOD
tOR
4-Wire Bus Communication Mode, Slave, CPHS = 0 SCS (input)
VIH or VOH
VIH or VOH
tLEAD
tHI
tFALL
tRISE
tLAG
SSCK (input) (CPOS = 1)
tLO
tHI
SSCK (input) (CPOS = 0)
tLO
tSUCYC
SSO (input)
tSU
tH
SSI (output)
tSA
tOD
tOR
CPHS, CPOS: Bits in SSMR register
Figure 5.5
I/O Timing of Clock Synchronous Serial I/O with Chip Select (Slave)
Rev.1.40 Dec 08, 2006 REJ03B0144-0140
Page 33 of 45
R8C/1A Group, R8C/1B Group
5. Electrical Characteristics
tHI
VIH or VOH
SSCK
VIH or VOH
tLO
tSUCYC
SSO (output)
tOD
SSI (input)
tSU
tH
Figure 5.6
I/O Timing of Clock Synchronous Serial I/O with Chip Select (Clock Synchronous Communication Mode)
Rev.1.40 Dec 08, 2006 REJ03B0144-0140
Page 34 of 45
R8C/1A Group, R8C/1B Group
5. Electrical Characteristics
Table 5.13
Symbol tSCL tSCLH tSCLL tsf tSP tBUF tSTAH tSTAS tSTOS tSDAS tSDAH
Timing Requirements of I2C bus Interface (1)
Parameter SCL input cycle time SCL input "H" width SCL input "L" width SCL, SDA input fall time SCL, SDA input spike pulse rejection time SDA input bus-free time Start condition input hold time Retransmit start condition input setup time Stop condition input setup time Data input setup time Data input hold time Condition Standard Typ. (2) - 12tCYC+600 Min. 3tCYC+300(2) 5tCYC+300(2) - - 5tCYC(2) 3tCYC(2) 3tCYC(2) 3tCYC(2) 1tCYC+20(2) 0
- - - - - - - - - -
Max. -
- -
Unit ns ns ns ns ns ns ns ns ns ns ns
300 1tCYC(2) -
- - - - -
NOTES: 1. VCC = 2.7 to 5.5 V, VSS = 0 V and Ta = -20 to 85 C / -40 to 85 C, unless otherwise specified. 2. 1tCYC = 1/f1(s)
VIH
SDA
VIL
tBUF
tSTAH
tSCLH
tSTAS
tSP
tSTOS
SCL
P(2) S(1)
tsf
tSCLL
Sr(3)
tSDAS
tSCL
tSDAH
P(2)
NOTES: 1. Start condition 2. Stop condition 3. Retransmit start condition
Figure 5.7
I/O Timing of I2C bus Interface
Rev.1.40 Dec 08, 2006 REJ03B0144-0140
Page 35 of 45
R8C/1A Group, R8C/1B Group
5. Electrical Characteristics
Table 5.14
Symbol VOH
Electrical Characteristics (1) [VCC = 5 V]
Parameter Condition IOH = -5 mA IOH = -200 A Drive capacity HIGH Drive capacity LOW IOL = 5 mA IOL = 200 A Drive capacity HIGH Drive capacity LOW Drive capacity LOW Drive capacity HIGH Drive capacity LOW Standard Min. Typ. VCC - 2.0 - VCC - 0.3 - VCC - 2.0 - VCC - 2.0
- - - - - - - - - - -
Output "H" voltage
Except XOUT XOUT
IOH = -1 mA IOH = -500 A
Max. VCC VCC VCC VCC 2.0 0.45 2.0 2.0 0.45 2.0 2.0 1.0
Unit V V V V V V V V V V V V
VOL
Output "L" voltage
Except P1_0 to P1_3, XOUT P1_0 to P1_3
IOL = 15 mA IOL = 5 mA IOL = 200 A IOL = 1 mA IOL = 500 A
- - - - -
XOUT
VT+-VT-
Hysteresis
INT0, INT1, INT3, KI0, KI1, KI2, KI3, CNTR0, CNTR1, TCIN, RXD0 RESET VI = 5 V VI = 0 V VI = 0 V
0.2
0.2
- -
- - -
2.2 5.0 -5.0 167 - 250 -
V
A A k M kHz V
IIH IIL RPULLUP RfXIN fRING-S VRAM
Input "H" current Input "L" current Pull-up resistance Feedback resistance XIN Low-speed on-chip oscillator frequency RAM hold voltage
During stop mode
30 - 40 2.0
50 1.0 125 -
NOTE: 1. VCC = 4.2 to 5.5 V at Topr = -20 to 85 C / -40 to 85 C, f(XIN) = 20 MHz, unless otherwise specified.
Rev.1.40 Dec 08, 2006 REJ03B0144-0140
Page 36 of 45
R8C/1A Group, R8C/1B Group
5. Electrical Characteristics
Table 5.15
Symbol ICC
Electrical Characteristics (2) [Vcc = 5 V] (Topr = -40 to 85 C, unless otherwise specified.)
Parameter Condition XIN = 20 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz No division XIN = 16 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz No division XIN = 10 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz No division XIN = 20 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz Divide-by-8 XIN = 16 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz Divide-by-8 XIN = 10 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz Divide-by-8 Main clock off High-speed on-chip oscillator on = 8 MHz Low-speed on-chip oscillator on = 125 kHz No division Main clock off High-speed on-chip oscillator on = 8 MHz Low-speed on-chip oscillator on = 125 kHz Divide-by-8 Main clock off High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz Divide-by-8 FMR47 = 1 Main clock off High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz While a WAIT instruction is executed Peripheral clock operation VCA27 = VCA26 = 0 Main clock off High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz While a WAIT instruction is executed Peripheral clock off VCA27 = VCA26 = 0 Main clock off, Topr = 25 C High-speed on-chip oscillator off Low-speed on-chip oscillator off CM10 = 1 Peripheral clock off VCA27 = VCA26 = 0 Min. - Standard Typ. 9 Max. 15 Unit mA
Power supply current High-speed (VCC = 3.3 to 5.5 V) mode Single-chip mode, output pins are open, other pins are VSS, A/D converter is stopped
-
8
14
mA
-
5
-
mA
Mediumspeed mode
-
4
-
mA
-
3
-
mA
-
2
-
mA
High-speed on-chip oscillator mode
-
4
8
mA
-
1.5
-
mA
Low-speed on-chip oscillator mode Wait mode
-
110
300
A
-
40
80
A
Wait mode
-
38
76
A
Stop mode
-
0.8
3.0
A
Rev.1.40 Dec 08, 2006 REJ03B0144-0140
Page 37 of 45
R8C/1A Group, R8C/1B Group Timing Requirements (Unless otherwise specified: VCC = 5 V, VSS = 0 V at Ta = 25 C) [ VCC = 5 V ] Table 5.16
Symbol tc(XIN) tWH(XIN) tWL(XIN) XIN input cycle time XIN input "H" width XIN input "L" width
5. Electrical Characteristics
XIN Input
Parameter Standard Min. Max. 50 - 25 - 25 - Unit ns ns ns
tc(XIN) tWH(XIN) XIN input tWL(XIN)
VCC = 5 V
Figure 5.8 Table 5.17
Symbol tc(CNTR0) tWH(CNTR0) tWL(CNTR0)
XIN Input Timing Diagram when VCC = 5 V CNTR0 Input, CNTR1 Input, INT1 Input
Parameter CNTR0 input cycle time CNTR0 input "H" width CNTR0 input "L" width Standard Min. Max. 100 - 40 - 40 - Unit ns ns ns
tc(CNTR0) tWH(CNTR0) CNTR0 input tWL(CNTR0)
VCC = 5 V
Figure 5.9 Table 5.18
Symbol tc(TCIN) tWH(TCIN) tWL(TCIN)
CNTR0 Input, CNTR1 Input, INT1 Input Timing Diagram when VCC = 5 V TCIN Input, INT3 Input
Parameter TCIN input cycle time TCIN input "H" width TCIN input "L" width Standard Min. Max. - 400(1) 200(2) 200(2)
- -
Unit ns ns ns
NOTES: 1. When using timer C input capture mode, adjust the cycle time to (1/timer C count source frequency x 3) or above. 2. When using timer C input capture mode, adjust the pulse width to (1/timer C count source frequency x 1.5) or above.
tc(TCIN) tWH(TCIN) TCIN input tWL(TCIN)
VCC = 5 V
Figure 5.10
TCIN Input, INT3 Input Timing Diagram when VCC = 5 V Page 38 of 45
Rev.1.40 Dec 08, 2006 REJ03B0144-0140
R8C/1A Group, R8C/1B Group
5. Electrical Characteristics
Table 5.19
Symbol tc(CK) tW(CKH) tW(CKL) td(C-Q) th(C-Q) tsu(D-C) th(C-D) i = 0 or 1
Serial Interface
Parameter CLKi input cycle time CLKi input "H" width CLKi input "L" width TXDi output delay time TXDi hold time RXDi input setup time RXDi input hold time Standard Min. Max. 200 - 100 - 100 - - 50 0 - 50 - 90 - Unit ns ns ns ns ns ns ns
VCC = 5 V
tc(CK) tW(CKH) CLKi tW(CKL) th(C-Q) TXDi td(C-Q) RXDi tsu(D-C) th(C-D)
i = 0 or 1
Figure 5.11
Serial Interface Timing Diagram when VCC = 5 V
Table 5.20
Symbol tW(INH) tW(INL)
External Interrupt INT0 Input
Parameter INT0 input "H" width INT0 input "L" width Standard Min. Max. - 250(1) 250(2)
-
Unit ns ns
NOTES: 1. When selecting the digital filter by the INT0 input filter select bit, use an INT0 input HIGH width of either (1/digital filter clock frequency x 3) or the minimum value of standard, whichever is greater. 2. When selecting the digital filter by the INT0 input filter select bit, use an INT0 input LOW width of either (1/digital filter clock frequency x 3) or the minimum value of standard, whichever is greater.
VCC = 5 V
tW(INL) INT0 input tW(INH)
Figure 5.12
External Interrupt INT0 Input Timing Diagram when VCC = 5 V
Rev.1.40 Dec 08, 2006 REJ03B0144-0140
Page 39 of 45
R8C/1A Group, R8C/1B Group
5. Electrical Characteristics
Table 5.21
Symbol VOH
Electrical Characteristics (3) [VCC = 3V]
Parameter Condition IOH = -1 mA Drive capacity HIGH Drive capacity LOW IOL = 1 mA Drive capacity HIGH Drive capacity LOW Drive capacity HIGH Drive capacity LOW Standard Min. Typ. VCC - 0.5 - VCC - 0.5 - VCC - 0.5
- - - - - - - -
Output "H" voltage
Except XOUT XOUT
IOH = -0.1 mA IOH = -50 A
Max. VCC VCC VCC 0.5 0.5 0.5 0.5 0.5 0.8
Unit V V V V V V V V V
VOL
Output "L" voltage
Except P1_0 to P1_3, XOUT P1_0 to P1_3
IOL = 2 mA IOL = 1 mA IOL = 0.1 mA IOL = 50 A
- - - -
XOUT
VT+-VT-
Hysteresis
INT0, INT1, INT3, KI0, KI1, KI2, KI3, CNTR0, CNTR1, TCIN, RXD0 VI = 3 V VI = 0 V VI = 0 V
0.2
IIH IIL RPULLUP RfXIN fRING-S VRAM
RESET Input "H" current Input "L" current Pull-up resistance Feedback resistance XIN Low-speed on-chip oscillator frequency RAM hold voltage
0.2
- - 66 - 40 2.0
- - - 160 3.0 125 -
1.8 4.0 -4.0 500 - 250 -
V
A A k M kHz V
During stop mode
NOTE: 1. VCC = 2.7 to 3.3 V at Topr = -20 to 85 C / -40 to 85 C, f(XIN) = 10 MHz, unless otherwise specified.
Rev.1.40 Dec 08, 2006 REJ03B0144-0140
Page 40 of 45
R8C/1A Group, R8C/1B Group
5. Electrical Characteristics
Table 5.22
Symbol ICC
Electrical Characteristics (4) [Vcc = 3 V] (Topr = -40 to 85 C, unless otherwise specified.)
Parameter Condition XIN = 20 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz No division XIN = 16 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz No division XIN = 10 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz No division XIN = 20 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz Divide-by-8 XIN = 16 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz Divide-by-8 XIN = 10 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz Divide-by-8 Main clock off High-speed on-chip oscillator on = 8 MHz Low-speed on-chip oscillator on = 125 kHz No division Main clock off High-speed on-chip oscillator on = 8 MHz Low-speed on-chip oscillator on = 125 kHz Divide-by-8 Main clock off High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz Divide-by-8 FMR47 = 1 Main clock off High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz While a WAIT instruction is executed Peripheral clock operation VCA27 = VCA26 = 0 Main clock off High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz While a WAIT instruction is executed Peripheral clock off VCA27 = VCA26 = 0 Main clock off, Topr = 25 C High-speed on-chip oscillator off Low-speed on-chip oscillator off CM10 = 1 Peripheral clock off VCA27 = VCA26 = 0 Min. - Standard Typ. 8 Max. 13 Unit mA
Power supply current High-speed (VCC = 2.7 to 3.3 V) mode Single-chip mode, output pins are open, other pins are VSS, A/D converter is stopped
-
7
12
mA
-
5
-
mA
Mediumspeed mode
-
3
-
mA
-
2.5
-
mA
-
1.6
-
mA
High-speed on-chip oscillator mode
-
3.5
7.5
mA
-
1.5
-
mA
Low-speed on-chip oscillator mode Wait mode
-
100
280
A
-
37
74
A
Wait mode
-
35
70
A
Stop mode
-
0.7
3.0
A
Rev.1.40 Dec 08, 2006 REJ03B0144-0140
Page 41 of 45
R8C/1A Group, R8C/1B Group
5. Electrical Characteristics
Timing requirements (Unless Otherwise Specified: VCC = 3 V, VSS = 0 V at Ta = 25 C) [VCC = 3 V] Table 5.23
Symbol tc(XIN) tWH(XIN) tWL(XIN) XIN input cycle time XIN input "H" width XIN input "L" width
XIN Input
Parameter Standard Min. Max. 100 - 40 - 40 - Unit ns ns ns
tc(XIN) tWH(XIN) XIN input tWL(XIN)
VCC = 3 V
Figure 5.13 Table 5.24
Symbol tc(CNTR0) tWH(CNTR0) tWL(CNTR0)
XIN Input Timing Diagram when VCC = 3 V CNTR0 Input, CNTR1 Input, INT1 Input
Parameter CNTR0 input cycle time CNTR0 input "H" width CNTR0 input "L" width Standard Min. Max. 300 - 120 - 120 - Unit ns ns ns
tc(CNTR0) tWH(CNTR0) CNTR0 input tWL(CNTR0)
VCC = 3 V
Figure 5.14 Table 5.25
Symbol tc(TCIN) tWH(TCIN) tWL(TCIN)
CNTR0 Input, CNTR1 Input, INT1 Input Timing Diagram when VCC = 3 V TCIN Input, INT3 Input
Parameter TCIN input cycle time TCIN input "H" width TCIN input "L" width Standard Min. Max. - 1,200(1) 600(2) 600(2)
- -
Unit ns ns ns
NOTES: 1. When using the timer C input capture mode, adjust the cycle time to (1/timer C count source frequency x 3) or above. 2. When using the timer C input capture mode, adjust the width to (1/timer C count source frequency x 1.5) or above.
tc(TCIN) tWH(TCIN) TCIN input tWL(TCIN)
VCC = 3 V
Figure 5.15
TCIN Input, INT3 Input Timing Diagram when VCC = 3 V
Rev.1.40 Dec 08, 2006 REJ03B0144-0140
Page 42 of 45
R8C/1A Group, R8C/1B Group
5. Electrical Characteristics
Table 5.26
Symbol tc(CK) tW(CKH) tW(CKL) td(C-Q) th(C-Q) tsu(D-C) th(C-D) i = 0 or 1
Serial Interface
Parameter CLKi input cycle time CLKi input "H" width CLKi input "L" width TXDi output delay time TXDi hold time RXDi input setup time RXDi input hold time Standard Min. Max. 300 - 150 - 150 - - 80 0 - 70 - 90 - Unit ns ns ns ns ns ns ns
tc(CK) tW(CKH)
VCC = 3 V
CLKi
tW(CKL) th(C-Q)
TXDi td(C-Q) RXDi tsu(D-C) th(C-D)
i = 0 or 1
Figure 5.16 Table 5.27
Symbol tW(INH) tW(INL)
Serial Interface Timing Diagram when VCC = 3 V External Interrupt INT0 Input
Parameter INT0 input "H" width INT0 input "L" width Standard Min. Max. - 380(1) 380(2)
-
Unit ns ns
NOTES: 1. When selecting the digital filter by the INT0 input filter select bit, use an INT0 input HIGH width of either (1/digital filter clock frequency x 3) or the minimum value of standard, whichever is greater 2. When selecting the digital filter by the INT0 input filter select bit, use an INT0 input LOW width of either (1/digital filter clock frequency x 3) or the minimum value of standard, whichever is greater
VCC = 3 V
tW(INL) INT0 input tW(INH)
Figure 5.17
External Interrupt INT0 Input Timing Diagram when VCC = 3 V
Rev.1.40 Dec 08, 2006 REJ03B0144-0140
Page 43 of 45
R8C/1A Group, R8C/1B Group
Package Dimensions
Package Dimensions
Diagrams showing the latest package dimensions and mounting information are available in the "Packages" section of the Renesas Technology website.
JEITA Package Code P-LSSOP20-4.4x6.5-0.65 RENESAS Code PLSP0020JB-A Previous Code 20P2F-A MASS[Typ.] 0.1g
20
11
HE
*1
E
F
NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET.
1
Index mark
10
c
A2
A1
*2
D
Reference Dimension in Millimeters Symbol
e y
*3
bp Detail F
D E A2 A A1 bp c HE e y L
Nom Max 6.5 6.6 4.4 4.5 1.15 1.45 0.1 0.2 0 0.17 0.22 0.32 0.13 0.15 0.2 0 10 6.2 6.4 6.6 0.53 0.65 0.77 0.10 0.3 0.5 0.7
JEITA Package Code P-SDIP20-6.3x19-1.78
A
RENESAS Code PRDP0020BA-A
Previous Code 20P4B
MASS[Typ.] 1.0g
20
11
L
Min 6.4 4.3
1
10
*1
c
e1
E
*2
D
NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET.
A
A2
Reference Symbol
Dimension in Millimeters
e
*3 b 3 SEATING PLANE
bp
e1 D E A A1 A2 bp b3 c e L
Min Nom Max 7.32 7.62 7.92 18.8 19.0 19.2 6.15 6.3 6.45 4.5 0.51 3.3 0.38 0.48 0.58 0.9 1.0 1.3 0.22 0.27 0.34 15 0 1.528 1.778 2.028 3.0
Rev.1.40 Dec 08, 2006 REJ03B0144-0140
L
Page 44 of 45
A1
R8C/1A Group, R8C/1B Group
Package Dimensions
JEITA Package Code P-HWQFN28-5x5-0.50
RENESAS Code PWQN0028KA-B
Previous Code 28PJW-B
MASS[Typ.] 0.05g
*1
D 15 15 21
21
22
14
14
22 D2
*2
E
E1
28
8
Lp
8
28
1
7
7 bp
e
1
NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH.
x
Reference Symbol
Dimension in Millimeters
y
F
Detail F
D E A2 A A1 bp e Lp x y D2 E1
Min Nom Max 4.9 5.0 5.1 4.9 5.0 5.1 0.75 0.8 0 0 0.05 0.15 0.2 0.25 0.5 0.5 0.6 0.7 0.05 0.05 2.0 2.0
A2
Rev.1.40 Dec 08, 2006 REJ03B0144-0140
Page 45 of 45
A1
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REVISION HISTORY REVISION HISTORY
Rev. 0.10 0.20 Date Feb 18, 2005 Jun 01, 2005
R8C/1A Group, R8C/1B Group Datasheet R8C/1A Group, R8C/1B Group Datasheet
Description
Page
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Summary First Edition issued Tables 1.1, 1.2: Item name changed Table 1.5: Timer C's Pin name revised, Reference Voltage Input Description revised Table 4.1 the value after reset revised; 0009h address "XXXXXX00b" "00h", 000Ah address "00XXX000b" "00h", 001Eh address "XXXXX000b" "00h". Table 4.2 004Fh address; "SSU/IIC Interrupt Control Register, SSUAIC/ IIC2AIC, XXXXX000b" added Table 4.3 the value after reset revised; 00BCh address "00h" "00h / 0000X000b"
2, 3 9
0.30
Jul 04, 2005
16
17 18
20 to 39 5. Electrical Characteristics added 1.00 Sep 01, 2005 all pages "Under development" deleted 3 Table 1.2 Performance Outline of the R8C/1B Group; Flash Memory: (Data area) (Data flash) (Program area) (Program ROM) revised Figure 1.1 Block Diagram; "Peripheral Function" added, "System Clock Generation" "System Clock Generator" revised Table 1.3 Product Information of R8C/1A Group; "(D)" and "(D): Under development" deleted Table 1.4 Product Information of R8C/1B Group; "(D)" and "(D): Under development" deleted ROM capacity: (Program area) (Program ROM), (Data area) (Data flash) revised Table 1.5 Pin Description; Power Supply Input: "VCC/AVCC" "VCC", "VSS/AVSS" "VSS" revised Analog Power Supply Input: added Figure 2.1 CPU Register; "Reserved Area" "Reserved Bit" revised 2.8.10 Reserved Area; "Reserved Area" "Reserved Bit" revised 3.2 R8C/1B Group, Figure 3.2 Memory Map of R8C/1B Group; "Data area" "Data flash", "Program area" "Program ROM" revised
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9
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A-1
REVISION HISTORY
R8C/1A Group, R8C/1B Group Datasheet
Description
Rev. 1.00
Date Sep 01, 2005
Page 18
Summary Table 4.3 SFR Information(3); 0085h: "Prescaler Z" "Prescaler Z Register" 0086h: "Timer Z Secondary" "Timer Z Secondary Register" 0087h: "Timer Z Primary" "Timer Z Primary Register" 008Ch: "Prescaler X" "Prescaler X Register" 008Dh: "Timer X" "Timer X Register" 0090h, 0091h: "Timer C" "Timer C Register" revised Table 5.3 A/D Converter Characteristics; Vref and VIA: Standard value, NOTE4 revised Table 5.4 Flash Memory (Program ROM) Electrical Characteristics; NOTES3 and 5 revised, NOTE8 deleted
Table 5.5 Flash Memory (Data flash Block A, Block B) Electrical Characteristics; NOTES1 and 3 revised
21 22 23 25 26
Table 5.8 Reset Circuit Electrical Characteristics (When Using Voltage Monitor 1 Reset); NOTE2 revised Table 5.10 High-speed On-Chip Oscillator Circuit Electrical Characteristics; "High-Speed On-Chip Oscillator ..." "High-Speed On-Chip Oscillator Frequency ..." revised, NOTE2 added Table 5.15 Electrical Characteristics (2) [Vcc = 5V]; NOTE1 deleted Table 5.22 Electrical Characteristics (4) [Vcc = 3V]; NOTE1 deleted Products of PWQN0028KA-B package included Table 1.3, Table 1.4 revised Table 5.4 Flash Memory (Program ROM) Electrical Characteristics; NOTE 8 added, Topr Ambient temperature Table 5.5 Flash Memory (Data flash Block A, Block B) Electrical Characteristics; NOTE 9 added, Topr Ambient temperature Table 5.10 High-speed On-Chip Oscillator Circuit Electrical Characteristics; NOTE 3 added Table 5.12; tSA and tOR revised, NOTE: 1. VCC = 2.2 to 2.7 to Table 5.13; NOTE: 1. VCC = 2.2 to 2.7 to Table 5.15, Table 5.22; The title revised, Condition of Stop Mode added Table 5.19, Table 5.26; td(C-Q) and tsu(D-C) revised Package Dimensions revised Table 1.3, Table 1.4; Type No. added, deleted Figure 3.1, Figure 3.2; Part Number added, deleted Table 5.4, Table 5.5; Conditions: VCC = 5.0 V at Topr = 25 C deleted,
33 37 1.10 Dec 16, 2005
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5, 6 24 25 28 29 33 35, 39 37, 41 42, 43 1.20 Mar 31, 2006 5, 6 16, 17 24, 25 1.30 Oct 03, 2006
all pages Y version added Factory programming product added
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REVISION HISTORY
R8C/1A Group, R8C/1B Group Datasheet
Description
Rev. 1.30
Date Oct 03, 2006
Page 1 2, 3 24 45
Summary 1.1 "portable equipment" added Table 1.1, Table 1.2; Specification Interrupts: "Internal: 9 sources" "Internal: 11 sources" Table 5.2; Parameter: System clock added Package Dimensions; PWQN0028KA-B revised Table 4.1; 000Fh: After reset "000XXXXXb" "00X11111b" Table 19.2; Parameter: OCD2 = 1 On-chip oscillator clock selected revised
1.40
Dec 08, 2006
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Sales Strategic Planning Div.
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When exporting the products or technology described herein, you should follow the applicable export control laws and regulations, and procedures required by such laws and regulations. 4. All information included in this document such as product data, diagrams, charts, programs, algorithms, and application circuit examples, is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas products listed in this document, please confirm the latest product information with a Renesas sales office. Also, please pay regular and careful attention to additional and different information to be disclosed by Renesas such as that disclosed through our website. (http://www.renesas.com ) 5. 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Renesas shall have no liability for malfunctions or damages arising out of the use of Renesas products beyond such specified ranges. 10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other applicable measures. Among others, since the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. 11. 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