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MC-ACT-6809
February 25, 2003
Software Compatible 6809 CPU
Datasheet v1.2
MemecCore Product Line 3721 Valley Centre Drive San Diego, CA 92130 USA Americas: +1 800-752-3040 Europe: +41 (0) 32 374 32 00 Asia: +(852) 2410 2720 E-mail: actel.info@memecdesign.com URL: www.memecdesign.com/actel
TM
Product Summary
Intended Use * * * Replacing existing 6809 designs System integration of 6809 designs Designs with complex 8bit processors
Key Features * * * * 6809 Software Compatible Illegal Opcode Recognition On-chip Bus Concept Fully Synchronous
Targeted Devices * * * Axcelerator Family ProASIC
PLUS
Family
SX-A/SX, RTSX Family
General Description
The MC-ACT-6809 is a software compatible 6809 microprocessor implemented in VHDL using a structured and synchronous design methodology. This flexible 8-bit microprocessor can be used for low to mid range applications and is easily integrated into recent Actel FPGA technologies. The 6809 is designed that application specific performance enhancements (e.g., high-speed multiplier) can be integrated, too. Memec Design built a simulation and a hardware verification environment. The simulation environment is VHDL based and simulates the synthesizable VHDL code of the 6809. This functional VHDL testbench reading instruction code from a file can be used for performance check, software verification or to get used to the functionality. A demonstration board is available which shows the functionality of the 6809 in a hardware testbench.
February 25, 2003
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Software Compatible 6809 CPU
Core Deliverables * * Netlist Version o Netlist compatible with the Actel Designer place and route tool RTL Version o VHDL Source Code o Test Bench All o User Guide
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*
Synthesis and Simulation Support * * * * Synthesis: Synplicity Simulation: ModelSim Other tools supported upon request
Verification Test Bench
clk reset_n
Status Information
6809
Interrupts
seq_state cc pc stack stack_operation opcode
irq_n firq_n nmi_n
bus_addr bus_rd_data
Bus Interface Unit
bus_wr_data bus_rw_n rd_trf_ebl wr_trf_ebl
bus_busy
Bus Request Unit
bus_want mem_rdy
Figure 1: Logic Symbol
February 25, 2003
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Software Compatible 6809 CPU Functional Description
Structure of 6809
Memec Design
The block diagram below shows the index arithmetic unit, the data ALU, command sequencer, memory fetch unit and program counter.
S U X Y D=A:B B A DP CC PC Address Register Write Data Register Read Data Register Data ALU Memory Fetch Unit Index ALU Command Sequencer
Figure 2: Block Diagram The memory interface contains registered read and write data and address registers, which makes the design of the interface easier for timing verification etc. Internal Registers The following part describes the existing registers in the MC-ACT-6809: Index Registers (X,Y) The index registers are used in indexed mode of addressing and are used for calculating the effective addresses. During some indexed modes, the contents of the index register are incremented or decremented to point to the next item of tabular type data. All 4 pointer register (U, S, X, Y) can be used as index register. Stack Pointer Registers (U,S) The system stack pointer S is automatically used by the processor during subroutine calls and interrupts! The user stack pointer is controlled by the programmer. Both stack pointers point to the top of the stack. Program Counter Register The program counter (PC) points to the address of the next instruction to be executed. Accumulators (A,B,D) The A and B accumulators are general purpose registers. Some instructions concatenate the registers A and B to achieve 16 bit values. This register is then referred as the D register with the A register as most significant byte.
February 25, 2003
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Software Compatible 6809 CPU
Condition Code (CC) Register Beginning with bit(0) the condition code register contains following flags: C: Carry from ALU V: Overflow (2 complement) from ALU Z: Zero from ALU N: Negative (2 complement) from ALU I: Interrupt mask register for irq_n H: Half Carry (low nibble) from ALU F: Interrupt mask for firq_n E: Entire Flag for irq_n/firq_n stack operations Direct Page (DP) Register
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These registers enhance the direct addressing mode. During direct addressing instruction execution, the contents of DP appears at the higher address outputs (A15- A8). Instructions The MC-ACT-6809 supports all 6809 instructions like load, store, and, or, add, sub, transfer/exchange instructions for all registers, 8 by 8 unsigned multiply, decimal adjust and signed/unsigned conditional branches. A powerful stack command is also available. Software interrupts are supported. Addressing Modes Nearly all instructions can be combined with the following addressing modes: Inherent: Register source and destination, no post bytes, e.g. INCA Immediate: Postbyte is parameter, e.g. LDA #100 Extended: Postbytes are address, e.g. LDA 1000 Direct: Postbyte is low address, DP is high address, e.g. LDA <50 Indexed: Postbyte(s) define indexed mode: - (Index registers are X,Y,U,S) - Post incr. by 1 and 2, e.g. LDA ,S++ - Pre decr. by 1 and 2, e.g. LDA ,-X - Zero offset, e.g. LDA 0,X - signed offset, e.g. LDA -7,Y - A/B/D signed offset, e.g. LDB A,U - 8/16bit signed offset PC relative, e.g. LDA 665,PCR Indexed indirect: The same types as indexed may be used. The indirect mode uses the argument of the index mode as address for an indirect access. Illegal Instructions To insure save operation, illegal opcodes are recognized and will lead to an exception, where a vector is fetched to enter the exception handler routine. For this purpose, the reserved vector of the 6809 is used. The address of the illegal instruction is pushed on the S stack.
February 25, 2003
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Software Compatible 6809 CPU
Interrupts For interrupting the MC-ACT-6809, there are 3 level-sensitive interrupts: irq_n: standard interrupt or interrupt request, low_active, pushes all registers on stack: PC(Low), PC(High), U(Low), U(High), Y(Low), Y(High), X(Low), X(High), DP, B, A, CC
Memec Design
firq_n: fast interrupt, pushes only PC and CC on stack: PC(Low), PC(High), CC nmi_n: non maskable interrupt, pushes all registers on stack: PC(Low), PC(High), U(Low), U(High), Y(Low), Y(High), X(Low), X(High), DP, B, A, CC The nmi_n is masked after reset until the system stack pointer is initialized. The different interrupts will fetch the corresponding vector for the interrupt in the memory: 0xfff0 Illegal Instruction 0xfff2 SWI3 0xfff4 SWI2 0xfff6 FIRQ 0xfff8 IRQ 0xfffa SWI 0xfffc NMI 0xfffe RESET The interrupt behavior of the MC-ACT-6809 matches exactly the one of the original 6809 in terms of results in registers and memory. An exception is the case where an illegal instruction is decoded by the 6809: in this case, the reserved interrupt is used.
February 25, 2003
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Software Compatible 6809 CPU Device Requirements
Family SX-A PLUS ProASIC Axcelerator Device SX32A-3 APA150-STD AX500-3 COMB 1625 (91%) n/a 1577 (30%) Utilization SEQ 344 (32%) n/a 339 (13%)
Memec Design
Performance Total 1969 (69%) 2795 (46%) 1916 (24%) 28 MHz 11 MHz 31 MHz
Table 1: Device Utilization and Performance
Verification and Compliance
Functional and timing simulation has been performed on the 6809 using VHDL and Verilog Test Benches. Simulation vectors used for verification are provided with the core. This core has also been used successfully in customer designs.
Signal Descriptions
The following signal descriptions define the IO signals. Signal Direction Description clk in system clock, rising edge used only reset_n in asynchronous system reset, active low, goes to all flip flops nmi_n in Non maskable interrupt, active low firq_n in Fast interrupt request, active low irq_n in Interrupt request, active low bus_busy in Bus busy, If `1' the uP can not access the bus and waits until bus is released. wr_trf_ebl out Write transfer enable bus_want out Bus want. The uP requests the bus. rd_trf_ebl out Read transfer enable rw_n out Read / write-not. If `1' then read cycle bus_addr[15:0] out Bus address bus_rd_data[7:0] in Read data bus_wr_data[7:0] out Write data mem_rdy out Memory ready, see `Internal Bus Interface Timing' for timing diagram seq_state[5:0] out Command sequencer state register cc[7:0] out Condition code register pc[15:0] out Program counter register stack[15:0] out Stack pointer stack_operation out Stack operation, if `1' a stack operation cycle is running opcode[5:0] out Operation code Table 2: Core I/O Signals
February 25, 2003
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Software Compatible 6809 CPU Recommended Design Experience
Memec Design
For the source version, users should be familiar with HDL entry and Actel design flows. Users should be familiar with Actel Libero v2.2 Integrated Design Environment (IDE) and preferably with Synplify and ModelSim.
Ordering Information
Part Number MC-ACT-6809-NET MC-ACT-6809-VHD Description Core Netlist Core VHDL
Table 3: Core Part Numbers The CORE is provided under license from Memec Design for use in Actel programmable logic devices. Please contact Memec Design for pricing and more information. Information furnished by Memec Design is believed to be accurate and reliable. Memec Design reserves the right to change specifications detailed in this data sheet at any time without notice, in order to improve reliability, function or design, and assumes no responsibility for any errors within this document. Memec Design does not make any commitment to update this information. Memec Design assumes no obligation to correct any errors contained herein or to advise any user of this text of any correction, if such be made, nor does the Company assume responsibility for the functioning of undescribed features or parameters. Memec Design will not assume any liability for the accuracy or correctness of any support or assistance provided to a user. Memec Design does not represent that products described herein are free from patent infringement or from any other third-party right. No license is granted by implication or otherwise under any patent or patent rights of Memec Design. MemecCore products are not intended for use in life support appliances, devices, or systems. Use of a MemecCore product in such application without the written consent of the appropriate Memec Design officer is prohibited. All trademarks, registered trademarks, or service marks are property of their respective owners.
Datasheet Revision History
Version Datasheet 1.0 Datasheet 1.1 Datasheet 1.2 Date December 19, 2002 January 23, 2003 February 25, 2003 Description First Release Modification done in section core deliverables, Added logo to footer Modification done in section device requirements, new URL and address inserted
February 25, 2003
Optimized for
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