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Features
* Operating Voltage: 3.3V * Access Time: 40 ns * Very Low Power Consumption * * * * * * * *
- Active: 160 mW (Max) - Standby: 70 W (Typ) Wide Temperature Range: -55C to +125C MFP 32 leads 400 Mils Width Package TTL Compatible Inputs and Outputs Asynchronous Designed on 0.35m Process No Single Event Latch-up below a LET threshold of 80 MeV/mg/cm2 Tested up to a Total Dose of 200 Krad (Si) according to MIL STD 883 Method 1019 Quality grades: QML Q or V with SMD 5962-02501
Description
The M65609E is a very low power CMOS static RAM organized as 131,072 x 8 bits. Utilizing an array of six transistors (6T) memory cells, the M65609E combines an extremely low standby supply current with a fast access time at 40 ns. The high stability of the 6T cell provides excellent protection against soft errors due to noise. The M65609E is processed according to the methods of the latest revision of the MIL PRF 38535 and ESCC 9000. It is produced on the same process as the MH1RT sea of gates series.
Rad Hard 128K x 8 3.3-volt Very Low Power CMOS SRAM M65609E
Rev. 4158I-AERO-07/07
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M65609E
Block Diagram
Pin Configuration
32 pins Flatpack 400 MILS
Pin Description
Name A0 - A16 I/O1 - I/O8 CS1 CS2 WE OE VCC GND Description Address Inputs Data Input/Output Chip Select 1 Chip Select 2 Write Enable Output Enable Power Ground
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Table 1. Truth Table
CS1 H X L L L Note: CS2 X L H H H WE X X H L H OE X X L X H Inputs/ Outputs Z Z Data Out Data In Z Mode Deselect/ Power-down Deselect/ Power-down Read Write Output Disable
L = low, H = high, X = H or L, Z = high impedance.
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M65609E
Electrical Characteristics
Absolute Maximum Ratings
Supply Voltage to GND Potential............................ -0.5V + 5V DC Input Voltage............................ GND - 0.3V to VCC + 0.3V DC Output Voltage High Z State .... GND - 0.3V to VCC + 0.3V Storage Temperature .................................... -65C to + 150C Output Current Into Outputs (Low) ............................... 20 mA Electro Statics Discharge Voltage................................. > 500V (MIL STD 883D Method 3015.3) *NOTE:
Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Military Operating Range
Operating Voltage 3.3V + 0.3V Operating Temperature -55C to + 125C
Recommended DC Operating Conditions
Parameter Description Supply voltage Ground Input low voltage Input high voltage Min 3 0.0 GND - 0.3 2.2 Typ 3.3 0.0 0.0 - Max 3.6 0.0 0.8 Unit V V V V
VCC
Gnd VIL VIH
VCC + 0.3
Capacitance
Parameter CIN(1) COUT(1) Note: Description Input low voltage Output high voltage Min - - Typ - - Max 8 8 Unit pF pF
1. Guaranteed but not tested.
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DC Parameters
DC Test Conditions
Parameter IIX
(1)
Description Input leakage current Output leakage current Output low voltage Output high voltage
Minimum -1 -1 2.4
Typical - - - -
Maximum 1 1 0.4 -
Unit A A V V
IOZ (1) VOL VOH 1. 2. 3.
(2) (3)
Gnd < Vin < VCC, Gnd < Vout < VCC Output Disabled. VCC min. IOL = 4 mA. VCC min. IOH = -2 mA.
Consumption
Symbol ICCSB (1) ICCSB1 (2) ICCOP (3) 1. 2. 3. Description Standby supply current Standby supply current Dynamic operating current 65609E-40 1.5 1 45 Unit mA mA mA Value max max max
CS1 > VIH or CS2 < VIL and CS1 < VIL. CS1 > VCC - 0.3V or, CS2 < Gnd + 0.3V and CS1 < 0.2V F = 1/TAVAV, IOUT = 0 mA, W = OE = VIH, Vin = Gnd or VCC, VCC max.
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M65609E
Write Cycle
Symbol tAVAW tAVWL tAVWH tDVWH tE1LWH tE2HWH tWLQZ tWLWH tWHAX tWHDX tWHQX Note: Parameter Write cycle time Address set-up time Address valid to end of write Data set-up time CS1 low to write end CS2 high to write end Write low to high Z (1) Write pulse width Address hold from to end of write Data hold time Write high to low Z (1) 65609E-40 35 0 28 18 28 28 15 28 3 0 0 Unit ns ns ns ns ns ns ns ns ns ns ns Value min min min min min min max min min min min
1. Parameters guaranteed, not tested, with 5 pF output loading (see Section "AC Test Conditions" Figure 2).
Read Cycle
Symbol tAVAV tAVQV tAVQX tE1LQV tE1LQX tE1HQZ tE2HQV tE2HQX tE2LQZ tGLQV tGLQX tGHQZ Note: Parameter Read cycle time Address access time Address valid to low Z Chip-select1 access time CS1 low to low Z (1) CS1 high to high Z (1) Chip-select2 access time CS2 high to low Z (1) CS2 low to high Z (1) Output Enable access time OE low to low Z (1) OE high to high Z (1) 65609E-40 40 40 3 40 3 15 40 3 15 12 0 10 Unit ns ns ns ns ns ns ns ns ns ns ns ns Value min max min max min max max min max max min max
1. Parameters guaranteed, not tested, with 5 pF output loading (seeSection "AC Test Conditions" Figure 2).
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AC Parameters
AC Test Conditions Input Pulse Level:......................................................... GND to 3.0V Input Rise/Fall Time: .................................................... 5 ns Input Timing Reference Level: ..................................... 1.5V Output loading IOL/IOH (see figure 1 and 2)................ +30 pF AC Test Loads Waveforms Figure 1
R1 2552 3.3V 3.3V
Figure 2
R1 2552
Figure 3
2824
2824
1340 V
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M65609E
Data Retention Mode
Atmel CMOS RAM's are designed with battery backup in mind. Data retention voltage and supply current are guaranteed over temperature. The following rules ensure data retention: 1. During data retention CS1 must be held high within VCC to VCC - 0.2V or chip select CS2 must be held down within GND to GND +0.2V. 2. Output Enable (OE) should be held high to keep the RAM outputs high impedance, minimizing power dissipation. 3. During power-up and power-down transitions CS1 and OE must be kept between VCC + 0.3V and 70% of VCC, or with BS between GND and GND -0.3V. 4. The RAM can begin operation > tR ns after VCC reaches the minimum operation voltages (3V). Figure 1. Data Retention Timing
Data Retention Characteristics
Parameter Description Min 2.0 0.0 tAVAV(1) - Typical TA = 25C - - - 0.010 Max - - - 1.0 Unit V ns ns mA
VCCDR
TCDR tR ICCDR1(2) Notes:
VCC for data
retention Chip deselect to data retention time Operation recovery time Data retention current at 2.0V
1. TAVAV = Read Cycle Time 2. CS1 = VCC or CS2 = CS1 = GND, VIN = GND/VCC.
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Write Cycle 1. WE Controlled. OE High During Write
Write Cycle 2. WE Controlled. OE Low
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M65609E
Write Cycle 3. CS1 or CS2 Controlled(1)
Note:
1. The internal write time of the memory is defined by the overlap of CS1 LOW and CS2 HIGH and W LOW. Both signals must be activated to initiate a write and either signal can terminate a write by going in activated. The data input setup and hold timing should be referenced to the actived edge of the signal that terminates the write. Data out is high impedance if OE = VIH.
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Read Cycle nb 1
Read Cycle nb 2
Read Cycle nb 3
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M65609E
Ordering Information
Part Number MMDJ-65609EV-40-E 5962-0250101QXC 5962-0250101VXC 5962R0250101VXC SMDJ-65609EV-40SCC MM0 -65609EV-40-E(1) MM0 -65609EV-40SV(1) Note: 1. Contact Atmel for availability. Temperature Range 25C -55 to +125C -55 to +125C -55 to +125 C -55 to +125C 25C -55 to +125C Speed 40 ns 40 ns 40 ns 40ns 40 ns 40 ns 40 ns Package FP32.4 FP32.4 FP32.4 FP32.4 FP32.4 Die Die Flow Engineering Samples QML Q QML V QML V RHA ESCC Engineering Samples QML V
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Package Drawing
32-pin Flat Pack (400 Mils)
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4158H-AERO-05/07 /xM

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