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ESMT
Flash
FEATURES
Single supply voltage 2.7~3.6V Speed - Read max frequency : 33MHz - Fast Read max frequency : 50MHz; 75MHz; 100MHz Low power consumption - Active current40mA - Standby current75 A Reliability - 100,000 typical program/erase cycles - 20 years Data Retention Program - Byte program time 9 s(typical) Erase - Chip erase time 4s(typical) - Block erase time 1sec (typical) - Sector erase time 90ms(typical)
F25L004A
Operation Temperature Condition -40 C ~85 C
3V Only 4 Mbit Serial Flash Memory
Auto Address Increment (AAI) WORD Programming - Decrease total chip programming time over Byte-Program operations SPI Serial Interface - SPI Compatible : Mode 0 and Mode3 End of program or erase detection Write Protect ( WP ) Hold Pin ( HOLD ) All Pb-free products are RoHS-Compliant
ORDERING INFORMATION
Part No. F25L004A -50PIG F25L004A -100PIG F25L004A -50PAIG Speed 50MHz 100MHz 50MHz Package 8 lead SOIC 8 lead SOIC 8 lead SOIC 150 mil 150 mil 200 mil COMMENTS Pb-free Pb-free Pb-free Part No. Speed Package 8 lead SOIC 8 lead PDIP 8 lead PDIP 200 mil 300 mil 300 mil COMMENTS Pb-free Pb-free Pb-free
F25L004A -100PAIG 100MHz F25L004A -50DIG F25L004A -100DIG 50MHz 100MHz
GENERAL DESCRIPTION
The F25L004A is a 4Megabit, 3V only CMOS Serial Flash memory device. ESMT's memory devices reliably store memory data even after 100,000 program and erase cycles. The F25L004A features a sector erase architecture. The device memory array is divided into 128 uniform sectors with 4K byte each ; 8 uniform blocks with 64K byte each. Sectors can be erased individually without affecting the data in other sectors. Blocks can be erased individually without affecting the data in other blocks. Whole chip erase capabilities provide the flexibility to revise the data in the device. The sector protect/unprotect feature disables both program and erase operations in any combination of the sectors of the memory.
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PIN CONFIGURATIONS 8-PIN SOIC
F25L004A
Operation Temperature Condition -40 C ~85 C
CE
1
8
VDD
SO
2 3
7 6
HOLD
SCK
WP
VSS
4
5
SI
8-PIN PDIP
CE
1
8
VDD
SO
2 3
7 6
HOLD SCK
WP
VSS
4
5
SI
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PIN Description
Symbol SCK SI Pin Name Serial Clock Serial Data Input Functions To provide the timing for serial input and output operations To transfer commands, addresses or data serially into the device. Data is latched on the rising edge of SCK. To transfer data serially out of the device. Data is shifted out on the falling edge of SCK. To activate the device when CE is low. The Write Protect ( WP ) pin is used to enable/disable BPL bit in the status register. To temporality stop serial communication with SPI flash memory without resetting the device. To provide power.
F25L004A
Operation Temperature Condition -40 C ~85 C
SO CE
WP
Serial Data Output Chip Enable Write Protect
HOLD VDD VSS
Hold Power Supply Ground
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SECTOR STRUCTURE
F25L004A
Operation Temperature Condition -40 C ~85 C
Table1 : F25L004A Sector Address Table
Block 7
Sector 127 : 112 111
Sector Size (Kbytes) 4KB : 4KB 4KB : 4KB 4KB : 4KB 4KB : 4KB 4KB : 4KB 4KB : 4KB 4KB : 4KB 4KB : 4KB
Address range 07F000H - 07FFFFH : 070000H - 070FFFH 06F000H - 06FFFFH : 060000H - 060FFFH 05F000H - 05FFFFH : 050000H - 050FFFH 04F000H - 04FFFFH : 040000H - 040FFFH 03F000H - 03FFFFH : 030000H - 030FFFH 02F000H - 02FFFFH : 020000H - 020FFFH 01F000H - 01FFFFH : 010000H - 010FFFH 00F000H - 00FFFFH : 000000H - 000FFFH
Block Address A18 A17 A16 1 1 1
6
: 96 95
1
1
0
5
: 80 79
1
0
1
4
: 64 63
1
0
0
3
: 48 47
0
1
1
2
: 32 31
0
1
0
1
: 16 15
0
0
1
0
: 0
0
0
0
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Table2 : F25L004A Block Protection Table
F25L004A
Operation Temperature Condition -40 C ~85 C
Protection Level 0 Upper 1/8 Upper 1/4 Upper 1/2 All Blocks All Blocks All Blocks All Blocks 0 0 0 0 1 1 1 1
Status Register Bit BP2 BP1 0 0 1 1 0 0 1 1 BP0 0 1 0 1 0 1 0 1
Protected Memory Area Block Range None Block 7 Block 6~7 Block 4~7 Block 0~7 Block 0~7 Block 0~7 Block 0~7 Address Range None 70000H - 7FFFFH 60000H - 7FFFFH 40000H - 7FFFFH 00000H - 7FFFFH 00000H - 7FFFFH 00000H - 7FFFFH 00000H - 7FFFFH
Block Protection (BP2, BP1, BP0) The Block-Protection (BP2, BP1, BP0) bits define the size of the memory area, as defined in Table2 to be software protected against any memory Write (Program or Erase) operations. The Write-Status-Register (WRSR) instruction is used to program the BP2, BP1, BP0 bits as long as WP is high or the Block-Protection-Look (BPL) bit is 0. Chip-Erase can only be executed if Block-Protection bits are all 0. After power-up, BP2, BP1 and BP0 are set to1.
Block Protection Lock-Down (BPL)
WP pin driven low (VIL), enables the Block-Protection -Lock-Down (BPL) bit. When BPL is set to 1, it prevents any further alteration of the BPL, BP2, BP1, and BP0 bits. When the WP pin is driven high (VIH), the BPL bit has no effect and its value is "Don't Care". After power-up, the BPL bit is reset to 0.
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FUNTIONAL BLOCK DIAGRAM
F25L004A
Operation Temperature Condition -40 C ~85 C
Address Buffers and Latches
X-Decoder
Flash
Y-Decoder
Control Logic
I/O Butters and Data Latches
Serial Interface
CE
SCK
SI
SO
WP
HOLD
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Hold Operation
HOLD pin is used to pause a serial sequence underway with the SPI flash memory without resetting the clocking sequence. To activate the HOLD mode, CE must be in active low state. The HOLD mode begins when the SCK active low state coincides with the falling edge of the HOLD signal. The HOLD mode ends when the HOLD signal's rising edge coincides with the SCK active low state. If the falling edge of the HOLD signal does not coincide with the SCK active low state, then the device enters Hold mode when the SCK next reaches the active low state. Similarly, if the rising edge of the HOLD signal does not
F25L004A
Operation Temperature Condition -40 C ~85 C
coincide with the SCK active low state, then the device exits in Hold mode when the SCK next reaches the active low state. See Figure 1 for Hold Condition waveform. Once the device enters Hold mode, SO will be in high impedance state while SI and SCK can be VIL or VIH. If CE is driven active high during a Hold condition, it resets the internal logic of the device. As long as HOLD signal is low, the memory remains in the Hold condition. To resume communication with the device, HOLD must be driven active high, and CE must be driven active low. See Figure 21 for Hold timing.
S CK
HO L D A ctive Ho ld A ctive Ho ld A ctive
Figure 1 : HOLD CONDITION WAVEFORM
Write Protection
F25L004A provides software Write protection. The Write Protect pin ( WP ) enables or disables the lockdown function of the status register. The Block-Protection bits (BP1, BP0, and BPL) in the status register provide Write protection to the memory array and the status register. See Table 2 for Block-Protection description.
TABLE3: CONDITIONS TO EXECUTE WRITE-STATUS- REGISTER (WRSR) INSTRUCTION
WP
BPL 1 0 X
Execute WRSR Instruction Not Allowed Allowed Allowed
L L
Write Protect Pin ( WP )
The Write Protect ( WP ) pin enables the lock-down function of the BPL bit (bit 7) in the status register. When WP is driven low, the execution of the Write-Status-Register (WRSR) instruction is determined by the value of the BPL bit (see Table 3). When WP is high, the lock-down function of the BPL bit is disabled.
H
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Status Register
The software status register provides status on whether the flash memory array is available for any Read or Write operation, whether the device is Write enabled, and the state of the memory Write protection. During an internal Erase or Program operation,
F25L004A
Operation Temperature Condition -40 C ~85 C
the status register may be read only to determine the completion of an operation in progress. Table 4 describes the function of each bit in the software status register.
TABLE 4: SOFTWARE STATUS REGISTER
Bit 0 1 2 3 4 5 6 7 Name BUSY WEL BP0 BP1 BP2 RESERVED AAI BPL Function 1 = Internal Write operation is in progress 0 = No internal Write operation is in progress 1 = Device is memory Write enabled 0 = Device is not memory Write enabled Indicate current level of block write protection (See Table 2) Indicate current level of block write protection (See Table 2) Indicate current level of block write protection (See Table 2) Reserved for future use Auto Address Increment Programming status 1 = AAI programming mode 0 = Byte-Program mode 1 = BP2,BP1,BP0 are read-only bits 0 = BP2,BP1,BP0 are read/writable Default at Power-up 0 0 1 1 1 0 0 0 Read/Write R R R/W R/W R/W N/A R R/W
Note1 : Only BP0,BP1,BP2 and BPL are writable Note2 : All register bits are volatility Note3 : All area are protected at power-on (BP2=BP1=BP0=1)
Busy
The Busy bit determines whether there is an internal Erase or Program operation in progress. A "1" for the Busy bit indicates the device is busy with an operation in progress. A "0" indicates the device is ready for the next valid operation.
Write Enable Latch (WEL)
The Write-Enable-Latch bit indicates the status of the internal memory Write Enable Latch. If the Write-Enable-Latch bit is set to "1", it indicates the device is Write enabled. If the bit is set to "0" (reset), it indicates the device is not Write enabled and does not accept any memory Write (Program/ Erase) commands. The Write-Enable-Latch bit is automatically reset under the following conditions: Power-up Write-Disable (WRDI) instruction completion Byte-Program instruction completion Auto Address Increment (AAI) programming reached its highest memory address * Sector-Erase instruction completion * Block-Erase instruction completion * Chip-Erase instruction completion * * * * * Write-Status-Register instructions
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Instructions
Instructions are used to Read, Write (Erase and Program), and configure the F25L004A. The instruction bus cycles are 8 bits each for commands (Op Code), data, and addresses. Prior to executing any Byte-Program, Auto Address Increment (AAI) programming, Sector-Erase, Block-Erase, or Chip-Erase instructions, the Write-Enable (WREN) instruction must be executed first. The complete list of the instructions is provided in Table 5. All instructions are synchronized off a high to low transition of CE . Inputs will be accepted on the rising edge of
F25L004A
Operation Temperature Condition -40 C ~85 C
SCK starting with the most significant bit. CE must be driven low before an instruction is entered and must be driven high after the last bit of the instruction has been shifted in (except for Read, Read-ID and Read-Status-Register instructions). Any low to high transition on CE , before receiving the last bit of an instruction bus cycle, will terminate the instruction in progress and return the device to the standby mode. Instruction commands (Op Code), addresses, and data are all input from the most significant bit (MSB) first
TABLE 5: DEVICE OPERATION INSTRUCTIONS
Cycle Type/ 1,2 Operation Read High-Speed-Read Sector-Erase4,5 (4K Byte) Block-Erase5 (64K Byte) Chip-Erase5 Byte-Program Auto-Address-Increment-word programming (AAI) 6 Read-Status-Register (RDSR) Enable-Write-Status-Register (EWSR)8 Write-Status-Register 8 (WRSR) Write-Enable (WREN) 11 Write-Disable (WRDI) Read-Electronic-Signature9 (RES) Jedec-Read-ID (JEDEC-ID) 10 Read-ID (RDID) Enable SO to output RY/BY# Status during AAI (EBSY) Disable SO to output RY/BY# Status during AAI (DBSY) 1. 2. 3. 4. 5. 6. 7. 8. 100MHz
5
Max Freq 33 MHz
1 SIN 03H 0BH 20H D8H 60H C7H 02H ADH SOUT Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z
2 SIN A23-A16 A23-A16 A23-A16 A23-A16 SOUT Hi-Z Hi-Z Hi-Z Hi-Z -
Bus Cycle 3 SIN SOUT A15-A8 Hi-Z A15-A8 Hi-Z A15-A8 Hi-Z A15-A8 Hi-Z Hi-Z Hi-Z Note7 20H Hi-Z -
4 5 6 SIN SOUT SIN SOUT SIN SOUT A7-A0 Hi-Z X DOUT A7-A0 Hi-Z X X X DOUT A7-A0 Hi-Z A7-A0 Hi-Z DIN Hi-Z A7-A0 Hi-Z
Hi-Z A23-A16 Hi-Z A15-A8 Hi-Z A23-A16 Hi-Z A15-A8 Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z X Data X X DOUT Hi-Z 12H 8CH X
A7-A0 Hi-Z DIN0 Hi-Z DIN1 Hi-Z -. X Note7 13H X Note7 8CH 12H X 12H 8CH
50MHz
05H 50H 01H 06H 04H ABH 9FH
90H (A0=0) Hi-Z A23-A16 Hi-Z A15-A8 90H (A0=1) 70H 80H Hi-Z Hi-Z -
A7-A0 Hi-Z -
Operation: SIN = Serial In, SOUT = Serial Out X = Dummy Input Cycles (VIL or VIH); - = Non-Applicable Cycles (Cycles are not necessary) One bus cycle is eight clock periods. Sector addresses: use AMS-A12, remaining addresses can be VIL or VIH Prior to any Byte-Program, Sector-Erase, Block-Erase,or Chip-Erase operation, the Write-Enable (WREN) instruction must be executed. To continue programming to the next sequential address location, enter the 8-bit command, ADH, followed by the data to be programmed. The Read-Status-Register is continuous with ongoing clock cycles until terminated by a low to high transition on CE . The Enable-Write-Status-Register (EWSR) instruction and the Write-Status-Register (WRSR) instruction must work in conjunction of each other. The WRSR instruction must be executed immediately (very next bus cycle) after the EWSR instruction to make both instructions effective. The Read-Electronic-Signature is continuous with on going clock cycles until terminated by a low to high transition on CE .
9.
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F25L004A
Operation Temperature Condition -40 C ~85 C
10. The Jedec-Read-ID is output first byte 8CH as manufacture ID; second byte 20H as top memory type; third byte 13H as memory capacity. 11. The Write-Enable (WREN) instruction and the Write-Status-Register (WRSR) instruction must work in conjunction of each other. The WRSR instruction must be executed immediately (very next bus cycle) after the WREN instruction to make both instructions effective. Both EWSR and WREN can enable WRSR, user just need to execute one of it. A successful WRSR can reset WREN.
Read (33 MHz)
The Read instruction supports up to 33 MHz, it outputs the data starting from the specified address location. The data output stream is continuous through all addresses until terminated by a low to high transition on CE . The internal address pointer will automatically increment until the highest memory address is reached. Once the highest memory address is reached, the address pointer will automatically increment to the beginning (wrap-around) of the address space, i.e. for 4Mbit density, once the data from address location 7FFFFH had been read, the next output will be from address location 00000H. The Read instruction is initiated by executing an 8-bit command, 03H, followed by address bits [A23-A0]. CE must remain active low for the duration of the Read cycle. See Figure 2 for the Read sequence.
CE MODE3 SCK MODE1 12345678 15 16 23 24 31 32 39 40 47 48 55 56 63 64 70
SI MSB
03
ADD. MSB
ADD.
ADD.
SO
HIGH IMPENANCE MSB
N DOUT
N+1 DOUT
N+2 DOUT
N+3 DOUT
N+4 DOUT
Figure 2 : READ SEQUENCE
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Fast-Read (50 MHz ; 100 MHz)
The High-Speed-Read instruction supporting up to 100 MHz is initiated by executing an 8-bit command, 0BH, followed by address bits [A23-A0] and a dummy byte. CE must remain active low for the duration of the High-Speed-Read cycle. See Figure 3 for the High-Speed-Read sequence. Following a dummy byte (8 clocks input dummy cycle), the High-Speed-Read instruction outputs the data starting from the specified address location. The data output stream is continuous
F25L004A
Operation Temperature Condition -40 C ~85 C
through all addresses until terminated by a low to high transition on CE . The internal address pointer will automatically increment until the highest memory address is reached. Once the highest memory address is reached, the address pointer will automatically increment to the beginning (wrap-around) of the address space, i.e. for 4Mbit density, once the data from address location 7FFFFH has been read, the next output will be from address location 000000H.
CE MODE3 SCK MODE0 012345678 15 16 23 24 31 32 39 40 47 48 55 56 63 64 71 72 80
SI MSB
0B
ADD. MSB HIGH IMPENANCE
ADD.
ADD.
X
N DOUT MSB
N+1 DOUT
N+2 DOUT
N+3 DOUT
N+4 DOUT
SO
Note : X = Dummy Byte : 8 Clocks Input Dummy (VIL or VIH)
Figure 3 : HIGH-SPEED-READ SEQUENCE
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Byte-Program
The Byte-Program instruction programs the bits in the selected byte to the desired data. The selected byte must be in the erased state (FFH) when initiating a Program operation. A Byte-Program instruction applied to a protected memory area will be ignored. Prior to any Write operation, the Write-Enable (WREN) instruction must be executed. CE must remain active low for the duration of the Byte-Program instruction. The Byte-Program
F25L004A
Operation Temperature Condition -40 C ~85 C
instruction is initiated by executing an 8-bit command, 02H, followed by address bits [A23-A0]. Following the address, the data is input in order from MSB (bit 7) to LSB (bit 0). CE must be driven high before the instruction is executed. The user may poll the Busy bit in the software status register or wait TBP for the completion of the internal self-timed Byte-Program operation. See Figure 4 for the Byte-Program sequence.
CE MODE3 SCK MODE0 012345678 15 16 23 24 31 32 39
SI MSB
02
ADD. MSB HIGH IMPENANCE
ADD.
ADD.
DIN MSB LSB
SO
Figure 4 : BYTE-PROGRAM SEQUENCE
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Auto Address Increment (AAI) WORD Program
F25L004A
Operation Temperature Condition -40 C ~85 C
The AAI program instruction allows multiple bytes of data to be programmed without re-issuing the next sequential address location. This feature decreases total programming time when the multiple bytes or entire memory array is to be programmed. An AAI program instruction pointing to a protected memory area will be ignored. The selected address range must be in the erased state (FFH) when initiating an AAI program instruction. While within AAI WORD programming sequence, the only valid instructions are AAI WORD program operation, RDSR, WRDI. Users have three options to determine the completion of each AAI WORD program cycle: hardware detection by reading the SO; software detection by polling the BUSY in the software status register or wait TBP. Refer to End-of-Write Detection section for details. Prior to any write operation, the Write-Enable (WREN) instruction must be executed. The AAI WORD program instruction is initiated by executing an 8-bit command, ADH, followed by address bits [A23-A0]. Following the addresses, two bytes of data is input sequentially. The data is input sequentially from MSB (bit 7) to LSB (bit 0). The first byte of data(DO) will be programmed into the initial address [A23-A1] with A0 =0; The second byte of data(D1) will be programmed into the initial address [A23-A1] with A0 =1. CE must be driven high before the AAI WORD program instruction is executed. The user must check the BUSY status before entering the next valid command. Once the device indicates it is no longer busy, data for next two sequential addresses may be programmed and so on. When the last desired byte had been entered, check the busy status using the hardware method or the RDSR instruction and execute the WRDI instruction, to terminate AAI. User must check busy status after WRDI to determine if the device is ready for any command. Please refer to Figures 7 and Figures 8. There is no wrap mode during AAI programming; once the highest unprotected memory address is reached, the device will exit AAI operation and reset the Write-Enable-Latch bit (WEL = 0) and the AAI bit (AAI=0).
End of Write Detection
There are three methods to determine completion of a program cycle during AAI WORD programming: hardware detection by reading the SO, software detection by polling the BUSY bit in the Software Status Register or wait TBP. The hardware end of write detection method is described in the section below.
Hardware End of Write Detection
The hardware end of write detection method eliminates the overhead of polling the BUSY bit in the software status register during an AAI Word PROGRAM OPERATION. The 8bit command, 70H, configures the SO to indicate Flash Busy status during AAI WORD programming (refer to figure5). The 8bit command, 70H, must be executed prior to executing an AAI WORD program instruction. Once an internal programming operation begins, asserting CE will immediately drive the status of the internal flash status on the SO pin. A "0" Indicates the device is busy ; a "1" Indicates the device is ready for the next instruction. De-asserting CE will return the SO pin to tri-state. The 8bit command, 80H,disables the SO pin to output busy status during AAI WORD program operation and return SO pin to output software register data during AAI WORD programming (refer to figure6).
FIGURE 5 : ENABLE SO AS HARDWARE RY / BY DURING AAI PROGRAMMING
FIGURE 6 : DISABLE SO AS HARDWARE RY / BY DURING AAI PROGRAMMING
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F25L004A
Operation Temperature Condition -40 C ~85 C
FIGURE 7 : AUTO ADDRESS INCREMENT (AAI) WORD-PROGRAM SEQUENCE WITH HARDWARE END-OF-WRITE DETETION
FIGURE 8 : AUTO ADDRESS INCREMENT (AAI) WORD-PROGRAM SEQUENCE WITH SOFTWARE END-OF-WRITE DETETION
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64K-Byte Block-Erase
The 64K Byte Block-Erase instruction clears all bits in the selected block to FFH. A Block-Erase instruction applied to a protected memory area will be ignored. Prior to any Write operation, the Write-Enable (WREN) instruction must be executed. CE must remain active low for the duration of the any command sequence. The Block-Erase instruction is initiated by executing an 8-bit command, D8H, followed by address bits
F25L004A
Operation Temperature Condition -40 C ~85 C
[A23-A0]. Address bits [AMS-A16] (AMS = Most Significant address) are used to determine the block address (BAX), remaining address bits can be VIL or VIH. CE must be driven high before the instruction is executed. The user may poll the Busy bit in the software status register or wait TBE for the completion of the internal self-timed Block-Erase cycle. See Figure 9 for the Block-Erase sequence.
FIGURE 9 : 64-KBYTE BLOCK-ERASE SEQUENCE
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4K-Byte-Sector-Erase
The Sector-Erase instruction clears all bits in the selected sector to FFH. A Sector-Erase instruction applied to a protected memory area will be ignored. Prior to any Write operation, the Write-Enable (WREN) instruction must be executed. CE must remain active low for the duration of the any command sequence. The Sector-Erase instruction is initiated by executing an 8-bit command, 20H, followed by address bits [A23-A0]. Address bits
F25L004A
Operation Temperature Condition -40 C ~85 C
[AMS-A12] (AMS = Most Significant address) are used to determine the sector address (SAX), remaining address bits can be VIL or VIH. CE must be driven high before the instruction is executed. The user may poll the Busy bit in the software status register or wait TSE for the completion of the internal self-timed Sector-Erase cycle. See Figure 10 for the Sector-Erase sequence.
CE MODE3 SCK MODE0 012345678 15 16 23 24 31
SI MSB
20
ADD. MSB HIGH IMPENANCE
ADD.
ADD.
SO
FIGURE 10 : SECTOR-ERASE SEQUENCE
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Chip-Erase
The Chip-Erase instruction clears all bits in the device to FFH. A Chip-Erase instruction will be ignored if any of the memory area is protected. Prior to any Write operation, the Write-Enable (WREN) instruction must be executed. CE must remain active low for the duration of the Chip-Erase instruction sequence. The Chip-Erase instruction is initiated by executing an 8-bit command,
F25L004A
Operation Temperature Condition -40 C ~85 C
60H or C7H. CE must be driven high before the instruction is executed. The user may poll the Busy bit in the software status register or wait TCE for the completion of the internal self-timed Chip-Erase cycle. See Figure 11 for the Chip-Erase sequence.
CE MODE3 SCK MODE0 01234567
SI MSB
60 or C7
SO
HIGH IMPENANCE
FIGURE 11 : CHIP-ERASE SEQUENCE
Read-Status-Register (RDSR)
The Read-Status-Register (RDSR) instruction allows reading of the status register. The status register may be read at any time even during a Write (Program/Erase) operation. When a Write operation is in progress, the Busy bit may be checked before sending any new commands to assure that the new commands are properly received by the device. CE must be driven low before the RDSR instruction is entered and remain low until the status data is read. Read-Status-Register is continuous with ongoing clock cycles until it is terminated by a low to high transition of the CE See Figure 12 for the RDSR instruction sequence.
CE MODE3 SCK MODE1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14
SI MSB HIGH IMPENANCE
05
SO
Bit7 MSB
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Status Register Out
Figure12 : READ-STATUS-REGISTER (RDSR) SEQUENCE
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Write-Enable (WREN)
The Write-Enable (WREN) instruction sets the WriteEnable-Latch bit to 1 allowing Write operations to occur.
The WREN instruction must be executed prior to any Write (Program/Erase) operation. CE must be driven high before the WREN instruction is executed.
F25L004A
Operation Temperature Condition -40 C ~85 C
CE MODE3 SCK MODE0 01234567
SI MSB
06
SO
HIGH IMPENANCE
FIGURE 13 : WRITE ENABLE (WREN) SEQUENCE
Write-Disable (WRDI)
The Write-Disable (WRDI) instruction resets the Write-Enable-Latch bit and AAI bit to 0 disabling any new Write operations from occurring. CE must be driven high before the WRDI instruction is executed.
CE MODE3 SCK MODE0 01234567
SI MSB
04
SO
HIGH IMPENANCE
Figure 14 : WRITE DISABLE (WRDI) SEQUENCE
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Enable-Write-Status-Register (EWSR) The Enable-Write-Status-Register (EWSR) instruction arms the Write-Status-Register (WRSR) instruction and opens the status register for alteration. The Enable-Write-Status-Register instruction does not have any effect and will be wasted, if it is not followed immediately by the Write-Status-Register (WRSR) instruction. CE must be driven low before the EWSR instruction is entered and must be driven high before the EWSR instruction is executed.
F25L004A
Operation Temperature Condition -40 C ~85 C
Write-Status-Register (WRSR)
The Write-Status-Register instruction writes new values to the BP2, BP1, BP0, and BPL bits of the status register. CE must be driven low before the command sequence of the WRSR instruction is entered and driven high before the WRSR instruction is executed. See Figure 15 for EWSR or WREN and WRSR instruction sequences. Executing the Write-Status-Register instruction will be ignored when WP is low and BPL bit is set to "1". When the WP is low, the BPL bit can only be set from "0" to "1" to lockdown the status register, but cannot be reset from "1" to "0". When WP is high, the lock-down function of the BPL bit is disabled and the BPL, BP0, BP1,and BP2 bits in the status register can all be changed. As long as BPL bit is set to 0 or WP pin is driven high (VIH) prior to the low-to-high transition of the CE pin at the end of the WRSR instruction, the bits in the status register can all be altered by the WRSR instruction. In this case, a single WRSR instruction can set the BPL bit to "1" to lock down the status register as well as altering the BP0 ;BP1 and BP2 bits at the same time. See Table 3 for a summary description of WP and BPL functions.
CE MODE3 SCK MODE0 STATUS REGISTER IN 76543210 01234567 0 1 2 3 4 5 6 7 8 9 1011 12 13 1415
SI MSB
50 or 06 MSB HIGH IMPENANCE
01
SO
Figure 15 : ENABLE-WRITE-STATUS-REGISTER (EWSR) or WRITE-ENABLE(WREN) and WRITE-STATUS-REGISTER (WRSR)
Elite Semiconductor Memory Technology Inc.
Publication Date: Jan. 2009 Revision: 1.3 19/33
ESMT
Read-Electronic-Signature (RES)
F25L004A
Operation Temperature Condition -40 C ~85 C
The RES instruction can be used to read the 8-bit Electronic Signature of the device on the SO pin. The RES instruction can provide access to the Electronic Signature of the device (except while an Erase, Program or WRSR cycle is in progress), Any ERS instruction executed while an Erase, Program or WRSR cycle is in progress is no decoded, and has no effect on the cycle in progress.
CE MODE3 SCK MODE1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14
SI MSB HIGH IMPENANCE
AB
SO
Bit7 MSB
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Status Register Out
Figure 16 : Read-Electronic-Signature (RES)
Elite Semiconductor Memory Technology Inc.
Publication Date: Jan. 2009 Revision: 1.3 20/33
ESMT
JEDEC Read-ID
F25L004A
Operation Temperature Condition -40 C ~85 C
The JEDEC Read-ID instruction identifies the device as F25L004A and the manufacturer as ESMT. The device information can be read from executing the 8-bit command,.9FH. Following the JEDEC Read-ID instruction, the 8-bit manufacturer's ID, 8CH, is output from the device. After that, a 16-bit device ID is shifted out on the SO pin. Byte1, 8CH, identifies the manufacturer as ESMT. Byte2, 20H, identifies the memory type as SPI Flash. Byte3, 13H, identifies the device as F25L004A. The instruction sequence is shown in Figure17. The JEDEC Read ID instruction is terminated by a low to high transition on CE at any time during data output. If no other command is issued after executing the JEDEC Read-ID instruction, issue a 00H (NOP) command before going into Standby Mode ( CE =VIH).
CE MODE3 SCK MODE0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
SI
9F
SO
HIGH IMPENANCE
M SB
8C
MSB
20
13
Figure 17 : Jedec Read ID Sequence
Table 9 : JEDEC READ-ID DATA
Manufacturer's ID Memory Type Byte1 8CH Byte 2 20H Device ID Memory Capacity Byte 3 13H
Elite Semiconductor Memory Technology Inc.
Publication Date: Jan. 2009 Revision: 1.3 21/33
ESMT
Read-ID (RDID)
F25L004A
Operation Temperature Condition -40 C ~85 C
The Read-ID instruction (RDID) identifies the devices as F25L004A and manufacturer as ESMT. This command is backward compatible to all ESMT SPI devices and should be used as default device identification when multiple versions of ESMT SPI devices are used in one design. The device information can be read from executing an 8-bit command, 90H or ABH, followed by address bits [A23-A0]. Following the Read-ID instruction, the manufacturer's ID is located in address 00000H and the device ID is located in address 00001H. Once the device is in Read-ID mode, the manufacturer's and device ID output data toggles between address 00000H and 00001H until terminated by a low to high transition on CE .
Figure 18 : Read-Electronic-Signature
Table 10 : JEDEC READ-ID DATA Address Manufacturer's ID Device ID ESMT F25L004A 00000H 00001H Byte1 8CH 12H Byte2 12H 8CH
Elite Semiconductor Memory Technology Inc.
Publication Date: Jan. 2009 Revision: 1.3 22/33
ESMT
ELECTRICAL SPECIFICATIONS
F25L004A
Operation Temperature Condition -40 C ~85 C
Absolute Maximum Stress Ratings (Applied conditions greater than those listed under "Absolute Maximum Stress Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.) Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to +150C D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VDD+0.5V Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . -2.0V to VDD+2.0V Package Power Dissipation Capability (Ta = 25C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W Surface Mount Lead Soldering Temperature (3 Seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240C Output Short Circuit Current (Note1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Note 1. Output shorted for no more than one second. No more than one output shorted at a time.
AC CONDITIONS OF TEST
Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . <5 ns Output Load . . . . . . . . . . . . . . . . . . . . . . . . CL = 15 pF for 75MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .CL = 30 pF for 50MHz See Figures 23 and 24
OPERATING RANGE
Parameter Operating Supply Voltage Ambient Operating Temperature Symbol VDD (for FCLK 75MHz) VDD (for FCLK = 100MHz) TA Value 2.7~3.6 3.0~3.6 -40~85 Unit V C
TABLE 6: DC OPERATING CHARACTERISTICS Symbol IDDR IDDW ISB ILI ILO VIL VIH VOL VOH Parameter Read Current Program and Erase Current Standby Current Input Leakage Current Output Leakage Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Min Limits Max 15 40 75 1 1 0.8 0.7 VDD 0.2 VDD-0.2 Units mA mA A A A V V V V Test Conditions CE =0.1 VDD/0.9 VDD@33 MHz, SO=open CE =VDD CE =VDD, VIN=VDD or VSS VIN=GND to VDD, VDD=VDD Max VOUT=GND to VDD, VDD=VDD Max VDD=VDD Min VDD=VDD Max IOL=100 A, VDD=VDD Min IOH=-100 A, VDD=VDD Min
TABLE 7 : RECOMMENDED SYSTEM POWER-UP TIMINGS Symbol Parameter Minimum Units TPU-READ1 VDD Min to Read Operation 10 s TPU-WRITE1 VDD Min to Write Operation 10 s 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. TABLE 8: CAPACITANCE (TA = 25C, f=1 Mhz, other pins open) Parameter Description Test Condition Maximum 1 COUT Output Pin Capacitance VOUT = 0V 12 pF 1 CIN Input Capacitance VIN = 0V 6 pF 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
Elite Semiconductor Memory Technology Inc.
Publication Date: Jan. 2009 Revision: 1.3 23/33
ESMT
TABLE 11: RELIABILITY CHARACTERISTICS
Symbol NEND1 TDR1 ILTH1 1. Parameter Endurance Data Retention Latch Up Minimum Specification 100,000 10 100 + IDD Units Cycles Years mA
F25L004A
Operation Temperature Condition -40 C ~85 C
Test Method JEDEC Standard A117 JEDEC Standard A103 JEDEC Standard 78
This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 12 : AC OPERATING CHARACTERISTICS
Normal 33MHz Fast 50 MHz Fast 100 MHz Symbol Parameter Min FCLK TSCKH TSCKL TCES
1
Units Max 33 13 13 5 5 5 5 100 9 0 3 3 5 5 5 5 9 9 0 12 0 8 0 3 3 5 5 5 5 9 9 0 7 9 9 5 5 5 5 100 9 0 3 3 5 5 5 5 9 9 Min Max 50 5 5 5 5 5 5 100 9 Min Max 100 MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Serial Clock Frequency Serial Clock High Time Serial Clock Low Time CE Active Setup Time CE Active Hold Time CE Not Active Setup Time CE Not Active Hold Time CE High Time CE High to High-Z Output SCK Low to Low-Z Output Data In Setup Time Data In Hold Time HOLD Low Setup Time HOLD High Setup Time HOLD Low Hold Time HOLD High Hold Time HOLD Low to High-Z Output HOLD High to Low-Z Output Output Hold from SCK Change Output Valid from SCK
TCEH1 TCHS1 TCHH1 TCPH TCHZ TCLZ TDS TDH THLS THHS THLH THHH THZ TLZ TOH TV 1. Relative to SCK.
Elite Semiconductor Memory Technology Inc.
Publication Date: Jan. 2009 Revision: 1.3 24/33
ESMT
ERASE AND PROGRAMMING PERFORMANCE
F25L004A
Operation Temperature Condition -40 C ~85 C
Limits Parameter Sector Erase Time Block Erase Time Chip Erase Time Byte Programming Time Chip Programming Time Erase/Program Cycles (1) Data Retention Notes: 1.Not 100% Tested, Excludes external system level over head. 2.Typical values measured at 25C, 3V. 3.Maximum values measured at 85C, VDD(min) Symbol TSE TBE TCE TBP Typ.(2) 90 1 4 9 12 100,000 20 Max.(3) 200 2 30 300 100 Unit ms s s us s Cycles Years
Elite Semiconductor Memory Technology Inc.
Publication Date: Jan. 2009 Revision: 1.3 25/33
ESMT
F25L004A
Operation Temperature Condition -40 C ~85 C
FIGURE 19: SERIAL INPUT TIMING DIAGRAM
FIGURE 20: SERIAL OUTPUT TIMING DIAGRAM
Elite Semiconductor Memory Technology Inc.
Publication Date: Jan. 2009 Revision: 1.3 26/33
ESMT
CE#
F25L004A
Operation Temperature Condition -40 C ~85 C
SCK
SO
SI HOLD#
FIGURE 21: HOLD TIMING DIAGRAM
FIGURE 22: POWER-UP TIMING DIAGRAM
Elite Semiconductor Memory Technology Inc.
Publication Date: Jan. 2009 Revision: 1.3 27/33
ESMT
F25L004A
Operation Temperature Condition -40 C ~85 C
Input timing reference level 0.8VCC 0.7VCC 0.3VCC AC Measurement Level
Output timing reference level
0.5VCC
0.2VCC
Note : Input pulse rise and fall time are <5ns
FIGURE 23 : AC INPUT/OUTPUT REFERENCE WAVEFORMS
FIGURE 24: A TEST LOAD EXAMPLE
Elite Semiconductor Memory Technology Inc.
Publication Date: Jan. 2009 Revision: 1.3 28/33
ESMT
PACKAGING DIAGRAMS 8-LEAD SOIC ( 150 mil )
F25L004A
Operation Temperature Condition -40 C ~85 C
8
5
E
H
GAUGE PLANE
0.25
0
L DETAIL "X"
1
4
b D
e
A2
A
SEATING PLANE
Dimension in mm Symbol Min A A1 A2 b c H 1.35 0.10 1.25 0.33 0.19 5.80 Norm 1.60 0.15 1.45 0.406 0.203 6.00 Max 1.75 0.25 1.55 0.51 0.25 6.20
Dimension in inch Symbol Min 0.053 0.004 0.049 0.013 0.0075 0.228 Norm 0.063 0.006 0.057 0.016 0.008 0.236 Max 0.069 0.010 0.061 0.020 0.010 0.244 D E L e L1
A1
"X"
L1
Dimension in mm Min 4.80 3.80 0.40 Norm 4.90 3.90 0.66 1.27 BSC 1.00 1.05 --1.10 8 Max 5.00 4.00 0.86
Dimension in inch Min 0.189 0.150 0.016 Norm 0.193 0.154 0.026 0.050 BSC 0.039 0.041 --0.043 8 Max 0.197 0.157 0.034
0
0
Controlling dimension : millimenter
Elite Semiconductor Memory Technology Inc.
Publication Date: Jan. 2009 Revision: 1.3 29/33
C
ESMT
PACKING 8-LEAD DIMENSIONS SOIC 200 mil (official name - 209 mil)
F25L004A
Operation Temperature Condition -40 C ~85 C
8
5
E1
1
b e
4
D
A2
A
E
L A1 L1
SEATING PLANE
DETAIL "X"
Dimension in mm Symbol Min A A1 A2 b c D --0.05 1.70 0.36 0.19 5.13 Norm --0.15 1.80 0.41 0.20 5.23 Max 2.16 0.25 1.91 0.51 0.25 5.33
Dimension in inch Symbol Min --0.002 0.067 0.014 0.007 0.202 Norm --0.006 0.071 0.016 0.008 0.206 Max 0.085 0.010 0.075 0.020 0.010 0.210 E E1 L e L1
Dimension in mm Min 7.70 5.18 0.50 Norm 7.90 5.28 0.65 1.27 BSC 1.27 1.37 --1.47 8 Max 8.10 5.38 0.80
Dimension in inch Min 0.303 0.204 0.020 Norm 0.311 0.208 0.026 0.050 BSC 0.050 0.054 --0.058 8 Max 0.319 0.212 0.032
0
0
Controlling dimension : millimenter
Elite Semiconductor Memory Technology Inc.
Publication Date: Jan. 2009 Revision: 1.3 30/33
ESMT
PACKING DIMENSIONS 8-Leads P-DIP ( 300 MIL )
D 8 5 0 E1 eB
F25L004A
Operation Temperature Condition -40 C ~85 C
1
4
A2
A S e a t in g P la n e L
b
1
b e
Symbol
A A1 A2 D E E1 L e eB b b1
O
Dimension in mm Min Norm Max 5.00 0.38 3.18 9.02 3.30 9.27 7.62 BSC. 6.22 9.02 6.35 9.27 2.54 TYP. 8.51 9.02 0.46 TYP. 1.52 TYP. 0
O
A1
E
Dimension in inch Min Norm Max 0.21 0.015
3.43 10.16
0.125 0.355
0.130 0.365 0.300 BSC.
0.135 0.400
6.48 10.16
0.245 0.115
0.250 0.130 0.100 TYP.
0.255 0.150
9.53
0.335
0.355 0.018 TYP. 0.060 TYP.
0.375
7
O
15
O
0
O
7O
15O
Controlling dimension : Inch.
Elite Semiconductor Memory Technology Inc.
Publication Date: Jan. 2009 Revision: 1.3 31/33
ESMT
Revision History
Revision 1.0 1.1 1.2 Date 2007.04.04 2007.10.02 2008.07.17 Original Description
F25L004A
Operation Temperature Condition -40 C ~85 C
1.3
2009.01.12
1. Modify part No. for I grade. 2. Delete bottom block protection table. 1. Add "All Pb-free products are RoHS-Compliant" in the description of features 2. Modify tSE timing 3. Add Revision History 1. Correct the size of "L" in the packaging diagram of SOIC 150 mil 2.Add operating range table 3.Delete the rating of Temperature Under Bias 4.Add the symbol for erase and byte programming time 5.Correct typo error 6.Modify headline
Elite Semiconductor Memory Technology Inc.
Publication Date: Jan. 2009 Revision: 1.3 32/33
ESMT
Important Notice All rights reserved.
F25L004A
Operation Temperature Condition -40 C ~85 C
No part of this document may be reproduced or duplicated in any form or by any means without the prior permission of ESMT. The contents contained in this document are believed to be accurate at the time of publication. ESMT assumes no responsibility for any error in this document, and reserves the right to change the products or specification in this document without notice. The information contained herein is presented only as a guide or examples for the application of our products. No responsibility is assumed by ESMT for any infringement of patents, copyrights, or other intellectual property rights of third parties which may result from its use. No license, either express , implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of ESMT or others. Any semiconductor devices may have inherently a certain rate of failure. To minimize risks associated with customer's application, adequate design and operating safeguards against injury, damage, or loss from such failure, should be provided by the customer when making application designs. ESMT 's products are not authorized for use in critical applications such as, but not limited to, life support devices or system, where failure or abnormal operation may directly affect human lives or cause physical injury or property damage. If products described here are to be used for such kinds of application, purchaser must do its own quality assurance testing appropriate to such applications.
Elite Semiconductor Memory Technology Inc.
Publication Date: Jan. 2009 Revision: 1.3 33/33

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