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| EM680FV8AU Series Low Power, 1Mx8 SRAM Document Title 1M x 8 bit Low Power and Low Voltage Full CMOS Static RAM Revision History Revision No. 0.0 0.1 0.2 0.3 History Initial Draft 0.1 Revision 0.2 Revision 0.3 Revision Add to address A19 information Product code table update Fix typo error Draft Date May 6, 2007 May 24, 2007 June 15, 2007 Nov. 12, 2007 Remark Preliminary Emerging Memory & Logic Solutions Inc. 4F Korea Construction Financial Cooperative B/D, 301-1 Yeon-Dong, Jeju-Si, Jeju-Do, Rep.of Korea Tel : +82-64-740-1712 Fax : +82-64-740-1749~1750 / Homepage : www.emlsi.com Zip Code : 690-719 The attached data sheets are provided by EMLSI reserve the right to change the specifications and products. EMLSI will answer to your questions about device. If you have any questions, please contact the EMLSI office. 1 EM680FV8AU Series Low Power, 1Mx8 SRAM FEATURES * * * * * * Process Technology : 0.15m Full CMOS Organization : 1M x 8 bit Power Supply Voltage : 2.7V ~ 3.6V Low Data Retention Voltage : 1.5V (Min.) Three state output and TTL Compatible Package Type : 44-TSOP2 GENERAL DESCRIPTION The EM680FV8AU is fabricated by EMLSI's advanced full CMOS process technology. The families support industrial temperature range and Chip Scale Package for user flexibility of system design. The families also supports low data retention voltage for battery back-up operation with low data retention current. PRODUCT FAMILY Power Dissipation Product Family EM680FV8AU-45LF EM680FV8AU-55LF EM680FV8AU-70LF Operating Temperature Industrial (-40 ~ 85oC) Industrial (-40 ~ 85oC) Industrial (-40 ~ 85oC) Vcc Range Speed Standby (ISB1, Typ.) 2 A 2 A 2 A Operating (ICC1.Max) 4mA 4mA 4mA PKG Type 2.7V~3.6V 2.7V~3.6V 2.7V~3.6V 45ns 55ns 70ns 44-TSOP2 44-TSOP2 44-TSOP2 PIN DESCRIPTION FUNCTIONAL BLOCK DIAGRAM Pre-charge Circuit A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 VCC Row Select VSS Memory Array 2048 x 4096 I/O0 ~ I/O7 Data Cont I/O Circuit Column Select A11 A12 A13 A14 A15 A16 A17 A18 A19 44-TSOP2 : Top view WE OE CS1 CS2 Control Logic Name Function Name Vcc Vss NC Function Power Supply Ground No Connected CS1, CS2 Chip select inputs OE WE A0~A19 Output Enable input Write Enable input Address Inputs I/O0~I/O7 Data Inputs/outputs 2 EM680FV8AU Series Low Power, 1Mx8 SRAM ABSOLUTE MAXIMUM RATINGS * Parameter Voltage on Any Pin Relative to Vss Voltage on Vcc supply relative to Vss Power Dissipation Operating Temperature Symbol VIN, VOUT VCC PD TA Minimum -0.2 to 4.0V -0.2 to 4.0V 1.0 -40 to 85 Unit V V W o C * Stresses greater than those listed above "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability. FUNCTIONAL DESCRIPTION CS1 H X L L L CS2 X L H H H OE X X H L X WE X X H H L I/O High-Z High-Z High-Z Data Out Data In Mode Deselected Deselected Output Disabled Read Write Power Stand by Stand by Active Active Active Note: X means don't care. (Must be low or high state) 3 EM680FV8AU Series Low Power, 1Mx8 SRAM RECOMMENDED DC OPERATING CONDITIONS 1) Parameter Supply voltage Ground Input high voltage Input low voltage 1. 2. 3. 4. Symbol VCC VSS VIH VIL Min 2.7 0 2.2 -0.23) Typ 3.3 0 - Max 3.6 0 VCC + 0.22) 0.6 Unit V V V V TA= -40 to 85oC, otherwise specified Overshoot: VCC +2.0 V in case of pulse width < 20ns Undershoot: -2.0 V in case of pulse width < 20ns Overshoot and undershoot are sampled, not 100% tested. CAPACITANCE1) (f =1MHz, TA=25oC) Item Input capacitance Input/Ouput capacitance 1. Capacitance is sampled, not 100% tested Symbol CIN CIO Test Condition VIN=0V VIO=0V Min - Max 8 10 Unit pF pF DC AND OPERATING CHARACTERISTICS Parameter Input leakage current Output leakage current Operating power supply Symbol ILI ILO ICC ICC1 Average operating current ICC2 Output low voltage Output high voltage Standby Current (TTL) VOL VOH ISB VIN=VSS to VCC CS1=VIH or OE=VIH or WE=VIL VIO=VSS to VCC IIO=0mA, CS1=VIL, CS2=WE=VIH, VIN=VIH or VIL Cycle time=1s, 100% duty, IIO=0mA, CS1<0.2V, CS2>VCC-0.2V VIN<0.2V or VIN>VCC-0.2V Cycle time = Min, IIO=0mA, 100% duty, CS1=VIL, CS2=VIH Others VIN=VIL or VIH IOL = 2.1mA IOH = -1.0mA CS1=VIH, CS2=VIL Other inputs=VIH or VIL CS1>VCC-0.2V, CS2>VCC-0.2V (CS1 controlled) Test Conditions Min -1 -1 45ns 55ns 70ns Typ - Max 1 1 2 4 45 35 25 0.4 0.5 Unit uA uA mA mA 2.2 - - mA V V mA or 0v LF - 2 15 uA 4 EM680FV8AU Series Low Power, 1Mx8 SRAM VTM3) R12) AC OPERATING CONDITIONS Test Conditions (Test Load and Test Input/Output Reference) Input Pulse Level : 0.4 to 2.4V Input Rise and Fall Time : 5ns Input and Output reference Voltage : 1.5V Output Load (See right) : CL1) = 100pF + 1 TTL (70ns) CL1) = 30pF + 1 TTL (45ns, 55ns) 1. Including scope and Jig capacitance 2. R1=3070 ohm, R2=3150 ohm 3. VTM=2.8V 4. CL = 5pF + 1 TTL (measurement with tLZ1,2, tHZ12, tOLZ, tOHZ, tWHZ) CL1) R22) READ CYCLE (Vcc =2.7 to 3.6V, Gnd = 0V, TA = -40oC to +85oC) Parameter Read cycle time Address access time Chip select to output Output enable to valid output Chip select to low-Z output Output enable to low-Z output Chip disable to high-Z output Output disable to high-Z output Output hold from address change Symbol tRC tAA tco1, tco2 tOE tLZ1, tLZ2 tOLZ tHZ1, tHZ2 tOHZ tOH 45ns Min 45 5 5 0 0 10 20 20 Max 45 45 30 Min 55 5 5 0 0 10 55ns Max 55 55 35 Min 70 5 5 20 20 0 0 10 70ns Max 70 70 35 20 20 - Unit ns ns ns ns ns ns ns ns ns WRITE CYCLE (Vcc =2.7 to 3.6V, Gnd = 0V, TA = -40oC to +85oC) Parameter Write cycle time Chip select to end of write Address setup time Address valid to end of write Write pulse width Write recovery time Write to ouput high-Z Data to write time overlap Data hold from write time End write to output low-Z Symbol tWC tCW1, tCW2 tAS tAW tWP tWR tWHZ tDW tDH tOW 45ns Min 45 45 0 45 45 0 0 25 0 5 Max 20 Min 55 45 0 45 45 0 0 30 0 5 55ns Max 20 Min 70 60 0 60 55 0 0 30 0 5 70ns Max 20 Unit ns ns ns ns ns ns ns ns ns ns 5 EM680FV8AU Series Low Power, 1Mx8 SRAM TIMING DIAGRAMS TIMING WAVEFORM OF READ CYCLE(1). (Address Controlled, CS1=OE=VIL, tRC Address tAA tOH Data Out Previous Data Valid Data Valid CS2=WE=VIL) TIMING WAVEFORM OF READ CYCLE(2) (WE = VIH) tRC Address tAA CS1 tCO1,2 tOH CS2 tOE OE tOLZ Data Out High-Z tLZ1,2 Data Valid tHZ1,2 tOHZ NOTES (READ CYCLE) 1. tHZ1,2 and tOHZ are defined as the outputs achieve the open circuit conditions and are not referanced to output voltage levels. 2. At any given temperature and voltage condition, tHZ1,2(Max.) is less than tLZ1,2(Min.) both for a given device and from device to device interconnection. 6 EM680FV8AU Series Low Power, 1Mx8 SRAM TIMING WAVEFORM OF WRITE CYCLE(1) (WE CONTROLLED) tWC Address tCW1,2(2) CS1 tWR(4) CS2 tAW tWP(1) WE tAS(3) Data in High-Z tWHZ Data out Data Undefined tDW Data Valid tDH High-Z tOW TIMING WAVEFORM OF WRITE CYCLE(2) (CS1 CONTROLLED) tWC Address tAS(3) CS1 CS2 tAW tWP(1) WE tDW Data in Data Valid tCW1,2(2) tWR(4) tDH Data out High-Z High-Z 7 EM680FV8AU Series Low Power, 1Mx8 SRAM TIMING WAVEFORM OF WRITE CYCLE(3) (CS2 CONTROLLED) tWC Address tCW1,2(2) CS1 tAS(3) tWR(4) CS2 tAW tWP(1) WE tDW Data in Data Valid tDH Data out High-Z High-Z NOTES (WRITE CYCLE) 1. A write occurs during the overlap(tWP) of low CS1, a high CS2 and low WE. A write begins at the latest transition among CS1 goes low, CS2 goes high and WE goes low. A write ends at the earliest transition among CS1 goes high, CS2 goes low and WE goes high. The tWP is measured from the beginning of write to the end of write. 2. tCW is measured from the CS1 going low or CS2 going high to end of write. 3. tAS is measured from the address valid to the beginning of write. 4. tWR is measured from the end or write to the address change. tWR applied in case a write ends as CS1 or WE going high or CS2 going low. 8 EM680FV8AU Series Low Power, 1Mx8 SRAM DATA RETENTION CHARACTERISTICS Parameter VCC for Data Retention Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time NOTES Symbol VDR IDR tSDR tRDR Test Condition CS1 Vcc-0.2V 1) VCC=1.5V, CS1 Vcc-0.2V 1) See data retention wave form Min 1.5 0 tRC Typ - Max 3.6 4 - Unit V uA ns - 1. CS1 Vcc-0.2V , CS2 Vcc-0.2V (CS1 controlled) or CS2 0.2V (CS2 controlled) DATA RETENTION WAVE FORM CS1 Controlled tSDR Vcc 2.7V Data Retention Mode tRDR 2.2V VDR CS1 > Vcc-0.2V CS1 GND CS2 Controlled Vcc 2.7V CS2 tSDR Data Retention Mode tRDR VDR 0.4V GND CS2 < 0.2V 9 EM680FV8AU Series Low Power, 1Mx8 SRAM PACKAGE DIMENSION 44 - TSOP2 (0.8mm pin pitch) 10 EM680FV8AU Series Low Power, 1Mx8 SRAM SRAM PART CODING SYSTEM EM X XX X X X XX X X - XX XX 1. EMLSI Memory 2. Product Type 3. Density 4. Function 5. Technology 6. Operating Voltage 1. Memory Component EM --------------------- Memory 2. Product Type 6 ------------------------ SRAM 3. Density 1 ------------------------- 1M 2 ------------------------- 2M 4 ------------------------- 4M 8 ------------------------- 8M 4. Function 0 ----------------------- Dual CS 1 ----------------------- Single CS 2 ----------------------- Multiplexed 3 ------------- Single CS / LBB, UBB(tBA=tOE) 4 ------------- Single CS / LBB, UBB(tBA=tCO) 5 ------------- Dual CS / LBB, UBB(tBA=tOE) 6 ------------- Dual CS / LBB, UBB(tBA=tCO) 5. Technology F ------------------------- Full CMOS 6. Operating Voltage T ------------------------- 5.0V V ------------------------- 3.3V U ------------------------- 3.0V S ------------------------- 2.5V R ------------------------- 2.0V P ------------------------- 1.8V 11. Power 10. Speed 9. Package 8. Generation 7. Organization 7. Organization 8 ---------------------- x8 bit 16 ---------------------- x16 bit 8. Generation Blank ----------------- 1st generation A ----------------------- 2nd generation B ----------------------- 3rd generation C ----------------------- 4th generation D ----------------------- 5th generation E ----------------------- 6th generation F ----------------------- 7th generation G ---------------------- 8th generation 9. Package Blank ---------------- KGD, 48&36FpBGA S ---------------------- 32 sTSOP1 T ---------------------- 32 TSOP1 U ---------------------- 44 TSOP2 V ---------------------- 32 SOP 10. Speed 45 ---------------------55 ---------------------70 ---------------------85 ---------------------10 ---------------------12 ---------------------- 45ns 55ns 70ns 85ns 100ns 120ns 11. Power LL ---------------------- Low Low Power LF ---------------------- Low Low Power(Pb-Free & Green) L ---------------------- Low Power S ---------------------- Standard Power 11 |
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