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Section I. HardCopy II Device Family Data Sheet This section provides designers with the data sheet specifications HardCopy(R) II devices. These cpaters contain feature definitions of the internal architecture, configuration and JTAG boundary-scan testing information, DC operationg conditions, AC timing parameters, a reference to power consumption, and ordering information for HardCopy II devices. This section contains the following: "Introduction to HardCopy II Devices" on page 1-1 "Description, Architecture, and Features" on page 2-1 "Boundary-Scan Support" on page 3-1 "DC and Switching Specifications and Operating Conditions" on page 4-1 "Quartus II Support for HardCopy II Devices" on page 5-1 "Script-Based Design for HardCopy II Devices" on page 6-1 "Timing Constraints for HardCopy II Devices" on page 7-1 "Migrating Stratix II Device Resources to HardCopy II Devices" on page 8-1 Revision History Refer to each chapter for its own specific revision history. For information on when each chapter was updated, refer to the Chapter Revision Dates section, which appears in the complete handbook. Altera Corporation Section I-1 Preliminary Revision History HardCopy Series Handbook, Volume 1 Section I-2 Preliminary Altera Corporation 1. Introduction to HardCopy II Devices H51015-2.6 Introduction HardCopy (R) II devices are low-cost, high-performance structured ASICs with pin-outs, densities, and architecture that complement Stratix (R) II devices. HardCopy II device features, such as phase-locked loops (PLLs), memory, and I/O elements (IOEs), are functionally and electrically equivalent to the Stratix II FPGA features. The combination of Stratix II FPGAs for in-system prototype and design verification, HardCopy II devices for high-volume production, and the Quartus (R) II software for design, provide a complete, low-risk design solution. HardCopy II devices improve on the successful and proven methodology of the two previous generations of HardCopy series devices. Altera(R) HardCopy II devices use the same base arrays across multiple designs for a given device density and are customized using only two metal layers. HardCopy II devices offer up to 90% cost reduction compared to Stratix II FPGA prototypes. The Quartus II software provides a complete set of tools, common for both designing Stratix II FPGA prototypes and for quickly migrating the design to a HardCopy II companion device. HardCopy II devices are also supported through other front-end design tools from Synopsys, Synplicity, and Mentor Graphics (R). Feature Overview HardCopy II structured ASICs are manufactured on a 1.2 V, 90 nm all-layer-copper metal fabrication process (up to nine layers of metal). HardCopy II devices offer the following features: Fine-grained HCell architecture resulting in a low-cost, high-performance, low-power structured ASIC Customized using only two metal layers for fast turn-around times and low non-recurring expenses (NRE) Fully tested prototypes are available in approximately 10 to 12 weeks from the date of your design submission Support for instant-on or instant-on-after-50-ms power-up modes Preserves the design functionality of a Stratix II FPGA prototype 1,000,000 to 3,600,000 usable gates for both logic and DSP functions Altera Corporation September 2008 1-1 Preliminary HardCopy Series Handbook, Volume 1 System performance up to 350 MHz Up to 50% power reduction (dynamic and static) for typical designs compared to Stratix II FPGA prototypes The actual performance and power consumption improvements mentioned in this datasheet are design-dependent. Internal Memory Up to 8,847,360 RAM bits available (including parity bits) True dual-port memory, suitable for use in first-in-first-out (FIFO) buffers Phase-Locked Loops (PLLs) Up to 16 global clocks with 24 clocking resources per device region Clock control block supports dynamic clock network enable/disable and dynamic global clock network source selection Up to 12 PLLs (four enhanced PLLs and eight fast PLLs) per device which provide identical features as the FPGA counterparts, including spread spectrum, programmable bandwidth, clock switchover, real-time PLL reconfiguration, advanced multiplication, and phase shifting I/O Standards and Intellectual Property (IP) Support for numerous single-ended and differential I/O standards such as LVTTL, LVCMOS, PCI, PCI-X, SSTL, HSTL, and LVDS High-speed differential I/O support on up to 116 channels with dynamic phase alignment (DPA) circuitry for 1-Gigabit-per-second (Gbps) performance Support for high-speed networking and communications bus standards including Parallel RapidIO, SPI-4 Phase 2 (POS-PHY Level 4), HyperTransportTM technology, and SFI-4 Support for high-speed external memory, including DDR and DDR2 SDRAM, RLDRAM II, QDRII SRAM, and SDR SDRAM Support for multiple intellectual property megafunctions from Altera MegaCore (R) functions, and Altera Megafunction Partners Program (AMPPSM) megafunctions Packaging Pin-compatible with Stratix II FPGA prototypes Up to 951 user I/O pins available Available in wire bond and flip-chip space-saving FineLine BGA packages (Table 1-3). 1 1-2 Preliminary Altera Corporation September 2008 Feature Overview The HardCopy II device family consists of five devices. Table 1-1 summarizes the features available in the HardCopy II devices. Table 1-1. HardCopy II Device Family Features Feature ASIC equivalent gates (2) M4K RAM blocks (4 Kbits plus parity) M-RAM blocks (512 Kbits plus parity) Total RAM bits (including parity bits) Enhanced PLLs Fast PLLs Maximum user I/O pins (4), (5) Notes to Table 1-1: (1) HC210W devices are in a wire bond package. All other HardCopy II devices and Stratix II FPGAs use a flip-chip package. Devices in a wire bond package offer different performance and signal integrity characteristics compared to devices in a flip-chip package. This is the number of ASIC equivalent gates available in the HardCopy II base array, shared between both adaptive logic module (ALM) logic and DSP functions from a Stratix II FPGA prototype. Each Stratix II adaptive logic module (ALM) is equal to approximately 30 ASIC equivalent gates. The number of ASIC equivalent gates usable is bounded by the number of ALMs in the companion Stratix II FPGA device. Total number of usable M4K blocks is 768, which allows migration compatibility when prototyping with an EP2S180 device. This may be different from the Quartus II software total physical M4K count of the HC240. The I/O pin counts include the dedicated CLK input pins, which can be used for clock signals or data inputs. The Quartus II I/O pin counts include an additional pin (PLLENA), which is not available as a general-purpose I/O pin. The PLLENA pin can only be used to enable the PLLs. HC210W (1) 1,000,000 190 0 875,520 2 2 308 HC210 1,000,000 190 0 875,520 2 2 334 HC220 1,900,000 408 2 3,059,712 2 2 494 HC230 2,900,000 614 6 6,368,256 4 4 698 HC240 3,600,000 768 (3) 9 8,847,360 4 8 951 (2) (3) (4) (5) Altera Corporation September 2008 1-3 Preliminary HardCopy Series Handbook, Volume 1 Migration and Packaging Overview HardCopy II devices offer pin-to-pin compatibility to the Stratix II prototype, which makes them drop-in replacements for the FPGAs. Therefore, the same system board and software developed for prototyping and field trials can be retained, enabling the fastest time-to-market for high-volume production. When migrating a specific Stratix II FPGA to a HardCopy II device, there are a number of FPGA prototype choices, as shown in Table 1-2. Depending on the design resource needs, designers can choose an appropriate HardCopy II device. Table 1-2. Stratix II FPGA to HardCopy II Migration Paths HardCopy II Device HC210W HC210 HC220 HC220 HC230 HC240 HC240 Stratix II Device Package EP2S30 484-pin FineLine BGA (1) 484-pin FineLine BGA 672-pin FineLine BGA 780-pin FineLine BGA 1,020-pin FineLine BGA 1,020-pin FineLine BGA 1,508-pin FineLine BGA EP2S60 v v v EP2S90 v (2) v (2) v v EP2S130 EP2S180 v v v (2) v v (2) v v Notes to Table 1-2: (1) (2) The HC210W device uses a wire bond package while the Stratix II FPGA prototype device uses a pin-compatible flip-chip package. Depending on design specific resource utilization, an opportunistic migration path may exist between this device pair. Be sure to confirm your design is a potential candidate for such a path by fitting with the Quartus II software and consulting an Altera applications engineer. 1-4 Preliminary Altera Corporation September 2008 Document Revision History HardCopy II devices are available in the packages shown in Table 1-3. Table 1-3. HardCopy II Package Options and I/O Pin Counts Package Type Dimension Pitch (mm) Area (mm2) 1.00 529 23 x 23 1.00 529 23 x 23 1.00 729 27 x 27 Notes (1), (2) 484-Pin 484-Pin 672-Pin 780-Pin 1,020-Pin 1,508-Pin FineLine BGA FineLine BGA FineLine BGA FineLine BGA FineLine BGA FineLine BGA (3) (3) Wire bond Flip-chip Flip-chip Flip-chip Flip-chip Flip-chip 1.00 841 29 x 29 1.00 1,089 33 x 33 1.00 1,600 40 x 40 Length x width (mm x mm) Device HC210W HC210 HC220 HC230 HC240 Notes to Table 1-3: (1) (2) (3) Maximum User I/O Pins 308 334 492 494 698 742 951 The Quartus II I/O pin counts include an additional pin (PLLENA) which is not available as a general-purpose I/O pin. The PLLENA pin can only be used to enable the PLLs. The I/O pin counts include the dedicated CLK input pins, which can be used for clock signals or data inputs. The EP2S90 FPGA prototype uses a 484-pin hybrid FineLine BGA package. For more information, refer to the Stratix II Device Handbook. Document Revision History Table 1-4 shows the revision history for this chapter. Table 1-4. Document Revision History (Part 1 of 2) Date and Document Version September 2008, v2.6 June 2007, v2.5 Changes Made Updated chapter number and metadata. Minor text edits. Summary of Changes -- -- Altera Corporation September 2008 1-5 Preliminary HardCopy Series Handbook, Volume 1 Table 1-4. Document Revision History (Part 2 of 2) Date and Document Version December 2006 v2.4 Changes Made Minor updates for the Quartus II software version 6.1.0 Merged Table 1-3 and Table 1-4 Added revision history Summary of Changes A minor update to the chapter, due to changes in the Quartus II software version 6.1 release. Merged Table 1-3 and Table 1-4. March 2006, v2.3 Updated Table 1-1 and Table 1-3. Minor edits and clarifications throughout. October 2005, v2.2. Updated graphics July 2005, v2.2. May 2005, v2.0 Updated graphics Updated Table 1-1. Updated migration process time. Updated "Features" section. January 2005 v1.0 Added document to the HardCopy Series Handbook. 1-6 Preliminary Altera Corporation September 2008 2. Description, Architecture, and Features H51016-2.5 Introduction Altera(R) HardCopy (R) II devices feature an architecture that provides high-density, high-performance, and low-power consumption suitable for a variety of applications. HardCopy II devices are low-cost structured ASICs with pin-outs, densities, and architecture that complement Stratix (R) II FPGAs. HardCopy II devices make optimal use of die area and core resources while offering features that are functionally equivalent to the Stratix II FPGA. The combination of Stratix II FPGAs for in-system prototype and design verification, HardCopy II devices for high-volume production, and the Quartus(R) II design software, provide a complete, seamless path from prototype to volume production. Table 2-1 provides an overview of the HardCopy II device features. Table 2-1. HardCopy II Family Overview (Part 1 of 2) Feature ASIC gates (2) M4K RAM blocks (4k bits plus parity) M-RAM blocks (512k bits plus parity) Total RAM bits (including parity bits) Enhanced PLLs Fast PLLs Package (maximum user I/O pins) (4), (5) HC210W (1) 1,000,000 190 0 875,520 2 2 484-pin FineLine BGA (308) HC210 1,000,000 190 0 875,520 2 2 484-pin FineLine BGA (334) HC220 1,900,000 408 2 3,059,712 2 2 672-pin FineLine BGA (492) 780-pin FineLine BGA (494) HC230 2,900,000 614 6 6,368,256 4 4 1,020-pin FineLine BGA (698) HC240 3,600,000 768 (3) 9 8,847,360 4 8 1,020-pin FineLine BGA (742) 1,508-pin FineLine BGA (951) Altera Corporation September 2008 2-1 Preliminary HardCopy Series Handbook, Volume 1 Table 2-1. HardCopy II Family Overview (Part 2 of 2) Feature FPGA prototype options Notes to Table 2-1: (1) HC210W devices use a wire bond package. All other HardCopy II devices and Stratix II FPGAs use a flip-chip package. Devices in a wire bond package offer different performance and signal integrity characteristics compared to devices in a flip-chip package. This is the number of ASIC gates available in the HardCopy II base array for both logic and DSP functions that can be implemented in a Stratix II FPGA prototype. Total number of usable M4K blocks is 768, which allows migration compatibility when prototyping with an EP2S180 device. This may be different from the Quartus II software total physical M4K count of the HC240. The I/O pin counts include the dedicated clock input pins, which can be used for clock signals or data inputs. The Quartus II I/O pin counts include an additional pin (PLLENA), which is not available as a general-purpose I/O pin. The PLLENA pin can only be used to enable the PLLs. HC210W (1) EP2S30 EP2S60 EP2S90 HC210 EP2S30 EP2S60 EP2S90 HC220 EP2S60 EP2S90 EP2S130 HC230 EP2S90 EP2S130 EP2S180 HC240 EP2S180 (2) (3) (4) (5) Functional Description The HardCopy II device family provides greater flexibility to design with FPGA prototypes before moving to structured ASICs for production. Before seamlessly migrating to the HardCopy II structured ASIC, designers can prototype and test their design functionality using a Stratix II FPGA. There are multiple options for the prototype FPGA, allowing designers to choose the right HardCopy II device for volume production and maximum cost savings. The Quartus II design software includes features such as the Device Resource Guide, to help select the optimal HardCopy II device based on the design requirements. For more information on the Device Resource Guide, refer to the Quartus II Support for HardCopy II Devices chapter in the HardCopy Series Handbook. HardCopy II devices require minimal involvement from the designer in the device migration process. Additionally, unlike ASICs, the designer is not required to generate test benches, test vectors, or timing and functional simulations since prototyping is performed using an FPGA. HardCopy II devices consist of base arrays that are common to all designs for a particular device density, with design-specific customization done using two metal layers. The reprogrammable FPGA logic, routing, memory, and FPGA configuration-related logic are stripped from HardCopy II devices. Removing all programmable and configuration resources and replacing them with direct metal connections results in considerable die size reduction and cost savings. A fine-grain architecture consisting of an array of HCells extends the die reduction and cost f 2-2 Preliminary Altera Corporation September 2008 Functional Description savings, which results in low-cost structured ASICs with high-performance and low-power suitable for a wide variety of applications. The SRAM configuration cells of the Stratix II FPGAs are replaced in HardCopy II devices with metal connections, which define the function of logic, memory, phase-locked loop (PLL), and I/O elements (IOEs) in the device. These resources are interconnected using metallization layers. Once a HardCopy II device is manufactured, the functionality of the device is fixed. HardCopy II devices are manufactured using the same 90-nm process technology and operate using the same core voltage (1.2 V) as Stratix II FPGAs. Additionally, almost all architectural features in HardCopy II devices are functionally equivalent to features found in the Stratix II FPGA architecture. HardCopy II devices feature HCells, memory blocks, PLLs, and IOEs (Figure 2-1). Figure 2-1. Example Block Diagram of HC230 Device M4K RAM Blocks IOE Array of HCells IOE M4K RAM Blocks IOEs Array of HCells Enhanced PLL Note (1) Fast PLL Array of HCells IOE IOE IOE IOE IOE IOE M-RAM Block IOE IOE IOE IOE IOE IOE Fast PLL Array of HCells Array of HCells Array of HCells Note to Figure 2-1: (1) Figure 2-1 shows a graphical representation of the device floor plan. A detailed floor plan is available in the Quartus II software. Altera Corporation September 2008 2-3 Preliminary HardCopy Series Handbook, Volume 1 HardCopy II and Stratix II Similarities and Differences HardCopy II devices preserve the functionality of Stratix II FPGAs. Implementation of these architectural features in HardCopy II structured ASICs matches Stratix II FPGA implementation, with a few exceptions. Table 2-2 shows a qualitative comparison of HardCopy II device feature implementation versus Stratix II FPGA feature implementation. Other sections within this chapter provide details on similarities and differences of a particular HardCopy II feature. Table 2-2. HardCopy II Device vs. Stratix II FPGA Feature Implementation Feature Logic blocks DSP blocks Memory Clock networks PLLs I/O features Configuration (1) Note to Table 2-2: (1) HardCopy II structured ASICs do not need to be configured upon power-up. Equivalent Different v v v v v v v The major similarities and differences between Stratix II FPGAs and HardCopy II devices are highlighted below: HardCopy II may result in a power reduction of up to 50% than an equivalent Stratix II FPGAs operating at the same frequency. Power consumption is design dependent and is a direct result of design performance and resource utilization. HardCopy II devices offer up to 100% performance improvement when compared to Stratix II FPGA prototypes. The performance improvement is achieved by efficient use of logic blocks, metal interconnect optimization, die size reduction, and customized signal buffering. Logic blocks, known as HCells, are the basic building block of the core logic in HardCopy II devices and replace Stratix II adaptive logic modules (ALMs). HCells implement logic and DSP functions. DSP block functions are implemented using HCells, instead of dedicated DSP blocks. M4K and M-RAM memory blocks can implement various types of memory (the same as Stratix II FPGAs), with or without parity, including true dual-port, simple dual-port, and single-port RAM, ROM, and first-in first-out (FIFO) buffers. 2-4 Preliminary Altera Corporation September 2008 HardCopy II and Stratix II Similarities and Differences Unlike Stratix II FPGAs, the HardCopy II M4K block contents cannot be pre-loaded with a Memory Initialization File (.mif) when used as RAM. When used as ROM, HardCopy II M4K blocks are initialized to the ROM contents. When used as RAM, and you select the non-registered output mode, HardCopy II M4K and M-RAM blocks power up with outputs unknown. In Stratix II FPGAs, M4K blocks power up with outputs cleared, while M-RAM blocks power up with outputs unknown. If registered outputs mode is selected, the outputs are cleared on both the M4K and M-RAM blocks in HardCopy II. The memory contents are unknown under both instances. All HardCopy II clock network features are the same as in Stratix II FPGAs. Enhanced PLL and fast PLL implementations in HardCopy II devices are the same as in Stratix II FPGAs. All Stratix II I/O features and supported I/O standards are offered in HardCopy II devices. The Joint Test Action Group (JTAG) boundary scan order and length in HardCopy II devices is different than that of the Stratix II FPGA. Use a HardCopy II boundary-scan description language (BSDL) file that describes the re-ordered and shortened boundary scan chain. Unlike Stratix II devices, HardCopy II devices are customized using two metal layers. Therefore, configuration circuitry is not required. FPGA configuration emulation and other configuration modes, including remote system upgrades and design security using configuration bitstream encryption, are not supported in HardCopy II devices. Even though configuration is not required, the CRC_ERROR pin function is supported by the HardCopy II using Quartus II software version 6.0 and above. There is no need to recompile the Stratix II design to eliminate this feature. Only supplementary information to highlight HardCopy II similarities and differences compared to the Stratix II FPGA architecture and functionality is provided in this chapter. For more information on similarities and differences of available resources of the HardCopy II, refer to the Migrating Stratix II Device Resources to HardCopy II Devices chapter of this Handbook. In addition, the Stratix II Device Handbook has detailed explanations of architectural features and functions that are similar to the HardCopy II devices. 1 Altera Corporation September 2008 2-5 Preliminary HardCopy Series Handbook, Volume 1 HCells HardCopy II devices are built using an array of fine-grained architecture blocks called HCells. HCells are a collection of logic transistors based on 1.2 V, 90 nm process technology, similar to Stratix II devices. The construction of logic using HCells allows flexible functionality such that when HCells are combined, all viable logic combinations of Stratix II functionality are replicated. These HCells constitute the array of HCells area in Figure 2-1. Only HCells needed to implement the customer design are assembled together, which optimizes HCell utilization. The unused area of the HCell logic fabric is powered down, resulting in significant power savings compared with the Stratix II FPGA prototype. The Quartus II software uses the library of pre-characterized HCell macros to place Stratix II ALM and DSP configurations into the HardCopy II HCell-based logic fabric. An HCell macro defines how a group of HCells are connected together within the array. HCell macros can construct all combinations of combinational logic, adder, and register functions that can be implemented by a Stratix II ALM. HCells not used for ALM configurations can be used to implement DSP block functions. Based on design requirements, the Quartus II software will chose the appropriate HCell macros to implement the design functionality. For example, Stratix II ALMs offer flexible look-up table (LUT) blocks, registers, arithmetic blocks, and LAB-wide control signals. In HardCopy II devices, if your design requires these architectural elements, the Quartus II synthesis tool will map the design to the appropriate HCells, resulting in improved design performance compared to the Stratix II FPGA prototype. Stratix II FPGAs have dedicated DSP blocks to implement various DSP functions. Stratix II DSP blocks consist of a multiplier block, an adder/subtractor/accumulator block, a summation block, input and output interfaces, and input and output registers. In HardCopy II devices, HCell macros implement Stratix II DSP block functionality with area efficiency and performance on par with the dedicated DSP blocks in Stratix II FPGAs. There are eight HCell macros which implement the eight supported modes of operation for the Stratix II DSP block: 9 x 9 multiplier 9 x 9 two-multiplier adder (9 x 9 complex multiply) 9 x 9 four-multiplier adder 18 x 18 multiplier 18 x 18 two-multiplier adder (18 x 18 complex multiply) 18 x 18 four-multiplier adder 52-bit (18 x 18) multiplier-accumulator 36 x 36 multiplier 2-6 Preliminary Altera Corporation September 2008 HCells Only HCells that are required to implement the design's DSP functions are enabled. HCells not needed for DSP functions can be used for ALM configurations, which results in efficient logic usage. In addition to area management, the placement of these HCell macros allows for optimized routing and performance. An example of efficient logic area usage can be seen when comparing the 18 x 18 multiplier implementation in Stratix II FPGAs using the dedicated DSP block versus the implementation in HardCopy II devices using HCells. If the Stratix II DSP function only calls for one 18 x 18 multiplier, the other three 18 x 18 multipliers and the DSP block's adder output block are not used (Figure 2-2). In HardCopy II devices, the HCell-based logic fabric that is not used for DSP functions can be used to implement other combinational logic, adder, and register functions. Figure 2-2. Stratix II DSP Block versus HardCopy II HCell 18 x 18-Bit Multiplier Implementation Stratix II DSP Block Input Registers Output Registers HardCopy II HCell-Based Logic Fabric Input Registers Output Registers 18 x 18 Multiplier 18 x 18 Multiplier 18 x 18 Multiplier These elements are implemented using HCell macros. Adder/ Subtractor/ Accumulator Block Input Registers 18 x 18 Multiplier Output Registers 18 x 18 Multiplier Unused logic area can be used to perform other logic functions. Used portions of the block Unused portions of the block HardCopy II devices support all Stratix II DSP configurations (9 x 9, 18 x 18, and 36 x 36 multipliers) and all Stratix II DSP block features, such as dynamic sign controls, dynamic addition/subtraction, saturation, rounding, and dynamic input shift registers, except for dynamic mode switching. Altera Corporation September 2008 2-7 Preliminary HardCopy Series Handbook, Volume 1 Dynamic mode switching allows the designer to set up each Stratix II DSP block to dynamically switch between the following three modes: Up to four 18-bit independent multipliers Up to two 8-bit multiplier-accumulators One 36-bit multiplier Each half of a Stratix II DSP block has separate mode control signals. Since DSP block functions are implemented in HardCopy II devices using HCells, HardCopy II devices do not support dynamic mode switching. If this feature is used, the Quartus II software flags the DSP implementation and does not allow you to migrate the design. The fitter reports that all HardCopy II devices are not compatible with the design. To migrate your Stratix II design to a HardCopy II companion device, disable dynamic switching in the DSP blocks. f For more information on the Stratix II DSP operational modes, refer to the Stratix II Device Handbook. HardCopy II memory blocks can implement various types of memory with or without parity, including true dual-port, simple dual-port, and single-port RAM, ROM, and FIFO buffers. HardCopy II devices support the same memory functions and features as Stratix II FPGAs. Functionally, the memory in both devices are identical. However, the number of available memory blocks differs based on density (Table 2-3). Embedded Memory Table 2-3. HardCopy II Embedded Memory Resources Feature M4K RAM blocks (4 Kbits) M-RAM blocks (512 Kbits) Total RAM bits (bits) HC210W 190 0 875,520 HC210 190 0 875,520 HC220 408 2 3,059,712 HC230 614 6 6,368,256 HC240 768 9 8,847,360 Since device functionality is fixed in HardCopy II devices, M4K block contents cannot be preloaded or initialized with a MIF when they are configured as RAM. When the M4K blocks are used as ROM, they will initialize to the design's ROM contents. When using the non-registered outputs mode for the HardCopy II M4K memory block, the outputs power up uninitialized. When using the registered outputs mode for the HardCopy II M4K memory blocks, the 2-8 Preliminary Altera Corporation September 2008 PLLs and Clock Networks outputs are cleared on power up. The designer needs to take these into consideration when designing logic that might evaluate the initial power-up values of the memory block. HardCopy II embedded memory consists of M4K and M-RAM memory blocks and have a one-to-one mapping from Stratix II M4K and M-RAM resources. Table 2-4 shows the size and features of the different RAM blocks. f For more information on the Stratix II memory block features, refer to the Stratix II Device Handbook. Both HardCopy II enhanced and fast PLLs are feature rich, supporting advanced capabilities such as clock switchover, reconfigurable phase shift, PLL reconfiguration, and reconfigurable bandwidth. PLLs are used for general-purpose clock management, supporting multiplication, division, phase shifting, and programmable duty cycle. In addition, enhanced PLLs support external clock feedback mode, spread-spectrum clocking, and counter cascading. Fast PLLs offer high speed outputs to manage the high-speed differential I/O interfaces. 1 All Stratix II PLL features are supported by HardCopy II PLLs. PLLs and Clock Networks Similar to Stratix II FPGAs, HardCopy II devices also support a power-down mode where unused clock networks can be disabled. HardCopy II and Stratix II clock control blocks support dynamic selection of the input clock from up to four possible sources, giving the designer the flexibility to choose from multiple (up to four) clock sources. Altera Corporation September 2008 2-9 Preliminary HardCopy Series Handbook, Volume 1 Table 2-4. HardCopy II Embedded Memory Features Feature Maximum performance (1), (4) Total RAM bits (including parity bits) Configurations (Part 1 of 2) Notes (1), (2), (3) M-RAM Blocks 350 MHz 589,824 64K x 8 64K x 9 32K x 16 32K x 18 16K x 32 16K x 36 8K x 64 8K x 72 4K x 128 4K x 144 M4K Blocks 350 MHz 4,608 4K x 1 2K x 2 1K x 4 512 x 8 512 x 9 256 x 16 256 x 18 128 x 32 128 x 36 Parity bits Byte enable Pack mode Address clock enable Single-port memory Simple dual-port memory True dual-port memory Embedded shift register ROM FIFO buffer Simple dual-port mixed width support True dual-port mixed width support Memory initialization file (.mif) Mixed-clock mode Power-up condition (2) Register clears (3) Same-port read-during-write Mixed-port read-during-write v v v v v v v v v v v v Not supported, except in ROM mode v v v v v v v v v v Not supported v Outputs unknown Output registers only v Outputs unknown Output registers only New data available at positive clock New data available at positive clock edge edge Outputs set to unknown or old data Unknown output 2-10 Preliminary Altera Corporation September 2008 PLLs and Clock Networks Table 2-4. HardCopy II Embedded Memory Features Feature Note to Table 2-4: (1) (2) (3) (4) (Part 2 of 2) Notes (1), (2), (3) M-RAM Blocks M4K Blocks Maximum performance information is preliminary until device characterization. The memory cells power up randomly, so reads before writes are not valid. Make sure you write to the memory location before you read it. Even though the output register is cleared, the memory cells power up randomly. So reads before write are not valid. Make sure you write to the memory location first before reading it. Violating the setup or hold time requirements on the address registers could corrupt the memory contents. This applies to both read and write operations. Enhanced and Fast PLLs The number of PLLs available differs based on density (Table 2-5). Table 2-5. HardCopy II PLLs Feature Enhanced PLLs Fast PLLs HC210W 2 2 HC210 2 2 HC220 2 2 HC230 4 4 HC240 4 8 The target HardCopy II device may not support the same number of enhanced PLLs as the prototyping Stratix II FPGA. However, since HardCopy II enhanced PLLs and fast PLLs offer a similar feature set (Table 2-7 on page 2-13), a fast PLL could be used in place of an enhanced PLL. The type of PLL used in the design should be chosen using the Quartus II software to accommodate the resources available in the HardCopy II device. Table 2-6 shows which PLLs are available in each device density. Figure 2-3 shows the location of each PLL. During the prototyping stage using the FPGA, you must select the appropriate number of enhanced and fast PLLs that will be used in your HardCopy II device. Use Table 2-6 to ensure that the FPGA prototyping design uses the same PLL resources available in the HardCopy II device. Table 2-6. HardCopy II PLLs Available Device 1 HC210W HC210 (Part 1 of 2) Note (1) Enhanced PLLs 8 9 10 5 v v 6 v v 11 12 Fast PLLs 2 v v 3 4 7 v v Altera Corporation September 2008 2-11 Preliminary HardCopy Series Handbook, Volume 1 Table 2-6. HardCopy II PLLs Available Device 1 HC220 HC230 HC240 (Part 2 of 2) Note (1) Enhanced PLLs 8 9 10 5 v 6 v v v v v v v 11 12 Fast PLLs 2 v v v v v v v v v v v 3 4 7 v v v v v Note to Table 2-6: (1) PLL performance in the HC210W device may differ from the Stratix II FPGA prototype. Figure 2-3. HardCopy II PLL Locations Notes (1), (2) CLK[3..0] 1 2 PLLs FPLL8CLK 8 12 6 CLK[7..4] Notes to Figure 2-3: (1) (2) The PLLs may be located in the periphery or in the core of the device. This is the die-level top view of the device and is only a graphical representation of the PLL locations. 2-12 Preliminary Altera Corporation September 2008 PLLs and Clock Networks PLL functionality in HardCopy II devices remains the same as in Stratix II FPGA PLLs. Therefore, the HardCopy II PLLs support PLL reconfiguration (the PLL can be dynamically configured in user mode). HardCopy II enhanced and fast PLLs support a one-to-one mapping from Stratix II PLL resources. Table 2-7 shows the features of the different PLLs. For more information on the Stratix II PLL features, refer to the Stratix II Device Handbook. Table 2-7. HardCopy II PLL Features Feature Clock multiplication and division Phase shift Clock switchover PLL reconfiguration Reconfigurable bandwidth Spread-spectrum clocking Programmable duty cycle Number of clock outputs per PLL (5) Enhanced PLL m/(n x post-scale counter) (1) Down to 125-ps increments (3) v v v v v 6 Fast PLL m/(n x post-scale counter) (2) Down to 125-ps increments (3) v (4) v v v 4 (6) Number of dedicated external clock outputs Three differential or six singledper PLL ended Number of feedback clock inputs per PLL Notes to Table 2-7: (1) (2) (3) 1 (7) (4) (5) (6) (7) For enhanced PLLs, m and n range from 1 to 512 and post-scale counters range from 1 to 512 with 50% duty cycle. For non-50% duty-cycle clock outputs, post-scale counters range from 1 to 256. For fast PLLs, n can range from 1 to 4. The post-scale and m counters range from 1 to 32. For non-50% duty-cycle clock outputs, post-scale counters range from 1 to 16. The smallest phase shift is determined by the voltage controlled oscillator (VCO) period divided by eight. The supported phase shift range is from 125 to 250 ps. HardCopy II devices can shift all output frequencies in increments of at least 45. Smaller degree increments are possible depending on the frequency and divide parameters. For non-50% duty cycle clock outputs post-scale counters range from 1 to 256. HardCopy II fast PLLs only support manual clock switchover. The clock outputs can be driven to internal clock networks or to a pin. The PLL clock outputs of the fast PLLs can drive to any I/O pin to be used as an external clock output. For high-speed differential I/O pins, the device uses a data channel to generate the transmitter output clock (txclkout). If the design uses external feedback input pins, you will lose one (or two, if fBIN is differential) dedicated external clock output pin. Altera Corporation September 2008 2-13 Preliminary HardCopy Series Handbook, Volume 1 Clock Networks There are 16 clock pins (CLK[15..0]) in HardCopy II devices that can drive either the global- or regional-clock networks. The CLK pins can drive clock ports or data inputs. HardCopy II devices provide 16 dedicated global-clock networks and 32 regional-clock networks; the same as in Stratix II FPGAs. These clocks are organized to provide 24 unique clock sources per device quadrant with low skew and delay. This clocking scheme provides up to 48 unique clock domains within the entire HardCopy II device. Table 2-8 lists the clock resources and features available in HardCopy II devices. Table 2-8. Clock Network Resources and Features Available in HardCopy II Devices Resources and Features Number of global clock networks Number of regional clock networks Global clock input sources Regional clock input sources Number of unique clock sources in a quadrant Number of unique clock sources in the entire device Power-down mode Clocking regions for high fan-out applications 16 32 Clock input pins, PLL outputs, logic array Clock input pins, PLL outputs, logic array 24 (16 global clocks and 8 regional clocks) 48 (16 global clocks and 32 regional clocks) Global- and regional-clock networks, dual-regional-clock region Quadrant region, dual-regional, entire device via globalor regional-clock networks Availability HardCopy II devices also support the same features as the Stratix II clock control block, which is available for each global- and regional-clock network. The control block has two functions: Clock source selection (dynamic selection for global clocks): You user can either dynamically select between two PLL outputs, between two clock pins (CLKp or CLKn), or a combination of the clock pins or PLL outputs. Clock power-down (dynamic clock enable or disable): In HardCopy II devices, you can dynamically turn the clock off or on in user-mode. I/O Structure and Features The structure and features of the HardCopy II IOE remains the same as in Stratix II. Any feature implemented in Stratix II IOEs can be migrated to Hardcopy II IOEs. 2-14 Preliminary Altera Corporation September 2008 I/O Structure and Features The IOE feature set in HardCopy II devices can be classified in one of three categories: General purpose IOEs--The most commonly used I/O type in designs. Memory Interface IOEs--Includes features to interface with common external memory standards. High-speed IOEs--Supports high-speed data transmission and reception. All I/O pins in Stratix II FPGAs support general-purpose I/O standards, which includes the LVTTL and LVCMOS I/O standards. In Stratix II FPGAs, the PCI clamping diode and memory interfaces are supported on the top and bottom I/O pins, while high-speed interfaces are supported on the left and right side I/O pins of the device. The new general purpose IOEs in HardCopy II devices are a cost saving and area efficient advantage. The complex memory interface and the high-speed IOE circuitry is removed to save die area while still offering the more commonly-used features. The memory interface IOE supports all the features available in the general purpose IOE. The high-speed IOE also supports all the same features and I/O standards as the general purpose IOE, except for the PCI clamping diode (supported on the bottom general purpose IOEs in HC210 and HC220 devices). In order to increase the I/O area efficiency of HardCopy II devices, the features available on any given IOE depends on the location. Table 2-9 shows which I/O standards are supported by the different IOE types. Table 2-9. HardCopy II Supported I/O Standards (Part 1 of 3) VCCIO Level (V) I/O Standard 3.3-V LVTTL/ LVCMOS 2.5-V LVTTL/ LVCMOS 1.8-V LVTTL/ LVCMOS 1.5-V LVCMOS SSTL-2 class I Type Input Single-ended Single-ended Single-ended Single-ended Voltage referenced 3.3/2.5 3.3/2.5 1.8/1.5 1.8/1.5 2.5 Output 3.3 2.5 1.8 1.5 2.5 Memory Interface IOEs v v v v v General Purpose IOEs v v v v High-Speed IOEs v v v v Altera Corporation September 2008 2-15 Preliminary HardCopy Series Handbook, Volume 1 Table 2-9. HardCopy II Supported I/O Standards (Part 2 of 3) VCCIO Level (V) I/O Standard SSTL-2 class II SSTL-18 class I SSTL-18 class II 1.8-V HSTL class I 1.8-V HSTL class II 1.5-V HSTL Class I 1.5-V HSTL Class II PCI/PCI-X Differential SSTL-2 class I and II input Differential SSTL-2 class I and II output Differential SSTL-18 class I and II input Differential SSTL-18 class I and II output 1.8-V differential HSTL class I and II input 1.8-V differential HSTL class I and II output 1.5-V differential HSTL class I and II input 1.5-V differential HSTL class I and II output LVDS HyperTransportTM technology Type Input Voltage referenced Voltage referenced Voltage referenced Voltage referenced Voltage referenced Voltage referenced Voltage referenced Single-ended Pseudo differential (1) Pseudo differential (1) Pseudo differential (1) Pseudo differential (1) Pseudo differential (1) Pseudo Differential (1) Pseudo differential (1) Pseudo Differential (1) Differential Differential 2.5 2.5 3.3/2.5/ 1.8/1.5 1.5 3.3/2.5/ 1.8/1.5 1.8 3.3/2.5/ 1.8/1.5 1.8 2.5 1.8 1.8 1.8 1.8 1.5 1.5 3.3 3.3/2.5/ 1.8/1.5 2.5 Output 2.5 1.8 1.8 1.8 1.8 1.5 1.5 3.3 Memory Interface IOEs v v v v v v v v (2) (3) (3) (3) (3) (3) General Purpose IOEs High-Speed IOEs v (2) (3) (3) (3) 2.5 2.5 (5) (5) (4), (6) (4), (6) v v 2-16 Preliminary Altera Corporation September 2008 I/O Structure and Features Table 2-9. HardCopy II Supported I/O Standards (Part 3 of 3) VCCIO Level (V) I/O Standard LVPECL Notes to Table 2-9: (1) Pseudo-differential HSTL and SSTL inputs only use the positive-polarity input in the speed path. The negative input is not connected internally. Pseudo-differential HSTL and SSTL outputs use two single-ended outputs with the second output programmed as inverted. This is similar to a Stratix II device implementation. The PCI clamping diode is only supported on the I/O pins on the top and bottom sides of the device. This I/O standard is only supported on the DQS, CLK and PLL_FB input pins or on the PLL_OUT output pins. This I/O standard is only supported on the bottom CLK and PLL_FB input pins or on the bottom PLL_OUT output pins. This I/O standard is only supported on the CLK and PLL_FB input pins or on the PLL_OUT output pins. Also supported on CLK9 and CLK11 pins. This I/O standard is only supported on CLK and PLL_FB input pins. LVPECL input I/O standard is supported on the top and bottom CLK and PLL_FB input pins. LVPECL output I/O standard is supported on the top and bottom PLL_OUT output pins. LVPECL support is similar to Stratix II devices. Type Input Differential 3.3/2.5/ 1.8/1.5 Output (8) Memory Interface IOEs (8) General Purpose IOEs (8) High-Speed IOEs (2) (3) (4) (5) (6) (7) (8) The three types of IOEs are located in different areas of the device and are described in the following sections. HardCopy II devices have eight I/O banks, just as in Stratix II FPGAs. Figures 2-4 through 2-6 show which I/O type each bank supports. Altera Corporation September 2008 2-17 Preliminary HardCopy Series Handbook, Volume 1 Figure 2-4. I/O Type Support in HC210 and HC220 Devices Bank 3 Memory Interface IOEs Bank 9 PLL 5 Notes (1), (2) Bank 4 Memory Interface IOEs I/O banks 3 & 4 support 3.3-V, 2.5-V, 1.8-V LVTTL/ LVCMOS, 1.5-V LVCMOS, SSTL-2, SSTL-18, 1.8-V HSTL, 1.5-V HSTL & PCI/PCI-X I/O standards. Bank 2 High-Speed IOEs CLK, PLL_FB input pins & PLL_OUT output pins support differential SSTL, differential HSTL, LVDS & HyperTransport technology. CLK & PLL_FB pins support LVPECL. DQS input pins support differential SSTL and differential HSTL I/O standards. Bank 5 General-Purpose IOEs PLL 1 PLL 2 I/O Banks 1 & 2 Support 3.3-, 2.5- & 1.8-V LVTTL/LVCMOS, 1.5-V LVCMOS, LVDS & HyperTransport Technology I/O Banks 5 & 6 Support 3.3-, 2.5- & 1.8-V LVTTL/LVCMOS &1.5-V LVCMOS Bank 1 High-Speed IOEs I/O banks 7 & 8 support 3.3-V, 2.5-V, 1.8-V LVTTL/ LVCMOS, 1.5-V LVCMOS & PCI/PCI-X I/O standards. CLK, PLL_FB input pins & PLL_OUT output pins support differential SSTL, differential HSTL, LVDS & HyperTransport technology. CLK & PLL_FB pins support LVPECL. Bank 6 General-Purpose IOEs Bank 8 General Purpose IOEs PLL 6 Bank 10 Bank 7 General Purpose IOEs 2-18 Preliminary Altera Corporation September 2008 I/O Structure and Features Figure 2-5. I/O Type Support in HC230 Devices PLL 7 Bank 3 Memory Interface IOEs Notes (1), (2) Bank 11 Bank 9 PLL 11 PLL 5 Bank 4 Memory Interface IOEs I/O banks 3 & 4 support 3.3-V, 2.5-V, 1.8-V LVTTL/ LVCMOS, 1.5-V LVCMOS, SSTL-2, SSTL-18, 1.8-V HSTL, 1.5-V HSTL & PCI/PCI-X I/O standards. Bank 2 High-Speed IOEs CLK, PLL_FB input pins & PLL_OUT output pins support differential SSTL, differential HSTL, LVDS & HyperTransport technology. CLK & PLL_FB pins support LVPECL. DQS input pins support differential SSTL and differential HSTL I/O standards. Bank 5 General-Purpose IOEs PLL 1 PLL 2 I/O Banks 1 & 2 Support 3.3-, 2.5- & 1.8-V LVTTL/LVCMOS, 1.5-V LVCMOS, LVDS & HyperTransport Technology I/O Banks 5 & 6 Support 3.3-, 2.5- & 1.8-V LVTTL/LVCMOS &1.5-V LVCMOS Bank 1 High-Speed IOEs I/O banks 7 & 8 support 3.3-V, 2.5-V, 1.8-V LVTTL/ LVCMOS, 1.5-V LVCMOS & PCI/PCI-X I/O standards. CLK, PLL_FB input pins, SSTL-2, SSTL-18, 1.8-V HSTL, 1.5-V HST, & PLL_OUT output pins support differential SSTL, differential HSTL, LVDS & HyperTransport technology. CLK & PLL_FB pins support LVPECL. DQS input pins support differential SSTL and differential HSTL I/O standards. Bank 6 General-Purpose IOEs PLL 8 Bank 8 Memory Interface IOEs PLL 12 PLL 6 Bank 12 Bank 10 Bank 7 Memory Interface IOEs Altera Corporation September 2008 2-19 Preliminary HardCopy Series Handbook, Volume 1 Figure 2-6. I/O Type Support in HC240 Devices PLL 7 Bank 3 Memory Interface IOEs Notes (1), (2) Bank 11 Bank 9 PLL 11 PLL 5 Bank 4 Memory Interface IOEs PLL 10 I/O banks 3 & 4 support 3.3-V, 2.5-V, 1.8-V LVTTL/ LVCMOS, 1.5-V LVCMOS, SSTL-2, SSTL-18, 1.8-V HSTL, 1.5-V HSTL & PCI/PCI-X I/O standards. Bank 2 High-Speed IOEs CLK, PLL_FB input pins & PLL_OUT output pins support differential SSTL, differential HSTL, LVDS & HyperTransport technology. CLK & PLL_FB pins support LVPECL. DQS input pins support differential SSTL and differential HSTL I/O standards. Bank 5 High-Speed IOEs PLL 1 PLL 2 I/O Banks 1 & 2 Support 3.3-, 2.5- & 1.8-V LVTTL/LVCMOS, 1.5-V LVCMOS, LVDS & HyperTransport Technology I/O Banks 5 & 6 Support 3.3-, 2.5- & 1.8-V LVTTL/LVCMOS, 1.5-V LVCMOS, LVDS & HyperTransport Technology PLL 4 PLL 3 Bank 1 High-Speed IOEs I/O banks 7 & 8 support 3.3-V, 2.5-V, 1.8-V LVTTL/ LVCMOS, 1.5-V LVCMOS & PCI/PCI-X I/O standards. CLK, PLL_FB input pins SSTL-2, SSTL-18, 1.8-V HSTL, 1.5-V HST, & PLL_OUT output pins support differential SSTL, differential HSTL, LVDS & HyperTransport technology. CLK & PLL_FB pins support LVPECL. DQS input pins support differential SSTL and differential HSTL I/O standards. Bank 6 High-Speed IOEs PLL 8 Bank 8 Memory Interface IOEs PLL 12 PLL 6 Bank 12 Bank 10 Bank 7 Memory Interface IOEs PLL 9 Notes to Figures 2-4 through 2-6: (1) In addition to supporting external memory interfaces, memory interface IOEs have the same features as general purpose IOEs. In addition to supporting high-speed I/O interfaces, high-speed IOEs have the same features as general purpose IOEs, except for the PCI clamping diode and LVPECL clock input support. This is a top view of the silicon die which corresponds to a reverse view for flip-chip packages. It is a graphical representation only. (2) 1 When planning I/O placement for designs targeting HardCopy II devices, care should be taken to ensure the same I/O standards are supported in the same HardCopy II I/O banks as in the Stratix II I/O banks. General Purpose IOE The general purpose IOEs in HC210 and HC220 devices are located on the right side and at the bottom of the device. The general purpose IOEs in HC230 devices are located on the right side of the device. (Directions are based on a top view of the silicon die.) HC240 devices do not have general purpose IOEs. The general purpose IOE functionality is supported in the memory interface IOEs for these devices. The high-speed IOEs also 2-20 Preliminary Altera Corporation September 2008 I/O Structure and Features provide the same features as the general purpose IOEs except for the PCI clamping diode. In Stratix II FPGAs, all IOEs support the general purpose IOE features except the PCI diode, which is only supported on the top and bottom I/O pins. The general purpose IOE has many features, including: Dedicated single-ended I/O buffers 3.3-V, 64-bit, 66 MHz PCI compliance 3.3-V, 64-bit, 133 MHz PCI-X 1.0 compliance JTAG boundary-scan test (BST) support On-chip driver series termination (non-calibrated) Output drive strength control Tri-state buffers Bus-hold circuitry Programmable pull-up resistors Open-drain outputs PCI clamping diode (supported on the bottom I/O pins only) Double data rate (DDR) registers General purpose IOEs support the following I/O standards: 3.3-V LVTTL/LVCMOS 2.5-V LVTTL/LVCMOS 1.8-V LVTTL/LVCMOS 1.5-V LVCMOS 3.3-V PCI 3.3-V PCI-X mode 1 The general purpose CLK and PLL_FB input pins and the PLL_OUT output pins support the following I/O standards: LVDS HyperTransport technology LVPECL (on input clocks and PLL_OUT only) The programmable drive strengths available vary depending on the I/O standard being used and are listed in Table 2-10. Table 2-10. Programmable Drive Strength Support for General-Purpose IOEs (Part 1 of 2) I/O Standard 3.3-V LVTTL 3.3-V LVCMOS 2.5-V LVTTL/LVCMOS Programmable Drive Strength Options (mA) 4, 8, 12 4, 8 4, 8, 12 Altera Corporation September 2008 2-21 Preliminary HardCopy Series Handbook, Volume 1 Table 2-10. Programmable Drive Strength Support for General-Purpose IOEs (Part 2 of 2) I/O Standard 1.8 V LVTTL/LVCMOS 1.5 V LVCMOS Programmable Drive Strength Options (mA) 2, 4, 6, 8 2, 4 General purpose IOEs support non-calibrated on-chip series termination. 50- and 25- on-chip series termination is available for 3.3-V or 2.5-V I/O standards. 50- on-chip series termination is available for 1.8- and 1.5-V I/O standards (pending characterization). Memory Interface IOE Memory interface IOEs in HC210 and HC220 devices are located on the top of the device. Memory interface IOEs in HC230 and HC240 devices are located on the top and the bottom of the device. In Stratix II FPGAs, the top and bottom IOEs support the memory interface IOE features. The memory interface IOE has many features, including: Dedicated single-ended I/O buffers 3.3-V, 64-bit, 66 MHz PCI compliance 3.3-V, 64-bit, 133 MHz PCI-X 1.0 compliance JTAG BST support On-chip driver series termination VREF pins Output drive strength control Tri-state buffers Bus-hold circuitry Programmable pull-up resistors Open-drain outputs PCI clamping diode DQ and DQS I/O pins Double data rate (DDR) registers The following I/O standards are supported when using the memory interface IOEs and can be used to interface to external memory, including DDR and DDR2 SDRAM, and QDRII, RLDRAM II, and SDR SRAM: 3.3-V LVTTL/LVCMOS 2.5-V LVTTL/LVCMOS 1.8-V LVTTL/LVCMOS 1.5-V LVCMOS 3.3-V PCI 3.3-V PCI-X mode 1 2-22 Preliminary Altera Corporation September 2008 I/O Structure and Features SSTL-2 class I and II SSTL-18 class I and II 1.8-V HSTL class I and II 1.5-V HSTL class I and II The memory interface DQS, CLK, and PLL_FB input pins and the PLL_OUT output pins support the following I/O standards: LVTTL/LVCMOS SSTL-2 class I and II SSTL-18 class I and II 1.8-V HSTL class I and II 1.5-V HSTL class I and II Differential SSTL-2 class I and II Differential SSTL-18 class I and II 1.8-V differential HSTL class I and II 1.5-V differential HSTL class I and II LVDS (not supported on DQS pins) HyperTransport technology (not supported on DQS pins) LVPECL on input clocks and PLL_OUT only (not supported on DQS pins) Pseudo-differential HSTL and SSTL inputs are supported on clock and DQS pins, while outputs are supported on dedicated PLL_OUT and DQS pins. Pseudo-differential HSTL and SSTL I/O standards use two single-ended outputs with the second output programmed as inverted. Pseudo-differential HSTL and SSTL inputs treat differential inputs as two single-ended HSTL and SSTL inputs and only decode one of them. This I/O support is the same as in Stratix II FPGAs. The functionality of all DQS circuitry in HardCopy II devices is the same as in Stratix II FPGAs. Table 2-11 shows the number of DQS/DQ groups supported in each HardCopy II device density and package. Table 2-11. DQS and DQ Bus Mode Support (Part 1 of 2) Device HC210W HC210 HC220 Package 484-pin FineLine BGA (Wire Bond) 484-pin FineLine BGA 672-pin FineLine BGA 780-pin FineLine BGA Number of x4 Number of x8/x9 Number of Number of Groups Groups x16/x18 Groups x32/x36 Groups 4 4 9 9 36 2 2 4 4 18 0 0 2 2 8 0 0 0 0 4 HC230 1,020-pin FineLine BGA Altera Corporation September 2008 2-23 Preliminary HardCopy Series Handbook, Volume 1 Table 2-11. DQS and DQ Bus Mode Support (Part 2 of 2) Device HC240 Package 1,020-pin FineLine BGA 1,508-pin FineLine BGA Number of x4 Number of x8/x9 Number of Number of Groups Groups x16/x18 Groups x32/x36 Groups 36 36 18 18 8 8 4 4 The programmable drive strengths available vary depending on the I/O standard used. The options are listed in Table 2-12. Table 2-12. Programmable Drive Strength Support for Memory Interface IOEs I/O Standard 3.3-V LVTTL 3.3-V LVCMOS 2.5-V LVTTL/LVCMOS 1.8-V LVTTL/LVCMOS 1.5-V LVCMOS SSTL-2 class I SSTL-2 class II SSTL-18 class I SSTL-18 class II 1.8-V HSTL class I 1.8-V HSTL class II 1.5-V HSTL class I 1.5-V HSTL class II Programmable Drive Strength Options (mA) 4, 8, 12, 16, 20, 24 4, 8, 12, 16, 20, 24 4, 8, 12, 16 2, 4, 6, 8, 10, 12 2, 4, 6, 8 8, 12 16, 20, 24 4, 6, 8, 10, 12 8, 16, 18, 20 4, 6, 8, 10, 12 16, 18, 20 4, 6, 8, 10, 12 16, 18, 20 Memory interface IOEs support both non-calibrated and calibrated on-chip series termination. 50- and 25- on-chip series termination is available for 3.3-, 2.5-, or 1.8-V I/O standards. 50- on-chip series termination is available for 1.5- or 1.2-V I/O standards (pending characterization). 1 If on-chip series termination is enabled, programmable drive strength support is not available. 2-24 Preliminary Altera Corporation September 2008 I/O Structure and Features High-Speed IOE High-speed IOEs in HC210, HC220, and HC230 devices are located on the left side of the device. High-speed IOEs in HC240 devices are located on the left and right sides of the device. (Directions are based on a top view of the silicon die.) Unlike Stratix II left and right side I/O pins, HardCopy II left and right side I/O pins do not support SSTL or HSTL I/O standards or the PCI clamping diode. In Stratix II FPGAs, the right and left IOEs support the high-speed IOE features. The high-speed IOE has many features, including: Dedicated single-ended I/O buffers Differential I/O buffer JTAG BST support On-chip driver series termination (non-calibrated) On-chip termination for differential I/O standards Output drive strength control Tri-state buffers Bus-hold circuitry Programmable pull-up resistors Open-drain outputs Transmit serializer Receive deserializer Dynamic phase alignment (DPA) Double data rate (DDR) registers The following I/O standards are supported when using high-speed IOEs: 3.3-V LVTTL/LVCMOS 2.5-V LVTTL/LVCMOS 1.8-V LVTTL/LVCMOS 1.5-V LVCMOS LVDS HyperTransport technology Altera Corporation September 2008 2-25 Preliminary HardCopy Series Handbook, Volume 1 The SERDES and DPA circuitry and functionality is the same in HardCopy II devices as in Stratix II FPGAs. HardCopy II devices support differential I/O standards at rates up to 1 Gbps when using DPA, and at rates up to 840 Mbps when not using DPA. Table 2-13 provides the number of differential channels per HardCopy II device. Table 2-13. Number of Differential Channels in HardCopy II Devices HC210W Channel 484-Pin FineLine BGA (WireBond) 13 17 Notes (1), (2) HC230 HC240 1,020-Pin FineLine BGA 88 92 HC210 484-Pin FineLine BGA 19 21 HC220 672-Pin FineLine BGA 29 31 780-Pin FineLine BGA 29 31 1,020-Pin FineLine BGA 44 46 1,508-Pin FineLine BGA 116 116 Transmitter channels Receiver channels Notes to Table 2-13: (1) (2) The pin count does not include dedicated PLL input and output pins. The total number of receiver channels includes the non-dedicated clock channels that can optionally be used as data channels. HardCopy II high-speed IOEs, which are on the left and/or right sides of the device, support fewer programmable drive strengths than Stratix II side IOEs. The programmable drive strengths available vary depending on the I/O standard being used. The options are listed in Table 2-14. Table 2-14. Programmable Drive Strength Support for High-Speed IOEs I/O Standard 3.3-V LVTTL 3.3-V LVCMOS 2.5-V LVTTL/LVCMOS 1.8-V LVTTL/LVCMOS 1.5-V LVCMOS Programmable Drive Strength Options (mA) 4, 8, 12 4, 8 4, 8, 12 2, 4, 6, 8 2, 4 High-speed IOEs support non-calibrated on-chip series termination and differential termination on the receiver channels. 50- and 25- on-chip series termination is available for 3.3- or 2.5-V I/O standards. 50- on-chip series termination is available for 1.8- and 1.5-V I/O standards (pending characterization). 2-26 Preliminary Altera Corporation September 2008 Power-Up Modes Power-Up Modes The functionality of structured ASICs is determined before they are produced. Therefore, they do not require programmability. HardCopy II structured ASICs follow the same principle, enabling traditional ASIC-like power up. Although prototyping FPGAs require configuration upon power up, the HardCopy II structured ASICs do not need to be configured. HardCopy II devices do not support configuration and designers should take this into account in the prototyping-to-production development process. The HardCopy II device does not require a configuration device, but you must ensure that the nCE pin is low and that the nCONFIG and nSTATUS pins are high after power up. 1 HardCopy II devices do not support FPGA configuration emulation and other configuration modes, including remote system upgrades and design security using configuration bitstream encryption. HardCopy II devices support both instant on and instant on after 50 ms power-up modes. In the instant on power-up mode, the HardCopy II device is available for use shortly after the device powers up to a safe operating voltage. The on-chip power-on reset (POR) circuit will reset all registers. The nCE, nCONFIG, and nSTATUS signals must be at the appropriate logic levels for the CONF_DONE output to be tristated once the POR has elapsed. This option is similar to an ASIC's functionality upon power up and is the most likely scenario in production. In the instant on after 50 ms power-up mode, the HardCopy II device behaves similarly to the instant on mode, except that there is an additional delay of 50 ms, during which time the device will be held in reset. The CONF_DONE output is pulled low during this time, and then tri-stated after the 50 ms have elapsed. f For more information about which power-up modes HardCopy II devices support, refer to the Power-Up Modes and Configuration Emulation in HardCopy Series Devices chapter in the HardCopy Series Handbook. Altera Corporation September 2008 2-27 Preliminary HardCopy Series Handbook, Volume 1 Document Revision History Table 2-15 shows the revision history for this chapter. Table 2-15.Document Revision History Date and Document Version September 2008, v2.5 June 2007, v2.4 December 2006 v2.3 March 2006, v2.2 October 2005, v2.1 May 2005, v2.0 Changes Made Updated chapter number and metadata. Summary of Changes -- -- -- -- -- -- Added Note 4 to Table 2-4. Updated Table 2-1, Table 2-4, and Table 2-11. Added revision history. Updated Table 2-1, Table 2-9, Table 2-13. Updated Figure 2-5 and Figure 2-6. Updated graphics. Added Table 2-1. Updated HCell information for DSP functions in the Functional Description section. Updated Table 2-9. Updated Figures 2-4, 2-5, and 2-6. January 2005, v1.0 Added document to the HardCopy Series Handbook. -- 2-28 Preliminary Altera Corporation September 2008 3. Boundary-Scan Support H51017-2.4 IEEE Std. 1149.1 (JTAG) Boundary-Scan Support All HardCopy(R) II structured ASICs provide Joint Test Action Group (JTAG) boundary-scan test (BST) circuitry that complies with the IEEE Std. 1149.1-1990 specification. The BST architecture offers the capability to efficiently test components on printed circuit boards (PCBs) with tight lead spacing by testing pin connections, without using physical test probes, and capturing functional data while a device is in normal operation. Boundary-scan cells in a device can force signals onto pins, or capture data from pin or core logic signals. Forced test data is serially shifted into the boundary-scan cells. Captured data is serially shifted out and externally compared to expected results. A device using the JTAG interface uses four required pins, TDI, TDO, TMS, and TCK, and one optional pin, TRST. The TCK pin has an internal weak pull-down resistor, while the TDI, TMS, and TRST pins have weak internal pull-up resistors. The TDO output is powered by VCCIO. HardCopy II devices support the JTAG instructions shown in Table 3-1. Table 3-1. HardCopy II JTAG Instructions (Part 1 of 2) JTAG Instruction SAMPLE/PRELOAD Instruction Code 00 0000 0101 Description Allows a snapshot of signals at the device pins to be captured and examined during normal device operation, and permits an initial data pattern to be output at the device pins. Allows the external circuitry and board-level interconnects to be tested by forcing a test pattern at the output pins and capturing test results at the input pins. Places the 1-bit BYPASS register between the TDI and TDO pins, which allows the BST data to pass synchronously through selected devices to adjacent devices during normal device operation. EXTEST (1) 00 0000 1111 BYPASS 11 1111 1111 Altera Corporation September 2008 3-1 Preliminary HardCopy Series Handbook, Volume 1 Table 3-1. HardCopy II JTAG Instructions (Part 2 of 2) JTAG Instruction USERCODE Instruction Code 00 0000 0111 Description Selects the 32-bit USERCODE register and places it between the TDI and TDO pins, allowing the USERCODE to be serially shifted out of TDO. Selects the IDCODE register and places it between TDI and TDO, allowing the IDCODE to be serially shifted out of TDO. Places the 1-bit BYPASS register between the TDI and TDO pins, which allows the BST data to pass synchronously through selected devices to adjacent devices during normal device operation, while tri-stating all of the I/O pins. Places the 1-bit BYPASS register between the TDI and TDO pins, which allows the BST data to pass synchronously through selected devices to adjacent devices during normal device operation while holding I/O pins to a state defined by the data in the boundary-scan register. IDCODE 00 0000 0110 HIGHZ (1) 00 0000 1011 CLAMP (1) 00 0000 1010 Note to Table 3-1: (1) Bus hold and weak pull-up resistor features override the high-impedance state of HIGHZ, CLAMP, and EXTEST. f The BSDL files for HardCopy II devices are different from the corresponding Stratix(R) II FPGAs. For more information, or to receive BSDL files for IEEE Std. 1149.1- compliant Hardcopy II devices, visit the Altera website at www.altera.com. The HardCopy II device instruction register length is 10 bits and the USERCODE register length is 32 bits. The USERCODE registers are not reprogrammable and are mask-programmed. The designer can choose an appropriate 32 bit sequence which will be programmed into the USERCODE registers. 3-2 Preliminary Altera Corporation September 2008 IEEE Std. 1149.1 (JTAG) Boundary-Scan Support Tables 3-2 and 3-3 show the boundary-scan register length and device IDCODE information for HardCopy II devices. Table 3-2. HardCopy II Boundary-Scan Register Length Device HC210W HC210 HC220 HC230 HC240 Boundary-Scan Register Length 1050 1050 1530 2154 2910 Table 3-3. 32-Bit HardCopy II Device IDCODE IDCODE (32 Bits) (1) Device HC210W HC210 HC220 HC230 HC240 Notes to Table 3-3: (1) (2) The most significant bit (MSB) is on the left. The least significant bit (LSB) of IDCODE is always 1. Version (4 Bits) 0000 0000 0000 0000 0000 Part Number (16 Bits) 0010 0000 1100 0001 0010 0000 1100 0010 0010 0000 1100 0011 0010 0000 1100 0100 0010 0000 1100 0101 Manufacturer Identity (11 Bits) 000 0110 1110 000 0110 1110 000 0110 1110 000 0110 1110 000 0110 1110 LSB (1 Bit) (2) 1 1 1 1 1 Boundary-Scan Test (BST) on HardCopy II Devices In order to run the boundary-scan test on HardCopy II devices, you need two files: 1. The generic HardCopy II BSDL file you can download from the Altera website at www.altera.com. The PIN file for your design from the Quartus II software. 2. With these two files, you must run through a tool called the BSDLCustomizer. Altera Corporation September 2008 3-3 Preliminary HardCopy Series Handbook, Volume 1 BSDLCustomizer is a TCL script which is used to modify the BSDL file's port definitions and boundary-scan chain groups' attributes according to the design and pin assignments from the Quartus II software PIN file. Once you run the generic BSDL file and your PIN file through the BSDLCustomizer tool, a modified BSDL file is created which should be used for the boundary-scan test. Before running the boundary scan test on your board make sure that the nCONFIG pin is externally pulled low and that the nSTATUS pin is low. For more information on the BSDLCustomizer tool, refer to the BSDLCustomizer User Guide that you can download with the BSDLCustomizer tool from the Altera website at www.altera.com. Figure 3-1 shows the timing requirements for the JTAG signals. Figure 3-1. HardCopy II JTAG Waveforms TDI t JCP t JCH TCK tJPZX TDO t JPCO t JPXZ t JCL t JPSU t JPH Table 3-4 shows the JTAG timing parameters and values for HardCopy II devices. Table 3-4. HardCopy II JTAG Timing Parameters and Values (Part 1 of 2) Symbol tJ C P tJ C H tJ C L tJ P S U Parameter TCK clock period TCK clock high time TCK clock low time JTAG port setup time Min 30 13 13 3 Max Unit ns ns ns ns 3-4 Preliminary Altera Corporation September 2008 Document Revision History Table 3-4. HardCopy II JTAG Timing Parameters and Values (Part 2 of 2) Symbol tJ P H tJ P C O tJ P Z X tJ P X Z tJ S S U tJ S H Parameter JTAG port hold time JTAG port clock to output JTAG port high impedance to valid output JTAG port valid output to high impedance Capture register setup time Capture register hold time Min 5 Max Unit ns 11 14 14 4 5 ns ns ns ns ns f For more information on JTAG or boundary-scan testing, refer to AN 39: IEEE Std. 1149.1 (JTAG) Boundary-Scan Testing in Altera Devices. 1 Like Stratix II FPGAs, HardCopy II devices support the SignalTap(R) II embedded logic analyzer, which monitors design operation over a period of time through the JTAG interface. The SignalTap II logic analyzer is a useful feature during the FPGA prototyping phase, but should be removed if not needed once the design has been migrated to a HardCopy II device. HardCopy II is a mask programmed device, and the Signal Tap logic cannot be eliminated after the HardCopy II device is fabricated. Document Revision History Table 3-5 shows the revision history for this chapter. Table 3-5. Document Revision History (Part 1 of 2) Date and Document Version September 2008, v2.4 June 2007, v2.3 Changes Made Updated chapter number and metadata. Summary of Changes -- -- Added resource information Figure 3-1 changes New section on Boundary-Scan Test (BST) on HardCopy II devices. Minor updates for Quartus II 6.1.0 software version Added revision history December 2006 v2.2 October 2005, v2.1 Updated for Quartus II 6.1 software version. -- Updated graphics. Altera Corporation September 2008 3-5 Preliminary HardCopy Series Handbook, Volume 1 Table 3-5. Document Revision History (Part 2 of 2) Date and Document Version May 2005, v2.0 January 2005 v1.0 Updated Table 3-2. Added document to the HardCopy Series Handbook. Changes Made Summary of Changes -- -- 3-6 Preliminary Altera Corporation September 2008 4. DC and Switching Specifications and Operating Conditions H51018-3.3 Introduction This chapter provides preliminary information on absolute maximum ratings, recommended operating conditions, DC electrical characteristics, and other specifications for HardCopy(R) II devices. HardCopy II devices are offered in both commercial and industrial grades. All parameter limits are representative of worst-case supply voltage and junction temperature conditions. Unless otherwise noted, the parameter values in this chapter apply to all HardCopy II devices. Table 4-1 contains the absolute maximum ratings for the HardCopy II device family. Absolute Maximum Ratings Table 4-1. HardCopy II Device Absolute Maximum Ratings Symbol VCCINT VCCIO VCCPD VCCA VCCD VI IOUT TSTG TJ Notes (1), (2), (3) Minimum -0.5 -0.5 -0.5 -0.5 -0.5 -0.5 -25 -65 -55 Parameter Supply voltage Supply voltage Supply voltage Analog power supply for PLLs Digital power supply for PLLs DC input voltage(4) DC output current, per pin Storage temperature Junction temperature Conditions With respect to ground With respect to ground With respect to ground With respect to ground With respect to ground -- -- No bias Ball-grid array (BGA) packages under bias Maximum 1.8 4.6 4.6 1.8 1.8 4.6 40 150 125 Unit V V V V V V mA C C Notes to Table 4-1: (1) (2) (3) (4) Refer to the Operating Requirements for Altera Devices Data Sheet for more information. Conditions beyond those listed in Table 4-1 may cause permanent damage to a device. Additionally, device operation at the absolute maximum ratings for extended periods of time may have adverse effects on the device. Supply voltage specifications apply to voltage readings taken at the device pins, not at the power supply. During transitions, the inputs may overshoot to the voltage shown in Table 4-2 based upon the input duty cycle. The DC case is equivalent to a 100% duty cycle. During transitions, the inputs may undershoot to -2.0 V for input currents less than 100 mA and periods shorter than 20 ns. Altera Corporation September 2008 4-1 Preliminary HardCopy Series Handbook, Volume 1 Table 4-2. Maximum Duty Cycles in Voltage Transitions VIN (V) 4 4.1 4.2 4.3 4.4 4.5 Maximum Duty Cycles 100% 90% 50% 30% 17% 10% Recommended Operating Conditions Table 4-3 contains the HardCopy II device family's recommended operating conditions. Table 4-3. HardCopy II Device Recommended Operating Conditions Symbol VCCINT VCCIO Note (1) (Part 1 of 2) Minimum Maximum Unit 1.15 3.135 (3.0) 2.375 1.71 1.425 3.135 1.25 3.465 (3.6) 2.625 1.89 1.575 3.465 V V V V V V Parameter Supply voltage for internal logic and input buffers Supply voltage for output buffers, 3.3-V operation Supply voltage for output buffers, 2.5-V operation Supply voltage for output buffers, 1.8-V operation Supply voltage for output buffers, 1.5-V operation Conditions 100 s rise time 100 ms (2) 100 s rise time 100 ms (2), (6) 100 s rise time 100 ms (2) 100 s rise time 100 ms (2) 100 s rise time 100 ms (2) 100 s rise time 100 ms (3) VCCPD Supply voltage for pre-drivers as well as configuration and JTAG I/O buffers Analog power supply for PLLs Digital power supply for PLLs Input voltage Output voltage VCCA VCCD VI VO 100 s rise time 100 ms (3) 100 s rise time 100 ms (3) (4), (5) -- 1.15 1.15 -0.5 0 1.25 1.25 4.0 VCCIO V V V V 4-2 Altera Corporation September 2008 DC Electrical Characteristics Table 4-3. HardCopy II Device Recommended Operating Conditions Symbol TJ Note (1) (Part 2 of 2) Minimum Maximum Unit 0 -40 85 100 C C Parameter Operating junction temperature Conditions For commercial use For industrial use Notes to Table 4-3: (1) (2) (3) (4) Supply voltage specifications apply to voltage readings taken at the device pins, not at the power supply. Maximum VCC rise time is 100 ms, and VCC must rise monotonically. VCCPD must ramp-up from 0 V to 3.3 V within 100 s to 100 ms. If VCCPD is not ramped up within this specified time, the HardCopy II device will not power up successfully. During transitions, the inputs may overshoot to the voltage shown in Table 4-2 based upon the input duty cycle. The DC case is equivalent to a 100% duty cycle. During transitions, the inputs may undershoot to -2.0 V for input currents less than 100 mA and periods shorter than 20 ns. All pins, including dedicated inputs, clock, I/O, and JTAG pins, may be driven before VCCINT, VCCPD, and VCCIO are powered. VCCIO maximum and minimum conditions for PCI and PCI-X are shown in parentheses. (5) (6) DC Electrical Characteristics Table 4-4 shows the HardCopy II device family's DC electrical characteristics. Table 4-4. HardCopy II Device DC Operating Conditions Symbol II IOZ ICCINT0 Note (1) (Part 1 of 2) Minimum Typical Maximum -10 all -10 all -- 0.09 (3) 0.09 (3) 0.19 (3) 0.34 (3) 0.52 (3) 3 (3) 3 (3) 4 (3) 5 (3) 5 (3) 10 (5) (5) (5) (5) (5) (5) (5) (5) (5) (5) A A A A A A mA mA mA mA mA -- 10 Parameter Input pin leakage current Tri-stated I/O pin leakage current Conditions VI = VCCIO max to 0 V (2) VO = VCCIO max to 0 V (2) Device Unit A VCCINT supply current VI = ground, no (standby) load, no toggling inputs TJ = 25 C HC210W HC210 HC220 HC230 HC240 -- -- -- -- -- -- -- -- -- -- ICCPD0 VCCPD supply current (standby) VI = ground, no load, no toggling inputs TJ = 25 C VCCPD = 3.3 V HC210W HC210 HC220 HC230 HC240 Altera Corporation September 2008 4-3 HardCopy Series Handbook, Volume 1 Table 4-4. HardCopy II Device DC Operating Conditions Symbol ICCIO0 Note (1) (Part 2 of 2) Minimum Typical Maximum -- -- -- -- -- 10 15 30 40 50 -- 3 (3) 3 (3) 3 (3) 3 (3) 3 (3) 25 35 50 75 90 1 (5) (5) (5) (5) (5) 50 70 100 150 170 2 Parameter VCCIO supply current (standby) Conditions VI = ground, no load, no toggling inputs TJ = 25 C Device HC210W HC210 HC220 HC230 HC240 Unit mA mA mA mA mA k k k k k k RCONF(4) Value of I/O pin pull-up resistor before and during configuration VI = 0; VCCIO = 3.3 V VI = 0; VCCIO = 2.5 V VI = 0; VCCIO = 1.8 V VI = 0; VCCIO = 1.8 V VI = 0; VCCIO = 1.2 V -- -- -- -- -- -- -- -- -- Recommended value of I/O pin external pull-down resistor before and during configuration Notes to Table 4-4: (1) (2) (3) (4) (5) -- Typical values are for TA = 25 C, VCCINT = 1.2 V, and VCCIO = 1.5-, 1.8-, 2.5-, and 3.3-V. This value is specified for normal device operation. The value may vary during power-up. This applies for all VCCIO settings (3.3-, 2.5-, 1.8-, and 1.5-V). This specification is preliminary and pending further device characterization. Pin pull-up resistor values will lower if an external source drives the pin higher than VCCIO. Maximum values depend on the actual TJ and design utilization. See the PowerPlay Early Power Estimator or the Quartus II PowerPlay Power Analyzer feature for maximum values. I/O Standard Specifications Tables 4-5 through 4-27 show the HardCopy II device family's I/O standard specifications. Table 4-5. LVTTL Specifications (Part 1 of 2) Symbol VCCIO (1) VIH VIL VOH Parameter Output-supply voltage High-level input voltage Low-level input voltage High-level output voltage Conditions -- -- -- IOH = -4 mA (2), (3) Minimum 3.135 1.7 -0.3 2.4 Maximum 3.465 4.0 0.8 -- Unit V V V V 4-4 Altera Corporation September 2008 I/O Standard Specifications Table 4-5. LVTTL Specifications (Part 2 of 2) Symbol VOL (1) (2) (3) Parameter Low-level output voltage Conditions IOL = 4 mA (2), (3) Minimum -- Maximum 0.45 Unit V Notes to Table 4-5: HardCopy II devices comply to the narrow range for the supply voltage as specified in the EIA/JEDEC Standard, JESD8-B. Drive strength is programmable according to values in Table 2-10, Table 2-12, and Table 2-14. Drive strength varies based on pin location. Refer to the Description, Architecture, and Features chapter in the HardCopy II Device Family Data Sheet section of volume 1 of the HardCopy Series Handbook for more information. Table 4-6. LVCMOS Specifications Symbol VCCIO (1) VIH VIL VOH VOL (1) (2) (3) Parameter Output-supply voltage High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage Conditions -- -- -- VCCIO = 3.0, IOH = -0.1 mA (2), (3) VCCIO = 3.0, IOL = 0.1 mA (2), (3) Minimum 3.135 1.7 -0.3 VCCIO - 0.2 -- Maximum 3.465 4.0 0.8 -- 0.2 Unit V V V V V Notes to Table 4-6: HardCopy II devices comply to the narrow range for the supply voltage as specified in the EIA/JEDEC Standard, JESD8-B. Drive strength is programmable according to values in Tables 2-10, 2-12, and 2-14. Drive strength varies based on pin location. Refer to the Description, Architecture, and Features chapter in the HardCopy II Device Family Data Sheet section in volume 1 of the HardCopy Series Handbook for more information. Table 4-7. 2.5-V I/O Specifications (Part 1 of 2) Symbol VCCIO (1) VIH VIL VOH Parameter Output-supply voltage High-level input voltage Low-level input voltage High-level output voltage Conditions -- -- -- IOH = -1 mA (2), (3) Minimum 2.375 1.7 -0.3 2.0 Maximum 2.625 4.0 0.7 -- Unit V V V V Altera Corporation September 2008 4-5 HardCopy Series Handbook, Volume 1 Table 4-7. 2.5-V I/O Specifications (Part 2 of 2) Symbol VOL (1) (2) (3) Parameter Low-level output voltage Conditions IOL = 1 mA (2), (3) Minimum -- Maximum 0.4 Unit V Notes to Table 4-7: HardCopy II devices VCCIO voltage-level support of 2.5 -5% is narrower than defined in the normal range of the EIA/JEDEC Standard. Drive strength is programmable according to values in Tables 2-10, 2-12, and 2-14. Drive strength varies based on pin location. Refer to the Description, Architecture, and Features chapter in the HardCopy II Device Family Data Sheet section in volume 1 of the HardCopy Series Handbook for more information. Table 4-8. 1.8-V I/O Specifications Symbol VCCIO (1) VIH VIL VOH VOL (1) (2) (3) Parameter Output-supply voltage High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage Conditions -- -- -- IOH = -2 to -8 mA (2), (3) IOL = 2 to 8 mA (2), (3) Minimum 1.71 0.65 x VCCIO -0.3 VCCIO - 0.45 -- Maximum 1.89 2.25 0.35 x VCCIO -- 0.45 Unit V V V V V Notes to Table 4-8: HardCopy II devices VCCIO voltage-level support of 1.8 -5% is narrower than defined in the normal range of the EIA/JEDEC Standard. Drive strength is programmable according to values in Tables 2-10, 2-12, and 2-14. Drive strength varies based on pin location. Refer to the Description, Architecture, and Features chapter in the HardCopy II Device Family Data Sheet section in volume 1 of the HardCopy Series Handbook for more information. Table 4-9. 1.5-V I/O Specifications (Part 1 of 2) Symbol VCCIO (1) VIH VIL VOH Parameter Output-supply voltage High-level input voltage Low-level input voltage High-level output voltage Conditions -- -- -- IOH = -2 mA (2), (3) Minimum 1.425 0.65 x VCCIO -0.3 0.75 x VCCIO Maximum 1.575 VCCIO + 0.3 0.35 x VCCIO -- Unit V V V V 4-6 Altera Corporation September 2008 I/O Standard Specifications Table 4-9. 1.5-V I/O Specifications (Part 2 of 2) Symbol VOL (1) (2) (3) Parameter Low-level output voltage Conditions IOL = 2 mA (2), (3) Minimum -- Maximum 0.25 x VCCIO Unit V Notes to Table 4-9: HardCopy II devices VCCIO voltage-level support of 1.5 -5% is narrower than defined in the normal range of the EIA/JEDEC Standard. Drive strength is programmable according to values in Tables 2-10, 2-12, and 2-14. Drive strength varies based on pin location. Refer to the Description, Architecture, and Features chapter in the HardCopy II Device Family Data Sheet section in volume 1 of the HardCopy Series Handbook for more information. Figure 4-1 and Figure 4-2 show receiver input and transmitter waveforms, respectively, for all differential I/O LVPECL and HyperTransport technology. Figure 4-1. Receiver Input Waveforms for Differential I/O Standards Single-Ended Waveform Positive Channel (p) = VIH VID Negative Channel (n) = VIL VCM Ground Differential Waveform (Mathematical Function of Positive & Negative Channel) VID p-n=0V VID (Peak-to-peak) VID Altera Corporation September 2008 4-7 HardCopy Series Handbook, Volume 1 Figure 4-2. Transmiter Output Waveforms for Differential I/O Standards Single-Ended Waveform Positive Channel (p) = VOH VOD Negative Channel (n) = VOL VCM Ground Differential Waveform (Mathematical Function of Positive & Negative Channel) VOD p-n=0V VOD Table 4-10. 2.5-V LVDS I/O Specifications Symbol VCCIO Parameter I/O supply voltage for I/O banks that support high-speed IOEs (1), (2) Input differential voltage swing (single-ended) Input common mode voltage Output differential voltage (single-ended) Output common mode voltage Receiver differential input discrete resistor (external to HardCopy II devices) Conditions -- -- -- -- RL = 100 RL = 100 -- Minimum 2.375 Typical 2.5 Maximum 2.625 Unit V VID VICM VOD VOCM RL 100 200 250 1.125 90 350 1,250 -- -- 100 900 1,800 450 1.375 110 mV mV mV V Notes to Table 4-10: (1) (2) IOEs = I/O elements. For information on which I/O banks support high-speed IOEs, refer to the Description, Architecture, and Features chapter in the HardCopy II Device Family Data Sheet section in volume 1 of the HardCopy Series Handbook. 4-8 Altera Corporation September 2008 I/O Standard Specifications Table 4-11. 3.3-V LVDS I/O Specifications Note (1) Symbol VCCIO VID VICM VOD VOCM RL Parameter Output and feedback pins in PLL banks 9, 10, 11, and 12 (2) Input differential voltage swing (single-ended) Input common mode voltage Output differential voltage (single-ended) Output common mode voltage Receiver differential input discrete resistor (external to HardCopy II devices) Conditions -- -- -- RL = 100 RL = 100 -- Minimum 3.135 100 200 250 0.84 90 Typical 3.3 350 1,250 -- -- 100 Maximum 3.465 900 1,800 710 1.570 110 Unit V mV mV mV V Notes to Table 4-11: (1) (2) Like Stratix II devices, 3.3-V LVDS is supported by the top and bottom clock input differential buffers, and by the PLL clock output and feedback pins. The top and bottom clock input differential buffers in I/O banks 3, 4, 7, and 8 are powered by VCCINT, not VCCIO. The PLL clock output and feedback differential buffers are powered by VCC_PLLOUT. For differential clock output and feedback operation, connect VCC_PLLOUT to 3.3 V. Table 4-12. LVPECL Specifications (Part 1 of 2) Symbol VCCIO Note (1) Minimum 3.135 Parameter I/O supply voltage for I/O banks that support highspeed IOEs (2) Input differential voltage swing (single-ended) Input common mode voltage Output differential voltage (single-ended) Output common mode voltage Conditions -- Typical 3.3 Maximum 3.465 Unit V VID (peakto-peak) VICM VOD VOCM -- 300 600 1,000 mV RL = 100 RL = 100 RL = 100 1.0 525 1.650 -- -- -- 2.5 970 2.275 mV mV V Altera Corporation September 2008 4-9 HardCopy Series Handbook, Volume 1 Table 4-12. LVPECL Specifications (Part 2 of 2) Symbol RL Note (1) Minimum 90 Parameter Receiver differential input discrete resistor (external to HardCopy II devices) Conditions -- Typical 100 Maximum 110 Unit Notes to Table 4-12: (1) (2) Like Stratix II devices, LVPECL is supported by the top and bottom clock input differential buffers, and by the PLL clock output and feedback pins. The top and bottom clock input differential buffers in I/O banks 3, 4, 7, and 8 are powered by VCCINT, not VCCIO. The PLL clock output and feedback differential buffers are powered by VCC_PLLOUT. For differential clock output and feedback operation, connect VCC_PLLOUT to 3.3 V. Table 4-13. HyperTransport Technology Specifications Symbol VCCIO Parameter I/O supply voltage for I/O banks that support high-speed IOEs (1), (2) Output and feedback pins in PLL banks 9, 10, 11, and 12 Conditions -- Minimum 2.375 Typical 2.5 Maximum 2.625 Unit V -- -- -- RL = 100 RL = 100 RL = 100 RL = 100 -- 3.135 300 385 400 -- 440 -- 90 3.3 600 600 600 -- 600 -- 100 3.465 900 845 820 75 780 50 110 V mV mV mV mV V mV VID (peakto-peak) VICM VOD VOD VOCM VOCM RL Input differential voltage swing (single-ended) Input common mode voltage Output differential voltage (single-ended) Change in VOD between high and low Output common mode voltage Change in VOCM between high and low Receiver differential input discrete resistor (external to HardCopy II devices) Notes to Table 4-13: (1) (2) For information on which I/O banks support high-speed IOEs, refer to the Description, Architecture, and Features chapter in the HardCopy II Device Family Data Sheet section in volume 1 of the HardCopy Series Handbook. The top and bottom clock input differential buffers in I/O banks 3, 4, 7, and 8 are powered by VCCINT, not VCCIO. The PLL clock output and feedback differential buffers are powered by VCC_PLLOUT. For differential clock output and feedback operation, connect VCC_PLLOUT to 3.3 V. 4-10 Altera Corporation September 2008 I/O Standard Specifications Table 4-14. 3.3-V PCI Specifications Symbol VCCIO VIH VIL VOH VOL Parameter Output-supply voltage High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage Conditions -- -- -- IOUT = -500 A IOUT = 1,500 A Minimum 3 0.5 x VCCIO -0.3 0.9 x VCCIO -- Typical 3.3 -- -- -- -- Maximum 3.6 VCCIO + 0.5 0.3 x VCCIO -- 0.1 x VCCIO Unit V V V V V Table 4-15. PCI-X Mode 1 Specifications Symbol VCCIO VIH VIL VIPU VOH VOL Parameter Output-supply voltage High-level input voltage Low-level input voltage Input pull-up voltage High-level output voltage Low-level output voltage Conditions -- -- -- -- IOUT = -500 A IOUT = 1,500 A Minimum 3 0.5 x VCCIO -0.3 0.7 x VCCIO 0.9 x VCCIO -- Typical -- -- -- -- -- -- Maximum 3.6 VCCIO + 0.5 0.35 x VCCIO -- -- 0.1 x VCCIO Unit V V V V V V Table 4-16. SSTL-18 Class I Specifications (Part 1 of 2) Symbol VCCIO VREF VTT VIH(DC) VIL(DC) VIH(AC) VIL(AC) VOH Parameter Output-supply voltage Reference voltage Termination voltage High-level DC input voltage Low-level DC input voltage High-level AC input voltage Low-level AC input voltage High-level output voltage Conditions -- -- -- -- -- -- -- IOH = -6.7 mA (1), (2) Minimum 1.71 0.855 VREF - 0.04 VREF + 0.125 -- VREF + 0.25 -- VTT + 0.475 Typical 1.8 0.9 VREF -- -- -- -- -- Maximum 1.89 0.945 VREF + 0.04 -- VREF - 0.125 -- VREF - 0.25 -- Unit V V V V V V V V Altera Corporation September 2008 4-11 HardCopy Series Handbook, Volume 1 Table 4-16. SSTL-18 Class I Specifications (Part 2 of 2) Symbol VOL (1) Parameter Low-level output voltage Conditions IOL = 6.7 mA (1), (2) Minimum -- Typical -- Maximum VTT - 0.475 Unit V Notes to Table 4-16: This specification is supported across all the programmable drive settings available for this I/O standard as shown in the I/O Structure and Features section located in the Description, Architecture, and Features chapter in volume 1 of the HardCopy Series Devices Handbook. Drive strength varies based on pin location. Refer to the Description, Architecture, and Features chapter in the HardCopy II Device Family Data Sheet section in volume 1 of the HardCopy Series Handbook for more information. (2) Table 4-17. SSTL-18 Class II Specifications Symbol VCCIO VREF VTT VIH(DC) VIL(DC) VIH(AC) VIL(AC) VOH VOL (1) Parameter Output-supply voltage Reference voltage Termination voltage High-level DC input voltage Low-level DC input voltage High-level AC input voltage Low-level AC input voltage High-level output voltage Low-level output voltage Conditions -- -- -- -- -- -- -- IOH = -13.4 mA (1), (2) IOL = 13.4 mA (1), (2) Minimum 1.71 0.855 VREF - 0.04 VREF + 0.125 -- VREF + 0.25 -- VTT - 0.28 -- Typical 1.8 0.9 VREF -- -- -- -- -- -- Maximum 1.89 0.945 VREF + 0.04 -- VREF - 0.125 -- VREF - 0.25 -- 0.28 Unit V V V V V V V V V Notes to Table 4-17: This specification is supported across all the programmable drive settings available for this I/O standard as shown in the I/O Structure and Features section located in the Description, Architecture, and Features chapter in volume 1 of the HardCopy Series Devices Handbook. Drive strength varies based on pin location. Refer to the Description, Architecture, and Features chapter in the HardCopy II Device Family Data Sheet section in volume 1 of the HardCopy Series Handbook for more information. (2) Table 4-18. SSTL-18 Differential Specifications (Part 1 of 2) Symbol VCCIO VSWING(DC) Parameter Output-supply voltage DC differential input voltage Conditions -- -- Minimum 1.71 0.25 Typical 1.8 -- Maximum 1.89 -- Unit V V 4-12 Altera Corporation September 2008 I/O Standard Specifications Table 4-18. SSTL-18 Differential Specifications (Part 2 of 2) Symbol VX(AC) VSWING(AC) VISO VISO VOX(AC) Parameter AC differential input cross point voltage AC differential input voltage Input clock signal offset voltage Input clock signal offset voltage variation AC differential cross point voltage Conditions -- -- -- -- -- Minimum (VCCIO/2) - 0.175 0.5 -- -- (VCCIO/2) - 0.125 Typical -- -- 0.5 x VCCIO 200 -- Maximum (VCCIO/2) + 0.175 -- -- -- (VCCIO/2) + 0.125 Unit V V V V V Table 4-19. SSTL-2 Class I Specifications Symbol VCCIO VTT VREF VIH (DC) VIL (DC) VIH (AC) VIL (AC) VOH VOL Parameter Output-supply voltage Termination voltage Reference voltage High-level input voltage Low-level input voltage High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage Conditions -- -- -- -- -- -- -- IOH = -8.1 mA (1), (2) IOL = 8.1 mA (1), (2) Minimum 2.375 VREF - 0.04 1.188 VREF + 0.18 -0.3 VREF + 0.35 -- VTT + 0.57 -- Typical 2.5 VREF 1.25 -- -- -- -- -- -- Maximum 2.625 VREF + 0.04 1.313 3.0 VREF - 0.18 -- VREF - 0.35 -- VTT - 0.57 Unit V V V V V V V V V Notes to Table 4-19: (1) This specification is supported across all the programmable drive settings available for this I/O standard as shown in the I/O Structure and Features section of the Description, Architecture, and Features chapter in volume 1 of the HardCopy Series Devices Handbook. Drive strength varies based on pin location. Refer to the Description, Architecture, and Features chapter in the HardCopy II Device Family Data Sheet section in volume 1 of the HardCopy Series Handbook for more information. (2) Altera Corporation September 2008 4-13 HardCopy Series Handbook, Volume 1 Table 4-20. SSTL-2 Class II Specifications Symbol VCCIO VTT VREF VIH (DC) VIL (DC) VIH (AC) VIL (AC) VOH VOL Parameter Output-supply voltage Termination voltage Reference voltage High-level input voltage Low-level input voltage High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage Conditions -- -- -- -- -- -- -- IOH = -16.4 mA (1), (2) IOL = 16.4 mA (1), (2) Minimum 2.375 VREF - 0.04 1.188 VREF + 0.18 -0.3 VREF + 0.35 -- VTT + 0.76 -- Typical 2.5 VREF 1.25 -- -- -- -- -- -- Maximum 2.625 VREF + 0.04 1.313 VCCIO + 0.3 VREF - 0.18 -- VREF - 0.35 -- VTT - 0.76 Unit V V V V V V V V V Notes to Table 4-20: (1) This specification is supported across all the programmable drive settings available for this I/O standard as shown in the I/O Structure and Features section located in the Description, Architecture, and Features chapter in volume 1 of the HardCopy Series Devices Handbook. Drive strength varies based on pin location. Refer to the Description, Architecture, and Features chapter in the HardCopy II Device Family Data Sheet section in volume 1 of the HardCopy Series Handbook for more information. (2) Table 4-21. SSTL-2 Differential Specifications Symbol VCCIO VSWING (DC) VX (AC) VSWING (AC) VISO VISO VOX (AC) Parameter Output-supply voltage DC differential input voltage AC differential input cross point voltage AC differential input voltage Input clock signal offset voltage Input clock signal offset voltage variation AC differential output cross point voltage Conditions -- -- -- -- -- -- -- Minimum 2.375 0.36 (VCCIO/2) - 0.2 0.7 -- -- (VCCIO/2) - 0.2 Typical 2.5 -- -- -- 0.5 x VCCIO 200 -- Maximum 2.625 -- (VCCIO/2) + 0.2 -- -- -- (VCCIO/2) + 0.2 Unit V V V V V V V 4-14 Altera Corporation September 2008 I/O Standard Specifications Table 4-22. 1.5-V HSTL Class I Specifications Symbol VCCIO VREF VTT VIH (DC) VIL (DC) VIH (AC) VIL(AC) VOH VOL (1) Parameter Output-supply voltage Input reference voltage Termination voltage DC high-level input voltage DC low-level input voltage AC high-level input voltage AC low-level input voltage High-level output voltage Low-level output voltage Conditions -- -- -- -- -- -- -- IOH = 8 mA (1), (2) IOL = -8 mA (1), (2) Minimum 1.425 0.713 0.713 VREF + 0.1 -0.3 VREF + 0.2 -- VCCIO - 0.4 -- Typical 1.5 0.75 0.75 -- -- -- -- -- -- Maximum 1.575 0.788 0.788 -- VREF - 0.1 -- VREF - 0.2 -- 0.4 Unit V V V V V V V V V Notes to Table 4-22: This specification is supported across all the programmable drive settings available for this I/O standard as shown in the I/O Structure and Features section located in the Description, Architecture, and Features chapter in volume 1 of the HardCopy Series Devices Handbook. Drive strength varies based on pin location. Refer to the Description, Architecture, and Features chapter in the HardCopy II Device Family Data Sheet section in volume 1 of the HardCopy Series Handbook for more information. (2) Table 4-23. 1.5-V HSTL Class II Specifications (Part 1 of 2) Symbol VCCIO VREF VTT VIH (DC) VIL (DC) VIH (AC) VIL (AC) VOH Parameter Output-supply voltage Input reference voltage Termination voltage DC high-level input voltage DC low-level input voltage AC high-level input voltage AC low-level input voltage High-level output voltage Conditions -- -- -- -- -- -- -- IOH = 16 mA (1), (2) Minimum 1.425 0.713 0.713 VREF + 0.1 -0.3 VREF + 0.2 -- VCCIO - 0.4 Typical 1.5 0.75 0.75 -- -- -- -- -- Maximum 1.575 0.788 0.788 -- VREF - 0.1 -- VREF - 0.2 -- Unit V V V V V V V V Altera Corporation September 2008 4-15 HardCopy Series Handbook, Volume 1 Table 4-23. 1.5-V HSTL Class II Specifications (Part 2 of 2) Symbol VOL (1) Parameter Low-level output voltage Conditions IOL = -16 mA (1), (2) Minimum -- Typical -- Maximum 0.4 Unit V Notes to Table 4-23: This specification is supported across all the programmable drive settings available for this I/O standard as shown inthe I/O Structure and Features section of the Description, Architecture, and Features chapter in volume 1 of the HardCopy Series Devices Handbook. Drive strength varies based on pin location. Refer to the Description, Architecture, and Features chapter in the HardCopy II Device Family Data Sheet section in volume 1 of the HardCopy Series Handbook for more information. (2) Table 4-24. 1.5-V Differential HSTL Specifications Symbol VCCIO VDIF (DC) VCM (DC) VDIF (AC) VOX (AC) Parameter I/O supply voltage DC input differential voltage DC common mode input voltage AC differential input voltage AC differential cross point voltage Conditions -- -- -- -- -- Minimum 1.425 0.2 0.68 0.4 0.68 Typical 1.5 -- -- -- -- Maximum 1.575 -- 0.9 -- 0.9 Unit V V V V V Table 4-25. 1.8-V HSTL Class I Specifications (Part 1 of 2) Symbol VCCIO VREF VTT VIH (DC) VIL (DC) VIH( AC) VIL (AC) VOH Parameter Output-supply voltage Input reference voltage Termination voltage DC high-level input voltage DC low-level input voltage AC high-level input AC low-level input voltage High-level output voltage Conditions -- -- -- -- -- -- -- IOH = 8 mA (1), (2) Minimum 1.71 0.85 0.85 VREF + 0.1 -0.3 VREF + 0.2 -- VCCIO - 0.4 Typical 1.8 0.9 0.9 -- -- -- -- -- Maximum 1.89 0.95 0.95 -- VREF - 0.1 -- VREF - 0.2 -- Unit V V V V V V V V 4-16 Altera Corporation September 2008 I/O Standard Specifications Table 4-25. 1.8-V HSTL Class I Specifications (Part 2 of 2) Symbol VOL (1) Parameter Low-level output voltage Conditions IOL = -8 mA (1), (2) Minimum -- Typical -- Maximum 0.4 Unit V Notes to Table 4-25: This specification is supported across all the programmable drive settings available for this I/O standard as shown in the I/O Structure and Features section located in the Description, Architecture, and Features chapter of the HardCopy Series Devices Handbook. Drive strength varies based on pin location. Refer to the Description, Architecture, and Features chapter in the HardCopy II Device Family Data Sheet section in volume 1 of the HardCopy Series Handbook for more information. (2) Table 4-26. 1.8-V HSTL Class II Specifications Symbol VCCIO VREF VTT VIH (DC) VIL (DC) VIH (AC) VIL (AC) VOH VOL (1) Parameter Output-supply voltage Input reference voltage Termination voltage DC high-level input voltage DC low-level input voltage AC high-level input voltage AC low-level input voltage High-level output voltage Low-level output voltage Conditions -- -- -- -- -- -- -- IOH = 16 mA (1), (2) IOL= -16 mA (1), (2) Minimum 1.71 0.85 0.85 VREF + 0.1 -0.3 VREF + 0.2 -- VCCIO - 0.4 -- Typical 1.8 0.9 0.9 -- -- -- -- -- -- Maximum 1.89 0.95 0.95 -- VREF - 0.1 -- VREF - 0.2 -- 0.4 Unit V V V V V V V V V Notes to Table 4-26: This specification is supported across all the programmable drive settings available for this I/O standard as shown in the I/O Structure and Features section located in the Description, Architecture, and Features chapter in volume 1 of the HardCopy Series Devices Handbook. Drive strength varies based on pin location. Refer to the Description, Architecture, and Features chapter in the HardCopy II Device Family Data Sheet section in volume 1 of the HardCopy Series Handbook for more information. (2) Table 4-27. 1.8-V Differential HSTL Specifications (Part 1 of 2) Symbol VCCIO VDIF (DC) VCM (DC) Parameter I/O supply voltage DC input differential voltage DC common mode input voltage Conditions -- -- -- Minimum 1.71 0.2 0.78 Typical 1.8 -- -- Maximum 1.89 VCCIO + 0.6 V 1.12 Unit V V V Altera Corporation September 2008 4-17 HardCopy Series Handbook, Volume 1 Table 4-27. 1.8-V Differential HSTL Specifications (Part 2 of 2) Symbol VDIF (AC) VOX (AC) Parameter AC differential input voltage AC differential cross point voltage Conditions -- -- Minimum 0.4 0.68 Typical -- -- Maximum VCCIO + 0.6 V 0.9 Unit V V Bus Hold Specifications Table 4-28 shows the HardCopy II device family's bus hold specifications. Table 4-28. Bus Hold Parameters VCCIO Level 1.5 V Parameter Low sustaining current High sustaining current Low overdrive current Conditions VIN > VIL (maximum) 1.8 V Min 30 Max -- 2.5 V Min 50 Max -- Min 70 3.3 V Max -- Unit A Min 25 Max -- VIN < VIH (minimum) 0 V < VIN < VCCIO -25 -- -30 -- -50 -- -70 -- A -- -- 0.50 160 -160 1.00 -- -- 0.68 200 -200 1.07 -- -- 0.70 300 -300 1.70 -- -- 0.80 500 -500 2.00 A A V High overdrive 0 V < VIN < current VCCIO Bus-hold trip point -- 4-18 Altera Corporation September 2008 On-Chip Termination Specifications On-Chip Termination Specifications Table 4-29 defines the specification for internal termination specification when using series or differential on-chip termination for HC210W devices only. Table 4-29. Series On-Chip Termination Specification for I/O Banks Supporting Memory Interface IOEs for HC210W Notes (1), (2), (3) Resistance Tolerance Symbol 25 RS 3.3/2.5 Description Internal series termination with calibration (25- setting) Internal series termination without calibration (25- setting) Conditions VCC IO = 3.3/2.5 V VCC IO = 3.3/2.5 V VCC IO = 3.3/2.5 V VCC IO = 3.3/2.5 V VCC IO = 1.8 V VCC IO = 1.8 V VCC IO = 1.8 V VCC IO = 1.8 V VCC IO = 1.5 V VCC IO = 1.5 V Commercial Max 10 30 10 30 10 30 10 30 13 36 Industrial Max 15 30 15 30 15 30 15 30 15 36 Unit % % % % % % % % % % 50 RS 3.3/2.5 Internal series termination with calibration (50- setting) Internal series termination without calibration (50- setting) 25 RS 1.8 Internal series termination with calibration (25- setting) Internal series termination without calibration (25- setting) 50 RS 1.8 Internal series termination with calibration (50- setting) Internal series termination without calibration (50- setting) 50 RS 1.5 Internal series termination with calibration (50- setting) Internal series termination without calibration (50- setting) Notes to Table 4-29: (1) (2) (3) For information on which I/O banks support memory interface IOEs, refer to the Description, Architecture, and Features chapter in the HardCopy II Device Family Data Sheet section in volume 1 of the HardCopy Series Handbook. The resistance tolerances for calibrated SOCT and POCT are at the time of initial of calibration. If the temperature or voltage changes over time, the tolerance may also change. This table applies only to the HC210W device. Altera Corporation September 2008 4-19 HardCopy Series Handbook, Volume 1 Tables 4-30 and 4-31 define the specification for internal termination specification when using series or differential on-chip termination. Table 4-30. Series On-Chip Termination Specification for I/O Banks Supporting Memory Interface IOEs Notes (1), (2), (3) Resistance Tolerance Symbol 25 RS 3.3/2.5 Description Internal series termination with calibration (25- setting) Internal series termination without calibration (25- setting) Conditions VCC IO = 3.3/2.5 V VCC IO = 3.3/2.5 V VCC IO = 3.3/2.5 V VCC IO = 3.3/2.5 V VCC IO = 1.8 V VCC IO = 1.8 V VCC IO = 1.8 V VCC IO = 1.8 V VCC IO = 1.5 V VCC IO = 1.5 V Commercial Max 5 30 5 30 5 30 5 30 8 36 Industrial Max 10 30 10 30 10 30 10 30 10 36 Unit % % % % % % % % % % 50 RS 3.3/2.5 Internal series termination with calibration (50- setting) Internal series termination without calibration (50- setting) 25 RS 1.8 Internal series termination with calibration (25- setting) Internal series termination without calibration (25- setting) 50 RS 1.8 Internal series termination with calibration (50- setting) Internal series termination without calibration (50- setting) 50 RS 1.5 Internal series termination with calibration (50- setting) Internal series termination without calibration (50- setting) Notes to Table 4-30: (1) (2) (3) For information on which I/O banks support memory interface IOEs, refer to the Description, Architecture, and Features chapter in the HardCopy II Device Family Data Sheet section in volume 1 of the HardCopy Series Handbook. The resistance tolerances for calibrated SOCT and POCT are at the time of initial calibration. If the temperature or voltage changes over time, the tolerance may also change. This table applies only to HC210, HC220, HC230 and HC240 devices. 4-20 Altera Corporation September 2008 Pin Capacitance Table 4-31. Series and Differential On-Chip Termination Specification for I/O Banks Supporting High-Speed and General Purpose IOEs Notes (1), (3), (4) Resistance Tolerance Symbol 25 RS 3.3/2.5 Description Internal series termination without calibration (25- setting) Conditions VCCIO = 3.3/2.5 V VCCIO = 3.3/2.5/1.8 V VCCIO = 1.5 V -- Commercial Max 30 30 36 20 Industrial Max 30 30 36 25 Unit % % % % Internal series termination without 50 RS 3.3/2.5/1.8 calibration (50- setting) 50 RS 1.5 RD (2) Internal series termination without calibration (50- setting) Internal differential termination for LVDS or HyperTransport technology Notes to Table 4-31: (1) (2) (3) (4) For information on which I/O banks support high-speed IOEs, refer to the Description, Architecture, and Features chapter in the HardCopy II Device Family Data Sheet section in volume 1 of the HardCopy Series Handbook. RD is only supported on high-speed IOEs. The resistance tolerances for calibrated SOCT and POCT are at the time of initial calibration. If the temperature or voltage changes over time, the tolerance may also change. This table applies only to HC210, HC220, HC230, and HC240 devices. Pin Capacitance Table 4-32 shows the HardCopy II device family's pin capacitance. Table 4-32. HardCopy II Device Capacitance Symbol CGPIO Note (1) (Part 1 of 2) HC210W Typical 5.7 Parameter Input capacitance on I/O pins in I/O banks supporting general-purpose IOEs. Input capacitance on I/O pins in I/O banks supporting memory interface IOEs. Input capacitance on I/O pins in I/O banks supporting high-speed IOEs. Input capacitance on top/bottom clock input pins CLK[4..7] and CLK[12..15]. HC210, HC220, HC230, HC240 Typical 5.0 Unit pF CMIIO 5.7 5.0 pF CHSIO CCLKTB 7.2 6.0 6.1 6.0 pF pF Altera Corporation September 2008 4-21 HardCopy Series Handbook, Volume 1 Table 4-32. HardCopy II Device Capacitance Symbol CCLKLR CCLKLR+ COUTFB Note (1) (Part 2 of 2) HC210W Typical 4.3 4.2 6.9 Parameter Input capacitance on left/right clock inputs CLK0, CLK2, CLK8, CLK10. Input capacitance on left/right clock inputs CLK1, CLK3, CLK9, and CLK11. Input capacitance on dual-purpose clock output/feedback pins in PLL banks 9, 10, 11, and 12. HC210, HC220, HC230, HC240 Typical 6.1 3.3 6.7 Unit pF pF pF Note to Table 4-32: (1) Capacitance is sample-tested only. Capacitance is measured using time-domain reflections (TDR). Measurement accuracy is within 0.5 pF. Maximum Input Clock Rates Tables 4-33 and 4-34 show the maximum input clocking rates of HardCopy II I/Os. Table 4-33. HardCopy II Maximum Input Clock Rates of HC210, HC220, HC230 and HC240 Devices (Part 1 of 2) I/OStandard LVTTL 2.5 V 1.8 V 1.5 V LVCMOS SSTL2 class I SSTL2 class II SSTL18 class I SSTL18 class II 1.5 V HSTL class I 1.5 V HSTL class II 1.8 V HSTL class I 1.8 V HSTL class II PCI (1) Memory Interface IOEs 500 500 500 500 500 500 500 500 500 500 500 500 500 500 High General Speed Purpose IOEs IOEs 500 500 500 500 500 -- -- -- -- -- -- -- -- -- 500 500 500 500 500 -- -- -- -- -- -- -- -- 500 CLK [0..3, 8..11] 500 500 500 500 500 -- -- -- -- -- -- -- -- -- CLK [4..7, FPLL_CLK PLL_FB 12..15] 500 500 500 500 500 500 500 500 500 500 500 500 500 500 500 500 500 500 500 -- -- -- -- -- -- -- -- -- 500 500 500 500 500 500 500 500 500 500 500 500 500 500 Unit MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz 4-22 Altera Corporation September 2008 Maximum Input Clock Rates Table 4-33. HardCopy II Maximum Input Clock Rates of HC210, HC220, HC230 and HC240 Devices (Part 2 of 2) I/OStandard PCI-X (1) Differential SSTL2 class I (2), (3) Differential SSTL2 class II (2), (3) Differential SSTL18 class I (2), (3) Differential SSTL18 class II (2), (3) 1.8-V Differential HSTL class I (2), (3) 1.8-V Differential HSTL class II (2), (3) 1.5-V Differential HSTL class I (2), (3) 1.5-V Differential HSTL class II (2), (3) LVDS LVPECL HyperTransport Notes to Table 4-33: (1) (2) (3) The PCI clamping diode is only supported on the top and bottom I/O pins. This I/O standard is only supported on the DQS, CLK, and PLL_FB input pins. For HC210 and HC220, differential HSTL/SSTL input is supported on top/bottom PLL_FB, the top clock pins and DQS pins located on the top I/Os. Memory Interface IOEs 500 500 500 500 500 500 500 500 500 -- -- -- High General Speed Purpose IOEs IOEs -- -- -- -- -- -- -- -- -- 520 -- 520 500 -- -- -- -- -- -- -- -- -- -- -- CLK [0..3, 8..11] -- -- -- -- -- -- -- -- -- 717 -- 717 CLK [4..7, FPLL_CLK PLL_FB 12..15] 500 500 500 500 500 500 500 500 500 450 450 -- -- -- -- -- -- -- -- -- -- 717 -- 717 500 500 500 500 500 500 500 500 500 450 450 -- Unit MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz Altera Corporation September 2008 4-23 HardCopy Series Handbook, Volume 1 Table 4-34. HardCopy II Maximum Input Clock Rates of HC210W Devices I/O Standard LVTTL 2.5-V LVTTL/LVCMOS 1.8-V LVTTL/LVCMOS 1.5-V LVTTL/LVCMOS LVCMOS SSTL2 class I SSTL2 class II SSTL18 class I SSTL18 class II 1.5-V HSTL class I 1.5-V HSTL class II 1.8-V HSTL class I 1.8-V HSTL class II PCI (1) PCI-X (1) Differential SSTL2 class I (2) Differential SSTL2 class II (2) Differential SSTL18 class I (2) Differential SSTL18 class II (2) 1.8-V differential HSTL class I (2) 1.8-V differential HSTL class II (2) 1.5-V differential HSTL class I (2) 1.5-V differential HSTL class II (2) LVDS LVPECL Note (3) (Part 1 of 2) CLK FPLL_C [4..7, PLL_FB LK 12..15] 350 350 350 270 350 350 350 350 350 350 350 350 350 315 315 350 350 350 350 350 350 350 350 320 320 350 350 350 270 350 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 320 -- 350 350 350 270 350 350 350 350 350 350 350 350 350 315 315 350 350 350 350 350 350 350 350 320 320 Memory Interface IOEs 350 350 350 270 350 350 350 350 350 350 350 350 350 315 315 -- -- -- -- -- -- -- -- -- -- High Speed IOEs 350 350 350 270 350 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 320 -- General Purpose IOEs 350 350 350 270 350 -- -- -- -- -- -- -- -- 315 315 -- -- -- -- -- -- -- -- -- -- CLK [0..3, 8..11] 350 350 350 270 350 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 320 -- Unit MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz 4-24 Altera Corporation September 2008 Maximum Output Clock Rates Table 4-34. HardCopy II Maximum Input Clock Rates of HC210W Devices I/O Standard HyperTransport Notes to Table 4-34: (1) (2) (3) Note (3) (Part 2 of 2) CLK FPLL_C [4..7, PLL_FB LK 12..15] -- 320 -- Memory Interface IOEs -- High Speed IOEs 320 General Purpose IOEs -- CLK [0..3, 8..11] 320 Unit MHz The PCI clamping diode is only supported on the top and bottom I/O pins. For HC210W, differential HSTL/SSTL input is supported on the top clock pins, the DQS pins on the top I/O banks and top/bottom PLL_FB input pins. These numbers are preliminary and pending further silicon characterization. Maximum Output Clock Rates Tables 4-35 and 4-36 show the maximum output toggle rates of HardCopy II I/O's for all available drive strengths. Table 4-35. HardCopy II Maximum Output Clock Rate of HC210, HC220, HC230 and HC240 Devices Note (1) (Part 1 of 5) Memory Interface IOEs 225 355 475 594 700 794 250 480 710 925 985 1040 I/O Standard Drive Strength 4 mA 8 mA 12 mA 16 mA 20 mA 24 mA (3) High Speed IOEs 225 355 475 -- -- -- 250 480 -- -- -- -- General Purpose CLK [0, CLK IOEs 2, 8, [4..7, PLL_OUT Bottom Right 10] (2) 12..15] Column Row 225 355 475 -- -- -- 250 480 -- -- -- -- 225 355 475 -- -- -- 250 480 -- -- -- -- 225 355 475 -- -- -- 250 480 -- -- -- -- 225 355 475 594 700 794 250 480 710 925 985 1040 225 355 475 594 700 794 250 480 710 925 985 1040 Unit 3.3-V LVTTL MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz 3.3-V LVCMOS 4 mA 8 mA 12 mA 16 mA 20 mA 24 mA (3) Altera Corporation September 2008 4-25 HardCopy Series Handbook, Volume 1 Table 4-35. HardCopy II Maximum Output Clock Rate of HC210, HC220, HC230 and HC240 Devices Note (1) (Part 2 of 5) Memory Interface IOEs 194 380 575 845 109 250 390 570 805 1040 200 370 430 495 300 400 350 350 400 150 250 300 400 550 200 350 400 500 I/O Standard Drive Strength 4 mA 8 mA 12 mA 16 mA (3) High Speed IOEs 194 380 575 -- 109 250 390 570 -- -- 200 370 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- General Purpose CLK [0, CLK IOEs 2, 8, [4..7, PLL_OUT Bottom Right 10] (2) 12..15] Column Row 194 380 575 -- 109 250 390 570 -- -- 200 370 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 194 380 575 -- 109 250 390 570 -- -- 200 370 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 194 380 575 -- 109 250 390 570 -- -- 200 370 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 194 380 575 845 109 250 390 570 805 1040 200 370 430 495 300 400 350 350 400 150 250 300 400 550 200 350 400 500 194 380 575 845 109 250 390 570 805 1040 200 370 430 495 300 400 350 350 400 150 250 300 400 550 200 350 400 500 Unit 2.5-V LVTTL / LVCMOS MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz 1.8-V LVTTL / LVCMOS 2 mA 4 mA 6 mA 8 mA 10 mA 12 mA (3) 1.5-V LVTTL / LVCMOS 2 mA 4 mA 6 mA 8 mA (3) SSTL2 class I SSTL2 class II 8 mA 12 mA (3) 16 mA 20 mA 24 mA (3) SSTL18 class I 4 mA 6 mA 8 mA 10 mA 12 mA (3) SSTL18 class II 8 mA 16 mA 18 mA 20 mA (3) 4-26 Altera Corporation September 2008 Maximum Output Clock Rates Table 4-35. HardCopy II Maximum Output Clock Rate of HC210, HC220, HC230 and HC240 Devices Note (1) (Part 3 of 5) Memory Interface IOEs 300 450 600 650 700 500 500 550 300 500 650 700 700 600 600 650 790 790 -- -- -- 300 400 350 350 400 I/O Standard Drive Strength 4 mA 6 mA 8 mA 10 mA 12 mA (3) High Speed IOEs -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 717 717 -- -- -- -- -- -- General Purpose CLK [0, CLK IOEs 2, 8, [4..7, PLL_OUT Bottom Right 10] (2) 12..15] Column Row -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 790 790 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 300 450 600 650 700 500 500 550 300 500 650 700 700 600 600 650 790 790 -- -- -- 300 400 350 350 400 300 450 600 650 700 500 500 550 300 500 650 700 700 600 600 650 790 790 400 -- 400 300 400 350 350 400 Unit 1.8-V HSTL class I MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz 1.8-V HSTL class II 16 mA 18 mA 20 mA (3) 1.5-V HSTL class I 4 mA 6 mA 8 mA 10 mA 12 mA (3) 1.5-V HSTL class II 16 mA 18 mA 20 mA (3) PCI (4) PCI-X (4) LVDS HyperTransport LVPECL Differential SSTL2 class I (5) Differential SSTL2 class II (5) -- -- -- -- -- 8 mA 12 mA (3) 16 mA 20 mA (3) 24 mA (3) Altera Corporation September 2008 4-27 HardCopy Series Handbook, Volume 1 Table 4-35. HardCopy II Maximum Output Clock Rate of HC210, HC220, HC230 and HC240 Devices Note (1) (Part 4 of 5) Memory Interface IOEs 150 250 300 400 550 200 350 400 500 300 450 600 650 700 500 500 550 300 500 650 700 700 I/O Standard Drive Strength 4 mA 6 mA 8 mA 10 mA 12 mA (3) High Speed IOEs -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- General Purpose CLK [0, CLK IOEs 2, 8, [4..7, PLL_OUT Bottom Right 10] (2) 12..15] Column Row -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 150 250 300 400 550 200 350 400 500 300 450 600 650 700 500 500 550 300 500 650 700 700 150 250 300 400 550 200 350 400 500 300 450 600 650 700 500 500 550 300 500 650 700 700 Unit Differential SSTL18 class I (5) MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz Differential SSTL18 class II (5) 8 mA 16 mA 18 mA 20 mA (3) 1.8-V differential HSTL class I (5) 4 mA 6 mA 8 mA 10 mA 12 mA (3) 1.8-V differential HSTL class II (5) 1.5-V differential HSTL class I (5) 16 mA 18 mA 20 mA (3) 4 mA 6 mA 8 mA 10 mA 12 mA (3) 4-28 Altera Corporation September 2008 Maximum Output Clock Rates Table 4-35. HardCopy II Maximum Output Clock Rate of HC210, HC220, HC230 and HC240 Devices Note (1) (Part 5 of 5) Memory Interface IOEs 600 600 650 I/O Standard Drive Strength 16 mA 18 mA 20 mA (3) High Speed IOEs -- -- -- General Purpose CLK [0, CLK IOEs 2, 8, [4..7, PLL_OUT Bottom Right 10] (2) 12..15] Column Row -- -- -- -- -- -- -- -- -- 600 600 650 600 600 650 Unit 1.5-V differential HSTL class II (5) Notes to Table 4-35: (1) MHz MHz MHz (2) (3) (4) (5) The toggle rate applies to 0 pF output load for all I/O standards except for LVDS and HyperTransport technology on row I/O pins. For LVDS and HyperTransport technology on row I/O pins, the toggle rates apply to load from 0 to 5 pF. CLK [1, 3, 9, 11] and FPLL_CLK are dedicated input clocks, and are excluded from this table. This is the default setting in the Quartus(R) II software if supported by the pin location. The PCI clamping diode is only supported on the top and bottom I/O pins. Like Stratix II devices, differential HSTL and SSTL is supported only on the column CLK, PLL_OUT and memory interface DQS IOE pins. For HC210 and HC220, only the top column clock pins support Differential HSTL and SSTL. Table 4-36. HardCopy II Maximum Output Clock Rate for HC210W Devices Memory Interface IOEs 100 170 230 240 280 300 175 230 260 270 290 310 Notes (1), (6) (Part 1 of 4) I/O Standard Drive Strength 4 mA 8 mA 12 mA 16 mA 20 mA 24 mA (3) High Speed IOEs 100 170 230 -- -- -- 175 230 -- -- -- -- General Purpose CLK [0, CLK IOEs 2, 8, [4..7, PLL_OUT Bottom Right 10] (2) 12..15] Column Row 100 170 230 -- -- -- 175 230 -- -- -- -- 100 170 230 -- -- -- 175 230 -- -- -- -- 100 170 230 -- -- -- 175 230 -- -- -- -- 100 170 230 240 280 300 175 230 260 270 290 310 100 170 230 240 280 300 175 230 260 270 290 310 Unit 3.3-V LVTTL MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz 3.3-V LVCMOS 4 mA 8 mA 12 mA 16 mA 20 mA 24 mA (3) Altera Corporation September 2008 4-29 HardCopy Series Handbook, Volume 1 Table 4-36. HardCopy II Maximum Output Clock Rate for HC210W Devices Memory Interface IOEs 136 230 370 405 77 150 180 200 250 290 60 110 150 190 210 280 245 245 280 105 175 210 220 230 140 220 220 350 Notes (1), (6) (Part 2 of 4) I/O Standard Drive Strength 4 mA 8 mA 12 mA 16 mA (3) High Speed IOEs 136 230 370 -- 77 150 180 200 -- -- 60 110 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- General Purpose CLK [0, CLK IOEs 2, 8, [4..7, PLL_OUT Bottom Right 10] (2) 12..15] Column Row 136 230 370 -- 77 150 180 200 -- -- 60 110 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 136 230 370 -- 77 150 180 200 -- -- 60 110 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 136 230 370 -- 77 150 180 200 -- -- 60 110 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 136 230 370 405 77 150 180 200 250 290 60 110 150 190 210 280 245 245 280 105 175 210 220 230 140 220 220 350 136 230 370 405 77 150 180 200 250 290 60 110 150 190 210 280 245 245 280 105 175 210 220 230 140 220 220 350 Unit 2.5-V LVTTL / LVCMOS MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz 1.8-V LVTTL / LVCMOS 2 mA 4 mA 6 mA 8 mA 10 mA 12 mA (3) 1.5-V LVTTL / LVCMOS 2 mA 4 mA 6 mA 8 mA (3) SSTL2 class I 8 mA 12 mA (3) SSTL2 class II 16 mA 20 mA 24 mA (3) SSTL18 class I 4 mA 6 mA 8 mA 10 mA 12 mA (3) SSTL18 class II 8 mA 16 mA 18 mA 20 mA (3) 4-30 Altera Corporation September 2008 Maximum Output Clock Rates Table 4-36. HardCopy II Maximum Output Clock Rate for HC210W Devices Memory Interface IOEs 210 210 220 250 270 190 200 210 150 160 170 180 190 170 170 170 315 315 -- -- -- 210 280 245 245 280 105 175 210 220 230 Notes (1), (6) (Part 3 of 4) I/O Standard Drive Strength 4 mA 6 mA 8 mA 10 mA 12 mA (3) High Speed IOEs -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 320 320 -- -- -- -- -- -- -- -- -- -- -- General Purpose CLK [0, CLK IOEs 2, 8, [4..7, PLL_OUT Bottom Right 10] (2) 12..15] Column Row -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 315 315 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 210 210 220 250 270 190 200 210 150 160 170 180 190 170 170 170 315 315 -- -- -- 210 280 245 245 280 105 175 210 220 230 210 210 220 250 270 190 200 210 150 160 170 180 190 170 170 170 315 315 280 -- 280 210 280 245 245 280 105 175 210 220 230 Unit 1.8-V HSTL class I MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz 1.8-V HSTL class II 16 mA 18 mA 20 mA (3) 1.5-V HSTL class I 4 mA 6 mA 8 mA 10 mA 12 mA (3) 1.5-V HSTL class II 16 mA 18 mA 20 mA (3) PCI (4) PCI-X (4) LVDS HyperTransport LVPECL Differential SSTL2 class I (5) Differential SSTL2 class II (5) -- -- -- -- -- 8 mA 12 mA (3) 16 mA 20 mA 24 mA (3) Differential SSTL18 class I (5) 4 mA 6 mA 8 mA 10 mA 12 mA (3) Altera Corporation September 2008 4-31 HardCopy Series Handbook, Volume 1 Table 4-36. HardCopy II Maximum Output Clock Rate for HC210W Devices Memory Interface IOEs 140 220 220 220 210 210 220 250 270 190 200 210 150 160 170 180 190 170 170 170 Notes (1), (6) (Part 4 of 4) I/O Standard Drive Strength 8 mA 16 mA 18 mA 20 mA (3) High Speed IOEs -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- General Purpose CLK [0, CLK IOEs 2, 8, [4..7, PLL_OUT Bottom Right 10] (2) 12..15] Column Row -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 140 220 220 220 210 210 220 250 270 190 200 210 150 160 170 180 190 170 170 170 140 220 220 220 210 210 220 250 270 190 200 210 150 160 170 180 190 170 170 170 Unit Differential SSTL18 class II (5) MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz 1.8-V differential HSTL class I (5) 4 mA 6 mA 8 mA 10 mA 12 mA (3) 1.8-V differential HSTL class II (5) 16 mA 18 mA 20 mA (3) 1.5-V differential HSTL class I (5) 4 mA 6 mA 8 mA 10 mA 12 mA (3) 1.5-V differential HSTL class II (5) 16 mA 18 mA 20 mA (3) Notes to Table 4-36: (1) The toggle rate applies to 0 pF output load for all I/O standards except for LVDS and HyperTransport technology on row I/O pins. For LVDS and HyperTransport technology on row I/O pins, the toggle rates apply to load from 0 to 5 pF. CLK [1, 3, 9, 11] and FPLL_CLK are dedicated input clocks, and excluded from this table. This is the default setting in the Quartus II software if supported by the pin location. The PCI clamping diode is only supported on the top and bottom I/O pins. Like Stratix II devices, differential HSTL and SSTL is supported only on the column CLK, PLL_OUT and memory interface DQS IOE pins. For HC210 and HC220, only the top column clock pins support Differential HSTL and SSTL. These numbers are preliminary and pending further silicon characterization. (2) (3) (4) (5) (6) 4-32 Altera Corporation September 2008 Maximum Output Clock Rates Tables 4-37 and 4-38 show the maximum output toggle rates of HardCopy II I/Os using OCT. Table 4-37. HardCopy II Maximum Output Clock Rate for HC210, HC220, HC230 and HC240 Devices (OCT) Note (1) (Part 1 of 2) Memory Interface IOEs 400 350 550 350 450 500 550 400 500 550 600 500 500 I/O Standard Drive Strength OCT 50 OCT 50 OCT 50 OCT 50 OCT 50 OCT 50 OCT 25 OCT 50 OCT 50 OCT 50 OCT 50 OCT 50 High Speed IOEs 400 350 550 350 450 -- -- -- -- -- -- -- -- General Purpose CLK [0, CLK IOEs 2, 8, [4..7, PLL_OUT Bottom Right 10] (2) 12..15] Column Row 400 350 550 350 450 -- -- -- -- -- -- -- -- 400 350 550 350 450 -- -- -- -- -- -- -- -- 400 350 550 350 450 -- -- -- -- -- -- -- -- 400 350 550 350 450 500 550 400 500 550 600 500 500 400 350 550 350 450 500 550 400 500 550 600 500 500 Unit 3.3-V LVTTL 2.5-V LVTTL 1.8-V LVTTL 3.3-V LVCMOS 1.5-V LVCMOS SSTL-2 Class I SSTL-2 Class II SSTL-18 Class I MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz SSTL-18 Class II OCT 25 1.5-V HSTL Class I 1.8-V HSTL Class I 1.8-V HSTL Class II Differential SSTL-2 Class I (3) Differential SSTL-2 Class II (3) Differential SSTL-18 Class I (3) OCT 25 550 -- -- -- -- 550 550 MHz OCT 50 400 -- -- -- -- 400 400 MHz OCT 25 Differential SSTL-18 Class II (3) 1.8-V Differential OCT 50 HSTL Class I (3) 1.8-V Differential OCT 25 HSTL Class II (3) 500 -- -- -- -- 500 500 MHz 600 500 -- -- -- -- -- -- -- -- 600 500 600 500 MHz MHz Altera Corporation September 2008 4-33 HardCopy Series Handbook, Volume 1 Table 4-37. HardCopy II Maximum Output Clock Rate for HC210, HC220, HC230 and HC240 Devices (OCT) Note (1) (Part 2 of 2) Memory Interface IOEs 550 I/O Standard Drive Strength High Speed IOEs -- General Purpose CLK [0, CLK IOEs 2, 8, [4..7, PLL_OUT Bottom Right 10] (2) 12..15] Column Row -- -- -- 550 550 Unit 1.5-V Differential OCT 50 HSTL Class I (3) Notes to Table 4-37: (1) MHz (2) (3) The toggle rate applies to 0 pF output load for all I/O standards except for LVDS and HyperTransport technology on row I/O pins. For LVDS and HyperTransport technology on row I/O pins, the toggle rates apply to load from 0 to 5 pF. CLK [1, 3, 9, 11] and FPLL_CLK are dedicated input clocks, and excluded from this table. Like Stratix II devices, differential HSTL and SSTL is supported only on the column CLK, PLL_OUT and memory interface DQS IOE pins. For HC210 and HC220, only the top column clock pins support Differential HSTL and SSTL. Table 4-38. HardCopy II Maximum Output Clock Rate for HC210W using OCT Memory Interface IOEs 280 245 290 245 190 280 280 230 220 190 270 210 Notes (1), (4) (Part 1 of 2) I/O Standard Drive Strength OCT 50 OCT 50 OCT 50 OCT 50 OCT 50 OCT 50 OCT 25 OCT 50 OCT 50 OCT 50 OCT 50 High Speed IOEs 280 245 290 245 190 -- -- -- -- -- -- -- General Purpose CLK [0, CLK IOEs 2, 8, [4..7, PLL_OUT Bottom Right 10] (2) 12..15] Column Row 280 245 290 245 190 -- -- -- -- -- -- -- 280 245 290 245 190 -- -- -- -- -- -- -- 280 245 290 245 190 -- -- -- -- -- -- -- 280 245 290 245 190 280 280 230 220 190 270 210 280 245 290 245 190 280 280 230 220 190 270 210 Unit 3.3-V LVTTL 2.5-V LVTTL 1.8-V LVTTL 3.3-V LVCMOS 1.5-V LVCMOS SSTL-2 Class I SSTL-2 Class II SSTL-18 Class I MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz SSTL-18 Class II OCT 25 1.5-V HSTL Class I 1.8-V HSTL Class I 1.8-V HSTL Class II 4-34 Altera Corporation September 2008 HighSpeed I/O Specifications Table 4-38. HardCopy II Maximum Output Clock Rate for HC210W using OCT Memory Interface IOEs 280 Notes (1), (4) (Part 2 of 2) I/O Standard Drive Strength OCT 50 High Speed IOEs -- General Purpose CLK [0, CLK IOEs 2, 8, [4..7, PLL_OUT Bottom Right 10] (2) 12..15] Column Row -- -- -- 280 280 Unit Differential SSTL-2 Class I (3) Differential SSTL-2 Class II (3) Differential SSTL-18 Class I (3) MHz OCT 25 280 -- -- -- -- 280 280 MHz OCT 50 230 -- -- -- -- 230 230 MHz OCT 25 Differential SSTL-18 Class II (3) 1.8-V Differential OCT 50 HSTL Class I (3) 1.8-V Differential OCT 25 HSTL Class II (3) 1.5-V Differential OCT 50 HSTL Class I (3) Notes to Table 4-38: (1) 220 -- -- -- -- 220 220 MHz 270 210 190 -- -- -- -- -- -- -- -- -- -- -- -- 270 210 190 270 210 190 MHz MHz MHz (2) (3) (4) The toggle rate applies to 0 pF output load for all I/O standards except for LVDS and HyperTransport technology on row I/O pins. For LVDS and HyperTransport technology on row I/O pins, the toggle rates apply to load from 0 to 5 pF. CLK [1, 3, 9, 11] and FPLL_CLK are dedicated input clocks, and excluded from this table. Like Stratix II devices, differential HSTL and SSTL is supported only on the column CLK, PLL_OUT and memory interface DQS IOE pins. For HC210 and HC220, only the top column clock pins support differential HSTL and SSTL. These numbers are preliminary and pending further silicon characterization. HighSpeed I/O Specifications Table 4-39 provides high-speed timing specifications definitions. Table 4-39. HighSpeed Timing Specifications and Definitions (Part 1 of 2) HighSpeed Timing Specifications tC fHSCLK J Definitions Highspeed receiver/transmitter input and output clock period. Highspeed receiver/transmitter input and output clock frequency. De-serialization factor (width of parallel data bus). Altera Corporation September 2008 4-35 HardCopy Series Handbook, Volume 1 Table 4-39. HighSpeed Timing Specifications and Definitions (Part 2 of 2) HighSpeed Timing Specifications W tRISE tFALL Timing unit interval (TUI) PLL multiplication factor Low-to-high transmission time. High-to-low transmission time. The timing budget allowed for skew, propagation delays, and data sampling window. (TUI = 1/(Receiver Input Clock Frequency x Multiplication Factor) = tC/w). Maximum/minimum LVDS data transfer rate (fHSDR = 1/TUI), non-DPA. Maximum/minimum LVDS data transfer rate (fHSDRDPA = 1/TUI), DPA. The timing difference between the fastest and slowest output edges, including tCO variation and clock skew. The clock is included in the TCCS measurement. The period of time during which the data must be valid in order to capture it correctly. The setup and hold times determine the ideal strobe position within the sampling window. Peak-to-peak input jitter on highspeed PLLs. Peak-to-peak output jitter on highspeed PLLs. Duty cycle on highspeed transmitter output clock. Lock time for highspeed transmitter and receiver PLLs. Definitions fHSDR fHSDRDPA Channel-to-channel skew (TCCS) Sampling window (SW) Input jitter (peak-to-peak) Output jitter (peak-to-peak) tDUTY tLOCK Table 4-40 shows the high-speed I/O timing specifications for HC210W F484 WireBond devices. Table 4-40. HardCopy II High-Speed I/O Specifications for HC210W Device Notes (1), (2) (Part 1 of 2) Symbol fHSCLK (clock frequency) fHSCLK = fHSDR / W Conditions W = 2 to 32 (LVDS, HyperTransport technology) (3) W = 1 (SERDES bypass, LVDS only) W = 1 (SERDES used, LVDS only) Min 16 16 150 150 (4) (4) 150 -- 400 -- Typ -- -- -- -- -- -- -- -- -- -- Max 320 320 320 640 640 320 640 240 -- (5) Unit MHz MHz MHz Mbps Mbps Mbps Mbps ps ps ps fHSDR (data rate) J = 4 to 10 (LVDS, HyperTransport technology) J = 2 (LVDS, HyperTransport technology) J = 1 t(LVDS only) fHSDRDPA (DPA data rate) TCCS SW Output jitter J = 4 to 10 (LVDS, HyperTransport technology) All differential standards All differential standards -- 4-36 Altera Corporation September 2008 HighSpeed I/O Specifications Table 4-40. HardCopy II High-Speed I/O Specifications for HC210W Device Notes (1), (2) (Part 2 of 2) Symbol Output tRISE Output tFALL tDUTY DPA run length DPA jitter tolerance (peak-to-peak) DPA lock time -- -- -- Standard -- SPI4 Parallel Rapid I/O -- Miscellaneous -- Notes to Table 4-40: (1) (2) (3) (4) These numbers are preliminary and pending further silicon characterization. When J = 4 to 10, the SERDES block is used. When J = 1 or 2, the SERDES block is bypassed. The input clock frequency and the W factor must satisfy the following fast PLL VCO specification: 150 input clock frequency x W 640. The minimum specification is dependent on the clock source (fast PLL, enhanced PLL, clock pin, and so on) and the clock routing resource (global, regional, or local) used. The I/O differential buffer and input register do not have a minimum toggle rate. Contact the Altera Applications Group for more information. Conditions All differential I/O standards All differential I/O standards -- -- -- Training Pattern -- 0000000000 1111111111 10010000 10010000 10101010 10101010 -- -- -- Transition Density -- 10% 25% 50% 100% -- Min -- -- 45 -- (5) -- -- (5) (5) (5) (5) (5) Typ -- -- 50 -- -- -- -- -- -- -- -- -- Max (5) (5) 55 6,400 -- -- -- -- -- -- -- -- Unit ps ps % UI UI Number of repetitions (5) Table 4-41 shows the high-speed I/O timing specifications for HC210, HC220, HC230 and HC240 HardCopy II devices. Table 4-41. HardCopy II High-Speed I/O Specifications for HC210, HC220, HC230 and HC240 Devices Note (1) (Part 1 of 2) Symbol fHSCLK (clock frequency) fHSCLK = fHSDR / W Conditions W = 2 to 32 (LVDS, HyperTransport technology) (2) W = 1 (SERDES bypass, LVDS only) W = 1 (SERDES used, LVDS only) Min 16 16 150 Typ -- -- -- Max 520 500 717 Unit MHz MHz MHz Altera Corporation September 2008 4-37 HardCopy Series Handbook, Volume 1 Table 4-41. HardCopy II High-Speed I/O Specifications for HC210, HC220, HC230 and HC240 Devices Note (1) (Part 2 of 2) Symbol fHSDR (data rate) Conditions J = 4 to 10 (LVDS, HyperTransport technology) J = 2 (LVDS, HyperTransport technology) J = 1 (LVDS only) Min 150 (3) (3) 150 -- 330 -- -- -- 45 -- 0.44 Transition Density -- 10% 25% 50% 100% -- -- -- 256 256 256 256 256 Typ -- -- -- -- -- -- -- -- -- 50 -- -- -- -- -- -- -- -- -- Max 1,040 760 500 1,040 200 -- 190 160 180 55 6,400 -- -- -- -- -- -- -- -- Unit Mbps Mbps Mbps Mbps ps ps ps ps ps % UI UI Number of repetitions fHSDRDPA (DPA data rate) TCCS SW Output jitter Output tRISE Output tFALL tDUTY DPA run length DPA jitter tolerance (peak-to-peak) DPA lock time J = 4 to 10 (LVDS, HyperTransport technology) All differential standards All differential standards -- All differential I/O standards All differential I/O standards -- -- -- Standard -- SPI4 Parallel Rapid I/O -- Miscellaneous -- Training Pattern -- 0000000000 1111111111 10010000 10010000 10101010 10101010 Notes to Table 4-41: (1) (2) (3) When J = 4 to 10, the SERDES block is used. When J = 1 or 2, the SERDES block is bypassed. The input clock frequency and the W factor must satisfy the following fast PLL VCO specification: 150 input clock frequency x W 1,040. The minimum specification is dependent on the clock source (fast PLL, enhanced PLL, clock pin, and so on) and the clock routing resource (global, regional, or local) used. The I/O differential buffer and input register do not have a minimum toggle rate. 4-38 Altera Corporation September 2008 PLL Timing Specifications PLL Timing Specifications Tables 4-42 and 4-43 describe the HardCopy II PLL specifications when operating in both the commercial junction temperature range (0 to 85 C) and the industrial junction temperature range (-40 to 100 C), except for the clock switchover feature. Like the Stratix II devices, the clock switchover feature is only supported from the 0 to 100 C junction temperature range. Table 4-42. HardCopy II Enhanced PLL Specifications (Part 1 of 2) Name fIN Description Input clock frequency for HC210, HC220, HC230 and HC240 devices Input clock frequency for the HC210W device Min 2 2 2 40 40 -- Typ -- -- -- -- -- 0.5 Max 500 320 (1) 420 60 60 -- Unit MHz MHz MHz % % ns (pp) ns (pp) ps or mUI fINPFD fINDUTY fEINDUTY tINJITTER Input frequency to the PFD Input clock duty cycle External feedback input clock duty cycle Input or external feedback clock input jitter tolerance in terms of period jitter. Bandwidth 0.85 MHz Input or external feedback clock input jitter tolerance in terms of period jitter. Bandwidth > 0.85 MHz -- 1 -- tOUTJITTER Dedicated clock output period jitter for HC210, HC220, HC230 and HC240 devices Dedicated clock output period jitter for HC210W device -- -- 250 ps for 100 MHz outclk 25 mUI for < 100 MHz outclk 300 ps for 100 MHz outclk 30 mUI for < 100 MHz outclk 10 550 55 100 -- (1) -- -- ps or mUI tFCOMP fOUT tOUTDUTY fSCANCLK tCONFIGEPLL fOUT_EXT External feedback compensation time Output frequency for internal global or regional clock Duty cycle for external clock output (when set to 50%). Scanclk frequency Time required to reconfigure scan chains for enhanced PLLs PLL external clock output frequency -- 1.5 (2) 45 -- -- 1.5 (2) -- -- 50 -- 174/fSCANCLK -- ns MHz % MHz ns MHz Altera Corporation September 2008 4-39 HardCopy Series Handbook, Volume 1 Table 4-42. HardCopy II Enhanced PLL Specifications (Part 2 of 2) Name tLOCK Description Time required for the PLL to lock from the time it is enabled or the end of device configuration Time required for the PLL to lock dynamically after automatic clock switchover between two identical clock frequencies Frequency range where the clock switchover performs properly PLL closed loop bandwidth PLL VCO operating range for HC210, HC220, HC230 and HC240 devices PLL VCO operating range for HC210W devices Min -- Typ 0.03 Max 1 Unit ms tDLOCK -- -- 1 ms fSWITCHOVER fCLKW fVCO 4 0.13 300 -- 1.2 -- 500 16.9 1,040 MHz MHz MHz 300 100 0.4 -- 10 (3) 500 (4) 500 -- -- 0.5 -- -- -- -- 840 500 0.6 15 -- -- -- MHz MHz % ps ns ns ns fSS % spread tPLL_PSERR tARESET tARESET_RECONFIG Spread spectrum modulation frequency Percent down spread for a given clock frequency Accuracy of PLL phase shift Minimum pulse width on ARESET signal. Minimum pulse width on the areset signal when using PLL reconfiguration. Reset the PLL after scan done goes high. Notes to Table 4-42: (1) (2) (3) (4) Limited by I/O fMAX. If the counter cascading feature of the PLL is used, there is no minimum output clock frequency. Applicable when the PLL input clock has been running continuously for at least 10 s. Applicable when the PLL input clock has stopped toggling or has been running continuously for less than 10 s. 4-40 Altera Corporation September 2008 PLL Timing Specifications Table 4-43. HardCopy II Fast PLL Specifications (Part 1 of 2) Name fIN Description Input clock frequency for HC210, HC220, HC230 and HC240 devices Input clock frequency for the HC210W device Min 16 16 16 40 -- -- 300 300 150 150 4.6875 150 Typ -- -- -- -- 0.5 1 -- -- -- -- -- -- Max 717 320 (1) 500 60 -- -- 1,040 840 520 420 550 1,040 Unit MHz MHz MHz % ns (pp) ns (pp) MHz MHz MHz MHz MHz MHz fINPFD fINDUTY tINJITTER Input frequency to the PFD Input clock duty cycle Input clock jitter tolerance in terms of period jitter. Bandwidth 2 MHz Input clock jitter tolerance in terms of period jitter. Bandwidth > 0.2 MHz fVCO Upper VCO frequency range for HC210, HC220, HC230 and HC240 devices Upper VCO frequency range for HC210W devices Lower VCO frequency range for HC210, HC220, HC230 and HC240 devices Lower VCO frequency range for HC210W device fOUT PLL output frequency to GCLK or RCLK PLL output frequency to LVDS or DPA clock for HC210, HC220, HC230 and HC240 devices PLL output frequency to LVDS or DPA clock for HC210W devices 150 4.6875 -- 1.16 -- -- -- 75/fSCANCLK 5 0.03 840 (1) -- 28 1 MHz MHz ns MHz ms fOUT_IO tCONFIGPLL fCLBW tLOCK PLL clock output frequency to regular I/O pin Time required to reconfigure scan chains for fast PLLs PLL closed loop bandwidth Time required for the PLL to lock from the time it is enabled or the end of the device configuration Accuracy of PLL phase shift Minimum pulse width on areset signal. tPLL_PSERR tARESET -- 10 -- -- 30 -- ps ns Altera Corporation September 2008 4-41 HardCopy Series Handbook, Volume 1 Table 4-43. HardCopy II Fast PLL Specifications (Part 2 of 2) Name Description Min 500 Typ -- Max -- Unit ns tARESET_RECONFIG Minimum pulse width on the areset signal when using PLL reconfiguration. Reset the PLL after scan done goes high. Note to Table 4-43: (1) Limited by I/O fMAX. External Memory Interface Specifications Table 4-44 summarizes the maximum clock rate that HardCopy II devices can support with external memory devices. Table 4-44. HardCopy II Maximum Clock Rate Support for External Memory Interfaces HardCopy II Device Memory Standards Wire Bond Package HC210W (2) Com (C) DDR DDR2 (7) QDRII (6) RLDRAMII (6) Notes to Table 4-44: (1) (2) (3) (4) (5) (6) (7) Note (1) Flip Chip Package HC210 / HC220 / HC230 / HC240 (3) Com (C) 200 267 250 250 (4) Unit Ind (I) 133 133 133 133 Ind (I) 200 233 233 (5) 233 (4) MHz MHz MHz MHz 150 150 150 150 HardCopy II devices do not support PLL-based external memory interface except for SDR SDRAMs which do not require the DLL. HC210W supports memory interface on the top I/O banks. HC210 and HC220 support memory interface on the top I/O banks. HC230 and HC240 support memory interface on the top and bottom I/O banks. You will need to under-clock a 300 MHz memory device. You will need to under-clock a 250 MHz memory device. Based on a DDIO scheme with the 1.8-V HSTL I/O standard. Based on the PLL dedicated scheme. Use the same FMAX specification for Static-PHY and Auto-PHY since the write-side is limited by the new tDS/tH specification. 4-42 Altera Corporation September 2008 External Memory Interface Specifications Tables 4-45 through 4-51 contain HardCopy II device specifications for the dedicated circuitry used for interfacing with external memory devices. Table 4-45. DLL Frequency Range Specifications Frequency Mode 0 1 2 3 Frequency Range 100 to 175 150 to 230 200 to 310 240 to 350 Resolution (Degrees) 30 22.5 30 36 Table 4-46 lists the maximum delay in the fast timing model for the HardCopy II DQS delay buffer. Multiply the number of delay buffers that you are using in the DQS logic block to get the maximum delay achievable in your system. For example, if you implement a 90 phase shift at 200 MHz, you use three delay buffers in mode 2. The maximum achievable delay from the DQS block is then 3 x .416 ps = 1.248 ns. Table 4-46. DQS Delay Buffer Maximum Delay in Fast Timing Model DLL Frequency Mode Maximum Delay Per Delay Buffer 0 1, 2, 3 0.833 0.416 Unit ns ns Table 4-47. DQS Period Jitter Specifications for DLL-Delayed Clock (tDQS_JITTER) Note (1) Number of DQS Delay Buffer Stages (2) 1 2 3 4 Notes to Table 4-47: (1) (2) Peak-to-peak period jitter on the phase shifted DQS clock. Delay stages used for requested DQS phase shift are reported in your project's Compilation Report in the Quartus II software. Commercial 80 110 130 160 Industrial 110 130 180 210 Unit ps ps ps ps Altera Corporation September 2008 4-43 HardCopy Series Handbook, Volume 1 Table 4-48. DQS Phase Jitter Specifications for DLL-Delayed Clock (tDQS PHASE_JITTER) Note (1) Number of DQS Delay Buffer Stages (2) 1 2 3 4 Notes to Table 4-48: (1) (2) Peak-to-peak phase jitter on the phase shifted DDS clock (digital jitter is caused by DLL tracking). Delay stages used for requested DQS phase shift are reported in your project's Compilation Report in the Quartus II software. DQS Phase Jitter 30 60 90 120 Unit ps ps ps ps Table 4-49. DQS Phase-Shift Error Specifications for DLL-Delayed Clock (tDQS_PSERR) Note (1) Number of DQS Delay Buffer Stages (2)) 1 2 3 4 Notes to Table 4-49: (1) This error specification is the absolute maximum and minimum error. For example, skew on three delay buffer stages with an HC240 device is 105 ps or 52.5 ps. Delay stages used for requested DQS phase shift are reported in your project's Compilation Report in the Quartus II software. HC210, HC220, HC230 HC240 30 60 90 120 Unit ps ps ps ps (2) 4-44 Altera Corporation September 2008 Hot Socketing Table 4-50. DQS Bus Clock Skew Adder Specifications (tDQS_CLOCK_SKEW_ADDER) Note (1) Mode x4 DQ per DQS x9 DQ per DQS x18 DQ per DQS x36 DQ per DQS Note to Table 4-50: (1) This skew specification is the absolute maximum and minimum skew. For example, skew on a x4 DQ group is 40 ps or 20 ps. DQS Clock Skew Adder 40 70 75 95 Unit ps ps ps ps Table 4-51. DQS Phase Offset Delay Per Stage Note (1) HardCopy II Devices All Note to Table 4-51 (1) The delay settings are linear. The valid settings for phase offset are -64 to +63 for frequency mode 0 and -32 to +31 for frequency modes 1, 2, and 3. The typical value equals the average of the minimum and maximum values. Min 9 Max 14 Unit ps Hot Socketing HardCopy II devices offer hot socketing, which is also known as hot plug-in or hot swap, and power sequencing support without the use of any external devices. You can insert or remove a HardCopy II device in a system during system operation without causing undesirable effects to the running system bus or the board that was inserted into the system. The hot socketing feature in HardCopy II devices allow: The device can be driven before power-up without any damage to the device itself. I/O pins remain tri-stated during power-up, so they do no disrupt bus operation when HardCopy II I/Os are inserted in the system. Signal pins do not drive the VCCIO, VCCPD, or VCCINT power supplies. External input signals to I/O pins of the device do not internally power the VCCIO or VCCINT power supplies of the device via internal paths within the device. Altera Corporation September 2008 4-45 HardCopy Series Handbook, Volume 1 In a hot socketing situation, a device's output buffers are turned off during system power-up or power-down. To simplify board design, HardCopy II devices support any power-up or power-down sequence (VCCIO and VCCINT). For mixed-voltage environments, you can drive signals into the device before or during power-up or power-down without damaging the device. You can power up or power down the VCCIO and VCCINT pins in any sequence. The power supply ramp rates can range from 100 ns to 100 ms. All VCC supplies must power down within 100 ms of each other to prevent the I/O pins from driving out. During hot socketing, the I/O pin capacitance is less than 15 pF and the clock pin capacitance is less than 20 pF. The hot socketing DC specification is | IIOPIN | < 300 A. The hot socketing AC specification is | IIOPIN | < 8 mA for 10 ns or less. The DC specification applies when all VCC supplies to the device are stable in the powered-up or powered-down conditions. The AC specification applies when the device is being powered up or powered down in any of the conditions mentioned above. 1 Electrostatic Discharge Electrostatic discharge (ESD) protection is a design practice that is integrated in Altera FPGAs and structured ASIC devices. HardCopy II devices are no exception, and they are designed with ESD protection on all I/O and power pins. 4-46 Altera Corporation September 2008 Electrostatic Discharge Figure 4-3 shows a typical HardCopy II CMOS I/O buffer structure which will be used to explain ESD protection. Figure 4-3. Transistor-Level Diagram of HardCopy II Device I/O Buffers The CMOS output drivers in the I/O pins intrinsically provide electrostatic discharge protection. There are two cases to consider for ESD voltage strikes: positive voltage zap and negative voltage zap. A positive ESD voltage zap occurs when a positive voltage is present on an I/O pin due to an ESD charge event. This can cause the N+ (Drain)/PSubstrate junction of the N-channel drain to break down and the N+ (Drain)/P-Substrate/N+ (Source) intrinsic bipolar transistor turns on to discharge ESD current from I/O pin to GND. Altera Corporation September 2008 4-47 HardCopy Series Handbook, Volume 1 The dashed line (see Figure 4-4) shows the ESD current discharge path during a positive ESD zap. Figure 4-4. ESD Protection During Positive Voltage Zap When the I/O pin receives a negative ESD zap at the pin that is less than -0.7 V (0.7 V is the voltage drop across a diode), the intrinsic P-Substrate/N+ drain diode is forward biased. Hence, the discharge ESD current path is from GND to the I/O pin, as shown in Figure 4-5. Figure 4-5. ESD Protection During Negative Voltage Zap 4-48 Altera Corporation September 2008 Document Revision History f Details of ESD protection are also outlined in the Hot-Socketing and Power-Sequencing Feature and Testing for Altera Devices white paper located on the Altera website at www.altera.com. For information on ESD results of Altera products, please see the Reliability Report on the Altera website at www.altera.com. Table 4-52 shows the revision history for this chapter. f Document Revision History Table 4-52. Document Revision History Date and Document Version Changes Made Summary of Changes -- Minor updates to correct information in tables. September 2008, v3.3 Updated chapter number and metadata. September 2007 v3.2 Updated Table 4-33 and Table 4-34. Updated drive strength value in Table 4-36. Changed fIN and fINPFD from 4 to 2 MHz in Table 4-42. Added industrial values to Table 4-44. Changed V to VIH in Table 4-16 Updated data for VIH in Table 4-17 Added Table 4-29 Updated Table 4-44 June 2007 v3.1 -- December 2006 v3.0 Major updates with new electrical characterization data Updated data in Table 4-1, Table 4-3, Table 4-4, Table 4-5,Table 4-10, Table 4-12, Table 4-13, Table 4-19, Table 4-20, Table 4-27 to Table 4-31. Added Table 4-11 and Tables 4-36 to Table 4-50. Merged Tables 4-27 to Table 4-32 into new Tables 4-32 to Table 4-33. Merged Tables 4-33 to Table 4-36 into new Tables 4-34 to Table 4-35. Added revision history Updated graphics. Updated various tables throughout chapter. Added document to the HardCopy Series Handbook. A major update to the chapter due to new electrical characterization data availability. October 2005, v2.1 May 2005, v2.0 January 2005 v1.0 -- -- -- Altera Corporation September 2008 4-49 HardCopy Series Handbook, Volume 1 4-50 Altera Corporation September 2008 5. Quartus II Support for HardCopy II Devices H51022-2.5 HardCopy II Device Support Altera(R) HardCopy(R) II devices feature 1.2-V, 90 nm process technology, and provide a structured ASIC alternative to increasingly expensive multi-million gate ASIC designs. The HardCopy II design methodology offers a fast time-to-market schedule, providing ASIC designers with a solution to long ASIC development cycles. Using the Quartus(R) II software, you can leverage a Stratix(R) II FPGA as a prototype and seamlessly migrate your design to a HardCopy II device for production. This document discusses the following topics: "HardCopy II Development Flow" on page 5-3 "HardCopy II Device Resource Guide" on page 5-7 "HardCopy II Recommended Settings in the Quartus II Software" on page 5-12 "HardCopy II Utilities Menu" on page 5-25 For more information about HardCopy II, HardCopy Stratix, and HardCopy APEXTM devices, refer to the respective device data sheets in the HardCopy Series Handbook. 1 HardCopy II Design Benefits Designing with HardCopy II structured ASICs offers substantial benefits over other structured ASIC offerings: Prototyping using a Stratix II FPGA for functional verification and system development reduces total project development time Seamless migration from a Stratix II FPGA prototype to a HardCopy II device reduces time to market and risk Unified design methodology for Stratix II FPGA design and HardCopy II design reduces the need for ASIC development software Low up-front development cost of HardCopy II devices reduces the financial risk to your project Altera Corporation September 2008 5-1 Preliminary HardCopy Series Handbook, Volume 1 Quartus II Features for HardCopy II Planning With the Quartus II software you can design a HardCopy II device using a Stratix II device as a prototype. The Quartus II software contains the following expanded features for HardCopy II device planning: HardCopy II Companion Device Assignment--Identifies compatible HardCopy II devices for migration with the Stratix II device currently selected. 1 This feature constrains the pins of your Stratix II FPGA prototype making it compatible with your HardCopy II device. It also constrains the correct resources available for the HardCopy II device making sure that your Stratix II FPGA design does not become incompatible. In addition, you are still required to compile the design targeting the HardCopy II device to ensure that the design fits, routes, and meets timing. HardCopy II Utilities--The HardCopy II Utilities functions create or overwrites HardCopy II companion revisions, change revisions to use, and compare revisions for equivalency. HardCopy II Advisor--The HardCopy II Advisor helps you follow the necessary steps to successfully submit a HardCopy II design to Altera's HardCopy Design Center. 1 The HardCopy II Advisor is similar to the Resource Optimization Advisor and Timing Optimization Advisor. The HardCopy II Advisor provides guidelines you can follow during development, reporting the tasks completed as well as the tasks that remain to be completed during development HardCopy II Floorplan--The Quartus II software can show a preliminary floorplan view of your HardCopy II design's Fitter placement results. HardCopy II Design Archiving--The Quartus II software archives the HardCopy II design project's files needed to handoff the design to the HardCopy Design Center. 1 This feature is similar to the Quartus II software HardCopy Files Wizard used for HardCopy Stratix and HardCopy APEX families. 5-2 Altera Corporation September 2008 HardCopy II Development Flow HardCopy II Device Preliminary Timing--The Quartus II software performs a timing analysis of HardCopy II devices based on preliminary timing models and Fitter placements. Final timing results for HardCopy II devices are provided by the HardCopy Design Center. HardCopy II Handoff Report---The Quartus II software generates a handoff report containing information about the HardCopy II design used by the HardCopy Design Center in the design review process. Formal Verification--Cadence Encounter Conformal software can now perform formal verification between the source RTL design files and post-compile gate level netlist from a HardCopy II design. HardCopy II Development Flow In the Quartus II software, you have two methods for designing your Stratix II FPGA and HardCopy II companion device together in one Quartus II project. Design the HardCopy II device first, and create the Stratix II FPGA companion device second and build your prototype for in-system verification Design the Stratix II FPGA first and create a HardCopy II companion device second Both of these flows are illustrated at a high level in Figure 5-1. The added features in the HardCopy II Utilities menu assist you in completing your HardCopy II design for submission to Altera's HardCopy Design Center for back-end implementation. Altera Corporation September 2008 5-3 HardCopy Series Handbook, Volume 1 Figure 5-1. HardCopy II Flow in Quartus II Software Prepare Design HDL Design Stratix II First Design Stratix II Second Yes Select Stratix II Device & HardCopy II Companion Device Design Stratix II First? No Select HardCopy II Device & Stratix II Companion Device Complete Stratix II Device First Flow (1) In-System Verification of Stratix II FPGA Design Compare Stratix II & HardCopy II Design Revisions Complete HardCopy II Device First Flow (2) Generate HardCopy II Archive Handoff Design Archive for Back-End Migration Notes for Figure 5-1: (1) (2) Refer to Figure 5-2 for an expanded description of this process. Refer to Figure 5-3 for an expanded description of this process. Designing the Stratix II FPGA First The HardCopy II development flow beginning with the Stratix II FPGA prototype is very similar to a traditional Stratix II FPGA design flow, but requires a few additional tasks be performed to migrate the design to the HardCopy II companion device. To design your HardCopy II device using the Stratix II FPGA as a prototype, complete the following tasks: Specify a HardCopy II device for migration Compile the Stratix II FPGA design Create and compile the HardCopy II companion revision Compare the HardCopy II companion revision compilation to the Stratix II device compilation Figure 5-2 provides an overview highlighting the development process for designing with a Stratix II FPGA first and creating a HardCopy II companion device second. 5-4 Altera Corporation September 2008 HardCopy II Development Flow Figure 5-2. Designing Stratix II Device First Flow Stratix II Prototype Device Development Phase Prepare Stratix II Design Select Stratix II Companion Device Review HardCopy II Advisor Apply Design Constraints In-System Verification Compile Stratix II Design Any Violations? No Yes Fix Violations Create or Overwrite HardCopy II Companion Revision HardCopy II Companion Device Development Phase Compile HardCopy II Companion Revision Select a Larger HardCopy II Companion Device? Fits in HardCopy II Device? Compare Stratix II & HardCopy II Revisions Any Violations? No Design Submission & Back-End Implementation Phase Generate Handoff Report Yes Archive Project for Handoff Prototype your HardCopy II design by selecting and then compiling a Stratix II device in the Quartus II software. After you compile the Stratix II design successfully, you can view the HardCopy II Device Resource Guide in the Quartus II software Fitter report to evaluate which HardCopy II devices meet your design's resource requirements. When you are satisfied with the compilation results and the choice of Stratix II and HardCopy II devices, on the Assignments menu, click Settings. In the Category list, select Device. In the Device page, select a HardCopy II companion device. Altera Corporation September 2008 5-5 HardCopy Series Handbook, Volume 1 After you select your HardCopy II companion device, do the following: Review the HardCopy II Advisor for required and recommended tasks to perform Enable Design Assistant to run during compilation Add timing and location assignments Compile your Stratix II design Create your HardCopy II companion revision Compile your design for the HardCopy II companion device Use the HardCopy II Utilities to compare the HardCopy II companion device compilation with the Stratix II FPGA revision Generate a HardCopy II Handoff Report using the HardCopy II Utilities Generate a HardCopy II Handoff Archive using the HardCopy II Utilities Arrange for submission of your HardCopy II handoff archive to Altera's HardCopy Design Center for back-end implementation f For more information about the overall design flow using the Quartus II software, refer to the Introduction to Quartus II manual on the Altera website at www.altera.com. Designing the HardCopy II Device First The HardCopy II family presents a new option in designing unavailable in previous HardCopy families. You can design your HardCopy II device first and create your Stratix II FPGA prototype second in the Quartus II software. This allows you to see your potential maximum performance in the HardCopy II device immediately during development, and you can create a slower performing FPGA prototype of the design for in-system verification. This design process is similar to the traditional HardCopy II design flow where you build the FPGA first, but instead, you merely change the starting device family. The remaining tasks to complete your design for both Stratix II and HardCopy II devices roughly follow the same process (Figure 5-3). The HardCopy II Advisor adjusts its list of tasks based on which device family you start with, Stratix II or HardCopy II, to help you complete the process seamlessly. 5-6 Altera Corporation September 2008 HardCopy II Device Resource Guide Figure 5-3. Designing HardCopy II Device First Flow HardCopy II Device Development Phase Prepare HardCopy II Design Select Stratix II Companion Device Review HardCopy II Advisor Apply Design Constraints Compile HardCopy II Design Any Violations? No Yes Fix Violations Create or Overwrite Stratix II Companion Revision Stratix II Companion Device Development Phase In-System Verification Compile Stratix II Companion Revision Compare HardCopy II & Stratix II Revisions Any Violations? No Design Submission & Back-End Implementation Phase Generate Handoff Report Yes Generate HardCopy II Archive for Handoff HardCopy II Device Resource Guide The HardCopy II Device Resource Guide compares the resources required to successfully compile a design with the resources available in the various HardCopy II devices. The report rates each HardCopy II device and each device resource for how well it fits the design. The Quartus II software generates the HardCopy II Device Resource Guide for all designs successfully compiled for Stratix II devices. This guide is found in the Fitter folder of the Compilation Report. Figure 5-4 shows an example of the HardCopy II Device Resource Guide. Refer to Table 5-1 for an explanation of the color codes in Figure 5-4. Altera Corporation September 2008 5-7 HardCopy Series Handbook, Volume 1 Figure 5-4. HardCopy II Device Resource Guide Use this report to determine which HardCopy II device is a potential candidate for migration of your Stratix II design. The HardCopy II device package must be compatible with the Stratix II device package. A logic resource usage greater than 100% or a ratio greater than 1/1 in any category indicates that the design does not fit in that particular HardCopy II device. 5-8 Altera Corporation September 2008 HardCopy II Device Resource Guide Table 5-1. HardCopy II Device Resource Guide Color Legend Color Package Resource (1) The design can migrate to the Hardcopy II package and the design has been fitted with target device migration enabled in the HardCopy II Companion Device dialog box. Device Resources The resource quantity is within the range of the HardCopy II device and the design can likely migrate if all other resources also fit. You are still required to compile the HardCopy II revision to make sure the design is able to route and migrate all other resources. Green (High) The design can migrate to the Hardcopy II package. However, the design has not been fitted with target device migration enabled in the HardCopy II Companion Device dialog box. The resource quantity is within the range of the HardCopy II device. However, the resource is at risk of exceeding the range for the HardCopy II package. If your target HardCopy II device falls in this category, compile your design targeting the HardCopy II device as soon as possible to check if the design fits and is able to route and migrate all other resources. You may need to migrate to a larger device. Orange (Medium) Red (None) The design cannot migrate to the Hardcopy II package. The resource quantity exceeds the range of the HardCopy II device. The design cannot migrate to this HardCopy II device. Note to Table 5-1: (1) The package resource is constrained by the Stratix II FPGA for which the design was compiled. Only vertical migration devices within the same package are able to migrate to HardCopy II devices. The HardCopy II architecture consists of an array of fine-grained HCells, which are used to build logic equivalent to Stratix II adaptive logic modules (ALMs) and digital signal processing (DSP) blocks. The DSP blocks in HardCopy II devices match the functionality of the Stratix II DSP blocks, though timing of these blocks is different than the FPGA DSP blocks because they are constructed of HCell Macros. The M4K and M-RAM memory blocks in HardCopy II devices are equivalent to the Stratix II memory blocks. Preliminary timing reports of the HardCopy II device are available in the Quartus II software. Final timing results of the HardCopy II device are provided by the HardCopy Design Center after back-end migration is complete. f For more information about the HardCopy II device resources, refer to the Introduction to HardCopy II Devices and the Description, Architecture and Features chapters in the HardCopy II Device Family Data Sheet in the HardCopy Series Handbook. Altera Corporation September 2008 5-9 HardCopy Series Handbook, Volume 1 The report example in Figure 5-4 shows the resource comparisons for a design compiled for a Stratix II EP2S130F1020 device. Based on the report, the HC230F1020 device in the 1,020-pin FineLine BGA(R) package is an appropriate HardCopy II device to migrate to. If the HC230F1020 device is not specified as a migration target during the compilation, its package and migration compatibility is rated orange, or Medium. The migration compatibilities of the other HardCopy II devices are rated red, or None, because the package types are incompatible with the Stratix II device. The 1,020-pin FBGA HC240 device is rated red because it is only compatible with the Stratix II EP2S180F1020 device. Figure 5-5 shows the report after the (unchanged) design was recompiled with the HardCopy II HC230F1020 device specified as a migration target. Now the HC230F1020 device package and migration compatibility is rated green, or High. Figure 5-5. HardCopy II Device Resource Guide with Target Migration Enabled HardCopy II Companion Device Selection In the Quartus II software, you can select a HardCopy II companion device to help structure your design for migration from a Stratix II device to a HardCopy II device. To make your HardCopy II companion device selection, on the Assignments menu, click Settings. In the Settings dialog box in the Category list, select Device (Figure 5-6) and select your companion device from the Available devices list. Selecting a HardCopy II Companion device to go with your Stratix II prototype constrains the memory blocks, DSP blocks, and pin assignments, so that your Stratix II and HardCopy II devices are migration-compatible. Pin assignments are constrained in the Stratix II design revision so that the HardCopy II device selected is pin-compatible. The Quartus II software also constrains the Stratix II design revision so it does not use M512 memory blocks or exceed the number of M-RAM blocks in the HardCopy II companion device. 5-10 Altera Corporation September 2008 HardCopy II Companion Device Selection Figure 5-6. Quartus II Settings Dialog Box You can also specify your HardCopy II companion device using the following tool command language (Tcl) command: set_global_assignment -name\ DEVICE_TECHNOLOGY_MIGRATION_LIST Altera Corporation September 2008 5-11 HardCopy Series Handbook, Volume 1 HardCopy II Recommended Settings in the Quartus II Software The HardCopy II development flow involves additional planning and preparation in the Quartus II software compared to a standard FPGA design. This is because you are developing your design to be implemented in two devices: a prototype of your design in a Stratix II prototype FPGA, and a companion revision in a HardCopy II device for production. You need additional settings and constraints to make the Stratix II design compatible with the HardCopy II device and, in some cases, you must remove certain settings in the design. This section explains the additional settings and constraints necessary for your design to be successful in both Stratix II FPGA and HardCopy II structured ASIC devices. Limit DSP and RAM to HardCopy II Device Resources On the Assignments menu, click Settings to view the Settings dialog box. In the Category list, select Device. In the Family list, select Stratix II. Under Companion device, Limit DSP and RAM to HardCopy II device resources is turned on by default (Figure 5-7). This maintains compatibility between the Stratix II and HardCopy II devices by ensuring your design does not use resources in the Stratix II device that are not available in the selected HardCopy II device. 1 If you require additional memory blocks or DSP blocks for debugging purposes using SignalTap(R) II, you can temporarily turn this setting off to compile and verify your design in your test environment. However, your final Stratix II and HardCopy II designs submitted to Altera for back-end migration must be compiled with this setting turned on. Figure 5-7. Limit DSP and RAM to HardCopy II Device Resources Check Box Enable Design Assistant to Run During Compile You must use the Quartus II Design Assistant to check all HardCopy series designs for design rule violations before submitting the designs to the Altera HardCopy Design Center. Additionally, you must fix all critical and high-level errors. 1 Altera recommends turning on the Design Assistant to run automatically during each compile, so that during development, you can see the violations you must fix. 5-12 Altera Corporation September 2008 HardCopy II Recommended Settings in the Quartus II Software f For more information about the Design Assistant and the rules it uses, refer to the Design Guidelines for HardCopy Series Devices chapter of the HardCopy Series Handbook. To enable the Design Assistant to run during compilation, on the Assignment menu, click Settings. In the Category list, select Design Assistant and turn on Run Design Assistant during compilation (Figure 5-8) or by entering the following Tcl command in the Tcl Console: set_global_assignment -name ENABLE_DRC_SETTINGS ON Figure 5-8. Enabling Design Assistant Timing Settings Beginning in Quartus II Software version 7.1, TimeQuest is the recommended timing analysis tool for all designs. Classic Timing Analyzer is no longer supported and the HardCopy Design Center will not accept any designs which use Classic Timing Analyzer for timing closure. If you are still using the Classic Timing Analyzer, Altera strongly recommends that you switch to TimeQuest. Altera Corporation September 2008 5-13 HardCopy Series Handbook, Volume 1 1 For more information on how to switch to TimeQuest, refer to the Switching to the TimeQuest Timing Analyzer chapter of the Quartus II Handbook, volume 3, on the Altera website at www.altera.com. When you specify the TimeQuest analyzer as the timing analysis tool, the TimeQuest analyzer guides the Fitter and analyzes timing results after compilation. TimeQuest The TimeQuest Timing Analyzer is a powerful ASIC-style timing analysis tool that validates timing in your design by using an industry-standard constraint, analysis, and reporting methodology. You can use the TimeQuest Timing Analyzer's GUI or command-line interface to constrain, analyze, and report results for all timing paths in your design. Before running the TimeQuest Timing Analyzer, you must specify initial timing constraints that describe the clock characteristics, timing exceptions, and signal transition arrival and required times. You can specify timing constraints in the Synopsys Design Constraints (SDC) file format using the GUI or command-line interface. The Quartus II Fitter optimizes the placement of logic to meet your constraints. During timing analysis, the TimeQuest Timing Analyzer analyzes the timing paths in the design, calculates the propagation delay along each path, checks for timing constraint violations, and reports timing results as slack in the Report pane and in the Console pane. If the TimeQuest Timing Analyzer reports any timing violations, you can customize the reporting to view precise timing information about specific paths, and then constrain those paths to correct the violations. When your design is free of timing violations, you can be confident that the logic will operate as intended in the target device. The TimeQuest Timing Analyzer is a complete static timing analysis tool that you can use as a sign-off tool for Altera FPGAs and structured ASICs. Setting Up the TimeQuest Timing Analyzer If you want use TimeQuest for timing analysis, from the Assignments tab in the Quartus II software, click on Timing Analysis Settings, and in the pop-up window, click the Use TimeQuest Timing Analyzer during compilation tab. 5-14 Altera Corporation September 2008 HardCopy II Recommended Settings in the Quartus II Software Use the following Tcl command to use TimeQuest as your timing analysis engine: set_global_assignment -name \ USE_TIMEQUEST_TIMING_ANALYZER ON You can launch the TimeQuest analyzer in one of the following modes: Directly from the Quartus II software Stand-alone mode Command-line mode In order to perform a thorough Static Timing Analysis, you would need to specify all the timing requirements. The most important timing requirements are clocks and generated clocks, input and output delays, false paths and multi-cycle paths, minimum and maximum delays. In TimeQuest, clock latency, and recovery and removal analysis are enabled by default. f For more information about TimeQuest, refer to the Quartus II TimeQuest Timing Analyzer chapter in volume 3 of the Quartus II Handbook on the Altera website at www.altera.com. Constraints for Clock Effect Characteristics The create_clock, create_generated_clock commands create ideal clocks and do not account for board effects. In order to account for clock effect characteristics, you can use the following commands: set_clock_latency set_clock_uncertainty For more information about how to use these commands, refer to the Quartus II TimeQuest Timing Analyzer chapter in volume 3 of the Quartus II Handbook. 1 Beginning in Quartus II version 7.1, you can use the new command derive_clock_uncertainty to automatically derive the clock uncertainties. This command is useful when you are not sure what the clock uncertainties might be. The calculated clock uncertainty values are based on I/O buffer, static phase errors (SPE) and jitter in the PLL's, clock networks, and core noises. Altera Corporation September 2008 5-15 HardCopy Series Handbook, Volume 1 The derive_clock_uncertainty command applies inter-clock, intra-clock, and I/O interface uncertainties. This command automatically calculates and applies setup and hold clock uncertainties for each clock-to-clock transfer found in your design. In order to get I/O interface uncertainty, you must create a virtual clock, then assign delays to the input/output ports by using the set_input_delay and set_output_delay commands for that virtual clock. 1 These uncertainties are applied in addition to those you specified using the set_clock_uncertainty command. However, if a clock uncertainty assignment for a source and destination pair was already defined, the new one will be ignored. In this case, you can use either the -overwrite command to overwrite the previous clock uncertainty command or manually remove them by using the remove_clock_uncertainty command. The syntax for the derive_clock_uncertainty is as follows: derive_clock_uncertainty [-h | -help] [-long_help] [-dtw] [-overwrite] where the arguments are listed in Table 5-2: Table 5-2. Arguments for derive_clock_uncertainty Option -h | -help -long_help -dtw -overwrite Short help Long help with examples and possible return values Creates PLLJ_PLLSPE_INFO.txt file Overwrites previously performed clock uncertainty assignments Description When the dtw option is used, a PLLJ_PLLSPE_INFO.txt file is generated. This file lists the name of the PLLs, as well as their jitter and SPE values in the design. This text file can be used by HCII_DTW_CU_Calculator. When this option is used, clock uncertainties are not calculated. f For more information on the derive_clock_uncertainty command, refer to the Quartus II TimeQuest Timing Analyzer chapter in volume 3 of the Quartus II Handbook. 5-16 Altera Corporation September 2008 HardCopy II Recommended Settings in the Quartus II Software Altera strongly recommends that you use the derive_clock_uncertainty command in the HardCopy II revision. The HardCopy Design Center will not be accepting designs that do not have clock uncertainty constraint by either using the derive_clock_uncertainty command or the HardCopy II Clock Uncertainty Calculator, and then using the set_clock_uncertainty command. For more information on how to use the HardCopy II Clock Uncertainty Calculator, refer to the HardCopy II Clock Uncertainty User Guide available on the Altera website at www.altera.com. Quartus II Software Features Supported for HardCopy II Designs The Quartus II software supports optimization features for HardCopy II prototype development, including: Physical Synthesis Optimization LogicLock Regions PowerPlay Power Analyzer Incremental Compilation (Synthesis and Fitter) Maximum Fan-Out Assignments Physical Synthesis Optimization To enable Physical Synthesis Optimizations for the Stratix II FPGA revision of the design, on the Assignments menu, click Settings. In the Settings dialog box, in the Category list, select Fitter Settings. These optimizations are migrated into the HardCopy II companion revision for placement and timing closure. When designing with a HardCopy II device first, physical synthesis optimizations can be enabled for the HardCopy II device, and these post-fit optimizations are migrated to the Stratix II FPGA revision. LogicLockTM Regions The use of LogicLock Regions in the Stratix II FPGA is supported for designs migrating to HardCopy II. However, LogicLock Regions are not passed into the HardCopy II Companion Revision. You can use LogicLock in the HardCopy II design but you must create new LogicLock Regions in the HardCopy II companion revision. In addition, LogicLock Regions in HardCopy II devices can not have their properties set to Auto Size. However, Floating LogicLock regions are supported. HardCopy II LogicLock Regions must be manually sized and placed in the floorplan. When LogicLock Regions are created in a HardCopy II device, they start with width and height dimensions set to (1,1), and the origin coordinates for placement are at X1_Y1 in the lower left corner of Altera Corporation September 2008 5-17 HardCopy Series Handbook, Volume 1 the floorplan. You must adjust the size and location of the LogicLock Regions you created in the HardCopy II device before compiling the design. f For information about using LogicLock Regions, refer to the Quartus II Analyzing and Optimizing Design Floorplan chapter in volume 2 of the Quartus II Handbook. PowerPlay Power Analyzer You can perform power estimation and analysis of your HardCopy II and Stratix II devices using the PowerPlay Early Power Estimator. Use the PowerPlay Power Analyzer for more accurate estimation of your device's power consumption. The PowerPlay Early Power Estimator is available in the Quartus II software version 5.1 and later. The PowerPlay Power Analyzer supports HardCopy II devices in version 6.0 and later of the Quartus II software. f For more information about using the PowerPlay Power Analyzer, refer to the Quartus II PowerPlay Power Analysis chapter in volume 3 of the Quartus II Handbook on the Altera website at www.altera.com. Incremental Compilation The use of the Quartus II Incremental Compilation in the Stratix II FPGA is supported when migrating a design to a HardCopy II device. Incremental compilation is supported in the Stratix II First design flow or HardCopy II First design flow. To take advantage of Quartus II Incremental Compilation, organize your design into logical and physical partitions for synthesis and fitting (or place-and-route). Incremental compilation preserves the compilation results and performance of unchanged partitions in your design. This feature dramatically reduces your design iteration time by focusing new compilations only on changed design partitions. New compilation results are then merged with the previous compilation results from unchanged design partitions. You can also target optimization techniques, such as physical synthesis, to specific partitions while leaving other partitions untouched. In addition, be aware of the following guidelines: User partitions and synthesis results are migrated to a companion device. LogicLock regions are suggested for user partitions, but are not migrated automatically. 5-18 Altera Corporation September 2008 Performing ECOs with Change Manager and Chip Planner The first compilation after migration to a companion device requires a full compilation (all partitions are compiled), but subsequent compilations can be incremental if changes to the source RTL are not required. For example, PLL phase changes can be implemented incrementally if the blocks are partitioned. The entire design must be migrated between Stratix II and HardCopy II companion devices. The Quartus II software does not support migration of partitions between companion devices. Bottom-up Quartus II Incremental Compilation is not supported for HardCopy II devices. Physical Synthesis can be run on individual partitions within the originating device only. The resulting optimizations are preserved in the migration to the companion device. f For information about using Quartus II Incremental Compilation, refer to the Quartus II Incremental Compilation for Hierarchical and Team-Based Design chapter in volume 1 of the Quartus II Handbook. Maximum Fanout Assignments This feature is supported beginning in Quartus II 6.1. In order to meet timing, it may be necessary to limit the number of fanouts of a net in your design. You can limit the maximum fanout of a given net by using this feature. For example, you can use the following Tcl command to enable the maximum fanout setting: set_instance_assignment -name MAX_FANOUT For example, if you want to limit the maximum fanout of net called "m3122_combout_1" to 25, the Tcl command is as follows: set_instance_assignment -name MAX_FANOUT 25 -to\ m3122_combout_1 Performing ECOs with Change Manager and Chip Planner Altera Corporation September 2008 As designs grow larger and larger in density, the need to analyze the design for performance, routing congestion, logic placement, and executing Engineering Change Orders (ECOs) becomes critical. In addition to design analysis, you can use various bottom-up and top-down flows to implement and manage the design. This becomes difficult to manage since ECOs are often implemented as last minute changes to your design. 5-19 HardCopy Series Handbook, Volume 1 With the Altera(R) Chip Planner tool, you can shorten the design cycle time significantly. When changes are made to your design as ECOs, you do not have to perform a full compilation in the Quartus II software. Instead, you would make changes directly to the post place-and-route netlist, generate a new programming file, test the revised design by performing a gate-level simulation and timing analysis, and proceed to verify the fix on the system (if you are using a Stratix II FPGA as a prototype). Once the fix has been verified on the Stratix II FPGA, switch to the HardCopy II revision, apply the same ECOs, run the timing analyzer and assembler, perform a revision compare and then run the HardCopy II Netlist Writer for design submission. There are three scenarios from a migration point of view: There are changes which can map one-to-one (that is, the same change can be implemented on each architecture--Stratix II FPGA and HardCopy II). There are changes that must be implemented differently on the two architectures to achieve the same result. There are some changes that cannot be implemented on both architectures. The following sections outline the methods for migrating each of these types of changes. Migrating One-to-One Changes One-to-one changes are implemented using identical commands in both architectures. In general, such changes include those that affect only I/O cells or PLL cells. Some examples of one-to-one changes are changes such as creating, deleting or moving pins, changing pin or PLL properties, or changing pin connectivity (provided the source and destination of the connectivity changes are I/Os or PLLs). These can be implemented identically on both architectures. If such changes are exported to Tcl, a direct reapplication of the generated Tcl script (with a minor text edit) on the companion revision should implement the appropriate changes as follows: Export the changes from the Change Manager to Tcl. Open the generated Tcl script, change the line "project_open 5-20 Altera Corporation September 2008 Performing ECOs with Change Manager and Chip Planner A partial list of examples of this type are as follows: I/O creation, deletion, and moves I/O property changes (for example, I/O standards, delay chain settings, etc.) PLL property changes Connectivity changes between non-LCELL_COMB atoms (for example, PLL to I/O, DSP to I/O, etc.) Migrating Changes that must be Implemented Differently Some changes must be implemented differently on the two architectures. Changes affecting the logic of the design may fall into this category. Examples are LUTMASK changes, LC_COMB/HSADDER creation and deletion, and connectivity changes not covered in the previous section. Another example of this would be to have different PLL settings for the Stratix II and the HardCopy II revisions. f For more information about how to use different PLL settings for the Stratix II and HardCopy II Devices, refer to AN432: Using Different PLL Settings Between Stratix II and HardCopy II Devices. Table 5-3 summarizes suggested implementation for various changes. Table 5-3. Implementation Suggestions for Various Changes (Part 1 of 2) Change Type LUTMASK changes Suggested Implementation Because a single Stratix II atom may require multiple HardCopy II atoms to implement, it may be necessary to change multiple HardCopy II atoms to implement the change, including adding or modifying connectivity If you are using a Stratix II LC_COMB in extended mode (7-LUT) or using a SHARE chain, you must create multiple atoms to implement the same logic functions in HardCopy II. Additionally, the placement of the LC_COMB cell has no meaning in the companion revision as the underlying resources are different. Make/Delete LC_COMB Altera Corporation September 2008 5-21 HardCopy Series Handbook, Volume 1 Table 5-3. Implementation Suggestions for Various Changes (Part 2 of 2) Change Type Make/Delete LC_FF Suggested Implementation The basic creation and deletion is the same on both architectures. However, as with LC_COMB creation and deletion, the location of an LC_FF in a HardCopy II revision has no meaning in the Stratix II revision and vice versa. Because a Stratix II LCELL_COMB atom may have to be broken up into several HardCopy II LCELL_COMB atoms, the source or destination ports for connectivity changes may need to be analyzed to properly implement the change in the companion revision. Editing Logic Connectivity Changes that Cannot be Migrated A small set of changes cannot be implemented in the other architecture because they do not make sense in the other architecture. The best example of this occurs when moving logic in a design; because the logic fabric is different between the two architectures, locations in Stratix II make no sense in HardCopy II and vice versa. Overall Migration Flow This section outlines the migration flow and the suggested procedure for implementing changes in both revisions to ensure a successful Revision Compare such that the design can be submitted to the HardCopy Design Center. Preparing the Revisions The general procedure for migrating changes between devices is the same, whether going from Stratix II to HardCopy II or vice versa. The major steps are as follows: 1. 2. Compile the design on the initial device. Migrate the design from the initial device to the target device in the companion revision. Compile the companion revision. Perform a Revision Compare operation. The two revisions should pass the Revision Compare. 3. 4. 5-22 Altera Corporation September 2008 Overall Migration Flow If testing identifies problems requiring ECO changes, equivalent changes can be applied to both Stratix II and HardCopy II revisions, as described in the next section. Applying ECO Changes The general flow for applying equivalent changes in companion revisions is as follows: 1. Make changes in one revision using the Chip Planner tools (Chip Planner, Resource Property Editor, and Change Manager), then verify and export these changes. The procedure for doing this is as follows: a. Make changes using the Chip Planner tool. b. Perform a netlist check using the Check and Save All Netlist Changes command. Verify correctness using timing analysis, simulation, and prototyping (Stratix II only). If more changes are required, repeat steps a-b. Export change records from the Change Manager to Tcl scripts, or .csv or .txt file formats. This exported file is used to assist in making the equivalent changes in the companion revision. 2. 3. Open the companion revision in the Quartus II software. Using the exported file, manually reapply the changes using the Chip Planner tool. As stated previously, some changes can be reapplied directly to the companion revision (either manually or by applying the Tcl commands), while others require some modifications. 4. Perform a Revision Compare operation. The revisions should now match once again. Verify the correctness of all changes (you may need to run timing analysis). Run the HardCopy II Assembler and the HardCopy II Netlist Writer for design submission along with handoff files. c. d. 5. 6. Altera Corporation September 2008 5-23 HardCopy Series Handbook, Volume 1 The Tcl command for running the HardCopy II Assembler is as follows: execute_module -tool asm -args "-read_settings_files=\ off --write_settings_files=off" The Tcl command for the HardCopy II Netlist Writer is as follows: execute_module -tool cdb -args "-generate_hardcopyii_files"\ f For more information about using Chip Planner, refer to the Quartus II Engineering Change Management with Chip Planner chapter in volume 3 of the Quartus II Handbook at www.altera.com. Third-party formal verification software is available for your HardCopy II design. Cadence Encounter Conformal verification software is used for Stratix II and HardCopy II families, as well as several other Altera product families. To use the Conformal software with the Quartus II software project for your Stratix II and HardCopy II design revisions, you must enable the EDA Netlist Writer. It is necessary to turn on the EDA Netlist Writer so it can generate the necessary netlists and command files needed to run the Conformal software. To automatically run the EDA Netlist Writer during the compile of your Stratix II and HardCopy II design revisions, perform the following steps: 1. On the Assignment menu, click EDA Tool Settings. The Settings dialog box displays. In the EDA Tool Settings list, select Formal Verification, and in the Tool name list, select Conformal LEC. Compile your Stratix II and Hardcopy II design revisions, with both the EDA Tool Settings and the Conformal LEC turned on so the EDA Netlist Writer automatically runs. Formal Verification of Stratix II and HardCopy II Revisions 2. 3. The Quartus II EDA Netlist Writer produces one netlist for Stratix II when it is run on that revision, and generates a second netlist when it runs on the HardCopy II revision. You can compare your Stratix II post-compile netlist to your RTL source code using the scripts generated by the EDA Netlist Writer. Similarly, you can compare your HardCopy II post-compile netlist to your RTL source code with scripts provided by the EDA Netlist Writer. 5-24 Altera Corporation September 2008 HardCopy II Utilities Menu f For more information about using the Cadence Encounter Conformal verification software, refer to the Cadence Encounter Conformal Support chapter in volume 3 of the Quartus II Handbook. The HardCopy II Utilities menu in the Quartus II software is shown Figure 5-9. To access this menu, on the Project menu, click HardCopy II Utilities. This menu contains the main functions you use to develop your HardCopy II design and Stratix II FPGA prototype companion revision. From the HardCopy II Utilities menu, you can: HardCopy II Utilities Menu Create or update HardCopy II companion revisions Set which HardCopy II companion revision is the current revision Generate a HardCopy II Handoff Report for design reviews Archive HardCopy II Handoff Files for submission to the HardCopy Design Center Compare the companion revisions for functional equivalence Track your design progress using the HardCopy II Advisor Figure 5-9. HardCopy II Utilities Menu Altera Corporation September 2008 5-25 HardCopy Series Handbook, Volume 1 Each of the features within HardCopy II Utilities is summarized in Table 5-4. The process for using each of these features is explained in the following sections. Table 5-4. HardCopy II Utilities Menu Options Menu Description Applicable Design Revision Stratix II prototype design and HardCopy II Companion Revision Restrictions Must disable Auto Device selection Must set a Stratix II device and a HardCopy II companion device Create a new companion Create/Overwrite revision or update an existing HardCopy II Companion Revision companion revision for your Stratix II and HardCopy II design. Specify which companion Set Current revision to associate with HardCopy II Companion Revision current design revision. Compare HardCopy II Companion Revisions Companion Revision must Stratix II prototype design and HardCopy II already exist Companion Revision Compilation of both revisions Compares the Stratix II design Stratix II prototype revision with the HardCopy II design and HardCopy II must be complete Companion Revision companion design revision and generates a report. Generate a report containing Stratix II prototype Generate HardCopy II Handoff important design information design and HardCopy II files and messages generated Companion Revision Report by the Quartus II compile Archive HardCopy II Handoff Files Generate a Quartus II Archive HardCopy II File specifically for submitting Companion Revision the design to the HardCopy Design Center. Similar to the HardCopy Files Wizard for HardCopy Stratix and APEX. Compilation of both revisions must be complete Compare HardCopy II Companion Revisions must have been executed Compilation of both revisions must be completed Compare HardCopy II Companion Revisions must have been executed Generate HardCopy Handoff Report must have been executed HardCopy II Advisor None Open an Advisor, similar to the Stratix II prototype design and HardCopy II Resource Optimization Companion Revision Advisor, helping you through the steps of creating a HardCopy II project. Companion Revisions HardCopy II designs follow a different development flow in the Quartus II software compared with previous HardCopy families. You can create multiple revisions of your Stratix II prototype design, but you can also create separate revisions of your design for a HardCopy II device. 5-26 Altera Corporation September 2008 HardCopy II Utilities Menu The Quartus II software creates specific HardCopy II design revisions of the project in conjunction to the regular project revisions. These parallel design revisions for HardCopy II devices are called companion revisions. 1 Although you can create multiple project revisions, Altera recommends that you maintain only one Stratix II FPGA revision once you have created the HardCopy II companion revision. When you have successfully compiled your Stratix II prototype FPGA, you can create a HardCopy II companion revision of your design and proceed with compiling the HardCopy II companion revision. To create a companion revision, on the Project menu, point to HardCopy II Utilities and click Create/Overwrite HardCopy II Companion Revision. Use the dialog box to create a new companion revision or overwrite an existing companion revision (Figure 5-10). Figure 5-10. Create or Overwrite HardCopy II Companion Revision You can associate only one Stratix II revision to one HardCopy II companion revision. If you created more than one revision or more than one companion revision, set the current companion for the revision you are working on. On the Project menu, point to HardCopy II Utilities and click Set Current HardCopy II Companion Revision (Figure 5-11). Altera Corporation September 2008 5-27 HardCopy Series Handbook, Volume 1 Figure 5-11. Set Current HardCopy II Companion Revision Compiling the HardCopy II Companion Revision The Quartus II software allows you to compile your HardCopy II design with preliminary timing information. The timing constraints for the HardCopy II companion revision can be the same as the Stratix II design used to create the revision. The Quartus II software contains preliminary timing models for HardCopy II devices and you can gauge how much performance improvement you can achieve in the HardCopy II device compared to the Stratix II FPGA. Altera verifies that the HardCopy II Companion Device timing requirements are met in the HardCopy Design Center. After you create your HardCopy II companion revision from your compiled Stratix II design, select the companion revision in the Quartus II software design revision drop-down box (Figure 5-12) or from the Revisions list. Compile the HardCopy II companion revision. After the Quartus II software compiles your design, you can perform a comparison check of the HardCopy II companion revision to the Stratix II prototype revision. Figure 5-12. Changing Current Revision 5-28 Altera Corporation September 2008 HardCopy II Utilities Menu Comparing HardCopy II and Stratix II Companion Revisions Altera uses the companion revisions in a single Quartus II project to maintain the seamless migration of your design from a Stratix II FPGA to a HardCopy II structured ASIC. This methodology allows you to design with one set of Register Transfer Level (RTL) code to be used in both Stratix II FPGA and HardCopy II structured ASIC, guaranteeing functional equivalency. When making changes to companion revisions, use the Compare HardCopy II Companion Revisions feature to ensure that your Stratix II design matches your HardCopy II design functionality and compilation settings. To compare companion revisions, on the Project menu, point to HardCopy II Utilities and click Compare HardCopy II Companion Revisions. 1 You must perform this comparison after both Stratix II and HardCopy II designs are compiled in order to hand off the design to Altera's HardCopy Design Center The Comparison Revision Summary is found in the Compilation Report and identifies where assignments were changed between revisions or if there is a change in the logic resource count due to different compilation settings. Generate HardCopy II Handoff Report In order to submit a design to the HardCopy Design Center, you must generate a HardCopy II Handoff Report providing important information about the design that you want the HardCopy Design Center to review. To generate the HardCopy II Handoff Report, you must: Successfully compile both Stratix II and HardCopy II revisions of your design Successfully run the Compare HardCopy II Companion Revisions utility Once you generate the HardCopy II Handoff Report, you can archive the design using the Archive HardCopy II Handoff Files utility described in "Archive HardCopy II Handoff Files" on page 5-29. Archive HardCopy II Handoff Files The last step in the HardCopy II design methodology is to archive the HardCopy II project for submission to the HardCopy Design Center for back-end migration. The HardCopy II archive utility creates a different Quartus II Archive File than the standard Quartus II project archive Altera Corporation September 2008 5-29 HardCopy Series Handbook, Volume 1 utility generates. This archive contains only the necessary data from the Quartus II project needed to implement the design in the HardCopy Design Center. In order to use the Archive HardCopy II Handoff Files utility, you must complete the following: Compile both the Stratix II and HardCopy II revisions of your design Run the Compare HardCopy II Revisions utility Generate the HardCopy II Handoff Report To select this option, on the Project menu, point to HardCopy II Utilities and click Archive HardCopy II Handoff File utility. HardCopy II Advisor The HardCopy II Advisor provides the list of tasks you should follow to develop your Stratix II prototype and your HardCopy II design. To run the HardCopy II Advisor, on the Project menu, point to HardCopy II Utilities and click HardCopy II Advisor. The following list highlights the checkpoints that the HardCopy II Advisor reviews. This list includes the major check points in the design process; it does not show every step in the process for completing your Stratix II and HardCopy II designs: 1. 2. 3. 4. 5. 6. 7. 8. 9. Select a Stratix II device. Select a HardCopy II device. Turn on the Design Assistant. Set up timing constraints. Check for incompatible assignments. Compile and check the Stratix II design. Create or overwrite the companion revision. Compile and check the HardCopy II companion results. Compare companion revisions. 10. Generate a Handoff Report. 11. Archive Handoff Files and send to Altera. 5-30 Altera Corporation September 2008 HardCopy II Utilities Menu The HardCopy II Advisor shows the necessary steps that pertain to your current selected device. The Advisor shows a slightly different view for a design with Stratix II selected as compared to a design with HardCopy II selected. In the Quartus II software, you can start designing with the HardCopy II device selected first, and build a Stratix II companion revision second. When you use this approach, the HardCopy II Advisor task list adjusts automatically to guide you from HardCopy II development through Stratix II FPGA prototyping, then completes the comparison archiving and handoff to Altera. When your design uses the Stratix II FPGA as your starting point, Altera recommends following the Advisor guidelines for your Stratix II FPGA until you complete the prototype revision. When the Stratix II FPGA design is complete, create and switch to your HardCopy II companion revision and follow the Advisor steps shown in that revision until you are finished with the HardCopy II revision and are ready to submit the design to Altera for back-end migration. Each category in the HardCopy II Advisor list has an explanation of the recommended settings and constraints, as well as quick links to the features in the Quartus II software that are needed for each section. The HardCopy II Advisor displays: A green check box when you have successfully completed one of the steps A yellow caution sign for steps that must be completed before submitting your design to Altera for HardCopy development An information callout for items you must verify Selecting an item within the HardCopy II flow menu provides a description of the task and recommended action. The view in the HardCopy II Advisor differs depending on the device you select. 1 Altera Corporation September 2008 5-31 HardCopy Series Handbook, Volume 1 Figure 5-13 shows the HardCopy II Advisor with the Stratix II device selected. Figure 5-13. HardCopy II Advisor with Stratix II Selected Figure 5-14 shows the HardCopy II Advisor with the HardCopy II device selected. Figure 5-14. HardCopy II Advisor with HardCopy II Device Selected 5-32 Altera Corporation September 2008 HardCopy II Utilities Menu HardCopy II Floorplan View The Quartus II software displays the preliminary timing closure floorplan and placement of your HardCopy II companion revision. This floorplan shows the preliminary placement and connectivity of all I/O pins, PLLs, memory blocks, HCell macros, and DSP HCell macros. Congestion mapping of routing connections can be viewed using the Layers Setting dialog box (in the View menu) settings. This is useful in analyzing densely packed areas of your floorplan that could be reducing the peak performance of your design. The HardCopy Design Center verifies final HCell macro timing and placement to guarantee timing closure is achieved. Figure 5-15 shows an example of the HC230F1020 device floorplan. Figure 5-15. HC230F1020 Device Floorplan In this small example design, the logic is placed near the bottom edge. You can see the placement of a DSP block constructed of HCell Macros, various logic HCell Macros, and an M4K memory block. A labeled close-up view of this region is shown in Figure 5-16. Altera Corporation September 2008 5-33 HardCopy Series Handbook, Volume 1 Figure 5-16. Close-Up View of Floorplan The HardCopy Design Center performs final placement and timing closure on your HardCopy II design based on the timing constraints provided in the Stratix II design. f For more information about the HardCopy Design Center's process, refer to the Back-End Design Flow for HardCopy Series Devices chapter in volume 1 of the HardCopy Series Device Handbook. You can use the Quartus II software to design HardCopy II devices and to develop prototypes using Stratix II FPGAs. This is done using the standard FPGA development process with the addition of the HardCopy II Device Resource Guide, HardCopy II Companion Devices assignment HardCopy II Utilities, and the HardCopy II Advisor. The addition of the HardCopy II Advisor to the Quartus II software provides an instrumental development guide for you to complete your HardCopy II and Stratix II device designs. The HardCopy II Utilities included in the Quartus II software provide you with the tools necessary to complete your Stratix II FPGA prototype and HardCopy II structured ASIC design. The addition of the HardCopy II companion revisions feature to the process allows for rapid development and verification that your HardCopy II design is functionally equivalent to your Stratix II FPGA prototype. Conclusion 5-34 Altera Corporation September 2008 Document Revision History Document Revision History Table 5-5 shows the revision history for this chapter. Table 5-5. Document Revision History Date and Document Version September 2008, v2.5 June 2007 v2.4 December 2006 v2.3 Changes Made Updated chapter number and metadata. Updated with the current Quartus II software version 7.1 information. Minor updates for the Quartus II software version 6.1.0 Added "Performing ECOs with Change Manager and Chip Planner" and "Overall Migration Flow" sections. Updated "Quartus II Software Features Supported for HardCopy II Designs" section. Summary of Changes -- -- A medium update to the chapter, due to changes in the Quartus II software version 6.1 release; most changes were in the "Performing ECOs with Change Manager and Chip Planner" and "Overall Migration Flow" sections. -- -- -- May 2006, v2.2 March 2006 October 2005 v2.1 Added information on support for HardCopy II devices in version 6.0 of the Quartus II software. Formerly chapter 18; no content change. Moved Chapter 17 Quartus II Support for HardCopy II Devices to Chapter 18 in Hardcopy Series Device Handbook 3.2. Updated Graphics. Updated technical content for Quartus II 5.1 support of HardCopy II devices. May 2005 v2.0 January 2005 v1.0 Added information on support for HardCopy II devices in version 5.0 of the Quartus II software. Added document to the HardCopy Series Handbook. -- -- Altera Corporation September 2008 5-35 HardCopy Series Handbook, Volume 1 5-36 Altera Corporation September 2008 6. Script-Based Design for HardCopy II Devices H51025-1.3 Introduction The Quartus (R) II software includes a set of command-line executables, many of which support an interactive Tcl shell. Using the Tcl shell, you can perform FPGA or HardCopy (R) design operations without using the Quartus (R) II window-based GUI. This chapter provides an introduction to Tcl operations for script-based HardCopy II design using the interactive Tcl shell. Topics covered in this chapter include: Overview of Tcl scripting features in the Quartus II software HardCopy II design flow Applying location and timing constraints Synthesis, place and route for HardCopy II designs, and Stratix (R) II prototypes Design verification and analysis Tcl Support in the Quartus II Software The Quartus II software provides different ways to execute Tcl commands and scripts, including: A Tcl Console window A Tcl Scripts dialogue box Command-line processing An interactive Tcl shell The Tcl Console window and Tcl Scripts dialogue box both run within the Quartus II GUI and are not described here. Instead, this chapter focuses on the Interactive Tcl shell that you can use with the Quartus II command-line executables. f For more information about command-line processing and the use of Quartus II command-line executables in batchfiles, makefiles, and scripts, refer to the Command-Line Scripting chapter in volume 2 of the Quartus II Handbook. For more information on the Quartus II Tcl implementation, refer to the Tcl Reference Manual and the Tcl Scripting chapter of the Quartus II Handbook. f Altera Corporation September 2008 6-1 HardCopy Series Handbook, Volume 1 Interactive Tcl Shell A number of the Quartus II executables can be run with an interactive Tcl shell as the user interface. These executables are identified in Table 6-1. The interactive Tcl shell supports Tcl version 8.4. Table 6-1. Quartus II Command-Line Executables with Interactive Tcl Support Executable Name quartus_sh Description A basic Tcl interpreter shell. Supports assignment specification, compile operations, and native operating system commands. For more information, refer to quartus_sh in the Command-Line Executables section of the Quartus II Scripting Reference Manual. The Quartus II TimeQuest timing analyzer engine supports building the timing graph for the design and timing analysis Tcl commands. For more information, refer to quartus_sta in the Command-Line Executables section of the Quartus II Scripting Reference Manual. The Quartus II Classic Timing Analyzer engine supports building the timing graph for the design and timing analysis Tcl commands. For more information, refer to quartus_tan in the Command-Line Executables section of the Quartus II Scripting Reference Manual. The Quartus II database interface executable. Supports operations related to the design database such as LogicLock, back-annotation, and FPGA-HardCopy comparison for HardCopy II designs. For more information, refer to quartus_cdb in the CommandLine Executables section of the Quartus II Scripting Reference Manual. The Quartus II Simulator. For more information, refer to quartus_sim in the Command-Line Executables section of the Quartus II Scripting Reference Manual. quartus_sta quartus_tan quartus_cdb quartus_sim 6-2 Altera Corporation September 2008 Tcl Support in the Quartus II Software The interactive Tcl shell for command-line executables is invoked using the -s command-line switch. For example, to run the basic Quartus shell, type quartus_sh -s at the command prompt: % quartus_sh -s Info: *********************************************************************** Info: Running Quartus II Shell Info: *********************************************************************** Info: The Quartus II Shell supports all TCL commands in addition Info: to Quartus II Tcl commands. All unrecognized commands are Info: assumed to be external and are run using Tcl's "exec" Info: command. Info: - Type "exit" to exit. Info: - Type "help" to view a list of Quartus II Tcl packages. Info: - Type "help -pkg The Quartus II Tcl implementation provides custom Tcl procedures to perform Quartus II operations. These procedures are organized into Tcl packages based on their functionality. Table 6-2 lists these Tcl packages and their availability. Some packages are loaded by default when the executable is invoked. Others must be explicitly loaded before their Tcl procedures are used. To load a particular package, use the load_package Tcl procedure. For example, to load the flow package in the quartus_sh shell, the following Tcl statement is executed: tcl> load_package flow 1 It is important to note that not all executables support all Tcl packages. Table 6-2. Tcl Package Support in Quartus II Executables Executable Name quartus_sta Supported Tcl Package device misc flow project report sdc sta (Part 1 of 2) Loaded by Default? Loaded Loaded Not loaded Loaded Loaded Loaded Loaded Altera Corporation September 2008 6-3 HardCopy Series Handbook, Volume 1 Table 6-2. Tcl Package Support in Quartus II Executables Executable Name quartus_sh Supported Tcl Package device flow misc project report (Part 2 of 2) Loaded by Default? Loaded Not Loaded Loaded Loaded Not Loaded Not Loaded Not Loaded Not Loaded Not Loaded Loaded Loaded Not Loaded Loaded Not Loaded Not Loaded Not Loaded Loaded Not Loaded Not Loaded Loaded Loaded Not Loaded Loaded Not Loaded Loaded Loaded Loaded Loaded quartus_tan advanced_timing device flow logiclock Misc project report timing timing_report quartus_cdb backannotate chip_editor device flow logiclock misc project report quartus_sim device flow misc project report simulator A brief description of each of the Tcl packages referenced in Table 6-2 is given in Table 6-3. f To find out which Tcl packages are loaded, use the command quartus_??? --tcl_eval help. For example: quartus_sta --tcl_eval help. 6-4 Altera Corporation September 2008 Tcl Support in the Quartus II Software Table 6-3. Quartus II Tcl Package Descriptions Tcl Package advanced_timing backannotate chip_editor database_manager device flow logiclock misc project report simulator stp timing timing_report Back annotate assignments. Identify and modify resource usage and routing with the Chip Editor. Manage version-comparable database files. Get device and family information from the device database. Compile a project, run command-line executables and other common flows. Create and manage LogicLock regions. Perform miscellaneous tasks. Create and manage projects and revisions and make any project assignments including timing assignments. Get information from report tables and create custom reports. Configure and perform simulations. Operate the SignalTap (R) II Analyzer. Annotate timing netlist with delay information, compute and report timing paths. List timing paths. Description Traverse the timing netlist and get information about timing modes. The Quartus II command-line executables and Tcl shells are supported on all Quartus II operating systems, including Microsoft Windows, Linux, and Unix platforms. f For more information on Quartus II Tcl packages and their available Tcl procedures, refer to the Tcl Packages and Commands chapter in the Quartus II Scripting Reference Manual. Command-Line Processing In addition to the interactive Tcl shell, the Quartus II command-line executables support command-line switches for executing Tcl scripts and commands. When used with these switches, a command-line executable quits when complete. The command-line executables also provide switches for performing specific Quartus II operations. For example, the following c-shell script takes as its argument the top-level design file and entity name and runs it through the entire HardCopy II design flow. !#/bin/csh quartus_sh --flow compile %1 quartus_cdb %1 --create_companion=%1_hcii quartus_sh --flow compile %1 -c %1_hcii quartus_cdb --compare=%1_hcii %1 -c %1 Altera Corporation September 2008 6-5 HardCopy Series Handbook, Volume 1 This example shows what is, perhaps, the simplest way to execute the HardCopy II design flow. If you have developed and applied the design I/O, location and timing constraints for the project, these constraints are included during script execution. f For more information on the Quartus II executables and command-line options, refer to the Command-Line Executables chapter in the Quartus II Scripting Reference Manual and the Command-Line Scripting section in volume 2 of the Quartus II Handbook. The Quartus II software supports both HardCopy II first and Stratix II first design flows. The Stratix II first flow involves the following: The HardCopy II Design Flow Compiling for the Stratix II FPGA prototype Verifying the Stratix II FPGA prototype Migrating the prototype design to a HardCopy II design Compiling the HardCopy II design Transferring your HardCopy II files to the Altera (R) Design Center The Hardcopy II first flow is similar, but starts with compiling the HardCopy II target device. Once the HardCopy II compile completes successfully, the design is migrated to the Stratix II target. The HardCopy II design flow in the Quartus II software is shown in Figure 6-1. To begin a design, create a new project and revision for the Stratix II FPGA prototype. Apply Quartus II settings together with I/O assignments and timing constraints. Compile the Stratix II prototype revision (synthesis, place and route, and assembly) to produce a complete layout, with timing closure and free from errors. You can now perform any additional functional and timing verification necessary and then implement and verify the prototype in hardware. Once the FPGA prototype is verified, you can compile the HardCopy II design. Begin by creating a HardCopy II companion revision for the FPGA prototype: 1. Create a HardCopy II companion revision for the FPGA prototype. All design settings and constraints are automatically migrated to the new companion revision. Compile the HardCopy II revision. As the compile runs, the Design Assistant checks for errors. When the compile completes, you should correct errors and resolve failures that appear in the Quartus II reports. 2. 6-6 Altera Corporation September 2008 The HardCopy II Design Flow 3. Run the HardCopy II Companion Revision Comparison tool to compare the HardCopy II design against the FPGA prototype. The comparison tool checks for structural equivalency and consistency between the two revisions. If there are no mismatches, you can prepare the HardCopy II design files for transfer to the Altera Design Center. In addition to design verification in the Quartus II software, the flow can generate files required to perform Static Timing Analysis (STA) in Synopsys' Primetime. 4. 1 Figure 6-1. The HardCopy II Design Flow Create a New Project Source .v, .vhd, .tdf .edf, .bdf Design Files Make Global Assignments Signal-Pin Assignment Tcl Files Prototype Stratix II Design Make Location Assignments Timing Constraint Tcl Files Make Timing Assignments Compilation Report Files Compile Stratix II Prototype Create HardCopy II Companion Revision Verify the Stratix II Prototype Compile HardCopy II Design Compare Design Report File Verify HardCopy II Design HardCopy II Archive Hand-Off to the Altera Design Center Altera Corporation September 2008 HardCopy II Design Compilation Report Files 6-7 HardCopy Series Handbook, Volume 1 The design flow of Figure 6-1 begins with a Stratix II FPGA prototype design and migrates this design to a HardCopy II device target, or begins with a HardCopy II target and migrates this design to a Stratix II target for FPGA prototyping. The design flow for both cases is shown in Figure 6-1. f For more information on the HardCopy II design flow and alternative methods to complete HardCopy II designs using the Quartus II GUI, refer to the Quartus II Support for HardCopy II Devices chapter in the Quartus II Handbook or the HardCopy II Design Considerations chapter in volume 1 of the HardCopy Series Handbook. The following sections describe each step of the flow shown in Figure 6-1 and explains how each step is completed using the interactive Tcl shell. Creating a New Project Both FPGA and HardCopy design in the Quartus II software revolve around the use of projects. You must create a project before you begin working with a new design. A project includes source design files (RTL and schematics), Quartus II tool settings, and a set of pin locations and timing constraints. Although a project can contain many different revisions for a design, each revision can have a unique set of design constraints, target device settings, and Quartus II software settings. You must explicitly open a project before you can perform other operations on the project. You must close the current project to switch to a different project or revision. This section details the different operations relating to project management using Tcl commands. Creating a Stratix II Prototype Project To create a new Stratix II prototype project, use the project_new Tcl command. The syntax for this command is: tcl> project_new [-family 6-8 Altera Corporation September 2008 Creating a New Project a project called demo_design with the default revision name of demo_design and an unspecified target device family or part, the following Tcl command is executed: tcl> project_new demo_design Creating a new project creates a quartus settings file (QSF) and a Quartus II Project file (QPF) in the current directory. In addition, a db subdirectory is created that is used to store Quartus II database files. In the case of the demo_design project example, the following files are created in the project directory: demo_design.qpf demo_design.qsf db/ demo_design.db_info Opening a Project The project created automatically opens when you use the project_new command. In future Quartus II sessions, or if you close the project, you must open the project with the Tcl command: project_open. The syntax for the project_open command is: tcl> project_open [-current_revision] \ [-revision Closing a Project Before ending a Quartus II project session, it is good practice to close the Quartus II project using the project_close command. This ensures that any changes you have made to your project are written to the Quartus II QSF file. The syntax for the project_close command is: tcl> project_close [-dont_export_assignments] Altera Corporation September 2008 6-9 HardCopy Series Handbook, Volume 1 New Project Example Script The following script shows the use of Tcl commands for opening and closing a project called demo_design with the revision name, demo_design_fpga. If the project does not already exist, it is created. This script makes use of the project_exists and project_open Tcl commands. ## Example Tcl Script for opening and closing a project ## Open Project demo_design. If the Project does not Already ## Exist, Create it if [is_project_open] project_close if [project_exists demo_design] { project_open demo_design -revision demo_design_fpga } else { project_new demo_design -revision demo_design_fpga } ## Include Other Tcl Commands Here ... ## Close project demo_design and write any changes to settings to ## demo_design.qsf project_close ## End of script f For more information on these and other useful project-related commands, refer to the Project section in the Tcl Packages and Commands chapter in the Quartus II Scripting Reference Manual. 6-10 Altera Corporation September 2008 Making Global Assignments Making Global Assignments Initializing a HardCopy II Design For a HardCopy II design, the following key operations are required after a Quartus II project is created: Specify design source files (Verilog, VHDL, AHDL, EDIF, and BDF files) Specify the Stratix II prototype target family and device name Specify the HardCopy II companion revision and migration device Enable the Design Assistant Make recommended HardCopy II specific Quartus II tool settings In addition to these, other project settings affecting downstream tools, such as synthesis and place-and-route, can be made at this time. The operations listed above are performed using the set_global_assignment command. The syntax for this command is: tcl> set_global_assignment [-comment Altera Corporation September 2008 6-11 HardCopy Series Handbook, Volume 1 The key global variables for a HardCopy II project are listed in Table 6-4. Table 6-4. Key HardCopy II Design Settings Global Variable Name VERILOG_FILE VHDL_FILE AHDL_FILE EDIF_FILE BDF_FILE FAMILY DEVICE TOP_LEVEL_ENTITY DEVICE_TECHNOLOGY_MIGRATION_LIST COMPANION_REVISION ENABLE_DRC_SETTINGS USE_TIMEQUEST_TIMING_ANALYZER SDC_FILE Value Description Verilog file name. VHDL file name. Altera HDL file name. EDIF file name. Altera schematic file name. Device family name, for example, Stratix II. Prototype FPGA target device name. Top-level design entity or module name. HardCopy II target device name. HardCopy II design revision name. Turn on the Design Assistant. Set TimeQuest as the default timing analyzer You only need the following settings when using Classic Timing Analyzer. Using Classic Timing Analyzer is not recommended. REPORT_IO_PATHS_SEPARATELY Creates a separate report panel for input and output min and max timing results. domains constraints and minimum and maximum constraints are set for all I/O paths). FLOW_ENABLE_TIMING_CONSTRAINT_CHECK Timing constraints are checked for completeness (all clock DO_COMBINED_ANALYSIS Timing analysis are run for fast and slow operating conditions and for best and worst-case timing analysis, respectively. This must be turned off. Verify recovery and removal times on asynchronous control and reset signals. Clock latency is included in timing analysis to asses clock-insertion timing and clock skew. IGNORE_CLOCK_SETTINGS ENABLE_RECOVERY_REMOVAL_ANALYSIS ENABLE_CLOCK_LATENCY 6-12 Altera Corporation September 2008 Making Global Assignments The DEVICE and DEVICE_TECHNOLOGY_MIGRATION_LIST variables are the parts used for the Stratix II prototype design and the HardCopy II design. The selected Stratix II prototype device must be compatible with the selected HardCopy II device to make migration possible. Valid pairings for these devices are listed in Table 6-5. For the DEVICE_TECHNOLOGY_MIGRATION_LIST variable, the HardCopy II part names listed in Table 6-5 are used. For the DEVICE variables, the Stratix II part names include the speed grade for the part. The speed grade is a two character code indicating industrial (I) or commercial (C) and the speed indicator (number 3, 4, or 5). For example, a -4 commercial part is denoted using the two character speed grade C4. The two-character speed grade is appended to the Stratix II part name to form the value string for the DEVICE variable. Table 6-5. Stratix II Prototype Options for HardCopy II HardCopy II Part HC210F484C HC210W484C (Part 1 of 2) Stratix II Prototype Part EP2S30F484C3 EP2S30F484C4 EP2S30F484C5 EP2S30F484I4 EP2S60F484C3 EP2S60F484C4 EP2S60F484C5 EP2S60F484I4 EP2S90H484C4 EP2S90H484C5 HC220F672C EP2S60F672C3 EP2S60F672C4 EP2S60F672C5 EP2S60F672I4 EP2S90F780C4 EP2S90F780C5 EP2S130F780C4 EP2S130F780C5 HC220F780C Altera Corporation September 2008 6-13 HardCopy Series Handbook, Volume 1 Table 6-5. Stratix II Prototype Options for HardCopy II HardCopy II Part HC230F1020C (Part 2 of 2) Stratix II Prototype Part EP2S90F1020C3 EP2S90F1020C4 EP2S90F1020C5 EP2S90F1020I4 EP2S130F1020C3 EP2S130F1020C4 EP2S130F1020C5 EP2S130F1020I4 EP2S180F1020C3 EP2S180F1020C4 EP2S180F1020C5 EP2S180F1020I4 HC2401020C EP2S180F1020C3 EP2S180F1020C4 EP2S180F1020C5 EP2S180F1020I4 EP2S180F1508C3 EP2S180F1508C4 EP2S180F1508C5 EP2S180F1508I4 HC240F1508C The following two Tcl commands demonstrate setting the DEVICE and DEVICE_TECHNOLOGY_MIGRATION_LIST variables. tcl> set_global_assignment -name DEVICE EP2S90F1020C4 tcl> set_global_assignment -name \ DEVICE_TECHNOLOGY_MIGRATION_LIST HC230F1020C 6-14 Altera Corporation September 2008 Making Global Assignments The Design Assistant You should turn on the Design Assistant at the beginning of the design process by turning on the ENABLE_DRC_SETTINGS global variable. tcl> set_global_assignment \ -name ENABLE_DRC_SETTINGS ON The Design Assistant runs concurrently with every step of both the prototype Stratix II and HardCopy II design flows. When the Design Assistant is turned on, the Quartus II software checks to ensure that the project fully complies with all HardCopy II design rules and requirements. f For more information on the Design Assistant, refer to the Design Guidelines for HardCopy II Devices chapter in volume 1 of the HardCopy Series Handbook and the Quartus Support for HardCopy II Devices chapter in the Quartus II Handbook. Altera Corporation September 2008 6-15 HardCopy Series Handbook, Volume 1 Example Tcl Script for Making Global Assignments The example Tcl script below illustrates the application of global constraints for a HardCopy II project. ## Example Global Assignments Script for a HardCopy II Design ## This Script Applies Settings for a EP2S90 Stratix II ## prototype FPGA target and a HC230 HardCopy II target ## Source Design File Settings ## =========================== set_global_assignment -name VERILOG_FILE demo_design.v set_global_assignment -name VERILOG_FILE example_ram.v ## Stratix II Prototype FPGA Target Settings ## ========================================= set_global_assignment -name FAMILY "Stratix II" set_global_assignment -name DEVICE EP2S90F1020C4 set_global_assignment -name TOP_LEVEL_ENTITY demo_design ## HardCopy II Companion Revision and Target Settings ## ================================================== set_global_assignment -name COMPANION_REVISION_NAME \ demo_design_hardcopyii set_global_assignment -name DEVICE_TECHNOLOGY_MIGRATION_LIST HC230F1020 ## Design Assistant Assignments and Settings Required for HardCopy II ##============================================================== set_global_assignment -name ENABLE_DRC_SETTINGS ON set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 set_global_assignment -name REPORT_IO_PATHS_SEPARATELY ON ## The following assignments are Classic Timing Analyzer only ## and are not used by TimeQuest. ##=========================================================== set_global_assignment -name FLOW_ENABLE_TIMING_CONSTRAINT_CHECK ON set_global_assignment -name DO_COMBINED_ANALYSIS ON set_global_assignment -name IGNORE_CLOCK_SETTINGS OFF set_global_assignment -name ENABLE_RECOVERY_REMOVAL_ANALYSIS ON set_global_assignment -name ENABLE_CLOCK_LATENCY ON ## End of Script 6-16 Altera Corporation September 2008 Making Global Assignments Making I/O Assignments Because of the complex rules governing the use of programmable I/O cells and their availability for specific pins and packages, Altera highly recommends that I/O assignments are completed using the Pin Planning tool and the Assignment Editor in the Quartus II GUI. These tools ensure that all of the rules regarding each pin and I/O cell are applied correctly. The Quartus II GUI can export a Tcl script containing all I/O assignments and specifications. I/O assignments are described here for information only. For more information on I/O location and type assignments using the Quartus II Assignment Editor and Pin Planner tools, refer to the Assignment Editor chapter in volume 2 of the Quartus II Handbook. In this section, I/O specification is considered in two parts: f Pin assignments I/O type assignments Pin Assignments Design I/O signals are assigned to package balls using the set_location_assignment command. The syntax for this command is given below: tcl> set_location_assignment [-comment Setting I/O Type and Parameters For I/O type and parameter specification, the set_instance_assignment command is used. The syntax for this command is: tcl> set_instance_assignment [-comment |
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