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ISL97650B
Data Sheet July 31, 2008 FN6748.0
4-Channel Integrated LCD Supply
The ISL97650B represents a high power, integrated LCD supply IC targeted at large panel LCD displays. The ISL97650B integrates a high power, 3.2A boost converter for AVDD generation, an integrated VON charge pump, a VOFF charge pump driver, VON slicing circuitry and a buck regulator with 2A switch for logic generation. The ISL97650B has been designed for ease of layout and low BOM cost. Supply sequencing is integrated for both AVDD -> VOFF -> VON and AVDD/VOFF -> VON sequences. The TFT power sequence uses a separate enable to the logic buck regulator for maximum flexibility. Peak efficiencies are >90% for both the boost and buck while operating from a 4.2V to 14V input supply. The current mode buck offers superior line and load regulation. Available in the 36 Ld TQFN package, the ISL97650B is specified for ambient operation over the -40C to +105C temperature range.
Features
* 4.2V to 14V input supply * AVDD boost up to 20V, with integrated 3.2A FET * Integrated VON charge pump, up to 35VOUT * VOFF charge pump driver, down to -18V * VLOGIC buck down to 1.2V, with integrated 2A FET * Automatic start-up sequencing - AVDD -> VOFF -> VON or AVDD/VOFF -> VON - Independent logic enable * VON slicing * Thermally enhanced 6x6 Thin QFN package * Pb-free plus anneal available (RoHS compliant)
Applications
* LCD monitors (15"+) * LCD-TVs (up to 40")
Pinout
ISL97650B (36 LD TQFN) TOP VIEW
29 CDEL 31 DELB 28 VDC1 36 VDC2 32 CM1 34 FBB 30 ENL 33 VIN 35 EN
* Notebook displays (up to 16") * Industrial/medical LCD displays
Ordering Information
27 AGND1 26 PGND1 25 PGND2 24 VINL
LX1 1 LX2 2 CB 3 LXL 4 NC 5 VSUP 6 FBL 7 CM2 8 CTL 9 AGND2 10 COM 12 POUT 13 C1- 14 C1+ 15 C2- 16 C2+ 17 DRN 11 NC 18 THERMAL PAD
PART NUMBER (Note) ISL97650BIRTZ-T* ISL97650BIRTZ-TK*
PART MARKING
PACKAGE (Pb-Free)
PKG. DWG. #
ISL976 50BIRTZ 36 Ld 6x6 TQFN L36.6x6 ISL976 50BIRTZ 36 Ld 6x6 TQFN L36.6x6
*Please refer to TB347 for details on reel specifications. NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
23 NOUT 22 PGND3 21 FBN 20 VREF 19 FBP
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2008. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
ISL97650B
Absolute Maximum Ratings (TA = +25C)
Maximum Pin Voltages, all pins except below . . . . . . . . . . . . . . 6.5V LX1, LX2, VSUP, NOUT, DELB, C2- . . . . . . . . . . . . . . . . . . . .24V C1- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14V VIN1, VINL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.5V DRN, COM, POUT, C1+, C2+ . . . . . . . . . . . . . . . . . . . . . . . . .36V CB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21V
Thermal Information
Thermal Resistance JA (C/W) JC (C/W) 6x6 TQFN Package (Notes 1, 2) . . . . . 30 2.5 Maximum Junction Temperature (Plastic Package) . . . . . . . +150C Maximum Storage Temperature Range . . . . . . . . . .-65C to +150C Power Dissipation TA +25C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3.3W TA = +70C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.8W TA = +85C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.3W TA = +100C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.8W Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Input Voltage Range, VIN . . . . . . . . . . . . . . . . . . . . . . . 4.2V to 14V Boost Output Voltage Range, AVDD . . . . . . . . . . . . . . . . . . . . +20V VON Output Range, VON . . . . . . . . . . . . . . . . . . . . . . +15V to +32V VOFF Output Range, VOFF . . . . . . . . . . . . . . . . . . . . . . . -15V to -5V Logic Output Voltage Range, VLOGIC . . . . . . . . . . . . +1.5V to +3.3V Input Capacitance, CIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2x10F Boost Inductor, L1 . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3H to 10H Output Capacitance, COUT . . . . . . . . . . . . . . . . . . . . . . . . . . 2x22F Buck Inductor, L2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3H to 10H Operating Ambient Temperature Range . . . . . . . . -40C to +105C Operating Junction Temperature . . . . . . . . . . . . . . -40C to +125C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty.
NOTES: 1. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with "direct attach" features. See Tech Brief TB379. 2. For JC, the "case temp" location is the center of the exposed metal pad on the package underside
Electrical Specifications
VIN = 12V, VBOOST = VSUP = 15V, VON = 25V, VOFF = -8V, over temperature from -40C to +105C; Parameters with MIN and/or MAX limits are 100% tested at +25C, unless otherwise specified. Temperature limits established by characterization and are not production tested. DESCRIPTION CONDITIONS MIN TYP MAX UNIT
PARAMETER SUPPLY PINS VIN VINL VSUP IVIN
Supply Voltage (VIN1) Logic Supply Voltage Charge Pumps and VON Slice Positive Supply Quiescent Current into VIN Enabled, No switching Disabled
4.2 4.2 4.0
12 12
14 14 20
V V V mA A mA A mA A V V
3 25 0.25 1
5 50 2 25 1
IINL
Logic Supply Current
Enabled, No switching Disabled
ISUP
VSUP Supply Current
Enabled, No Switching and VPOUT = VSUP Disabled 1 3.85 3.3 1.18 1.177 3.8 1.205 1.205 500
10 4.0
VLOR VLOF VREF
Undervoltage Lockout Threshold Undervoltage Lockout Threshold Reference Voltage
VDC rising VDC falling TA = +25C
1.225 1.228 560
V V kHz
FOSC AVDD BOOST DMIN DMAX ILX
Oscillator Frequency
440
Minimum Duty Cycle Maximum Duty Cycle LX Leakage Current LX = 0V and 24V 92 -50
7 94 0.1
10 96 50
% % A
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ISL97650B
Electrical Specifications
VIN = 12V, VBOOST = VSUP = 15V, VON = 25V, VOFF = -8V, over temperature from -40C to +105C; Parameters with MIN and/or MAX limits are 100% tested at +25C, unless otherwise specified. Temperature limits established by characterization and are not production tested. (Continued) DESCRIPTION Boost Output Range Boost Switch Current Peak Efficiency Switch ON-Resistance Line Regulation Load Regulation Boost Feedback Voltage 5V < VIN < 13V, load = 300mA 100mA < Iload < 200mA TA = +25C 1.192 1.188 ACCBOOST tSS VLOGIC BUCK VBUCK IBUCK EFFBUCK RDS-ONBK VBUCK/VIN VBUCK/IOUT VFBL Buck Output Voltage Buck Switch Current Peak Efficiency Switch ON-Resistance Line Regulation Load Regulation FBL Regulation Voltage 5V < VIN < 13V, load = 300mA 100mA < Iload < 500mA TA = +25C 1.176 1.174 ACCLOGIC DMIN BUCK DMAX BUCK tssL VLOGIC Output Accuracy Minimum Duty Cycle Maximum Duty Cycle Soft-Start Period for VLOGIC C(VREF) = 220nF (Note - no soft-start if EN asserted HIGH before ENB) 91 TA = +25C -2 10 92 0.5 Output current = 0.5A Current limit See graphs and component recommendations 1.5 2.0 2.4 92 200 0.01 0.2 1.2 1.2 400 0.15 1 1.224 1.226 2 16 94 5.5 2.9 V A % m %/V % V V % % % ms AVDD Output Accuracy Soft-Start Period for AVDD TA = +25C CDEL = 220nF -1.5 9.6 Current limit See graphs and component recommendations CONDITIONS MIN 1.25 *VIN 2.6 3.2 90+ 160 0.08 0.1 1.205 1.205 300 0.4 0.5 1.218 1.222 1.5 TYP MAX 20 3.85 UNIT V A % m %/V % V V % ms
PARAMETER VBOOST IBOOST EFFBOOST rDS(ON) VBOOST/VIN VBOOST/IOUT VFBB
NEGATIVE (VOFF) CHARGE PUMP VOFF ILoad_NCP_min RON(NOUT)H RON(NOUT)L Ipu(NOUT)lim Ipd(NOUT)lim I(NOUT)leak VFBN VOFF Output Voltage Range External Load Driving Capability High-Side Driver ON-Resistance at NOUT Low-Side Driver ON-Resistance at NOUT Pull-Up Current Limit in NOUT Pull-Down Current Limit in NOUT Leakage Current in NOUT FBN Regulation Voltage 2X Charge Pump VSUP > 5V I(NOUT) = +60mA I(NOUT) = -60mA V(NOUT) = 0V to V(SUP) - 0.5V V(NOUT) = 0.36V to V(VSUP) V(FBN) < 0 or EN = LOW TA = +25C -5 0.173 0.171 ACCN VOFF Output Accuracy IOFF = 1mA, TA = +25C -3 0.203 0.203 60 270 -200 -60 5 0.233 0.235 +3 -VSUP +1.4V 30 10 5 0 V mA mA mA A V V %
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Electrical Specifications
VIN = 12V, VBOOST = VSUP = 15V, VON = 25V, VOFF = -8V, over temperature from -40C to +105C; Parameters with MIN and/or MAX limits are 100% tested at +25C, unless otherwise specified. Temperature limits established by characterization and are not production tested. (Continued) DESCRIPTION Max Duty Cycle of the Negative Charge Pump Pull-Down Resistance, Not Active I(FBN) = 500A 1.5 CONDITIONS MIN TYP 50 3.3 5.5 MAX UNIT % k
PARAMETER D_NCP_max Rpd(FBN)off
POSITIVE (VON) CHARGE PUMP VON ILoad_PCP_min VON Output Voltage Range External Load Driving Capability 2X or 3X Charge Pump VON = 25V (2X Charge Pump) VON = 34V (3X Charge Pump) RON(VSUP_SW) RON(C1/2-)H RON(C1/2-)L Ipu(VSUP_SW) Ipu(C1/2-) Ipd(C1/2-) I(POUT)leak VFBP ON-Resistance of VSUP Input Switch High-Side Driver ON-Resistance at C1- and C2Low-Side Driver ON-Resistance at C1- and C2Pull-Up Current Limit in VSUP Input Switch Pull-Up Current Limit in C1- and C2Pull-Down Current Limit in C1- and C2Leakage Current in POUT FBP Regulation Voltage I(switch) = +40mA I(C1/2-) = +40mA I(C1/2-) = -40mA V(C2+) = 0V to V(SUP) - 0.4V - V(diode) V(C1/2-) = 0V to V(VSUP) - 0.4V V(C1/2-) = 0.2V to V(VSUP) EN = LOW TA = +25C -5 1.176 1.172 ACCP D_PCP_max V(diode) ENABLE INPUTS VHI-EN VLO_EN IEN_pd VHI-ENL VLO-ENL IENL_pd Enable "HIGH" Enable "LOW" Enable Pin Pull-Down Current Logic Enable "HIGH" Logic Enable "LOW" Logic Enable Pin Pull-Down Current VENL > VLO_ENL VEN > VLO_EN 2.2 0.8 25 2.2 0.8 25 V V A V V A VON Output Accuracy Max Duty Cycle of the Positive Charge Pump Internal Schottky Diode Forward Voltage I(diode) = +40mA ION = 1mA, TA = +25C -2 50 700 800 1.2 1.2 40 40 4 100 100 -100 -40 5 1.224 1.228 +2 VSUP+ 2V 20 20 10 17 30 7 34 V mA mA mA mA mA A V V % % mV
VON SLICE POSITIVE SUPPLY = V(POUT) I(POUT)_slice VON Slice Current from POUT Supply CTL = VDD, sequence complete CTL = AGND, sequence complete RON(POUT-COM) ON-Resistance between POUT - COM RON(DRN-COM) RON_COM VLO VHI ON-Resistance between DRN - COM ON-Resistance between COM and PGND3 CTL Input LOW Voltage CTL Input HIGH Voltage 2.2 CTL = VDD, sequence complete CTL = ACGND, sequence complete 200 200 100 5 30 500 400 150 10 60 1500 0.8 A A V V
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ISL97650B
Electrical Specifications
VIN = 12V, VBOOST = VSUP = 15V, VON = 25V, VOFF = -8V, over temperature from -40C to +105C; Parameters with MIN and/or MAX limits are 100% tested at +25C, unless otherwise specified. Temperature limits established by characterization and are not production tested. (Continued) DESCRIPTION CONDITIONS MIN TYP MAX UNIT
PARAMETER
FAULT DETECTION THRESHOLDS T_off Vth_AVDD(FBB) Thermal Shut-Down (latched and reset by power cycle or EN cycle) AVDD Boost Short Detection Temperature rising V(FBB) falling less than V(FBL) falling less than V(FBP) falling less than V(FBN) rising more than 150 0.9 0.9 0.9 0.4 52 C V V V V ms
Vth_VLOGIC(FBL) VLOGIC Buck Short Detection Vth_POUT(FBP) Vth_NOUT(FBN) tFD POUT Charge Pump Short Detection NOUT Charge Pump Short Detection Fault Delay Time to Chip Turns Off
START-UP SEQUENCING tSTART-UP IDELB_ON Enable to AVDD Start Time CDEL = 220nF 36 1.00 80 50 1.326 70 1.75 500 10 CDEL = 220nF CDEL = 220nF CDEL = 220nF 9 20 17 220 ms A k nA nF ms ms ms
DELB Pull-Down Current or Resistance VDELB > 0.9V when Enabled by the Start-Up Sequence VDELB < 0.9V DELB Pull-Down Current or Resistance VDELB < 20V when Disabled Sequence Timing and Fault Time Out Capacitor AVDD to VOFF VOFF to VON Delay VON to VON-SLICE Delay
IDELB_OFF CDEL tVOFF tVON tVON-SLICE
Typical Performance Curves
100 0.25 VIN = 12V 0.20 0.15 0.10 VIN = 5V 0.05 0 -0.05 0 500 1000 1500 IO (mA) 2000 2500 VIN = 12V
60
40
20
0 0 500 1000 1500 IO (mA) 2000 2500 3000
FIGURE 1. BOOST EFFICIENCY
LOAD REGULATION (%)
80 EFFICIENCY (%)
VIN = 5V
FIGURE 2. BOOST LOAD REGULATION
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ISL97650B Typical Performance Curves (Continued)
100 0 -0.5 LOAD REGULATION (%) 80 EFFICIENCY (%) VIN = 12V 60 VIN = 5V -1.0 -1.5 -2.0 -2.5 -3.0 -3.5 0 0 500 1000 1500 2000 2500 IO (mA) -4.0 0 500 1000 IO (mA) 1500 2000 VIN = 5V VIN = 12V
40
20
FIGURE 3. BUCK EFFICIENCY
FIGURE 4. BUCK LOAD REGULATION
0 VOFF LOAD REGULATION(%) -0.1 -0.2 -0.3 -0.4 -0.5 -0.6 -0.7 0 10 20 30 40 IO (mA) 50 60 70 80 VOFF = -8 VON LOAD REGULATION (%)
0 -0.1 -0.2 -0.3 -0.4 -0.5 -0.6 0 10 20 30 ION (mA) 40 50 60 VON = 25V
FIGURE 5. VOFF LOAD REGULATION vs IOFF
FIGURE 6. VON LOAD REGULATION vs ION
Ch1 = LX(boost)(5V/DIV) Ch2 = IO(Boost)(10mA/DIV)
Ch1 = LX(boost)(5V/DIV) Ch2 = IO(Boost)(10mA/DIV)
400ns/DIV
400ns/DIV
FIGURE 7. BOOST DISCONTINUOUS MODE
FIGURE 8. THRESHOLD OF BOOST FROM DC TO CC MODE
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ISL97650B Typical Performance Curves (Continued)
Ch1 = LX(buck)(5V/DIV) Ch2 = IO(Buck)(10mA/DIV) Ch1 = LX(buck)(5V/DIV) Ch2 = IO(Buck)(10mA/DIV)
800ns/DIV
800ns/DIV
FIGURE 9. BUCK DISCONTINUOUS MODE
FIGURE 10. THRESHOLD OF BUCK FROM DC TO CC MODE
Ch1 = VIN Ch2 = LX, Ch3 = AVDD, Ch4 = IINDUCTOR
Ch1 = AVDD(VBOOST)(100mV/DIV) Ch2 = IO(Boost)(200mA/DIV)
2ms/DIV
FIGURE 11. BOOST CONVERTER PULSE-SKIPPING MODE WAVEFORM
FIGURE 12. TRANSIENT RESPONSE OF BOOST
Ch1 = VLOGIC(VBUCK)(50mV/DIV) Ch2 = IO(Buck)(500mA/DIV)
Ch1 = CDLY, Ch2 = VREF, Ch3 = VLOGIC, Ch4 = VON R1 = AVDD, R2 = AVDD_DELAY, R3 = VOFF
1ms/DIV
FIGURE 13. TRANSIENT RESPONSE OF BUCK
FIGURE 14. START-UP SEQUENCE
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ISL97650B Pin Descriptions
PIN NUMBER 1 2 3 4 5, 18 6 7 8 9 10 11 12 13 14 15 16 17 19 20 21 22 23 24 25, 26 27 28 29 30 31 32 33 34 35 36 Thermal Pad PIN NAME LX1 LX2 CB LXL NC VSUP FBL CM2 CTL AGND2 DRN COM POUT C1C1+ C2C2+ FBP VREF FBN PGND3 NOUT VINL PGND2, 1 AGND1 VDC1 CDEL ENL DELB CM1 VIN FBB EN VDC2 N/A Internal boost switch connection Internal boost switch connection Logic buck, boost strap pin Buck converter output No connect. Connect to die pad and GND for improved thermal efficiency. Positive supply for charge pumps Logic buck feedback pin Buck compensation network pin Input control for VON slice output Signal GND pin Lower reference voltage for VON slice output VON slice output: when CTL = 1, COM is connected to SRC through a 5 resistor; when CTL = 0, COM is connected to DRN through a 30 resistor Positive charge pump out Charge pump capacitor 1, negative connection Charge pump capacitor 1, positive connection Charge pump capacitor 2, negative connection Charge pump capacitor 2, positive connection Positive charge pump feedback pin Reference voltage Negative charge pump feedback pin Power ground for VOFF, VON and VON slice Negative charge pump output Logic buck supply voltage Boost Power grounds Signal ground pin Internal supply decoupling capacitor Delay capacitor for start up sequencing, soft-start and fault detection timers Buck enable for VLOGIC output Open drain NFET output to drive optional AVDD delay PFET Boost compensation network pin Input voltage pin Boost feedback pin Enable for Boost, charge pumps and VON slice (independent of ENL) Internal supply decoupling capacitor Connect exposed die plate on rear of package to ACGND and the PGND1, 2 pins. See "Layout Recommendation" on page 19 for PCB layout thermal considerations. DESCRIPTION
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ISL97650B Block Diagram
VREF
CM1 GM AMPLIFIER FBB VREF UVLO COMPARATOR + +
SAWTOOTH GENERATOR SLOPE COMPENSATION LX1 LX2
BUFFER
CONTROL LOGIC
RSENSE 0.75 VREF 0.5MHz OSCILLATOR VDC1 VIN1, VIN2 EN CDEL ENL DELB VDC2 VIN2 VSUP LXL NOUT CURRENT LIMIT COMPARATOR + CURRENT LIMIT THRESHOLD BUFFER CURRENT AMPLIFIER CONTROL LOGIC GM AMPLIFIER CM2 FBL VREF REGULATOR CB CURRENT LIMIT COMPARATOR CURRENT LIMIT THRESHOLD CURRENT AMPLIFIER PGND1 PGND2
REGULATOR REFERENCE BIAS AND SEQUENCE CONTROLLER
FBN 0.2V
+
SLOPE COMPENSATION SAWTOOTH GENERATOR
+
UVLO COMPARATOR + 0.4V 0.75 VREF +
UVLO COMPARATOR + 0.75 VREF
FBP VREF
+
SUP
POUT SUP
C1-
C1+
POUT
C2+
C2-
DRIV
CTL
COM
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ISL97650B Typical Application Diagram
VIN R18 4.7 VIN C1 2.2F C3 R1 CM1 PGND1 PGND2 BOOST LX2 R16* C18* LX1 L1 6.8F D1 C2 20F AVDD R3 55k AVDD_DELAY 15V C4 OPEN R4 300k C5 1F
4.7nF 10k
FBB EN CDEL C6 0.22F VDC1 C18 0.47F VDC2 C18 0.47F C1+ C7 220nF C8 220nF C1C2+ C2VON CP FBP POUT VOFF CP FBN BIAS AND SEQUENCE CONTROL DELB PGND3 C20 820p R6 40k R10 500k
R5 5k
VREF
C11 220nF
C19 100p R7 328k D2 D3 -8V VOFF C13 470nF
NOUT
C12 220nF VSUP C21 100p R8 983k R9 50k
C14 470nF
+25V VON
VDC2 C17 0.47F CTL COM VINL CB C10 10F C9 4.7nF R2 10k ENL FBL AGND CM2 BUCK LXL DRN VON SLICE R12
C22 2.2nF R11 C15 0.1F 1k
VON SLICE R13 100k C16 1F D4 L2 6.8H R14 2k R15 1.2k
TO GATE DRIVER IC
3.3V VLOGIC C17 20F
*Open component positions
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FN6748.0 July 31, 2008
ISL97650B Applications Information
The ISL97650B provides a complete power solution for TFT LCD applications. The system consists of one boost converter to generate AVDD voltage for column drivers, one buck converter to provide voltage to logic circuit in the LCD panel, one integrated VON charge pump and one VOFF linear-regulator controller to provide the voltage to row drivers. This part also integrates VON-slice circuit which can help to optimize the picture quality. With the high output current capability, this part is ideal for big screen LCD TV and monitor panel application. The integrated boost converter and buck converter operate at 0.5MHz which can allow to use multilayer ceramic capacitors and low profile inductor which result in low cost, compact and reliable system. The logic output voltage is independently enabled to give flexibility to the system designers. Where IL is peak to peak inductor ripple current, and is set by Equation 4:
V IN D I L = --------- x ---L fS (EQ. 4)
where fs is the switching frequency(0.5MHz). Table 1 gives typical values (margins are considered 10%, 3%, 20%, 10% and 15% on VIN, VO, L, fs and IOMAX):
TABLE 1. MAXIMUM OUTPUT CURRENT CALCULATION VIN (V) 5 5 4 12 12 VO (V) 9 12 15 15 18 L (H) 6.8 6.8 6.8 6.8 6.8 fs (MHz) 0.5 0.5 0.5 0.5 0.5 IOMAX (mA) 1138 777 560 1345 998
Boost Converter
The boost converter is a current mode PWM converter operating at a fixed frequency of 0.5MHz. It can operate in both discontinuous conduction mode (DCM) at light load and continuous mode (CCM). In continuous current mode, current flows continuously in the inductor during the entire switching cycle in steady state operation. The voltage conversion ratio in continuous current mode is given by Equation 1:
V boost 1 ----------------- = -----------1-D V IN (EQ. 1)
Where D is the duty cycle of the switching MOSFET. The boost converter uses a summing amplifier architecture consisting of gm stages for voltage feedback, current feedback and slope compensation. A comparator looks at the peak inductor current cycle by cycle and terminates the PWM cycle if the current limit is reached. An external resistor divider is required to divide the output voltage down to the nominal reference voltage. Current drawn by the resistor network should be limited to maintain the overall converter efficiency. The maximum value of the resistor network is limited by the feedback input bias current and the potential for noise being coupled into the feedback pin. A resistor network in the order of 60k is recommended. The boost converter output voltage is determined by Equation 2:
R3 + R5 A VDD = --------------------- x V FBB R5 (EQ. 2)
The minimum duty cycle of the ISL97650B is 25%. When the operating duty cycle is lower than the minimum duty cycle, the part will not switch in some cycles randomly, which will cause some LX pulses to be skipped. In this case, LX pulses are not consistent any more, but the output voltage (AVDD) is still regulated by the ratio of R3 and R5. This relationship is given by Equation 2. Because some LX pulses are skipped, the ripple current in the inductor will become bigger. Under the worst case, the ripple current will be from 0 to the threshold of the current limit. In turn, the bigger ripple current will increase the output voltage ripple. Hence, it will need more output capacitors to keep the output ripple at the same level. When the input voltage equals, or is larger than, the output voltage, the boost converter will stop switching. The boost converter is not regulated any more, but the part will still be on and other channels are still regulated. The typical waveforms of pulse-skipping mode are shown in the "Typical Performance Curves" on page 5.
Boost Converter Input Capacitor
An input capacitor is used to suppress the voltage ripple injected into the boost converter. The ceramic capacitor with capacitance larger than 10F is recommended. The voltage rating of input capacitor should be larger than the maximum input voltage. Some capacitors are recommended in Table 2 for input capacitor.
TABLE 2. BOOST CONVERTER INPUT CAPACITOR RECOMMENDATION CAPACITOR 10F/25V SIZE 1210 1210 VENDOR TDK Murata PART NUMBER C3225X7R1E106M GRM32DR61E106K
The current through the MOSFET is limited to 3.2Apeak. This restricts the maximum output current (average) based on Equation 3:
I L V IN I OMAX = I LMT - -------- x -------- V 2 O (EQ. 3)
10F/25V
Boost Inductor
The boost inductor is a critical part which influences the output voltage ripple, transient response, and efficiency.
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ISL97650B
Values of 3.3H to 10H are to match the internal slope compensation. The inductor must be able to handle the following average and peak current:
IO I LAVG = -----------1-D I L I LPK = I LAVG + -------2 (EQ. 5)
increases. COUT in the equation above assumes the effective value of the capacitor at a particular voltage and not the manufacturer's stated value, measured at zero volts. The following table shows some selections of output capacitors.
TABLE 5. BOOST OUTPUT CAPACITOR RECOMMENDATION
(EQ. 6)
CAPACITOR 10F/25V 10F/25V
SIZE 1210 1210
VENDOR TDK Murata
PART NUMBER C3225X7R1E106M GRM32DR61E106K
Some inductors are recommended in Table 3.
TABLE 3. BOOST INDUCTOR RECOMMENDATION INDUCTOR 6.8H/ 3APEAK 6.8H/ 2.9APEAK 5.2H/ 4.55APEAK DIMENSIONS (mm) VENDOR 7.3x6.8x3.2 TDK PART NUMBER RLF7030T-6R8N3R0 CDR7D28MNNP-6R8NC
PI Loop Compensation (Boost Converter)
The boost converter of ISL97650B can be compensated by a RC network connected from CM1 pin to ground. C3 = 4.7nF and R1 = 10k RC network is used in the demo board. A higher resistor value can be used to lower the transient overshoot - however, this may be at the expense of stability to the loop. The stability can be examined by repeatedly changing the load between 100mA and a max level that is likely to be used in the system being used. The AVDD voltage should be examined with an oscilloscope set to AC 100mV/div and the amount of ringing observed when the load current changes. Reduce excessive ringing by reducing the value of the resistor in series with the CM1 pin capacitor.
7.6X7.6X3.0 Sumida
10x10.1x3.8 Cooper CD1-5R2 Bussmann
Rectifier Diode (Boost Converter)
A high-speed diode is necessary due to the high switching frequency. Schottky diodes are recommended because of their fast recovery time and low forward voltage. The reverse voltage rating of this diode should be higher than the maximum output voltage. The rectifier diode must meet the output current and peak inductor current requirements. The following table is some recommendations for boost converter diode.
TABLE 4. BOOST CONVERTER RECTIFIER DIODE RECOMMENDATION DIODE SS23 SL23 VR/IAVG RATING 30V/2A 30V/2A PACKAGE SMB SMB VENDOR Fairchild Semiconductor Vishay Semiconductor
Boost Converter Feedback Resistors and Capacitor
An RC network across feedback resistor R5 may be required to optimize boost stability when AVDD voltage is set to less than 12V. This network reduces the internal voltage feedback used by the IC. This RC network sets a pole in the control loop. This pole is set to approximately fp = 10kHz for COUT = 10F and fp = 4kHz for COUT = 30F. Alternatively, adding a small capacitor (20pF to 100pF) in parallel with R5 (i.e. R16 = short) may help to reduce AVDD noise and improve regulation, particularly if high value feedback resistors are used.
1 1 - -1 R16 = ---------------------- - ------- 0.1 x R5 R3 1 C18 = ---------------------------------------------------------( 2 x 3.142 x fp x R15 ) (EQ. 8)
Output Capacitor
The output capacitor supplies the load directly and reduces the ripple voltage at the output. Output ripple voltage consists of two components: the voltage drop due to the inductor ripple current flowing through the ESR of output capacitor, and the charging and discharging of the output capacitor.
IO V O - V IN 1 V RIPPLE = I LPK x ESR + ----------------------- x --------------- x --C f V
O OUT s
(EQ. 9)
(EQ. 7)
For low ESR ceramic capacitors, the output ripple is dominated by the charging and discharging of the output capacitor. The voltage rating of the output capacitor should be greater than the maximum output voltage. Note: Capacitors have a voltage coefficient that makes their effective capacitance drop as the voltage across then 12
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Cascaded MOSFET Application
An 20V N-channel MOSFET is integrated in the boost regulator. For the applications where the output voltage is greater than 20V, an external cascaded MOSFET is needed as shown in Figure 15. The voltage rating of the external MOSFET should be greater than AVDD.
VIN AVDD
Feedback Resistors
The buck converter output voltage is determined by the following equation:
R14 + R15 V LOGIC = ---------------------------- x V FBL R15 (EQ. 13)
LX1, LX2 FBB INTERSIL ISL97650B
Where R14 and R15 are the feedback resistors of buck converter to set the output voltage Current drawn by the resistor network should be limited to maintain the overall converter efficiency. The maximum value of the resistor network is limited by the feedback input bias current and the potential for noise being coupled into the feedback pin. A resistor network in the order of 1k is recommended.
Buck Converter Input Capacitor
The capacitor should support the maximum AC RMS current which happens when D = 0.5 and maximum output current.
I acrms ( C IN ) = FIGURE 15. CASCADED MOSFET TOPOLOGY FOR HIGH OUTPUT VOLTAGE APPLICATIONS D ( 1 - D ) IO (EQ. 14)
Buck Converter
The buck converter is the step down converter, which supplies the current to the logic circuit of the LCD system. The ISL97650B integrates an 20V N-channel MOSFET to save cost and reduce external component count. In the continuous current mode, the relationship between input voltage and output voltage is as following:
V LOGIC --------------------- = D V IN (EQ. 10)
Where IO is the output current of the buck converter. The following table shows some recommendations for input capacitor.
TABLE 6. INPUT CAPACITOR (BUCK) RECOMMENDATION CAPACITOR 10F/16V 10F/10V 22F/16V SIZE 1206 0805 1210 TDK Murata Murata VENDOR PART NUMBER C3216X7R1C106M GRM21BR61A106K C3225X7R1C226M
Buck Inductor
A 3.3H to 10H inductor is the good choice for the buck converter. Besides the inductance, the DC resistance and the saturation current are also the factor needed to be considered when choosing buck inductor. Low DC resistance can help maintain high efficiency, and the saturation current rating should be 2A. Here are some recommendations for buck inductor.
TABLE 7. BUCK INDUCTOR RECOMMENDATION INDUCTOR 4.7H/ 2.7APEAK 6.8H/ 3APEAK 10H/ 2.4APEAK DIMENSIONS (mm) 5.7x5.0x4.7 7.3x6.8x3.2 VENDOR Murata TDK PART NUMBER LQH55DN4R7M01K RLF7030T-6R8M2R8 DO3308P-103
Where D is the duty cycle of the switching MOSFET. Because D is always less than 1, the output voltage of buck converter is lower than input voltage. The peak current limit of buck converter is set to 2A, which restricts the maximum output current (average) based on Equation 11:
I OMAX = 2A - I P-P (EQ. 11)
Where IP-P is the ripple current in the buck inductor as shown in Equation 12,
V LOGIC I P-P = --------------------- ( 1 - D ) L fs
(EQ. 12)
Where L is the buck inductor, fs is the switching frequency (0.5MHz).
12.95x9.4x3.0 Coilcraft
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Rectifier Diode (Buck Converter)
A Schottky diode is recommended due to fast recovery and low forward voltage. The reverse voltage rating should be higher than the maximum input voltage. The peak current rating is 2A, and the average current should be as shown in Equation 15:
I avg = ( 1 - D )*I o (EQ. 15)
The minimum load can be adjusted by the feedback resistors to FBL. The bootstrap capacitor can only be charged when the higher side MOSFET is off. If the load is too light which can not make the on time of the low side diode be sufficient to replenish the boot strap capacitor, the MOSFET can't turn on. Hence there is minimum load requirement to charge the bootstrap capacitor properly.
Where IO is the output current of buck converter. The following table shows some diode recommended.
TABLE 8. BUCK RECTIFIER DIODE RECOMMENDATION DIODE PMEG2020EJ SS22 VR/IAVG RATING 20V/2A 20V/2A PACKAGE SOD323F SMB VENDOR Philips Semiconductors Fairchild Semiconductor
Charge Pump Controllers (VON and VOFF)
The ISL97650B includes 2 independent charge pumps (see charge pump block and connection diagram). The negative charge pump inverters the VSUP voltage and provides a regulated negative output voltage. The positive charge pump doubles or triples the VSUP voltage and provided a regulated positive output voltage. The regulation of both the negative and positive charge pumps is generated by internal comparator that senses the output voltage and compares it with the internal reference. The pumps use pulse width modulation to adjust the pump period, depending on the load present. The pumps can provide 30mA for VOFF and 20mA for VON.
Output Capacitor (Buck Converter)
Four 10F or two 22F ceramic capacitors are recommended for this part. The overshoot and undershoot will be reduced with more capacitance, but the recovery time will be longer.
TABLE 9. BUCK OUTPUT CAPACITOR RECOMMENDATION CAPACITOR 10F/6.3V 10F/6.3V 22F/6.3V 100F/6.3V SIZE 0805 0805 1210 1206 VENDOR TDK Murata TDK Murata PART NUMBER C2012X5R0J106M GRM21BR60J106K C3216X5R0J226M GRM31CR60J107M
Positive Charge Pump Design Consideration
The positive charge pump integrates all the diodes (D1, D2 and D3 shown in the "Block Diagram" on page 9) required for x2 (VSUP doubler) and x3 (VSUP Tripler) modes of operation. During the chip start-up sequence the mode of operation is automatically detected when the charge pump is enabled. With both C7 and C8 present, the x3 mode of operation is detected. With C7 present, C8 open and with C1+ shorted to C2+, the x2 mode of operation will be detected. Due to the internal switches to VSUP (M1, M2 and M3), POUT is independent of the voltage on VSUP until the charge pump is enabled. This is important for TFT applications where the negative charge pump output voltage (VOFF) and AVDD supplies need to be established before POUT. The maximum POUT charge pump current can be estimated from the following equations assuming a 50% switching duty:
I MAX ( 2x ) min of 50mA or 2 * V SUP - 2 * V DIODE ( 2 * I MAX ) - V ( V ON ) ---------------------------------------------------------------------------------------------------------------------- * 0.95A ( 2 * ( 2 * R ONH + R ONL ) ) I MAX ( 3x ) min of 50mA or 3 * V SUP - 3 * V DIODE ( 2 * I MAX ) - V ( V ON ) ---------------------------------------------------------------------------------------------------------------------- * 0.95V ( 2 * ( 3 * R ONH + 2 * R ONL ) ) (EQ. 16)
PI Loop Compensation (Buck Converter)
The buck converter of ISL97650B can be compensated by a RC network connected from CM2 pin to ground. C9 = 4.7nF and R2 = 2k RC network is used in the demo board. The larger value resistor can lower the transient overshoot, however, at the expense of stability of the loop. The stability can be optimized in a similar manner to that described in"PI Loop Compensation (Boost Converter)" on page 12.
Bootstrap Capacitor (C16)
This capacitor is used to provide the supply to the high driver circuitry for the buck MOSFET. The bootstrap supply is formed by an internal diode and capacitor combination. A 1F is recommended for ISL97650B. A low value capacitor can lead to overcharging and in turn damage the part. If the load is too light, the on-time of the low side diode may be insufficient to replenish the bootstrap capacitor voltage. In this case, if VIN - VBUCK < 1.5V, the internal MOSFET pull-up device may be unable to turn-on until VLOGIC falls. Hence, there is a minimum load requirement in this case.
Note: VDIODE (2 * IMAX) is the on-chip diode voltage as a function of IMAX and VDIODE (40mA) < 0.7V.
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VSUP M2 C1C7 C1+ VSUP M1 External Connections and Components x2 Mode x3 Mode Both
M4
Control 0.5MHz 0.9V
D3
D2
D1
POUT C14
VSUP Error M3 VREF FB
C2+ C8 C2C21 R8
M5
FBP
C22
R9
FIGURE 16. VON FUNCTION DIAGRAM
In voltage doubler configuration, the maximum VON is as given by Equation 17:
V ON_MAX(2x) = 2 * ( V SUP - V DIODE ) - 2 * I OUT * ( 2 * R ONH + R ONL ) (EQ. 17)
For Voltage Tripler:
VON_MAX(3x) = 3 * ( V SUP - V DIODE ) - 2 * I OUT * ( 3 * R ONH + 2 * RONL ) (EQ. 18)
VON output voltage is determined by Equation 19:
R 8 V ON = V FBP * 1 + ------ R 9 (EQ. 19)
Negative Charge Pump Design Consideration
The negative charge pump consists of an internal switcher M1, M2 which drives external steering diodes D2 and D3 via a pump capacitor (C12) to generate the negative VOFF supply. An internal comparator (A1) senses the feedback voltage on FBN and turns on M1 for a period up to half a CLK period to maintain V(FBN) in regulated operation at 0.2V. External feedback resistor R6 is referenced to VREF. Faults on VOFF which cause VFBN to rise to more than 0.4V, are detected by comparator (A2) and cause the fault detection system to start a fault ramp on CDLY pin which will cause the chip to power down if present for more than the time TFD (see "Electrical Specifications" table on page 2 and also Figure 16.
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VREF A2 FAULT 0.4V FBN A1 0.2V VDD VSUP C20 820pF R6 40k R7 328k C19 100pF
0.5MHz
STOP
M2 C12 220nF D2 VOFF (-8V) D3 C13 470nF
CLK NOUT
EN
PWM CONTROL
M1 PGND
FIGURE 17. NEGATIVE CHARGE PUMP BLOCK DIAGRAM
The maximum VOFF output voltage of a single stage charge pump is:
V OFF_MAX ( 2x ) = - V SUP + V DIODE + 2 * I OUT * ( R ON ( NOUT )H + R ON ( NOUT )L ) (EQ. 20)
R6 and R7 in the "Typical Application Diagram" on page 10 determine VOFF output voltage.
R7 R7 V OFF = V FBN * 1 + ------- - V REF * ------- R6 R6 (EQ. 21)
The slew rate of start-up of the switch control circuit is mainly restricted by the load capacitance at COM pin as shown in Equation 22:
Vg V ------- = -----------------------------------( R i || R L ) x C L t (EQ. 22)
Improving Charge Pump Noise Immunity
Depending on PCB layout and environment, noise pick-up at the FBP and FBN inputs, which may degrade load regulation performance, can be reduced by the inclusion of capacitors across the feedback resistors (e.g. in the Application Diagram, C21 and C22 for the positive charge pump). Set R6 * C20 = R7 * C19 with C19 ~ 100pF.
Where Vg is the supply voltage applied to DRN or voltage at POUT, which range is from 0V to 36V. Ri is the resistance between COM and DRN or POUT including the internal MOSFET rDS(On), the trace resistance and the resistor inserted, RL is the load resistance of switch control circuit, and CL is the load capacitance of switch control circuit. In the Typical Application Circuit, R10, R11 and C15 give the bias to DRN based on Equation 23:
V ON R11+AVDD R10 V DRN = ---------------------------------------------------------------R10 + R11 (EQ. 23)
VON Slice Circuit
The VON Slice Circuit functions as a three way multiplexer, switching the voltage on COM between ground, DRN and SRC, under control of the start-up sequence and the CTL pin. During the start-up sequence, COM is held at ground via an NDMOS FET, with ~1k impedance. Once the start-up sequence has completed, CTL is enabled and acts as a multiplexer control such that if CTL is low, COM connects to DRN through a 30 internal MOSFET, and if CTL is high, COM connects to POUT internally via a 5 MOSFET.
And R12 can be adjusted to adjust the slew rate.
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AVDD SOFT-START
VON SOFT-START
FAULT DETECTED tVON-SLICE NORMAL OPERATION
VREF, VLOGIC ON
VCDLY
VIN EN VREF
VBOOST tSTART-UP tSS VLOGIC
VOFF
tVOFF DELAYED VBOOST
VOFF, DELB ON
tVON VON
VON SLICE
NOTE: Not to scale
START-UP SEQUENCE TIMED BY CDLY
FAULT PRESENT
FIGURE 18. START-UP SEQUENCE
Start-Up Sequence
Figure 18 shows a detailed start up sequence waveform. For a successful power-up, there should be 6 peaks at VCDLY. When a fault is detected, the device will latch off until either EN is toggled or the input supply is recycled. When the input voltage is higher than 3.85V, VREF turns on, as well as VLOGIC if the ENL is high. an internal current source starts to charge CCDLY to an upper threshold using a
fast ramp followed by a slow ramp. During the initial slow ramp, the device checks whether there is a fault condition. If no fault is found, CCDLY is discharged after the first peak and VREF turns on. Initially the boost is not enabled so AVDD rises to VINVDIODE through the output diode. Hence, there is a step at AVDD during this part of the start-up sequence. If this step is not desirable, an external PMOS FET can be used to delay
17
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the output until the boost is enabled internally. The delayed output appears at AVDD. AVDD soft-starts at the beginning of the third ramp. The soft start ramp depends on the value of the CDLY capacitor. For CDLY of 220nF, the soft-start time is ~9.6ms. VOFF turns on at the start of the fourth peak. At the same time, DELB gate goes low to turn on the external PMOS to generate a delayed AVDD output. VON is enabled at the beginning of the sixth ramp. Once the start-up sequence is complete, the voltage on the CDLY capacitor remains at 1.15V until either a fault is detected or the EN pin is disabled. If a fault is detected, the voltage on CDLY rises to 2.4V at which point the chip is disabled until the power is cycled or enable is toggled. If the maximum VGS voltage of M0 is less than the AVDD voltage being used, then a resistor may be inserted between the DELB pin and the gate of M0 such that it's potential divider action with R4 ensures the gate/source stays below VGS(M0)max. This additional resistor allows much larger values of C4 to be used, and hence longer AVDD delay, without affecting the fault protection on DELB.
Component Selection for Start-Up Sequencing and Fault Protection
The CREF capacitor is typically set at 220nF and is required to stabilize the VREF output. The range of CREF is from 22nF to 1F and should not be more than five times the capacitor on CDEL to ensure correct start-up operation. The CDEL capacitor is typically 220nF and has a usable range from 47nF minimum to several microfarads - only limited by the leakage in the capacitor reaching A levels. CDEL should be at least 1/5 of the value of CREF (see above). Note, with 220nF on CDEL, the fault time-out will be typically 50ms. and the use of a larger/smaller value will vary this time proportionally (e.g. 1F will give a fault time-out period of typically 230ms).
AVDD_delay Generation Using DELB
DELB pin is an open drain internal N-FET output used to drive an external optional P-FET to provide a delayed AVDD supply which also has no initial pedestal voltage (see Figure 14 and compare the AVDD and AVDD_delayed curves). When the part is enabled, the N-FET is held off until CDLY reaches the 4th peak in the start-up sequence. During this period, the voltage potential of the source and gate of the external P-FET (M0 in application diagram) should be almost the same due to the presence of the resistor (R4) across the source and gate, hence M0 will be off. Please note that the maximum leakage of DELB in this period is 500nA. To avoid any mis-trigger, the maximum value of R4 should be less than:
V GS ( th )_min(M0) R 4_max < ------------------------------------------500nA (EQ. 24)
Fault Sequencing
The ISL97650B has advanced overall fault detection systems including Overcurrent Protection (OCP) for both boost and buck converters, Undervoltage Lockout Protection (UVLP) and Over-Temperature Protection. Once the peak current flowing through the switching MOSFET of the boost and buck converters triggers the current limit threshold, the PWM comparator will disable the output, cycle by cycle, until the current is back to normal. The ISL97650B detects each feedback voltage of AVDD, VON, VOFF and VLOGIC. If any of the VON, VOFF or AVDD feedback is lower than the fault threshold, then a timed fault ramp will appear on CDEL. If it completes, then VON, VOFF and AVDD will shut down, but VLOGIC will stay on. If VLOGIC feedback is lower than the fault threshold, then all channels will switch off, and VIN or Enable needs recycling to turn them on again. An internal temperature sensor continuously monitors the die temperature. In the event that the die temperature exceeds the thermal trip point of +150C, the device will shut down. Operation with die temperatures between +125C and +150C can be tolerated for short periods of time, however, in order to maximize the operating life of the IC, it is recommended that the effective continuous operating junction temperature of the die should not exceed +125C.
Where VGS(th)_min(M0) is the minimum value of gate threshold voltage of M0. After CDLY reaches the 4th peak, the internal N-FET is turned-on and produces an initial current output of IDELB_ON1 (~50A). This current allows the user to control the turn-on inrush current into the AVDD_delay supply capacitors by a suitable choice of C4. This capacitor can provide extra delay and also filter out any noise coupled into the gate of M0, avoiding spurious turn-on, however, C4 must not be so large that it prevents DELB reaching 0.6V by the end of the start-up sequence on CDLY, else a fault time-out ramp on CDLY will start. A value of 22nF is typically required for C4. The 0.6V threshold is used by the chip's fault detection system and if V(DELB) is still above 0.6V at the end of the power sequencing then a fault time-out ramp will be initiated on CDLY. When the voltage at DELB falls below ~0.6V it's current is increased to IDELB_ON2 (~1.4mA) to firmly pull the DELB voltage to ground.
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Layout Recommendation
The device's performance including efficiency, output noise, transient response and control loop stability is dramatically affected by the PCB layout. PCB layout is critical, especially at high switching frequency. There are some general guidelines for layout: 1. Place the external power components (the input capacitors, output capacitors, boost inductor and output diodes, etc.) in close proximity to the device. Traces to these components should be kept as short and wide as possible to minimize parasitic inductance and resistance. 2. Place VREF and VDC bypass capacitors close to the pins. 3. Reduce the loop with large AC amplitudes and fast slew rate. 4. The feedback network should sense the output voltage directly from the point of load, and be as far away from LX node as possible. 5. The power ground (PGND) and signal ground (SGND) pins should be connected at only one point. 6. The exposed die plate, on the underneath of the package, should be soldered to an equivalent area of metal on the PCB. This contact area should have multiple via connections to the back of the PCB as well as connections to intermediate PCB layers, if available, to maximize thermal dissipation away from the IC. 7. To minimize the thermal resistance of the package when soldered to a multi-layer PCB, the amount of copper track and ground plane area connected to the exposed die plate should be maximized and spread out as far as possible from the IC. The bottom and top PCB areas especially should be maximized to allow thermal dissipation to the surrounding air. 8. Minimize feedback input track lengths to avoid switching noise pick-up. A demo board is available to illustrate the proper layout implementation.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 19
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Package Outline Drawing
L36.6x6
36 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 4, 06/08
6.00
A B 28 27
32x 0.50 36
6 PIN #1 INDEX AREA
6 PIN 1 INDEX AREA 1
6.00
4X 4.00
4.15 +0.10/-0.15
19 (4X) 0.15 18 36X 0.55 0.1 BOTTOM VIEW 10
9
36X 0.25 +0.05/-.07 4 0.10 M C A B
TOP VIEW ( 5.65 ) ( 4.15) Exp. Dap. SEE DETAIL "X"
( 5.65 ) ( 32x 0.50) ( 4.15) Exp. Dap.
Max 0.80
0.10 C
C 0.08 C
SIDE VIEW
(36X .25)
C
0 . 2 REF
5
0 . 00 MIN. 0 . 05 MAX. ( 4X 4.00) (36X 0.75) DETAIL "X"
TYPICAL RECOMMENDED LAND PATTERN
1. Dimensions are in millimeters. 2. Dimensioning and tolerancing conform to AMSEY14.5m-1994. 3. Unless otherwise specified, tolerance : Decimal 0.0 4. Dimension applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 5. Tiebar shown (if present) is a non-functional feature. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature.
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