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SE95
Ultra high accuracy digital temperature sensor and thermal watchdog
Rev. 07 -- 2 September 2009 Product data sheet
1. General description
The SE95 is a temperature-to-digital converter using an on-chip band gap temperature sensor and Sigma Delta analog-to-digital conversion technique. The device is also a thermal detector providing an overtemperature detection output. The SE95 contains a number of data registers accessed by a controller via the 2-wire serial I2C-bus interface:
* Configuration register (Conf) to store the device settings such as sampling rate,
device operation mode, OS operation mode, OS polarity, and OS fault queue
* Temperature register (Temp) to store the digital Temp reading * Set-point registers (Tos and Thyst) to store programmable overtemperature shutdown
and hysteresis limits
* Identification register (ID) to store manufacturer numbers
The device includes an open-drain output (pin OS) which becomes active when the temperature exceeds the programmed limits. There are three selectable logic address pins (pins A2 to A0) so that eight devices can be connected on the same bus without address conflict. The SE95 can be configured for different operation conditions. It can be set in normal mode to periodically monitor the ambient temperature, or in shutdown mode to minimize power consumption. The OS output operates in either of two selectable modes: OS comparator mode and OS interrupt mode. Its active state can be selected as either HIGH or LOW. The fault queue that defines the number of consecutive faults in order to activate the OS output is programmable as well as the set-point limits. The temperature register always stores a 13-bit two's complement data giving a temperature resolution of 0.03125 C. This high temperature resolution is particularly useful in applications of measuring precisely the thermal drift or runaway. For normal operation and compatibility with the LM75A, only the 11 MSBs are read, with a resolution of 0.125 C to provide the accuracies specified. To be compatible with the LM75, read only the 9 MSBs. The device is powered-up in normal operation mode with the OS in comparator mode, temperature threshold of 80 C and hysteresis of 75 C, so that it can be used as a stand-alone thermostat with those pre-defined temperature set points. The conversion rate is programmable, with a default of 10 conversions/s.
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SE95
Ultra high accuracy digital temperature sensor and thermal watchdog
2. Features
I I I I I I I I I I I I Pin-for-pin replacement for industry standard LM75/LM75A Specification of a single part over supply voltage from 2.8 V to 5.5 V Small 8-pin package types: SO8 and TSSOP8 (MSOP8) I2C-bus interface to 400 kHz with up to 8 devices on the same bus Supply voltage from 2.8 V to 5.5 V Temperature range from -55 C to +125 C 13-bit ADC that offers a temperature resolution of 0.03125 C Temperature accuracy of 1 C from -25 C to +100 C Programmable temperature threshold and hysteresis set points Supply current of 7.0 A in shutdown mode for power conservation Stand-alone operation as thermostat at power-up ESD protection exceeds 1000 V for Human Body Model (HBM) per JESD22-A114 and 150 V for Machine Model (MM) per JESD22-A115 I Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
3. Applications
I I I I System thermal management Personal computers Electronics equipment Industrial controllers
4. Ordering information
Table 1. Type number SE95D SE95DP SE95U Ordering information Package Temperature range -55 C to +125 C -55 C to +125 C -55 C to +125 C Name SO8 TSSOP8 Description plastic small outline package; 8 leads; body width 3.9 mm plastic thin shrink small outline package; 8 leads; body width 3 mm wafer Version SOT96-1 SOT505-1 -
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5. Block diagram
SE95
ADC CONTROL AND OTP CONTROL
OTP 8 VCC
BIAS bit stream
Conf Temp
BAND GAP SIGMA DELTA MODULATOR OSCILLATOR
Tos DECIMATION FILTER Thyst INTERRUPTION LOGIC
POR
REGISTER BANK 3 I2C-BUS INTERFACE LOGIC 5 A2 6 A1 7 A0 2 SCL 1 SDA 4 GND
002aae892
OS
Fig 1.
Block diagram of SE95
6. Pinning information
6.1 Pinning
SDA SCL OS GND
1 2
8 7
VCC A0 A1 A2
SDA SCL OS GND
1 2 3 4
002aac536
8 7
VCC A0 A1 A2
SE95D
3 4
002aac537
6 5
SE95DP
6 5
Fig 2.
Pin configuration for SO8
Fig 3.
Pin configuration for TSSOP8
6.2 Pin description
Table 2. Symbol SDA SCL OS GND A2 Pin description Pin 1 2 3 4 5 Description I2C-bus serial bidirectional data line digital I/O; open-drain I2C-bus serial clock digital input overtemperature shutdown output; open-drain ground; to be connected to the system ground user-defined address bit 2 digital input
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Ultra high accuracy digital temperature sensor and thermal watchdog
Pin description ...continued Pin 6 7 8 Description user-defined address bit 1 digital input user-defined address bit 0 digital input supply voltage
Table 2. Symbol A1 A0 VCC
7. Functional description
7.1 General operation
The SE95 uses the on-chip band gap sensor to measure the device temperature with a resolution of 0.03125 C and stores the 13-bit two's complement digital data, resulting from 13-bit analog to digital conversion, into register Temp. Register Temp can be read at any time by a controller on the I2C-bus. Reading temperature data does not affect the conversion in progress during the read operation. The device can be set to operate in either mode: normal or shutdown mode. In normal operation mode, by default, the temperature-to-digital conversion is executed every 100 ms and register Temp is updated at the end of each conversion. In shutdown mode, the device becomes idle, data conversion is disabled and register Temp holds the latest result; however, the device I2C-bus interface is still active and register write/read operation can be performed. The device operation mode is controlled by programming bit SHUTDOWN of register Conf. The temperature conversion is initiated when the device is powered up or returned to normal mode from shutdown mode. In addition, at the end of each conversion in normal mode, the temperature data (or Temp) in register Temp is automatically compared with the overtemperature shutdown threshold data (or Tos) stored in register Tos, and the hysteresis data (or Thyst) stored in register Thyst, in order to set the state of the device OS output accordingly. The registers Tos and Thyst are write/read capable, and both operate with 9-bit two's complement digital data. To match with this 9-bit operation, register Temp uses only the 9 MSB bits of its 13-bit data for the comparison. The device temperature conversion rate is programmable and can be chosen to be one of the four values: 0.125, 1.0, 10, and 30 conversions/s. The default conversion rate is 10 conversions/s. Furthermore, the conversion rate is selected by programming bits RATEVAL[1:0] of register Conf as shown in Table 6. Note that the average supply current as well as the device power consumption increase with the conversion rate. The way that the OS output responds to the comparison operation depends upon the OS operation mode selected by configuration bit OS_COMP_INT, and the user-defined fault queue defined by configuration bits OS_F_QUE[1:0]. In OS comparator mode, the OS output behaves like a thermostat. It becomes active when the temperature exceeds Tos, and is reset when the temperature drops below Thyst. Reading the device registers or putting the device into shutdown mode does not change the state of the OS output. The OS output in this case can be used to control cooling fans or thermal switches.
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In OS interrupt mode, the OS output is used for thermal interruption. When the device is powered-up, the OS output is first activated only when Temp exceeds Tos; then it remains active indefinitely until being reset by a read of any register. Once the OS output has been activated by crossing Tos and then reset, it can be activated again only when Temp drops below Thyst; then again, it remains active indefinitely until being reset by a read of any register. The OS interrupt operation would be continued in this sequence: Tos trip, reset, Thyst trip, reset, Tos trip, reset, Thyst trip, reset, and etc. Putting the device into shutdown mode also resets the OS output. In both cases, comparator mode and interrupt mode, the OS output is activated only if a number of consecutive faults, defined by the device fault queue, has been met. The fault queue is programmable and stored in bits OS_F_QUE[1:0], of register Conf. Also, the OS output active state is selectable as HIGH or LOW by setting accordingly the bit OS_POL of register Conf. At power-up, the device is put into normal operation mode, register Tos is set to 80 C, register Thyst is set to 75 C, OS active state is selected LOW and the fault queue is equal to 1. The data reading of register Temp is not available until the first conversion is completed in about 33 ms. The OS response to the temperature is illustrated in Figure 4.
Tos
Thyst
reading temperature limits OS RESET OS ACTIVE OS output in comparator mode
OS RESET OS ACTIVE
(1)
(1)
(1)
OS output in interrupt mode
001aad623
(1) OS is reset by either reading register or putting the device in shutdown mode. Assumed that the fault queue is met at each Tos and Thyst crossing point.
Fig 4.
OS response to temperature
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7.2 OS output and polarity
The OS output is an open-drain output and its state represents results of the device watchdog operation as described in Section 7.1. In order to observe this output state, an external pull-up resistor is needed. The resistor should be as large as possible, up to 200 k, to minimize the Temp reading error due to internal heating by the high OS sinking current. The OS output active state can be selected as HIGH or LOW by programming bit OS_POL of register Conf: setting bit OS_POL to logic 1 selects OS active HIGH and setting to logic 0 sets OS active LOW. At power-up, bit OS_POL is equal to logic 0 and the OS active state is LOW.
7.3 OS comparator and interrupt modes
As described in Section 7.1, the OS output responds to the result of the comparison between register Temp data and the programmed limits, in registers Tos and Thyst, in different ways depending on the selected OS mode: OS comparator or OS interrupt. The OS mode is selected by programming bit OS_COMP_INT of register Conf: setting bit OS_COMP_INT to logic 1 selects the OS interrupt mode, and setting to logic 0 selects the OS comparator mode. At power-up, bit OS_COMP_INT is equal to logic 0 and the OS comparator is selected. The main difference between the two modes is that in OS comparator mode, the OS output becomes active when Temp has exceeded Tos and reset when Temp has dropped below Thyst, reading a register or putting the device into shutdown mode does not change the state of the OS output; while in OS interrupt mode, once it has been activated either by exceeding Tos or dropping below Thyst, the OS output will remain active indefinitely until reading a register or putting the device into shutdown mode occurs, then the OS output is reset. Temperature limits Tos and Thyst must be selected so that Tos > Thyst. Otherwise, the OS output state will be undefined.
7.4 OS fault queue
Fault queue is defined as the number of faults that must occur consecutively to activate the OS output. It is provided to avoid false tripping due to noise. Because faults are determined at the end of data conversions, fault queue is also defined as the number of consecutive conversions returning a temperature trip. The value of fault queue is selectable by programming the two bits OS_F_QUE[1:0] in register Conf. Notice that the programmed data and the fault queue value are not the same. Table 3 shows the one-to-one relationship between them. At power-up, fault queue data = 00 and fault queue value = 1.
Table 3. Fault queue table Fault queue value OS_F_QUE[0] 0 1 0 1 Decimal 1 2 4 6
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Fault queue data OS_F_QUE[1] 0 0 1 1
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7.5 Shutdown mode
The device operation mode is selected by programming bit SHUTDOWN of register Conf. Setting bit SHUTDOWN to logic 1 will put the device into shutdown mode. Resetting bit SHUTDOWN to logic 0 will return the device to normal mode. In shutdown mode, the device draws a small current of approximately 7.5 A and the power dissipation is minimized; the temperature conversion stops, but the I2C-bus interface remains active and register write/read operation can be performed. If the OS output is in comparator mode, then it remains unchanged. In interrupt mode, the OS output is reset.
7.6 Power-up default and power-on reset
The SE95 always powers-up in its default state with:
* * * * * *
Normal operation mode OS comparator mode Tos = 80 C Thyst = 75 C OS output active state is LOW Pointer value is logic 0
When the power supply voltage is dropped below the device power-on reset level of approximately 1.9 V (POR) and then rises up again, the device will be reset to its default condition as listed above.
8. I2C-bus serial interface
The SE95 can be connected to a compatible 2-wire serial interface I2C-bus as a slave device under the control of a controller or master device, using two device terminals, SCL and SDA. The controller must provide the SCL clock signal and write/read data to and from the device through the SDA terminal. Note that if the I2C-bus common pull-up resistors have not been installed as required for I2C-bus, then an external pull-up resistor, approximately 10 k, is needed for each of these two terminals. The bus communication protocols are described in Section 8.7 "Protocols for writing and reading the registers".
8.1 Slave address
The SE95 slave address on the I2C-bus is partially defined by the logic applied to the device address pins A2, A1 and A0. Each pin is typically connected either to GND for logic 0, or to VCC for logic 1. These pins represent the three LSB bits of the device 7-bit address. The other four MSB bits of the address data are preset to 1001 by hard wiring inside the SE95. Table 4 shows the device's complete address and indicates that up to 8 devices can be connected to the same bus without address conflict. Because the input pins SCL, SDA and A2 to A0, are not internally biased, it is important that they should not be left floating in any application. 0Ch is a reserved address for SMBus Alert Response Address (ARA). This is an optional command from the SMBus specification to allow SMBus devices to respond to an SMBus master with their slave device if they are generating an interrupt. The SE95 will send a
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false alert if the address 0Ch is sent and cannot be active on the I2C-bus if this address is used. Consider using the SE98 since it supports SMBus ARA as well as time-out features and provides 1 C accuracy.
Table 4. MSB 1 0 0 1 A2 A1 Address table LSB A0
8.2 Register list
The SE95 contains 7 data registers. The registers can be 1 byte or 2 bytes wide, and are defined in Table 5. The registers are accessed by the value in the content of the pointer register during I2C-bus communication. The types of registers are: read only, read/write, and reserved for manufacturer use. Note that when reading a two-byte register, the host must provide enough clock pulses as required by the I2C-bus protocol (see Section 8.7) for the device to completely return both data bytes. Otherwise the device may hold the SDA line in LOW state, resulting in a bus hang condition.
Table 5. Register name Conf Temp Tos Register table Pointer value 01h 00h 03h R/W R/W read only R/W POR state 00h N/A 5000h Description configuration register: contains a single 8-bit data byte; to set an operating condition temperature register: contains two 8-bit data bytes; to store the measured Temp overtemperature shutdown threshold register: contains two 8-bit data bytes; to store the overtemperature shutdown limit; default Tos = 80 C hysteresis register: contains two 8-bit data bytes; to store the hysteresis limit; bit 7 to bit 0 are also used in OTP (One Time Programmable) test mode to supply OTP write data; default Thyst = 75 C identification register: contains a single 8-bit data byte for the manufacturer ID code reserved reserved
Thyst
02h
R/W
4B00h
ID Reserved Reserved
05h 04h 06h
read only N/A N/A
A1h N/A N/A
8.3 Register pointer
The register pointer or pointer byte is an 8-bit data byte that is equivalent to the register command in the I2C-bus definitions and is used to identify the device register to be accessed for a write or read operation. Its values are listed as pointer values in Table 5. For the device register I2C-bus communication, the pointer byte may or may not need to be included within the command as illustrated in the I2C-bus protocol figures in Section 8.7. The command statements for writing data to a register must always include the pointer byte; while the command statements for reading data from a register may or may not include it. To read a register that is different from the one that has been recently read, the pointer byte must be included. However, to re-read a register that has been recently read, the pointer byte may not have to be included in the reading.
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Ultra high accuracy digital temperature sensor and thermal watchdog
At power-up, the pointer value is preset to logic 0 for register Temp; users can then read the temperature without specifying the pointer byte.
8.4 Configuration register
The Configuration (Conf) register is a read/write register and contains an 8-bit non-complement data byte that is used to configure the device for different operating conditions. Table 6 shows the bit assignments of this register.
Table 6. Conf register Legend: * = default value. Bit 7 6 and 5 Symbol reserved RATEVAL[1:0] Access R/W R/W 00* 01 10 11 4 and 3 OS_F_QUE[1:0] R/W 00* 01 10 11 2 OS_POL R/W 0* 1 1 OS_COMP_INT R/W 0* 1 0 SHUTDOWN R/W 0 0* 1 Value 0* Description reserved for manufacturer's use sets the conversion rate 10 conversion/s 0.125 conversion/s 1 conversion/s 30 conversion/s OS fault queue programming queue value = 1 queue value = 2 queue value = 4 queue value = 6 OS polarity selection OS active LOW OS active HIGH OS operation mode selection OS comparator OS interrupt operation mode normal shutdown
8.5 Temperature register
The Temperature (Temp) register holds the digital result of temperature measurement or monitor at the end of each analog to digital conversion. This register is read only and contains two 8-bit data bytes consisting of one Most Significant Byte (MSByte) and one Least Significant Byte (LSByte). However, only 13 bits of those two bytes are used to store the Temp data in two's complement format with the resolution of 0.03125 C. Table 7 shows the bit arrangement of the Temp data in the data bytes.
Table 7. MSByte 7 6 5 4 3 2 1 D9 0 D8 D15 D14 D13 D12 D11 D10 Temp register LSByte 7 D7 6 D6 5 D5 4 D4 3 D3 2 D2 1 D1 0 D0
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When reading register Temp, all 16 bits of the two data bytes (MSByte and LSByte) must be collected and then the two's complement data value according to the desired resolution must be selected for the temperature calculation. Table 8 shows the example for 11-bit two's complement data value, Table 9 shows the example for 13-bit two's complement data value.
Table 8. MSByte 7 D10 6 D9 5 D8 4 D7 3 D6 2 D5 1 D4 0 D3 Example 11-bit two's complement Temp register LSByte 7 D2 6 D1 5 D0 4 X 3 X 2 X 1 X 0 X
Table 9. MSByte 7 6
Example 13-bit two's complement register LSByte 5 4 D9 3 D8 2 D7 1 D6 0 D5 7 D4 6 D3 5 D2 4 D1 3 D0 2 X 1 X 0 X
D12 D11 D10
When converting into the temperature the proper resolution must be used as listed in Table 10 using either one of these two formulae: 1. If the Temp data MSB = 0, then: Temp (C) = +(Temp data) x value resolution 2. If the Temp data MSB = 1, then: Temp (C) = -(two's complement Temp data) x value resolution
Table 10. 8 bit 9 bit 10 bit 11 bit 12 bit 13 bit Temp data and Temp value resolution Value resolution 1.0 C 0.5 C 0.25 C 0.125 C 0.0625 C 0.03125 C
Data resolution
Table 11 shows some examples of the results for the 11-bit calculations.
Table 11. Temp register value Hexadecimal value 3F8 3F7 3F1 3E8 0C8 001 000 7FF 738 649 648 Decimal value 1016 1015 1009 1000 200 1 0 -1 -200 -439 -440 Value +127.000 C +126.875 C +126.125 C +125.000 C +25.000 C +0.125 C 0.000 C -0.125 C -25.000 C -54.875 C -55.000 C
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11-bit binary (two's complement) 011 1111 1000 011 1111 0111 011 1111 0001 011 1110 1000 000 1100 1000 000 0000 0001 000 0000 0000 111 1111 1111 111 0011 1000 110 0100 1001 110 0100 1000
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Obviously, for 9-bit Temp data application in replacing the industry standard LM75, just use only 9 MSB bits of the two bytes and disregard 7 LSB of the LSByte. The 9-bit Temp data with 0.5 C resolution of the SE95 is defined exactly in the same way as for the standard LM75 and it is here similar to the Tos and Thyst registers.
8.6 Overtemperature shutdown threshold and hysteresis registers
These two registers, are write/read registers, and also called set-point registers. They are used to store the user-defined temperature limits, called overtemperature shutdown threshold (Tos) and hysteresis temperature (Thyst), for the device watchdog operation. At the end of each conversion the Temp data will be compared with the data stored in these two registers in order to set the state of the device OS output; see Section 7.1. Each of the set-point registers contains two 8-bit data bytes consisting of one MSByte and one LSByte the same as register Temp. However, only 9 bits of the two bytes are used to store the set-point data in two's complement format with the resolution of 0.5 C. Table 12 and Table 13 show the bit arrangement of the Tos data and Thyst data in the data bytes. Notice that because only 9-bit data are used in the set-point registers, the device uses only the 9 MSB of the Temp data for data comparison.
Table 12. MSByte 7 D8 6 D7 5 D6 4 D5 3 D4 2 D3 1 D2 0 D1 Tos register LSByte 7 D0 6 X 5 X 4 X 3 X 2 X 1 X 0 X
Table 13. MSByte 7 D8 6 D7
Thyst register LSByte 5 D6 4 D5 3 D4 2 D3 1 D2 0 D1 7 D0 6 X 5 X 4 X 3 X 2 X 1 X 0 X
When a set-point register is read, all 16 bits are provided to the bus and must be collected by the controller to complete the bus operation. However, only the 9 most significant bits should be used and the 7 LSB of the LSByte are equal to zero and should be ignored. Table 14 shows examples of the limit data and value.
Table 14. Tos and Thyst register Hexadecimal value 0FA 032 001 000 1FF 1CE 192 Decimal value 250 50 1 0 -1 -50 -110 Value 125.0 C 25.0 C 0.5 C 0.0 C -0.5 C -25.0 C -55.0 C
11-bit binary (two's complement) 0 1111 1010 0 0011 0010 0 0000 0001 0 0000 0000 1 1111 1111 1 1100 1110 1 1001 0010
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8.7 Protocols for writing and reading the registers
The communication between the host and the SE95 must follow the rules strictly as defined by the I2C-bus management. The protocols for SE95 register read/write operations are illustrated in Figure 5 to Figure 10 together with the following definitions: 1. Before a communication, the I2C-bus must be free or not busy. It means that the SCL and SDA lines must both be released by all devices on the bus, and they become HIGH by the bus pull-up resistors. 2. The host must provide SCL clock pulses necessary for the communication. Data is transferred in a sequence of 9 SCL clock pulses for every 8-bit data byte followed by 1-bit status of the acknowledgement. 3. During data transfer, except the START and STOP signals, the SDA signal must be stable while the SCL signal is HIGH. It means that the SDA signal can be changed only during the LOW duration of the SCL line. 4. S: START signal, initiated by the host to start a communication, the SDA goes from HIGH-to-LOW while the SCL is HIGH. 5. RS: RE-START signal, same as the START signal, to start a read command that follows a write command. 6. P: STOP signal, generated by the host to stop a communication, the SDA goes from LOW-to-HIGH while the SCL is HIGH. The bus becomes free thereafter. 7. W: write bit, when the write/read bit is in a write command. 8. R: read bit, when the write/read bit is logic 1 in a read command. 9. A: device acknowledge bit, returned by the SE95. It is logic 0 if the device works properly and logic 1 if not. The host must release the SDA line during this period in order to give the device the control on the SDA line. 10. A': master acknowledge bit, not returned by the device, but set by the master or host in reading 2-byte data. During this clock period, the host must set the SDA line to LOW in order to notify the device that the first byte has been read for the device to provide the second byte onto the bus. 11. NA: not-acknowledge bit. During this clock period, both the device and host release the SDA line at the end of a data transfer, the host is then enabled to generate the stop signal. 12. In a write protocol, data is sent from the host to the device and the host controls the SDA line, except during the clock period when the device sends the device acknowledgement signal to the bus. 13. In a read protocol, data is sent to the bus by the device and the host must release the SDA line during the time that the device is providing data onto the bus and controlling the SDA line, except during the clock period when the master sends the master acknowledgement signal to the bus.
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1 SCL SDA S 1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
0
0
1
A2 A1 A0 W
A
0
0
0
0
0
0
0
1
A
0
0
0
D4 D3 D2 D1 D0 A
P
device address START write device acknowledge
pointer byte device acknowledge
configuration data byte device acknowledge STOP
001aad624
Fig 5.
Write configuration register (1-byte data)
1 SCL SDA S 1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9 (next)
0
0
1
A2
A1
A0 W
A
0
0
0
0
0
0
0
1
A
RS (next)
device address START write device acknowledge 1 SCL (cont.) SDA (cont.) 1 0 0 1 A2 A1 A0 R A 2 3 4 5 6 7 8 9 1 2
pointer byte device acknowledge RE-START
3
4
5
6
7
8
9
D7 D6 D5 D4 D3 D2 D1 D0 NA data byte from device
P
device address read device acknowledge
master not acknowledged
STOP
001aad625
Fig 6.
Read configuration register including pointer byte (1-byte data)
1 SCL SDA S 1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
0
0
1
A2
A1
A0 R
A
D7 D6 D5 D4 D3 D2 D1 D0 NA data byte from device
P
device address START read device acknowledge
master not acknowledged
STOP
001aad626
Fig 7.
Read configuration register with preset pointer (1-byte data)
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1 SCL SDA S 1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9 (next)
0
0
1
A2
A1
A0
W
A
0
0
0
0
0
0
P1
P0
A
(next)
device address START write device acknowledge 1 SCL (cont.) SDA (cont.) D7 D6 D5 D4 D3 D2 D1 D0 A ms byte data device acknowledge 2 3 4 5 6 7 8 9 1 2
pointer byte device acknowledge
3
4
5
6
7
8
9
D7 D6 D5 D4 D3 D2 D1 D0 ls byte data device acknowledge
A
P
STOP
001aad627
Fig 8.
Write Tos or Thyst register (2-byte data)
1 SCL SDA S 1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
0 (next)
0
0
1
A2 A1 A0 W A
0
0
0
0
0
0
P1 P0 A RS (next)
device address START write device acknowledge 5678
pointer byte device acknowledge 9 1 2 3 4 5 6 7 8 9 1 RE-START
1 SCL (cont) SDA (cont) 1
2
3
4
2
3
4
5
6
7
8
9
0
0
1
A2 A1 A0 R
A
D7 D6 D5 D4 D3 D2 D1 D0 A4 D7 D6 D5 D4 D3 D2 D1 D0 NA ms byte from device ls byte from device master not acknowledged
P
device address read device acknowledge
master acknowledge
STOP
001aad628
Fig 9.
Read Temp, Tos or Thyst register including pointer byte (2-byte data)
1 SCL SDA S 1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
0
0
1
A2 A1 A0 R
A
D7 D6 D5 D4 D3 D2 D1 D0 A4 D7 D6 D5 D4 D3 D2 D1 D0 NA ms byte from device ls byte from device master not acknowledged
P
device address START read device acknowledge
master acknowledge
STOP
001aad629
Fig 10. Read Temp, Tos or Thyst register with preset pointer (2-byte data)
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9. Limiting values
Table 15. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol VCC VI(SCL) VI(SDA) VI(A0) VI(A1) VI(A2) II(PIN) IO(OS) VO(OS) VESD Tstg Tj Parameter supply voltage input voltage on pin SCL input voltage on pin SDA input voltage on pin A0 input voltage on pin A1 input voltage on pin A2 input current on input pins output current on pin OS output voltage on pin OS electrostatic discharge voltage storage temperature junction temperature human body model machine model Conditions Min -0.3 -0.3 -0.3 -3.0 -3.0 -3.0 -5.0 -0.3 -65 Max +6.0 +6.0 +6.0 VCC + 0.3 VCC + 0.3 VCC + 0.3 +5.0 10.0 +6.0 1000 150 +150 150 Unit V V V V V V mA mA V V V C C
10. Recommended operating conditions
Table 16. Symbol VCC Tamb Recommended operating characteristics Parameter supply voltage ambient temperature Conditions Min 2.8 -55 Typ Max 5.5 +125 Unit V C
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11. Static characteristics
Table 17. Static characteristics VCC = 2.8 V to 5.5 V, Tamb = -55 C to +125 C; unless otherwise specified. Symbol Parameter Tacc temperature accuracy Conditions VCC = 2.8 V to 3.6 V Tamb = -25 C to +100 C Tamb = -55 C to +125 C VCC = 3.6 V to 5.5 V Tamb = -25 C to +100 C Tamb = -55 C to +125 C Tres tconv(T) ICC temperature resolution temperature conversion time supply current 11-bit digital temperature data normal mode normal mode: normal mode: VIH VIL VI(hys) IIH IIL VOL ILO VPOR OSQ Tos fsam Thyst Ci
[1] [2] [3] [4]
[2] [2]
Min -1.0 -2.0 -2 -3 I2C-bus I2C-bus inactive active
[3] [3]
Typ[1] 0.125 33 150 7.5 300 300 80 10 75 20
Max +1.0 +2.0 +2 +3 1.0 VCC + 0.3 +0.3VCC +1.0 +1.0 0.4 0.8 10 2.5 6 30 -
Unit C C C C C ms A mA A V V mV mV A A V V A V
0.7VCC -0.3 [3] [3]
shutdown mode HIGH-level input voltage LOW-level input voltage hysteresis of input voltage HIGH-level input current LOW-level input current LOW-level output voltage output leakage current power-on reset voltage OS fault queue overtemperature shutdown threshold sampling rate hysteresis temperature input capacitance digital pins digital pins pins SCL and SDA pins A2 to A0 digital pins; VIN = VCC digital pins; VIN = 0 V pins SDA and OS; IOL = 3 mA IOL = 4 mA pins SDA and OS; VOH = VCC VCC supply below which the logic is reset programmable default value programmable default value digital pins
[4]
-1.0 -1.0 1.0 1 0.125 -
C sample/s C pF
Typical values are at VCC = 3.3 V and Tamb = 25 C. Assumes a minimum 11-bit temperature reading. The digital pins are pin SCL, SDA and A2 to A0. Device analog-to-digital conversion.
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12. Dynamic characteristics
Table 18. Dynamic characteristics[1] VCC = 2.8 V to 5.5 V, Tamb = -55 C to +125 C; unless otherwise specified. Symbol Parameter TCLK t(SCL)H t(SCL)L tHD;STA tSU;DAT tHD;DAT tSU;STO tf SCL clock period HIGH period of the SCL clock LOW period of the SCL clock hold time (repeated) START condition data set-up time data hold time set-up time for STOP condition fall time pins SDA and OS; CL = 400 pF; IOL = 3 mA Conditions see Figure 11 Min 2.5 0.6 1.3 100 100 0 100 Typ 250 Max Unit s s s ns ns ns ns ns
[1]
These specifications are guaranteed by design and not tested in production.
SDA tLOW tf
tf SCL tHD;STA
tSU;DAT
tHD;STA
s
tHD;DAT
tHIGH
sr
tSU;STO
p
s
001aad616
Fig 11.
Timing diagram
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Ultra high accuracy digital temperature sensor and thermal watchdog
13. Performance curves
001aad617 001aad618
25 ICC(SD) (A) 20
300 ICC (A) 200 VCC = 5.5 V 3.9 V 3.3 V 2.8 V
VCC = 5.5 V
15 3.9 V 10 3.3 V 2.8 V 100
5
0 -50
-25
0
25
50
75
100 125 T (C)
0 -50
-25
0
25
50
75
100 125 T (C)
Fig 12. Shutdown supply current as a function of temperature
300 ICC (A) 200 10 conversions/s 1 conversions/s 0.125 conversions/s 100
001aad619
Fig 13. Typical normal I2C-bus inactive supply current as a function of temperature
0.25 VOL(SDA) (V) VCC = 2.8 V 0.20 3.3 V 0.15 3.9 V 5.5 V
001aad620
30 conversions/s
0.10
0.05
0 -50
-25
0
25
50
75
100 125 T (C)
0 -50
-25
0
25
50
75
100 125 T (C)
Fig 14. Typical normal I2C-bus inactive supply current as a function of temperature
25 tconv(T) (ms) 20
001aad621
Fig 15.
Typical SDA VOL as a function of temperature
25 VOL(OS) (V) 20
001aad622
15
15
VCC = 2.8 V 3.3 V 3.9 V 5.5 V
10
10
5
5
0 -50
-25
0
25
50
75
100 125 T (C)
0 -50
-25
0
25
50
75
100 125 T (C)
Fig 16. Typical conversion time as a function of temperature
Fig 17. Typical OS VOL as a function of temperature
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Ultra high accuracy digital temperature sensor and thermal watchdog
14. Application information
The SE95 is sensitive to power supplies with ramp-up time 2 ms and could NACK or hang the I2C-bus. In most applications the SE95 will function properly since power supplies have a >2 ms ramp-up time. If the power supply ramp-up time is 2 ms, use an RC network with R = 300 and C = 10 F, as shown in Figure 18, to add about 3 ms to the ramp-up time. The 10 F capacitor is the same as the bypass capacitor that is typically used to prevent fluctuations on the power supply. The 300 resistor will reduce the supply voltage by about 45 mV since the SE95 supply current is about 150 A. Ensure the SE95 is the only device connected to the end of 300 resistor since additional devices would draw more current and cause a larger voltage drop across the resistor.
power supply
300
power supply
10 k 10 F
VCC SCL I2C-bus SDA
SE95
OS A2 A1 A0 digital logic or tie to VCC or GND
detector or interrupt line
GND
002aae891
Fig 18.
Typical application circuit
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Ultra high accuracy digital temperature sensor and thermal watchdog
15. Package outline
SO8: plastic small outline package; 8 leads; body width 3.9 mm SOT96-1
D
E
A X
c y HE vMA
Z 8 5
Q A2 A1 pin 1 index Lp 1 e bp 4 wM L detail X (A 3) A
0
2.5 scale
5 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches Notes 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. OUTLINE VERSION SOT96-1 REFERENCES IEC 076E03 JEDEC MS-012 JEITA EUROPEAN PROJECTION A max. 1.75 0.069 A1 0.25 0.10 A2 1.45 1.25 A3 0.25 0.01 bp 0.49 0.36 c 0.25 0.19 D (1) 5.0 4.8 0.20 0.19 E (2) 4.0 3.8 0.16 0.15 e 1.27 0.05 HE 6.2 5.8 L 1.05 Lp 1.0 0.4 Q 0.7 0.6 v 0.25 0.01 w 0.25 0.01 y 0.1 0.004 Z (1) 0.7 0.3 0.028 0.012
0.010 0.057 0.004 0.049
0.019 0.0100 0.014 0.0075
0.244 0.039 0.028 0.041 0.228 0.016 0.024
8o o 0
ISSUE DATE 99-12-27 03-02-18
Fig 19. Package outline SOT96-1 (SO8)
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SE95
Ultra high accuracy digital temperature sensor and thermal watchdog
TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm
SOT505-1
D
E
A
X
c y HE vMA
Z
8
5
A2 pin 1 index
A1
(A3)
A
Lp L
1
e bp
4
detail X wM
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.1 A1 0.15 0.05 A2 0.95 0.80 A3 0.25 bp 0.45 0.25 c 0.28 0.15 D(1) 3.1 2.9 E(2) 3.1 2.9 e 0.65 HE 5.1 4.7 L 0.94 Lp 0.7 0.4 v 0.1 w 0.1 y 0.1 Z(1) 0.70 0.35 6 0
Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT505-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-04-09 03-02-18
Fig 20. Package outline SOT505-1 (TSSOP8)
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Ultra high accuracy digital temperature sensor and thermal watchdog
16. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 "Surface mount reflow soldering description".
16.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization.
16.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following:
* Through-hole components * Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are:
* * * * * *
Board specifications, including the board finish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus SnPb soldering
16.3 Wave soldering
Key characteristics in wave soldering are:
* Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are exposed to the wave
* Solder bath specifications, including temperature and impurities
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Ultra high accuracy digital temperature sensor and thermal watchdog
16.4 Reflow soldering
Key characteristics in reflow soldering are:
* Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 21) than a SnPb process, thus reducing the process window
* Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
* Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 19 and 20
Table 19. SnPb eutectic process (from J-STD-020C) Package reflow temperature (C) Volume (mm3) < 350 < 2.5 2.5 Table 20. 235 220 Lead-free process (from J-STD-020C) Package reflow temperature (C) Volume (mm3) < 350 < 1.6 1.6 to 2.5 > 2.5 260 260 250 350 to 2000 260 250 245 > 2000 260 245 245 350 220 220
Package thickness (mm)
Package thickness (mm)
Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 21.
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Product data sheet
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NXP Semiconductors
SE95
Ultra high accuracy digital temperature sensor and thermal watchdog
temperature
maximum peak temperature = MSL limit, damage level
minimum peak temperature = minimum soldering temperature
peak temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 21. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365 "Surface mount reflow soldering description".
17. Abbreviations
Table 21. Acronym ADC ESD HBM I2C-bus I/O LSB LSByte MM MSB MSByte OTP POR SMBus Abbreviations Description Analog-to-Digital Converter ElectroStatic Discharge Human Body Model Inter-Integrated Circuit bus Input/Output Least Significant Bit Least Significant Byte Machine Model Most Significant Bit Most Significant Byte One-Time Programmable Power-On Reset System Management Bus
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Ultra high accuracy digital temperature sensor and thermal watchdog
18. Revision history
Table 22. SE95_7 Modifications: Revision history Release date 20090902 Data sheet status Product data sheet Change notice Supersedes SE95_6 Document ID
* *
Figure 1 "Block diagram of SE95": changed from "AVD CONTOL" to "ADC CONTROL" Section 14 "Application information": - Added first paragraph - Figure 18 "Typical application circuit" modified
* *
SE95_6 SE95_5 SE95_4 SE95_3 (9397 750 14388) SE95_2 (9397 750 14163) SE95_1 (9397 750 10265)
Added soldering information Added Section 17 "Abbreviations" Product data sheet Product data sheet Product data sheet Product data sheet Objective specification Objective specification SE95_5 SE95_4 SE95_3 SE95_2 SE95_1 -
20090604 20071213 20070212 20051212 20041005 20031003
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Ultra high accuracy digital temperature sensor and thermal watchdog
19. Legal information
19.1 Data sheet status
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]
Product status[3] Development Qualification Production
Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification.
Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
19.2 Definitions
Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.
damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control -- This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities.
19.3 Disclaimers
General -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental
19.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. I2C-bus -- logo is a trademark of NXP B.V.
20. Contact information
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com
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Ultra high accuracy digital temperature sensor and thermal watchdog
21. Contents
1 2 3 4 5 6 6.1 6.2 7 7.1 7.2 7.3 7.4 7.5 7.6 8 8.1 8.2 8.3 8.4 8.5 8.6 8.7 9 10 11 12 13 14 15 16 16.1 16.2 16.3 16.4 17 18 19 19.1 19.2 19.3 19.4 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 4 General operation . . . . . . . . . . . . . . . . . . . . . . . 4 OS output and polarity . . . . . . . . . . . . . . . . . . . 6 OS comparator and interrupt modes . . . . . . . . 6 OS fault queue . . . . . . . . . . . . . . . . . . . . . . . . . 6 Shutdown mode . . . . . . . . . . . . . . . . . . . . . . . . 7 Power-up default and power-on reset . . . . . . . . 7 I2C-bus serial interface . . . . . . . . . . . . . . . . . . . 7 Slave address . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Register list . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Register pointer . . . . . . . . . . . . . . . . . . . . . . . . 8 Configuration register . . . . . . . . . . . . . . . . . . . . 9 Temperature register. . . . . . . . . . . . . . . . . . . . . 9 Overtemperature shutdown threshold and hysteresis registers . . . . . . . . . . . . . . . . . 11 Protocols for writing and reading the registers . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 15 Recommended operating conditions. . . . . . . 15 Static characteristics. . . . . . . . . . . . . . . . . . . . 16 Dynamic characteristics . . . . . . . . . . . . . . . . . 17 Performance curves . . . . . . . . . . . . . . . . . . . . 18 Application information. . . . . . . . . . . . . . . . . . 19 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 20 Soldering of SMD packages . . . . . . . . . . . . . . 22 Introduction to soldering . . . . . . . . . . . . . . . . . 22 Wave and reflow soldering . . . . . . . . . . . . . . . 22 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 22 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 23 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 25 Legal information. . . . . . . . . . . . . . . . . . . . . . . 26 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 26 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 20 21 Contact information . . . . . . . . . . . . . . . . . . . . 26 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'.
(c) NXP B.V. 2009.
All rights reserved.
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 2 September 2009 Document identifier: SE95_7

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