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| SSM4228M/GM DUAL N-CHANNEL ENHANCEMENT-MODE POWER MOSFETS Low on-resistance High Vgs rating Surface-mount package D1 D1 D2 D2 BV DSS R DS(ON) G2 S2 30V 25m 6.8A ID SO-8 S1 G1 Description D1 D2 Power MOSFETs from Silicon Standard provide the designer with the best combination of fast switching, ruggedized device design, ultra low on-resistance and cost-effectiveness. G1 S1 G2 S2 This device is available with Pb-free lead finish (second-level interconnect) as SSM4228GM. Absolute Maximum Ratings Symbol VDS VGS ID @ TA=25C ID @ TA=70C IDM PD @ TA=25C TSTG TJ Parameter Drain-Source Voltage Gate-Source Voltage Continuous Drain Current Continuous Drain Current Pulsed Drain Current 1,4 3 3 Rating 30 25 6.8 5.5 30 2 0.016 -55 to 150 -55 to 150 Units V V A A A A W/C C C Total Power Dissipation Linear Derating Factor Storage Temperature Range Operating Junction Temperature Range Thermal Data Symbol Rthj-a Parameter Thermal Resistance Junction-ambient Max. Value 62.5 Unit C/W 4/26/2004 Rev.2.10 www.SiliconStandard.com 1 of 6 SSM4228M/GM Electrical Characteristics @ T j=25oC (unless otherwise specified) Symbol BVDSS BV DSS/ Tj Parameter Drain-Source Breakdown Voltage Test Conditions VGS=0V, ID=250uA Min. 30 1 - Typ. 0.03 15 22 15 17.5 4.7 8.5 10.6 12.4 26.2 12 1535 310 200 Max. Units 25 35 3 1 25 100 V V/C m m V S uA uA nA nC nC nC ns ns ns ns pF pF pF Breakdown Voltage Temperature Coefficient Reference to 25C, ID=1mA RDS(ON) VGS(th) gfs IDSS IGSS Qg Qgs Qgd td(on) tr td(off) tf Ciss Coss Crss Static Drain-Source On-Resistance VGS=10V, ID=6A VGS=4.5V, ID=4A VDS=VGS, ID=250uA VDS=10V, ID=6A Gate Threshold Voltage Forward Transconductance Drain-Source Leakage Current (Tj=25 C) Drain-Source Leakage Current (Tj=70 C) o o VDS=30V, VGS=0V VDS=24V ,VGS=0V VGS= 25V ID=6A VDS=20V VGS=5V VDS=20V ID=2A RG=3.3 ,VGS=10V RD=10 VGS=0V VDS=25V f=1.0MHz Gate-Source Leakage Total Gate Charge 2 Gate-Source Charge Gate-Drain ("Miller") Charge Turn-on Delay Time Rise Time Turn-off Delay Time Fall Time Input Capacitance Output Capacitance Reverse Transfer Capacitance 2 Source-Drain Diode Symbol IS ISM VSD Parameter Continuous Source Current ( Body Diode ) Test Conditions VD=VG=0V , VS=1.3V 1 Min. - Typ. - Max. Units 1.7 30 1.3 A A V Pulsed Source Current ( Body Diode ) Forward On Voltage 2 Tj=25C,IS=1.7A, VGS=0V Notes: 1.Pulse width limited by Max. junction temperature. 2.Pulse width <300us , duty cycle <2%. 3.Surface mounted on FR4 board, t<10 sec. 4.Pulse width <10us , duty cycle <1%. 4/26/2004 Rev.2.10 www.SiliconStandard.com 2 of 6 SSM4228M/GM 35 35 T C =25 o C 28 V G =10V V G =5.0V V G =4.0V ID , Drain Current (A) 28 T C =150 o C V G =10V V G =5.0V V G =4.0V ID , Drain Current (A) 21 21 14 14 7 7 V G =3.0V V G =3.0V 0 0 1 2 3 0 0 1 2 3 V DS , Drain-to-Source Voltage (V) V DS , Drain-to-Source Voltage (V) Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics 80 1.8 Id=6A T c =25C 60 1.6 I D =6A V G =10V Normalized R DS(ON) 2 4 6 8 10 12 1.4 RDSON (m ) 40 1.2 1 20 0.8 0 0.6 -50 0 50 100 150 V GS (V) T j , Junction Temperature ( C) o Fig 3. On-Resistance vs. Gate Voltage Fig 4. Normalized On-Resistance vs. Junction Temperature 4/26/2004 Rev.2.10 www.SiliconStandard.com 3 of 6 SSM4228M/GM 8 2.5 2 6 ID , Drain Current (A) 1.5 4 PD (W) 1 0.5 0 2 0 25 50 75 100 125 150 0 50 100 150 T c , Case Temperature ( C) o T c , Case Temperature ( C) o Fig 5. Maximum Drain Current vs. Case Temperature Fig 6. Typical Power Dissipation 100 1 DUTY=0.5 Normalized Thermal Response (R thja) 10 0.2 1ms 10ms ID (A) 1 0.1 0.1 0.05 100ms 0.02 0.01 PDM 1s 0.1 0.01 SINGLE PULSE t T 10s T c =25 o C Single Pluse Duty factor = t/T Peak Tj = P DM x Rthja + Ta DC 0.001 0.01 0.1 1 10 100 0.0001 0.001 0.01 0.1 1 10 100 1000 V DS (V) t , Pulse Width (s) Fig 7. Maximum Safe Operating Area Fig 8. Effective Transient Thermal Impedance 4/26/2004 Rev.2.10 www.SiliconStandard.com 4 of 6 SSM4228M/GM 15 f=1.0MHz 10000 Id=6A V DS =20V 12 VGS , Gate to Source Voltage (V) Ciss 1000 9 C (pF) Coss 6 Crss 100 3 0 0 10 20 30 40 10 1 6 11 16 21 26 31 Q G , Total Gate Charge (nC) V DS (V) Fig 9. Gate Charge Characteristics Fig 10. Typical Capacitance Characteristics 10 2.5 Tj=150 o C Tj=25 o C 2 1 VGS(th) (V) 1.5 1 0 0.4 0.8 1.2 1.6 -50 0 50 100 150 IS(A) 0.1 V SD (V) T j , Junction Temperature ( C ) o Fig 11. Forward Characteristic of Fig 12. Gate Threshold Voltage vs. Reverse Diode Junction Temperature 4/26/2004 Rev.2.10 www.SiliconStandard.com 5 of 6 SSM4228M/GM VDS RD 90% D VDS TO THE OSCILLOSCOPE 0.64 x RATED VDS RG G + 10 v - S VGS 10% VGS td(on) tr td(off) tf Fig 13. Switching Time Circuit Fig 14. Switching Time Waveform VG VDS TO THE OSCILLOSCOPE QG 5V D 0.64 x RATED VDS G S + QGS QGD VGS 1~ 3 mA IG I D Charge Q Fig 15. Gate Charge Circuit Fig 16. Gate Charge Waveform Information furnished by Silicon Standard Corporation is believed to be accurate and reliable. However, Silicon Standard Corporation makes no guarantee or warranty, express or implied, as to the reliability, accuracy, timeliness or completeness of such information and assumes no responsibility for its use, or for infringement of any patent or other intellectual property rights of third parties that may result from its use. Silicon Standard reserves the right to make changes as it deems necessary to any products described herein for any reason, including without limitation enhancement in reliability, functionality or design. No license is granted, whether expressly or by implication, in relation to the use of any products described herein or to the use of any information provided herein, under any patent or other intellectual property rights of Silicon Standard Corporation or any third parties. 4/26/2004 Rev.2.10 www.SiliconStandard.com 6 of 6 |
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