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ESMT
SDRAM
M12L128324A
1M x 32 Bit x 4 Banks Synchronous DRAM
FEATURES
JEDEC standard 3.3V power supply LVTTL compatible with multiplexed address Four banks operation MRS cycle with address key programs - CAS Latency (1, 2 & 3 ) - Burst Length ( 1, 2, 4, 8 & full page ) - Burst Type ( Sequential & Interleave ) All inputs are sampled at the positive going edge of the system clock DQM for masking Auto & self refresh 64ms refresh period (4K cycle)
ORDERING INFORMATION
Product No. M12L128324A-6TG M12L128324A-7TG M12L128324A-6BG M12L128324A-7BG MAX FREQ. PACKAGE COMMENTS 166MHz 143MHz 166MHz 143MHz 86 TSOPII 86 TSOPII 90 FBGA 90 FBGA Pb-free Pb-free Pb-free Pb-free
GENERAL DESCRIPTION
The M12L128324A is 134,217,728 bits synchronous high data rate Dynamic RAM organized as 4 x 1,048,576 words by 32 bits. Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.
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Publication Date: Aug. 2009 Revision: 1.4 1/46
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PIN ARRANGEMENT
Top View
V DD DQ0 VD
DQ
M12L128324A
DQ1 DQ2 VSSQ DQ3 DQ4 V D DQ DQ5 DQ6 VSSQ DQ7 NC V
DD
D Q M0 WE C AS R AS CS A 11 BA0 BA1 A1 0/AP A0 A1 A2 D Q M2 VD D NC D Q 16 V S SQ D Q 17 D Q 18 VDDQ D Q 19 D Q 20 V S SQ D Q 21 D Q 22 VD DQ D Q 23 V
DD
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44
VS
S
D Q 15 V S SQ D Q 14 D Q 13 VD DQ D Q 12 D Q 11 V S SQ D Q 10 DQ9 VD DQ DQ8 NC VS
S
DQM 1 NC NC C LK C KE A9 A8 A7 A6 A5 A4 A3 DQM 3 VS
S
NC DQ3 1 VD DQ DQ3 0 DQ2 9 V S SQ DQ2 8 DQ2 7 VD DQ DQ2 6 DQ2 5 V S SQ DQ2 4 VS S 86Pi n T SO P( II) ( 4 0 0 m il x 8 7 5 m i l) ( 0 . 5 m m P in p i t c h )
90 Ball FBGA
1 A B C D E F G H J K L M N P R 2 3 4 5 6 7 8 9
DQ26 DQ24 VSS DQ28 VDDQ VSSQ VSSQ DQ27 DQ25 VSSQ DQ29 DQ30 VDDQ DQ31 VSS DQM3 A4 A7 CLK DQM1 A5 A8 CKE NC NC A3 A6 NC A9 NC VSS
VDD DQ23 DQ21 VDDQ VSSQ DQ19 DQ22 DQ20 VDDQ DQ17 DQ18 VDDQ NC A2 A10 NC BA0 CAS VDD DQ6 DQ1 DQ16 VSSQ DQM2 VDD A0 BA1 CS
WE
A1 A11 RAS DQM0
VDDQ DQ8
DQ7 VSSQ DQ5 VDDQ DQ3 VDDQ
VSSQ DQ10 DQ9 VSSQ DQ12 DQ14 DQ11 VDDQ VSSQ DQ13 DQ15 VSS
VDDQ VSSQ DQ4 VDD DQ0 DQ2
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ESMT
BLOCK DIAGRAM
CLK CKE Address
Mode Register Clock Generator Bank D Bank C Bank B Row Address Buffer & Refresh Counter Row Decoder
M12L128324A
Bank A
Sense Amplifier Command Decoder Control Logic
CS RAS CAS WE
Data Control Circuit
Input & Output Buffer
Latch Circuit
Column Address Buffer & Refresh Counter
DQM0~3
Column Decoder
DQ
PIN DESCRIPTION
PIN CLK CS CKE A0 ~ A11 BA0 , BA1 RAS NAME System Clock Chip Select Clock Enable Address Bank Select Address Row Address Strobe INPUT FUNCTION Active on the positive going edge to sample all inputs Disables or enables device operation by masking or enabling all inputs except CLK, CKE and DQM0-3. Masks system clock to freeze operation from the next clock cycle. CKE should be enabled at least one cycle prior new command. Disable input buffers for power down in standby. Row / column address are multiplexed on the same pins. Row address : RA0~RA11, column address : CA0~CA7 Selects bank to be activated during row address latch time. Selects bank for read / write during column address latch time. Latches row addresses on the positive going edge of the CLK with RAS low. Enables row access & precharge. Latches column address on the positive going edge of the CLK with CAS low. Enables column access. Enables write operation and row precharge. Latches data in starting from CAS , WE active. Makes data output Hi-Z, tSHZ after the clock and masks the output. Blocks data input when DQM active. Data inputs / outputs are multiplexed on the same pins. Power and ground for the input buffers and the core logic. Isolated power supply and ground for the output buffers to provide improved noise immunity. This pin is recommended to be left No Connection on the device.
CAS
WE
Column Address Strobe Write Enable Data Input / Output Mask Data Input / Output Power Supply / Ground Data Output Power / Ground No Connection
DQM0~3 DQ0 ~ DQ31 VDD / VSS VDDQ / VSSQ N.C
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ABSOLUTE MAXIMUM RATINGS
Parameter Voltage on any pin relative to VSS Voltage on VDD supply relative to VSS Storage temperature Power dissipation Short circuit current Note: Symbol VIN, VOUT VDD, VDDQ TSTG PD IOS Value -1.0 ~ 4.6 -1.0 ~ 4.6 -55 ~ +150 1 50
M12L128324A
Unit V V
C
W mA
Permanent device damage may occur if ABSOLUTE MAXIMUM RATING are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC OPERATING CONDITION
Recommended operating conditions (Voltage referenced to VSS = 0V, TA = 0 to 70 C ) Parameter Supply voltage Input logic high voltage Input logic low voltage Output logic high voltage Output logic low voltage Input leakage current Output leakage current Note: Symbol VDD, VDDQ VIH VIL VOH VOL IIL IOL Min 3.0 2.0 -0.3 2.4 -5 -5 Typ 3.3 3.0 0 Max 3.6 VDD+0.3 0.8 0.4 5 5 Unit V V V V V 1 2 IOH = -2mA IOL = 2mA 3 4 Note
A A
1. VIH(max) = 4.6V AC for pulse width 10ns acceptable. 2. VIL(min) = -1.5V AC for pulse width 10ns acceptable. 3. Any input 0V VIN VDD , all other pins are not under test = 0V. 4. Dout is disabled, 0V VOUT VDD.
CAPACITANCE (VDD = 3.3V, TA = 25 C , f = 1MHz)
Parameter Input capacitance (A0 ~ A11, BA0 ~ BA1) Input capacitance (CLK, CKE, CS , RAS , CAS , WE & DQM) Data input/output capacitance (DQ0 ~ DQ31) Symbol CIN1 CIN2 COUT Min 2 2 2 Max 4 4 5 Unit pF pF pF
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DC CHARACTERISTICS
Recommended operating condition unless otherwise notedTA = 0 to 70 C Test Condition Burst Length = 1 ICC1 ICC2P ICC2PS ICC2N ICC2NS Active Standby Current in power-down mode ICC3P ICC3PS ICC3N ICC3NS tRC tRC(min) IOL = 0 mA CKE VIL(max), tCC = 10ns CKE & CLK VIL(max), tCC = CKE VIH(min), CS VIH(min), tCC = 10ns Input signals are changed one time during 20ns CKE VIH(min), CLK VIL(max), tCC = input signals are stable CKE VIL(max), tCC = 10ns CKE & CLK VIL(max), tCC = CKE VIH(min), CS VIH(min), tCC=15ns Input signals are changed one time during 2clks All other pins VDD-0.2V or 0.2V CKE VIH(min), CLK VIL(max), tCC = input signals are stable IOL = 0 mA Page Burst 2 Banks activated tCC = tCC(min) tRFC tRFC(min) CKE 0.2V
M12L128324A
Version -6 120 2 1 25 mA 9 7 6 30 15 mA mA mA -7 100 Unit Note
Parameter Operating Current (One Bank Active) Precharge Standby Current in power-down mode
Symbol
mA
1,2
mA
Precharge Standby Current in non power-down mode
Active Standby Current in non power-down mode (One Bank Active)
Operating Current (Burst Mode) Refresh Current Self Refresh Current Note:
ICC4
270
240
mA mA mA
1,2
ICC5 ICC6
270 2
240
1. Measured with outputs open. 2. Input signals are changed one time during 2 CLKS.
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AC OPERATING TEST CONDITIONS (VDD = 3.3V 0.3V TA = 0 to 70 C )
Parameter Input levels (Vih/Vil) Input timing measurement reference level Input rise and fall-time Output timing measurement reference level Output load condition Value 2.4/0.4 1.4 tr/tf = 1/1 1.4 See Fig. 2
M12L128324A
Unit V V ns V
3.3V 1200 Output 870 30pF
Vtt = 1.4V
VOH (DC) =2.4V , IOH = -2 mA VOL (DC) =0.4V , IOL = 2 mA Output Z0 =50
50
30pF
(Fig. 1) DC Output Load Circuit
(Fig. 2) AC Output Load Circuit
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted) Version Parameter Row active to row active delay RAS to CAS delay Row precharge time Row active time @ Operating @ Auto Refresh Symbol tRRD (min) tRCD (min) tRP (min) tRAS (min) tRAS (max) tRC (min) tRFC (min) tCDL (min) tRDL (min) tBDL (min) 60 60 1 2 1 -6 12 18 18 42 100 63 63 -7 14 18 20 42 Unit ns ns ns ns us ns CLK CLK CLK 1 1, 5 2 2 2 Note 1 1 1 1
Row cycle time
Last data in to col. address delay Last data in to row precharge Last data in to burst stop
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Version Parameter Col. address to col. address delay Number of valid Output data Symbol -6 tCCD(min) 1 2 1 0 ea -7 CLK Unit
M12L128324A
Note 3
CAS latency = 3 CAS latency = 2 CAS latency = 1
4
Note: 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer. 2. Minimum delay is required to complete write. 3. All parts allow every cycle column address change. 4. In case of row precharge interrupt, auto precharge and read burst stop. 5. A new command may be given tRFC after self refresh exit.
AC CHARACTERISTICS (AC operating condition unless otherwise noted)
-6 Parameter CAS latency = 3 CLK cycle time CAS latency = 2 CAS latency = 1 CLK to valid output delay CAS latency = 3 CAS latency = 2 CAS latency = 1 CAS latency = 3 CAS latency = 2 CAS latency = 1 tCH tCL tSS tSH tSLZ tOH tSAC tCC Symbol Min 6 10 20 2 2 2 2 2 2 1 1 tSHZ 5.5 6 17 5.5 6 17 1000 Max Min 7 8.6 20 2 2 2 2.5 2.5 2 1 1 6 6 18 6 6 18 ns ns ns ns ns ns 3 3 3 3 2 ns 2 ns 1,2 1000 ns 1 Max -7 Unit Note
Output data hold time CLK high pulse width CLK low pulse width Input setup time Input hold time
CLK to output in Low-Z CLK to output in Hi-Z Note: CAS latency = 3 CAS latency = 2 CAS latency = 1
1. Parameters depend on programmed CAS latency. 2. If clock rising time is longer than 1ns. (tr/2 - 0.5) ns should be considered. 3. Assumed input rise and fall time (tr & tf) =1ns. If tr & tf is longer than 1ns transient time compensation should be considered. i.e., [(tr + tf)/2 - 1] ns should be added to the parameter.
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SIMPLIFIED TRUTH TABLE
COMMAND Register Mode Register set Auto Refresh Refresh Self Refresh Entry Exit CKEn-1 H H CKEn X H L H X X CS RAS CAS L L L H L L L L H X L H L L H X H L
WE
M12L128324A
DQM BA0,1 A10/AP X X X X X X V V OP CODE X
A11, A9~A0
Note 1,2 3 3 3 3
L H H X H H
L H H
X Row Address L H L H X V X L H X Column Address (A0~A7) Column Address (A0~A7)
Bank Active & Row Addr. Read & Column Address Write & Column Address Auto Precharge Disable Auto Precharge Enable Auto Precharge Disable Auto Precharge Enable
4 4,5 4 4,5 6
H H H
X X X L H L H
L L L H L X H L H L H L
H H L X V X X H X V X X H
L H H X V X X H X V X H
L L L X V X X H X V X H
X X X X X X
V
Burst Stop Precharge Clock Suspend or Active Power Down Bank Selection All Banks Entry Exit Entry Precharge Power Down Mode Exit DQM No Operating Command
H L H L H H
X
X X V X X X 7
X
(V = Valid, X = Don't Care. H = Logic High, L = Logic Low) Note: 1.OP Code: Operating Code A0~A11 & BA0~BA1: Program keys. (@ MRS) 2.MRS can be issued only at all banks precharge state. A new command can be issued after 2 CLK cycles of MRS. 3.Auto refresh functions are as same as CBR refresh of DRAM. The automatical precharge without row precharge of command is meant by "Auto". Auto/self refresh can be issued only at all banks idle state. 4.BA0~BA1: Bank select addresses. If both BA1 and BA0 are "Low" at read, write, row active and precharge, bank A is selected. If both BA1 is "Low" and BA0 is "High" at read, write, row active and precharge, bank B is selected. If both BA1 is "High" and BA0 is "Low" at read, write, row active and precharge, bank C is selected. If both BA1 and BA0 are "High" at read, write, row active and precharge, bank D is selected If A10/AP is "High" at row precharge, BA1 and BA0 is ignored and all banks are selected. 5.During burst read or write with auto precharge, new read/write command can not be issued. Another bank read/write command can be issued after the end of burst. New row active of the associated bank can be issued at tRP after the end of burst. 6.Burst stop command is valid at every burst length. 7.DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (write DQM latency is 0), but makes Hi-Z state the data-out of 2 CLK cycles after.(Read DQM latency is 2)
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MODE REGISTER FIELD TABLE TO PROGRAM MODES
Register Programmed with MRS Address Function A11 RFU BA0~BA1 RFU A10/AP RFU A9 W.B.L A8 TM A7 A6 A5
M12L128324A
A4
A3 BT
A2
A1
A0
CAS Latency
Burst Length
Test Mode A8 0 0 1 1 A7 0 1 0 1 Type Mode Register Set Reserved Reserved Reserved A6 0 0 0 0 1 1 1 1
CAS Latency A5 0 0 1 1 0 0 1 1 A4 0 1 0 1 0 1 0 1 Latency Reserved 1 2 3 Reserved Reserved Reserved Reserved
Burst Type A3 0 1 Type Sequential Interleave A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1
Burst Length A0 0 1 0 1 0 1 0 1 BT = 0 1 2 4 8 BT = 1 1 2 4 8
Write Burst Length A9 0 1 Length Burst Single Bit
Reserved Reserved Reserved Reserved Reserved Reserved Full Page Reserved
Full Page Length: 256
Note:
1. RFU (Reserved for future use) should stay "0" during MRS cycle. 2. If A9 is high during MRS cycle, "Burst Read single Bit Write" function will be enabled. 3. The full column burst (256 bit) is available only at sequential mode of burst type.
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BURST SEQUENCE (BURST LENGTH = 4)
Initial Address A1 0 0 1 1 A0 0 1 0 1 0 1 2 3 1 2 3 0 2 3 0 1 3 0 1 2 0 1 2 3 1 0 3 2 Sequential
M12L128324A
Interleave 2 3 0 1 3 2 1 0
BURST SEQUENCE (BURST LENGTH = 8)
Initial Address A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 0 1 2 3 4 5 6 7 1 2 3 4 5 6 7 0 2 3 4 5 6 7 0 1 3 4 5 6 7 0 1 2 4 5 6 7 0 1 2 3 5 6 7 0 1 2 3 4 6 7 0 1 2 3 4 5 7 0 1 2 3 4 5 6 0 1 2 3 4 5 6 7 1 0 3 2 5 4 7 6 2 3 0 1 6 7 4 5 3 2 1 0 7 6 5 4 4 5 6 7 0 1 2 3 5 4 7 6 1 0 3 2 6 7 4 5 2 3 0 1 7 6 5 4 3 2 1 0 Sequential Interleave
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DEVICE OPERATIONS
CLOCK (CLK) The clock input is used as the reference for all SDRAM operations. All operations are synchronized to the positive going edge of the clock. The clock transitions must be monotonic between VIL and VIH. During operation with CKE high all inputs are assumed to be in valid state (low or high) for the duration of setup and hold time around positive edge of the clock for proper functionality and ICC specifications. CLOCK ENABLE(CKE) The clock enable (CKE) gates the clock onto SDRAM. If CKE goes low synchronously with clock (set-up and hold time same as other inputs), the internal clock suspended from the next clock cycle and the state of output and burst address is frozen as long as the CKE remains low. All other inputs are ignored from the next clock cycle after CKE goes low. When all banks are in the idle state and CKE goes low synchronously with clock, the SDRAM enters the power down mode from the next clock cycle. The SDRAM remains in the power down mode ignoring the other inputs as long as CKE remains low. The power down exit is synchronous as the internal clock is suspended. When CKE goes high at least "1CLK + tSS" before the high going edge of the clock, then the SDRAM becomes active from the same clock edge accepting all the input commands. POWER-UP
M12L128324A
1.Apply power and start clock, Attempt to maintain CKE = "H", DQM = "H" and the other pins are NOP condition at the inputs. 2.Maintain stable power, stable clock and NOP input condition for minimum of 200us. 3.Issue precharge commands for all banks of the devices. 4.Issue 2 or more auto-refresh commands. 5.Issue a mode register set command to initialize the mode register. cf.) Sequence of 4 & 5 is regardless of the order. The device is now ready for normal operation.
MODE REGISTER SET (MRS) The mode register stores the data for controlling the various operating modes of SDRAM. It programs the CAS latency, burst type, burst length, test mode and various vendor specific options to make SDRAM useful for variety of different applications. The default value of the mode register is not defined, therefore the mode register must be written after power up to operate the SDRAM. The mode register is written by asserting low on CS , RAS , CAS and WE (The SDRAM should be in active mode with CKE already high prior to writing the mode register). The state of address pins A0~A11 and BA0~BA1 in the same cycle as CS , RAS , CAS and WE going low is the data written in the mode register. Two clock cycles is required to complete the write in the mode register. The mode register contents can be changed using the same command and clock cycle requirements during operation as long as all banks are in the idle state. The mode register is divided into various fields into depending on functionality. The burst length field uses A0~A2, burst type uses A3, CAS latency (read latency from column address) use A4~A6, vendor specific options or test mode use A7~A8, A10/AP~A11 and BA0~BA1. The write burst length is programmed using A9. A7~A9, A10/AP~A11 and BA0~BA1 must be set to low for normal SDRAM operation. Refer to the table for specific codes for various burst length, burst type and CAS latencies.
BANK ADDRESSES (BA0~BA1) This SDRAM is organized as four independent banks of 1,048,576 words x 32 bits memory arrays. The BA0~BA1 inputs are latched at the time of assertion of RAS and CAS to select the bank to be used for the operation. The banks addressed BA0~BA1 are latched at bank active, read, write, mode register set and precharge operations.
ADDRESS INPUTS (A0~ A11) The 20 address bits are required to decode the 1,048,576 word locations are multiplexed into 12 address input pins (A0~A11). The 12 row addresses are latched along with RAS and BA0~BA1 during bank active command. The 8 bit column addresses are latched along with CAS , WE and BA0~BA1 during read or with command.
BANK ACTIVATE The bank activate command is used to select a random row in an idle bank. By asserting low on RAS and CS with desired row and bank address, a row access is initiated. The read or write operation can occur after a time delay of tRCD (min) from the time of bank activation. tRCD is the internal timing parameter of SDRAM, therefore it is dependent on operating clock frequency. The minimum number of clock cycles required between bank activate and read or write command should be calculated by dividing tRCD (min) with cycle time of the clock and then rounding of the result to the next higher integer.
NOP and DEVICE DESELECT When RAS , CAS and WE are high , The SDRAM performs no operation (NOP). NOP does not initiate any new operation, but is needed to complete operations which require more than single clock cycle like bank activate, burst read, auto refresh, etc. The device deselect is also a NOP and is entered by asserting CS high. CS high disables the command decoder so that RAS , CAS , WE and all the address inputs are ignored.
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DEVICE OPERATIONS (Continued)
The SDRAM has four internal banks in the same chip and shares part of the internal circuitry to reduce chip area, therefore it restricts the activation of four banks simultaneously. Also the noise generated during sensing of each bank of SDRAM is high requiring some time for power supplies to recover before another bank can be sensed reliably. tRRD (min) specifies the minimum time required between activating different bank. The number of clock cycles required between different bank activation must be calculated similar to tRCD (min) specification. The minimum time required for the bank to be active to initiate sensing and restoring the complete row of dynamic cells is determined by tRAS (min). Every SDRAM bank activate command must satisfy tRAS (min) specification before a precharge command to that active bank can be asserted. The maximum time any bank can be in the active state is determined by tRAS (max) and tRAS (max) can be calculated similar to tRCD specification. DQM OPERATION
M12L128324A
The DQM is used mask input and output operations. It works similar to OE during operation and inhibits writing during write operation. The read latency is two cycles from DQM and zero cycle for write, which means DQM masking occurs two cycles later in read cycle and occurs in the same cycle during write cycle. DQM operation is synchronous with the clock. The DQM signal is important during burst interrupts of write with read or precharge in the SDRAM. Due to asynchronous nature of the internal write, the DQM operation is critical to avoid unwanted or incomplete writes when the complete burst write is required. Please refer to DQM timing diagram also.
PRECHARGE The precharge is performed on an active bank by asserting low on clock cycles required between bank activate and clock cycles required between bank activate and CS , RAS , WE and A10/AP with valid BA0~BA1 of the bank to be procharged. The precharge command can be asserted anytime after tRAS (min) is satisfy from the bank active command in the desired bank. tRP is defined as the minimum number of clock cycles required to complete row precharge is calculated by dividing tRP with clock cycle time and rounding up to the next higher integer. Care should be taken to make sure that burst write is completed or DQM is used to inhibit writing before precharge command is asserted. The maximum time any bank can be active is specified by tRAS (max). Therefore, each bank activate command. At the end of precharge, the bank enters the idle state and is ready to be activated again. Entry to power-down, Auto refresh, Self refresh and Mode register set etc. is possible only when all banks are in idle state.
BURST READ The burst read command is used to access burst of data on consecutive clock cycles from an active row in an active bank. The burst read command is issued by asserting low on CS and RAS with WE being high on the positive edge of the clock. The bank must be active for at least tRCD (min) before the burst read command is issued. The first output appears in CAS latency number of clock cycles after the issue of burst read command. The burst length, burst sequence and latency from the burst read command is determined by the mode register which is already programmed. The burst read can be initiated on any column address of the active row. The address wraps around if the initial address does not start from a boundary such that number of outputs from each I/O are equal to the burst length programmed in the mode register. The output goes into high-impedance at the end of burst, unless a new burst read was initiated to keep the data output gapless. The burst read can be terminated by issuing another burst read or burst write in the same bank or the other active bank or a precharge command to the same bank. The burst stop command is valid at every page burst length.
AUTO PRECHARGE The precharge operation can also be performed by using auto precharge. The SDRAM internally generates the timing to satisfy tRAS (min) and "tRP" for the programmed burst length and CAS latency. The auto precharge command is issued at the same time as burst write by asserting high on A10/AP, the bank is precharge command is asserted. Once auto precharge command is given, no new commands are possible to that particular bank until the bank achieves idle state.
BURST WRITE The burst write command is similar to burst read command and is used to write data into the SDRAM on consecutive clock cycles in adjacent addresses depending on burst length and burst sequence. By asserting low on CS , CAS and WE with valid column address, a write burst is initiated. The data inputs are provided for the initial address in the same clock cycle as the burst write command. The input buffer is deselected at the end of the burst length, even though the internal writing can be completed yet. The writing can be complete by issuing a burst read and DQM for blocking data inputs or burst write in the same or another active bank. The burst stop command is valid at every burst length. The write burst can also be terminated by using DQM for blocking data and procreating the bank tRDL after the last data input to be written into the active row. See DQM OPERATION also.
ALL BANKS PRECHARGE Four banks can be precharged at the same time by using Precharge all command. Asserting low on CS , RAS , and WE with high on A10/AP after all banks have satisfied tRAS (min) requirement, performs precharge on all banks. At the end of tRP after performing precharge all, all banks are in idle state.
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DEVICE OPERATIONS (Continued)
AUTO REFRESH The storage cells of SDRAM need to be refreshed every 64ms to maintain data. An auto refresh cycle accomplishes refresh of a single row of storage cells. The internal counter increments automatically on every auto refresh cycle to refresh all the rows. An auto refresh command is issued by asserting low on CS , RAS and CAS with high on CKE and WE . The auto refresh command can only be asserted with all banks being in idle state and the device is not in power down mode (CKE is high in the previous cycle). The time required to complete the auto refresh operation is specified by tRFC (min). The minimum number of clock cycles required can be calculated by driving tRFC with clock cycle time and them rounding up to the next higher integer. The auto refresh command must be followed by NOP's until the auto refresh operation is completed. The auto refresh is the preferred refresh mode when the SDRAM is being used for normal data transactions. The auto refresh cycle can be performed once in 15.6us or the burst of 4096 auto refresh cycles in 64ms. SELF REFRESH
M12L128324A
The self refresh is another refresh mode available in the SDRAM. The self refresh is the preferred refresh mode for data retention and low power operation of SDRAM. In self refresh mode, the SDRAM disables the internal clock and all the input buffers except CKE. The refresh addressing and timing is internally generated to reduce power consumption. The self refresh mode is entered from all banks idle state by asserting low on CS , RAS , CAS and CKE with high on WE . Once the self refresh mode is entered, only CKE state being low matters, all the other inputs including clock are ignored to remain in the refresh. The self refresh is exited by restarting the external clock and then asserting high on CKE. This must be followed by NOP's for a minimum time of tRFC before the SDRAM reaches idle state to begin normal operation. 4K cycles of burst auto refresh is required immediately before self refresh entry and immediately after self refresh exit.
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COMMANDS Mode register set command
( CS , RAS , CAS , WE = Low) The M12L128324A has a mode register that defines how the device operates. In this command, A0 through A11 and BA0~BA1 are the data input pins. After power on, the mode register set command must be executed to initialize the device. The mode register can be set only when all banks are in idle state. During 2CLK following this command, the M12L128324A cannot accept any other commands.
M12L128324A
CLK CKE CS RAS CAS WE BA0, BA1
(Bank select)
H
A10 Add Fig. 1 Mode register set command
Activate command
( CS , RAS = Low, CAS , WE = High) The M12L128324A has four banks, each with 4,096 rows. This command activates the bank selected by BA1 and BA0 and a row address selected by A0 through A11. This command corresponds to a conventional DRAM's RAS falling.
CLK CKE CS RAS CAS WE BA0, BA1
(Bank select)
H
A10 Add
Row Row
Fig. 2 Row address stroble and bank active command
Precharge command
( CS , RAS , WE = Low, CAS = High ) This command begins precharge operation of the bank selected by BA1 and BA0. When A10 is High, all banks are precharged, regardless of BA1 and BA0. When A10 is Low, only the bank selected by BA1 and BA0 is precharged. After this command, the M12L128324A can't accept the activate command to the precharging bank during tRP (precharge to activate command period). This command corresponds to a conventional DRAM's RAS rising.
CLK CKE CS RAS CAS WE
(Bank select) (Precharge select)
H
BA0, BA1 A10
Add Fig. 3 Precharge command
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Write command
( CS , CAS , WE = Low, RAS = High) If the mode register is in the burst write mode, this command sets the burst start address given by the column address to begin the burst write operation. The first write data in burst can be input with this command with subsequent data on following clocks.
M12L128324A
CLK CKE CS RAS CAS WE BA0, BA1 H
(Bank select)
A10 Add Col.
Fig. 4 Column address and write command
Read command
( CS , CAS = Low, RAS , WE = High) Read data is available after CAS latency requirements have been met. This command sets the burst start address given by the column address.
CLK CKE CS RAS CAS WE BA0, BA1
(Bank select)
H
A10 Add Col.
Fig. 5 Column address and read command
CLK
CBR (auto) refresh command
CKE
H
( CS , RAS , CAS = Low, WE , CKE = High) This command is a request to begin the CBR refresh operation. The refresh address is generated internally. Before executing CBR refresh, all banks must be precharged. After this cycle, all banks will be in the idle (precharged) state and ready for a row activate command. During tRFC period (from refresh command to refresh or activate command), the M12L128324A cannot accept any other command.
CS RAS CAS WE BA0, BA1
(Bank select)
A10 Add Fig. 6 Auto refresh command
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Self refresh entry command
( CS , RAS , CAS , CKE = Low , WE = High) After the command execution, self refresh operation continues while CKE remains low. When CKE goes to high, the M12L128324A exits the self refresh mode. During self refresh mode, refresh interval and refresh operation are performed internally, so there is no need for external control. Before executing self refresh, all banks must be precharged.
M12L128324A
CLK CKE CS RAS CAS WE BA0, BA1
(Bank select)
A10 Add Fig. 7 Self refresh entry command
Burst stop command
( CS , WE = Low, RAS , CAS = High) This command terminates the current burst operation. Burst stop is valid at every burst length.
CLK CKE CS RAS CAS WE
(Bank select)
H
BA0, BA1
A10 Add Fig. 8 Burst stop command
CLK
No operation
( CS = Low , RAS , CAS , WE = High) This command is not a execution command. No operations begin or terminate by this command.
CKE CS RAS CAS WE
(Bank select)
H
BA0, BA1 A10 Add
Fig. 9 No operation
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BASIC FEATURE AND FUNCTION DESCRIPTIONS 1. CLOCK Suspend
1) Cl oc k Su spe nd ed Du r in g W rite ( BL=4)
M12L128324A
2) Clock Suspended During Read (BL=4)
CLK CMD CKE Internal CLK DQ( CL 2) DQ( CL3) D0 D0 D1 D1 D2 D2 D3 Q0 Q1 Q2 Q3 Q3 WR RD
Mask ed by C K E
D3
Q0
Q1
Q2
Not W r itten
Su s pen ded Dou t
2. DQM Operation
1)W rite Mask (BL=4) 2) Read Mas k (B L=4)
CLK CMD WR
RD
DQM
Ma s k e d b y D Q M Ma s k e d b y D Q M Hi-Z
DQ(CL2) DQ(CL3)
D0
D1 D1
D3 D3
Q0
Q2 Q1
Q3 Q3
D0
Hi-Z
Q2
DQ M t o D at a- i n M a sk = 0
DQ M t o D at a- ou t Ma sk = 2
*Note2 3)DQM with clcok su sp end ed (F ull Page Read )
CLK CMD CKE Inter nal CLK DQM Q0
Hi- Z
RD
DQ(CL2) DQ(CL3)
Q2 Q1
Hi-Z
Q4 Q3
Hi-Z
Q6 Q5
Q7 Q6
Q8 Q7
Hi-Z
Hi-Z
Hi-Z
*Note:
1. CKE to CLK disable/enable = 1CLK. 2. DQM masks data out Hi-Z after 2CLKs which should masked by CKE "L". 3. DQM masks both data-in and data-out.
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3. CAS Interrupt (I)
*Note1 1)Read int er ru pt ed by Read ( BL=4)
M12L128324A
CLK CMD ADD RD A RD B QB0 QA0
CCD *Not e 2
DQ( CL2) DQ(CL3)
QA0
QB1 QB0
QB2 QB1
QB3 QB2 QB3
t
2) W r it e in t err u p t ed b y W r it e (B L= 2)
3) Wr ite in terr u pt ed by Read ( BL= 2)
CLK CMD
WR
WR
*Note 2
WR
RD
*Note 2
tCCD
ADD DQ A DA0
tCCD
A
B DB0 DB1 DQ( CL2) DQ( CL3)
B
DA0 DA0
CDL *Not e 3
DQ0
DQ1 DQ0 DQ1
CDL *Note 3
t
t
*Note:
1. By "interrupt" is meant to stop burst read/write by external before the end of burst. By " CAS interrupt ", to stop burst read/write by CAS access ; read and write. 2. tCCD: CAS to CAS delay. (=1CLK) 3. tCDL: Last data in to new column address delay. (=1CLK)
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4. CAS Interrupt (II): Read Interrupted by Write & DQM
( a) CL =2 , B L= 4 CLK i)CMD DQM RD WR
M12L128324A
DQ ii)CMD DQM RD
D0
D1 WR
D2
D3
DQ iii)CMD DQM RD
Hi-Z
D0
D1 WR
D2
D3
DQ iv)CMD DQM
Hi-Z
D0
D1 WR
D2
D3
RD
DQ
Q0
HH - - Z i iZ
*Note1
D0
D1
D2
D3
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(b) CL =3 ,B L= 4 CLK i)CMD DQM DQ RD WR
M12L128324A
D0
D1 WR
D2
D3
ii)CMD DQM DQ
RD
D0
D1 WR
D2
D3
iii)CMD DQM
RD
DQ iv)CMD DQM DQ v)CM D DQM DQ RD
D0
D1
D2
D3
RD
WR
Hi-Z
D0
D1 WR
D2
D3
Q0
Hi-Z
*Note1
D0
D1
D2
D3
*Note: 1. To prevent bus contention, there should be at least one gap between data in and data out.
5. Write Interrupted by Precharge & DQM
1)Normal W rit e (B L=4)
CLK CMD DQM DQ WR
*Note3
PRE
*Note2
D0
D1
D2
D3
Ma s k e d b y D Q M
tRDL(min)
*Note:
1. To prevent bus contention, DQM should be issued which makes at least one gap between data in and data out. 2. To inhibit invalid write, DQM should be issued. 3. This precharge command and burst write command should be of the same bank, otherwise it is not precharge interrupt but only another bank precharge of four banks operation.
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6. Precharge
1) Nor mal W rit e (B L=4) 2) Normal Read (B L= 4)
M12L128324A
CLK WR DQ D0 D1 D2 D3 PRE
CLK CMD RD Q0 Q1 PRE CL= 2 Q2 Q3
1*Note2
DQ(CL2)
tRDL
*Note1
CMD DQ( CL 3)
PRE CL= 3
2*Note2
Q0
Q1
Q2
Q3
.
7. Auto Precharge
1)Normal W rit e (BL=4) 2) No rm al Read (B L= 4 )
CLK
CLK WR D0 D1 D2 D3 CMD RD Q0 Q1 Q0 Q2 Q1 Q3 Q2 Q3
CMD DQ
DQ(CL2) DQ( CL 3)
*Note3
tRDL
Au t o Pr ech ar ge st ar t s
*Note3
Auto Pr ech arge st art s
*Note:
1. tRDL: Last data in to row precharge delay. 2. Number of valid output data after row precharge: 1, 2 for CAS Latency = 2, 3 respectively. 3. The row active command of the precharge bank can be issued after tRP from this point. The new read/write command of other activated bank can be issued from this point. At burst read/write with auto precharge, CAS interrupt of the same/another bank is illegal.
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8. Burst Stop & Interrupted by Precharge
1)W rite Burst Stop (BL=8)
M12L128324A
1)W rite interrupted by precharge (BL=4)
CLK CMD WR STOP
CLK CMD WR PRE
* No te1
tRDL
DQM DQ D3
DQM DQ D2 Mask
D0
D1
D2
D4
D5
D0
D1
tBDL
*Note2
2)Read Burst Stop (BL=4)
2)Read in terru pted by precharge (BL=4)
CLK CMD RD STOP
*Note3
CLK CMD RD PRE
*Note3
DQ(CL2) DQ(CL3)
Q0
Q1
DQ(CL2) Q1
Q0
Q1 Q0 Q1
Q0
DQ(CL3)
9. MRS
1) Mo d e Re g is t e r S e t
CLK
*Note4
CMD
PRE
MRS
ACT
tRP
2CLK
*Note: 1. tRDL: 2 CLK; Last data in to Row Precharge. 2. tBDL: 1 CLK; Last data in to burst stop delay. 3. Number of valid output data after burst stop: 1, 2 for CAS latency = 2, 3 respectiviely. 4. PRE: All banks precharge, if necessary. MRS can be issued only at all banks precharge state.
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10. Clock Suspend Exit & Power Down Exit
1) Cl o ck S u sp en d (= Ac t ive P ow er Do wn ) Exi t
M12L128324A
2)P ower Down (= Pr ec ha rg e Power Down )
CLK CKE
CLK CKE Internal CLK RD CMD
tSS
Inter nal CLK CMD
*Note1
tSS
*Note2
NOP AC T
11. Auto Refresh & Self Refresh
1)Auto Refresh & Self Refresh *Note3
CLK
*Note4
CMD
*Note5
PRE
AR
CMD
CKE
tRP
2)Self Refresh *Note6
tRFC
CLK
*Note4
CMD
PRE
SR
CMD
CKE
tRP
tRFC
*Note:
1. Active power down: one or more banks active state. 2. Precharge power down: all banks precharge state. 3. The auto refresh is the same as CBR refresh of conventional DRAM. No precharge commands are required after auto refresh command. During tRFC from auto refresh command, any other command can not be accepted. 4. Before executing auto/self refresh command, all banks must be idle state. 5. MRS, Bank Active, Auto/Self Refresh, Power Down Mode Entry. 6. During self refresh entry, refresh interval and refresh operation are performed internally. After self refresh entry, self refresh mode is kept while CKE is low. During self refresh entry, all inputs expect CKE will be don't cared, and outputs will be in Hi-Z state. For the time interval of tRFC from self refresh exit command, any other command can not be accepted. 4K cycles of burst auto refresh is required immediately before self refresh entry and immediately after self refresh exit.
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12. About Burst Type Control
Sequential Counting Basic MODE Interleave Counting
M12L128324A
At MRS A3 = "0". See the BURST SEQUENCE TABLE. (BL = 4,8) BL = 1, 2, 4, 8 and full page. At MRS A3 = "1". See the BURST SEQUENCE TABLE. (BL = 4,8) BL = 4, 8 At BL =1, 2 interleave Counting = Sequential Counting Every cycle Read/Write Command with random column address can realize Random Column Access. That is similar to Extended Data Out (EDO) Operation of conventional DRAM.
Random Random Column Access tCCD = 1 CLK MODE
13. About Burst Length Control
1 Basic MODE 2 4 8 Full Page Random MODE Burst Stop RAS Interrupt (Interrupted by Precharge) At MRS A210 = "000" At auto precharge. tRAS should not be violated. At MRS A210 = "001" At auto precharge. tRAS should not be violated. At MRS A210 = "010" At MRS A210 = "011" At MRS A210 = "111" At the end of the burst length, burst is warp-around. tBDL = 1, Valid DQ after burst stop is 1, 2 for CAS latency 2, 3 respectively. Using burst stop command, any burst length control is possible. Before the end of burst. Row precharge command of the same bank stops read /write burst with auto precharge. tRDL = 1 with DQM , Valid DQ after burst stop is 1, 2 for CAS latency 2, 3 respectively. During read/write burst with auto precharge, RAS interrupt can not be issued. Before the end of burst, new read/write stops read/write burst and starts new read/write burst. During read/write burst with auto precharge, CAS interrupt can not be issued.
Interrupt MODE
CAS Interrupt
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FUNCTION TRUTH TABLE (TABLE 1)
Current State
CS RAS CAS
M12L128324A
WE
BA
ADDR
ACTION
Note
IDLE
Row Active
Read
Write
Read with Auto Precharge
Write with Auto Precharge
H L L L L L L L H L L L L L L L H L L L L L L L H L L L L L L L H L L L L L H L L L L L
X H H H L L L L X H H H H L L L X H H H H L L L X H H H H L L L X H H H L L X H H H L L
X H H L H H L L X H H L L H H L X H H L L H H L X H H L L H H L X H H L H L X H H L H L
X H L X H L H L X H L H L H L X X H L H L H L X X H L H L H L X X H L X X X X H L X X X
X X X BA BA BA X OP code X X X BA BA BA BA X X X X BA BA BA BA X X X X BA BA BA BA X X X X BA BA X X X X BA BA X
X X X CA, A10/AP RA A10/AP X OP code X X X CA, A10/AP CA, A10/AP RA A10/AP X X X X CA, A10/AP CA, A10/AP RA A10/AP X X X X CA, A10/AP CA, A10/AP RA A10/AP X X X X CA, A10/AP RA, RA10 X X X X CA, A10/AP RA, RA10 X
NOP NOP ILLEGAL ILLEGAL Row (&Bank) Active ; Latch RA NOP Auto Refresh or Self Refresh Mode Register Access NOP NOP ILLEGAL Begin Read ; latch CA ; determine AP Begin Write ; latch CA ; determine AP ILLEGAL Precharge ILLEGAL NOP (Continue Burst to End Row Active) NOP (Continue Burst to End Row Active) Term burst Row active Term burst, New Read, Determine AP Term burst, New Write, Determine AP ILLEGAL Term burst, Precharge timing for Reads ILLEGAL NOP (Continue Burst to End Row Active) NOP (Continue Burst to End Row Active) Term burst Row active Term burst, New Read, Determine AP Term burst, New Write, Determine AP ILLEGAL Term burst, Precharge timing for Writes ILLEGAL NOP (Continue Burst to End Precharge) NOP (Continue Burst to End Precharge) ILLEGAL ILLEGAL ILLEGAL ILLEGAL NOP (Continue Burst to End Precharge) NOP (Continue Burst to End Precharge) ILLEGAL ILLEGAL ILLEGAL ILLEGAL
2 2 4 5 5 2 2
3 2
3 3 2 3
2
2
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Current State
CS RAS CAS
M12L128324A
WE BA ADDR ACTION Note
Precharging
Row Activating
Refreshing
Mode Register Accessing
H L L L L L L H L L L L L L H L L L L H L L L L
X H H H L L L X H H H L L L X H H L L X H H H L
X H H L H H L X H H L H H L X H L H L X H H L X
X H L X H L X X H L X H L X X X X X X X H L X X
X X X BA BA BA X X X X BA BA BA X X X X X X X X X X X
X X X CA RA A10/AP X X X X CA RA A10/AP X X X X X X X X X X X
NOP Idle after tRP NOP Idle after tRP ILLEGAL ILLEGAL ILLEGAL NOP Idle after tRDL ILLEGAL NOP Row Active after tRCD NOP Row Active after tRCD ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL NOP Idle after tRFC NOP Idle after tRFC ILLEGAL ILLEGAL ILLEGAL NOP Idle after 2clocks NOP Idle after 2clocks ILLEGAL ILLEGAL ILLEGAL BA = Bank Address CA = Column Address
2 2 2 4
2 2 2 2
Abbreviations: *Note:
RA = Row Address NOP = No Operation Command
AP = Auto Precharge
1. All entries assume the CKE was active (High) during the precharge clock and the current clock cycle. 2. Illegal to bank in specified state; Function may be legal in the bank indicated by BA, depending on the state of the bank. 3. Must satisfy bus contention, bus turn around, and/or write recovery requirements. 4. NOP to bank precharge or in idle state. May precharge bank indicated by BA (and A10/AP). 5. Illegal if any bank is not idle.
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FUNCTION TRUTH TABLE (TABLE2)
Current State CKE ( n-1 ) H L L L L L L H L L L L L L H H H H H H H H L H H L L CKE n X H H H H H L X H H H H H L H L L L L L L L L H L H L
CS RAS CAS
M12L128324A
WE
X X H L X X X X X H L X X X X X H L X H H L X X X X X
ADDR
X X X X X X X X X X X X X X X X X X X RA X OP Code X X X X X
ACTION
INVALID Exit Self Refresh Idle after tRFC (ABI) Exit Self Refresh Idle after tRFC (ABI) ILLEGAL ILLEGAL ILLEGAL NOP (Maintain Self Refresh) INVALID Exit Self Refresh ABI Exit Self Refresh ABI ILLEGAL ILLEGAL ILLEGAL NOP (Maintain Low Power Mode) Refer to Table1 Enter Power Down Enter Power Down ILLEGAL ILLEGAL Row (& Bank) Active Enter Self Refresh Mode Register Access NOP Refer to Operations in Table 1 Begin Clock Suspend next cycle Exit Clock Suspend next cycle Maintain Clock Suspend
Note
6 6
Self Refresh
All Banks Precharge Power Down
All Banks Idle
Any State other than Listed above
X H L L L L X X H L L L L X X H L L L L L L X X X X X
X X H H H L X X X H H H L X X X H H H L L L X X X X X
X X H H L X X X X H H L X X X X H H L H L L X X X X X
7 7
8 8
8
9 9
Abbreviations: ABI = All Banks Idle, RA = Row Address *Note: 6.CKE low to high transition is asynchronous. 7.CKE low to high transition is asynchronous if restart internal clock. A minimum setup time 1CLK + tSS must be satisfy before any command other than exit. 8.Power down and self refresh can be entered only from the all banks idle state. 9.Must be a legal command.
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tCH
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14
M12L128324A
Single Bit Read-Write-Read Cycle (Same Page) @ CAS Latency = 3, Burst Length = 1
15
16
17
18
19
CLOCK tCL tCC CKE
HIGH
tRAS tRC
*Note1
tSH
CS tSH RAS tSS CAS tSH ADDR Ra tSS BA 0, BA1 tSS Ca Cb Cc Rb tSH tCCD tRCD tSS tRP
*Note2
*Note2, 3
*Note2, 3
*Note2, 3
*Note4
*Note2
BS
BS
BS
BS
BS
BS
A10 /AP
Ra
*Note3
*Note3
*Note3
*Note4
Rb
tSAC DQ tSLZ Qa tOH Db
tSH Qc tSS tSH
WE tSS tSS DQM tSH
Row Active
Read
W rite
Read Precharge
Row Act ive
:D on' t Care
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Note:
M12L128324A
1. All input expect CKE & DQM can be don't care when CS is high at the CLK high going edge. 2. Bank active @ read/write are controlled by BA0~BA1.
BA1
0 0 1 1
BA0
0 1 0 1
Active & Read/Write
Bank A Bank B Bank C Bank D
3. Enable and disable auto precharge function are controlled by A10/AP in read/write command
A10/AP
BA1
0
BA0
0 1 0 1 0 1 0 1
Operating
Disable auto precharge, leave A bank active at end of burst. Disable auto precharge, leave B bank active at end of burst. Disable auto precharge, leave C bank active at end of burst. Disable auto precharge, leave D bank active at end of burst. Enable auto precharge, precharge bank A at end of burst. Enable auto precharge, precharge bank B at end of burst. Enable auto precharge, precharge bank C at end of burst. Enable auto precharge, precharge bank D at end of burst.
0
0 1 1 0
1
0 1 1
4. A10/AP and BA0~BA1 control bank precharge when precharge is asserted.
A10/AP
0 0 0 0 1
BA1
0 0 1 1 X
BA0
0 1 0 1 X
Precharge
Bank A Bank B Bank C Bank D All Banks
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Power Up Sequence
0
CLOCK
M12L128324A
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CKE
High level is necessary
CS
tRP
RAS
tRFC
tRFC
CAS
ADDR
Key
RAa
BA1
BA0
A10/AP
RAa
DQ
High-Z
WE
DQM
High level is necessary
Precharge (All Banks)
Auto Refresh
Auto Refresh
Mode Register Set Row Active (A-Bank)
: Don't care
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Read & Write Cycle at Same Bank @ Burst Length = 4
M12L128324A
*Note:
1. Minimum row cycle times is required to complete internal DRAM operation. 2. Row precharge can interrupt burst on any cycle. [CAS Latency-1] number of valid output data is available after Row precharge. Last valid output will be Hi-Z (tSHZ) after the clock. 3. Output will be Hi-Z after the end of burst. (1, 2, 4, 8 & Full page bit burst)
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Page Read & Write Cycle at Same Bank @ Burst Length = 4
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14
M12L128324A
15
16
17
18
19
CLOCK
HIGH CKE
CS
tRCD
RAS
*Note2
CAS
ADDR
Ra
Ca
Cb
Cc
Cd
BA1
BA0
A10 /A P
Ra
tRDL
CL = 2 DQ CL = 3 Qa0 Qa1 Qb0 Q b1 Dc0 Dc1 Dd0 Dd1 Qa0 Q a1 Q b0 Q b1 Q b2 Dc0 Dc1 Dd0 Dd1
tCDL
WE
*Note1
*Note3
DQM
Row Active ( A - Bank )
Read ( A - Bank )
Read ( A - Bank )
Write ( A - Bank )
Write ( A - Bank )
Precharge (A - B an k )
:D on' t Care
Note: 1. To Write data before burst read ends. DQM should be asserted three cycle prior to write command to avoid bus contention. 2. Row precharge will interrupt writing. Last data input, tRDL before row precharge, will be written. 3. DQM should mask invalid input data on precharge command cycle when asserting precharge before end of burst. Input data after Row precharge cycle will be masked internally.
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Page Read Cycle at Different Bank @ Burst Length = 4
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14
M12L128324A
15
16
17
18
19
CLOCK
CKE
HIGH
*Note1
CS
RAS
*Note2
CAS
ADDR
RAa
RBb
CAa
RCc
CBb
RDd
CCc
CDd
BA1
BA0
A10 /AP
RAa
RBb
RCc
RDd
CL= 2 DQ CL= 3
QAa0
Q A a 1 Q A a 2 Q B b 0 Q B b 1 Q B b 2 Q C c 0 Q C c 1 Q C c 2 QD d 0 QD d 1 Q D d 2
Q A a 0 Q A a 1 Q A a 2 Q B b 0 Q B b 1 Q B b 2 Q C c 0 Q C c 1 Q C c 2 QD d 0 Q D d 1 QD d 2
WE
DQM
Row Act ive ( A-B ank )
Read (A -Bank )
Read (B -Bank )
Read ( C- Bank ) Row Act ive ( D- Bank )
Read ( D- Bank ) Pre charg e (C -B an k)
Pre charg e (D -B an k)
Row Active ( B-B ank )
Row Act ive (C -B an k)
Pre charg e (A- Ban k)
Pre charg e (B- Ban k)
:Don't Care
Note: 1. CS can be don't cared when RAS , CAS and WE are high at the clock high going edge. 2. To interrupt a burst read by row precharge, both the read and the precharge banks must be the same.
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Page Write Cycle at Different Bank @ Burst Length = 4
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
M12L128324A
16
17
18
19
CLOCK
CKE
HIGH
CS
RAS
*Note2
CAS
ADDR
RAa
RBb
CAa
CBb
RCc
RDd
CCc
CDd
BA1
BA0
A10 /AP
RAa
RBb
RCc
RDd
DQ
DAa0 DAa1 DAa2 DAa3 DBb0 DBb1 DBb2 DBb3 D C c 0 D C c 1 DD d0 DD d1 CD d2
tCDL
WE
tRDL
*Note1
DQM
Row Act ive ( A - Bank )
Write (A -Bank )
Write (B -Bank )
Row Act ive ( D- Bank )
Wri te (D -B an k)
Pr echarg e (A ll Bank s)
Row Active ( B-B ank )
Row Act ive ( C- Bank )
Write (C -B an k)
: Don't care
*Note:
1. To interrupt burst write by Row precharge, DQM should be asserted to mask invalid input data. 2. To interrupt burst write by Row precharge, both the write and the precharge banks must be the same.
Elite Semiconductor Memory Technology Inc.
Publication Date: Aug. 2009 Revision: 1.4 34/46
ESMT
Read & Write Cycle at Different Bank @ Burst Length = 4
0 CLOCK 1 2 3 4 5 6 7 8 9 10 11 12 13 14
M12L128324A
15
16
17
18
19
CKE
HIGH
CS
RAS
CAS
ADDR
RAa
CAa
RDb
CDb
RBc
CBc
BA1
BA0
A10 /AP
RAa
RBb
RAc
tRCD
CL = 2 DQ CL = 3
*Note2
tCDL
QAa0 QAa1 QAa2 QAa3 DD b0 Ddb1 DD b2 DD d3
*Note1
QBc0 QBc1 QBc2
QAa0 QAa1 QAa2 QAa3
DD b0 Ddb1 DD b2 DD d3
QBc0 QBc1
WE
DQM
Row Active (A-Bank)
Read (A-Bank)
Precharge (A-Bank) Row Active (D-Bank)
W rite (D-Bank) Row Active (B-Bank)
Read (B- Ban k )
:D on' t Ca re
*Note:
1. tCDL should be met to complete write. 2. tRCD should be met.
Elite Semiconductor Memory Technology Inc.
Publication Date: Aug. 2009 Revision: 1.4 35/46
ESMT
Read & Write cycle with Auto Precharge @ Burst Length = 4
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14
M12L128324A
15
16
17
18
19
CLOCK
CKE
HIGH
CS
RAS
CAS
ADDR
Ra
Rb
Ca
Cb
BA0
BA1
A10 /AP
Ra
Rb
CL =2 DQ CL =3
QAa0 QAa1 QAa2 QAa3
DD b0 Ddb1 DD b2 DD d3
QAa0 QAa1 QAa2 QAa3
DD b0 Ddb1 DD b2 DD d3
WE
DQM
Row Active ( A - Bank )
Read with Auto Precharge ( A - Bank ) Row Active ( D - Bank )
Auto Pr echar ge Star t Poin t
W rite with Auto Pr echar ge ( D- B an k )
Auto Pr echar ge Star t Poin t (D- Ban k )
:D on' t Ca re
*Note:
1. tCDL should be controlled to meet minimum tRAS before internal precharge start. (In the case of Burst Length = 1 & 2)
Elite Semiconductor Memory Technology Inc.
Publication Date: Aug. 2009 Revision: 1.4 36/46
ESMT
0 CLOCK 1 2 3 4 5 6 7 8 9 10 11 12 13 14
M12L128324A
Clock Suspension & DQM Operation Cycle @ CAS Latency = 2, Burst Length = 4
15 16 17 18 19
CKE
CS
RAS
CAS
ADDR
Ra
Ca
Cb
Cc
BA1
BA0
A10 /A P
Ra
tRCD
DQ
*Note2
Q a0
Qa1
Qa2
Q a3
Q b0
Q b1
Dc0
Dc2
tSHZ
WE
tSHZ
*Note1
DQM
Row Active
Read
Clock Su pen s i on
Read Read DQM W rite
W rite DQM
W rite DQM
Clock Suspension
:Don't Care
*Note:
1. DQM is needed to prevent bus contention. 2. tRCD should be met.
Elite Semiconductor Memory Technology Inc.
Publication Date: Aug. 2009 Revision: 1.4 37/46
ESMT
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14
M12L128324A
Read interrupted by Precharge Command & Read Burst Stop Cycle @ Burst Length = Full page
15 16 17 18 19
CLOCK
HIGH CKE
CS
RAS
CAS
ADDR
RAa
CAa
CAb
BA1
BA0
*Note1 *Note 1
A10 /AP
RAa
*Note2
1
1 QAb0 QAb1 QAb2 QAb3 QAb4 QAb5 2
CL=2 DQ CL= 3
QAa0 QAa1 QAa2 QAa3 QAa4
2 QAb0 QAb1 QAb2 QAb3 QAb4 QAb5
QAa0 QAa1 QAa2 QAa3 QAa4
WE
DQM
Row Active ( A- B an k )
Read (A- Ban k)
Burst Stop
Read (A- Ban k)
Precharge ( A- Ban k )
:Don't Care
*Note:
1. About the valid DQs after burst stop, it is same as the case of RAS interrupt. Both cases are illustrated above timing diagram. See the lable 1, 2 on them. But at burst write, Burst stop and RAS interrupt should be compared carefully. Refer the timing diagram of "Full page write burst stop cycles". 2. Burst stop is valid at every burst length.
Elite Semiconductor Memory Technology Inc.
Publication Date: Aug. 2009 Revision: 1.4 38/46
ESMT
0 CLOCK 1 2 3 4 5 6 7 8 9 10 11 12 13 14
M12L128324A
Write interrupted by Precharge Command & Write Burst Stop Cycle @ Burst Length = Full page
15
16
17
18
19
CKE
HIGH
CS
RAS
CAS
ADDR
RAa
CAa
CAb
BA1
BA0
A10 /AP
RAa
tBDL
DQ DAa0 DAa1 DAa2 DAa3 DAa4
tRDL
*Note1
DAb0 DAb1 DAb2 DAb3 DAb4 DAb5
WE
DQM
Row Active ( A- B an k )
W rite (A- Ban k)
Burst Stop
W rite (A- Ban k )
Precharge ( A- B an k )
:Don't Care
*Note:
1. Data-in at the cycle of interrupted by precharge can not be written into the corresponding memory cell. It is defined by AC parameter of tRDL. DQM at write interrupted by precharge command is needed to prevent invalid write. DQM should mask invalid input data on precharge command cycle when asserting precharge before end of burst. Input data after Row precharge cycle will be masked internally. 2. Burst stop is valid at every burst length.
Elite Semiconductor Memory Technology Inc.
Publication Date: Aug. 2009 Revision: 1.4 39/46
ESMT
0 CLOCK
*Note2
M12L128324A
Active/Precharge Power Down Mode @ CAS Latency = 2, Burst Length = 4
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
tSS
*Note1
tSS
*Note3
tSS
CKE
CS
RAS
CAS
ADDR
Ra
Ca
BA1
BA0
A10 /AP
Ra
tSHZ
DQ Q a0 Qa1 Qa2
WE
DQM
Pr ech ar ge Pow er - D own Entry
Row Active Pr ech arge Power - Down Exi t Active Power - dow n Entry
Read
Precharge
Active Power - down Exi t
: Don't care
*Note:
1. All banks should be in idle state prior to entering precharge power down mode. 2. CKE should be set high at least 1CLK + tSS prior to Row active command.
Elite Semiconductor Memory Technology Inc.
Publication Date: Aug. 2009 Revision: 1.4 40/46
ESMT
Self Refresh Entry & Exit Cycle
0 CLOCK
*Note2 *Note1 *Note4
M12L128324A
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
1
t R F C min
*Note6
CKE
*Note3
tSS
CS
*Note5
RAS
*Note7
CAS
ADDR
BA0,BA1
A10/AP
DQ
Hi-Z
Hi-Z
WE
DQM
Self Refresh Entry
Self Refresh Exit
Auto Refresh
: Don't care
*Note:
TO ENTER SELF REFRESH MODE
1. CS , RAS & CAS with CKE should be low at the same clock cycle. 2. After 1 clock cycle, all the inputs including the system clock can be don't care except for CKE. 3. The device remains in self refresh mode as long as CKE stays "Low". cf.) Once the device enters self refresh mode, minimum tRAS is required before exit from self refresh.
TO EXIT SELF REFRESH MODE 4. System clock restart and be stable before returning CKE high.
5. CS starts from high. 6. Minimum tRFC is required after CKE going high to complete self refresh exit. 7. 4K cycles of burst auto refresh is required immediately before self refresh entry and immediately after self refresh exit.
Elite Semiconductor Memory Technology Inc.
Publication Date: Aug. 2009 Revision: 1.4 41/46
ESMT
Mode Register Set Cycle Auto Refresh Cycle
0 CLOCK 1 2 3 4 5 6 0 1 2 3 4 5
M12L128324A
6
7
8
9
10
CKE
HIGH
HIG H
CS
*Note2
tRFC
RAS
*Note1
CAS
*Note3
ADDR
Key
Ra
DQ
HI-Z
HI-Z
WE
DQM
MRS
New Command
Auto Refresh
New Command
:Don't Care
All banks precharge should be completed before Mode Register Set cycle and auto refresh cycle.
MODE REGISTER SET CYCLE
*Note: 1. CS , RAS , CAS , & WE activation at the same clock cycle with address key will set internal mode register. 2. Minimum 2 clock cycles should be met before new RAS activation. 3. Please refer to Mode Register Set table.
Elite Semiconductor Memory Technology Inc.
Publication Date: Aug. 2009 Revision: 1.4 42/46
ESMT
PACKING 86 - LEAD DIMENSIONS TSOP(II) DRAM(400mil)
M12L128324A
Symbol
Min A A1 A2 b b1 c c1 D ZD E E1 L L1 e R1 R2
1
Dimension in mm Norm
0.10 1.00 0.20 0.127 22.22 BSC 0.61 REF 11.76 BSC 10.16 BSC 0.50 0.80 REF 0.50 BSC
0.05 0.95 0.17 0.17 0.12 0.10
Max 1.20 0.15 1.05 0.27 0.23 0.21 0.16
Min 0.002 0.037 0.007 0.007 0.005 0.004
Dimension in inch Norm
0.004 0.039 0.008 0.005 0.875 BSC 0.024 REF 0.463 BSC 0.400 BSC 0.020 0.031 REF 0.020 BSC
Max 0.047 0.006 0.011 0.018 0.009 0.008 0.006
0.40
0.60
0.016
0.024
0.12 0.12
0 0 10 10 15 15
0.25
8 20 20
0.005 0.005
0 0 10 10 15 15
0.010
8 20 20
2
3
Elite Semiconductor Memory Technology Inc.
Publication Date: Aug. 2009 Revision: 1.4 43/46
ESMT
PACKING 90-BALL DIMENSIONS SDRAM ( 8x13 mm )
M12L128324A
Dimension in mm Min Norm Max A 1.40 A1 0.30 0.40 A2 0.84 0.89 0.94 ob 0.40 0.50 D 7.90 8.00 8.10 E 12.90 13.00 13.10 D1 6.40 E1 11.20 e 0.80 Controlling dimension : Millimeter. Elite Semiconductor Memory Technology Inc.
Symbol
Dimension in inch Min Norm Max 0.055 0.012 0.016 0.033 0.035 0.037 0.016 0.020 0.311 0.315 0.319 0.508 0.512 0.516 0.252 0.441 0.031
Publication Date: Aug. 2009 Revision: 1.4 44/46
ESMT
Revision History
Revision
0.1 0.2 1.0 1.1 1.2 1.3
M12L128324A
Date
2005.05.13 2005.08.08 2005.12.22 2006.02.14 2006.03.13 2007.03.02 Original
Description
Delete Non-Pb-free of ordering information 1. Delete "Preliminary" from datasheet 2. Add 90BGA Packing Dimension Modify ICC4, ICC5 spec Modify ICC2N, ICC3N spec Delete BGA ball name of packing dimensions 1.Move Revision History to the last 2.Modify the test condition of IIL and ICC3N 3.Correct the timing for Auto Refresh 4.Delete power up sequence and frequency vs. AC parameter relationship table 5.Correct the description of bank address, address inputs and MRS of device operations 6.Modify the description about self refresh operation
1.4
2009.08.14
Elite Semiconductor Memory Technology Inc.
Publication Date: Aug. 2009 Revision: 1.4 45/46
ESMT
Important Notice All rights reserved.
M12L128324A
No part of this document may be reproduced or duplicated in any form or by any means without the prior permission of ESMT. The contents contained in this document are believed to be accurate at the time of publication. ESMT assumes no responsibility for any error in this document, and reserves the right to change the products or specification in this document without notice. The information contained herein is presented only as a guide or examples for the application of our products. No responsibility is assumed by ESMT for any infringement of patents, copyrights, or other intellectual property rights of third parties which may result from its use. No license, either express , implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of ESMT or others. Any semiconductor devices may have inherently a certain rate of failure. To minimize risks associated with customer's application, adequate design and operating safeguards against injury, damage, or loss from such failure, should be provided by the customer when making application designs. ESMT's products are not authorized for use in critical applications such as, but not limited to, life support devices or system, where failure or abnormal operation may directly affect human lives or cause physical injury or property damage. If products described here are to be used for such kinds of application, purchaser must do its own quality assurance testing appropriate to such applications.
Elite Semiconductor Memory Technology Inc.
Publication Date: Aug. 2009 Revision: 1.4 46/46

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