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Techwell, Inc.
TW9910 - Low Power NTSC/PAL/SECAM Video Decoder with VBI Slicer Data Sheet
Techwell Confidential. Information may change without notice.
Disclaimer
This document provides technical information for the user. Techwell, Inc. reserves the right to modify the information in this document as necessary. The customer should make sure that they have the most recent data sheet version. Techwell, Inc. holds no responsibility for any errors that may appear in this document. Customers should take appropriate action to ensure their use of the products does not infringe upon any patents. Techwell, Inc. respects valid patent rights of third parties and does not infringe upon or assist others to infringe upon such rights.
TECHWELL, INC.
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REV. A 09/21/2006
TW9910
Techwell, Inc. ...............................................................................1 Disclaimer.................................................................................1 Features........................................................................................3 Functional Description...............................................................4 Introduction...............................................................................4 Introduction...............................................................................5 Analog Front End.....................................................................5 Sync Processor........................................................................5 Y/C separation .........................................................................5 Color demodulation..................................................................6 Automatic Chroma Gain Control..........................................6 Color Killer ............................................................................6 Automatic standard detection ..............................................6 Component Processing ...........................................................7 Sharpness.............................................................................7 Color Transient Improvement ..............................................7 Power Management ................................................................7 Host Interface...........................................................................7 Down-scaling and Cropping ....................................................8 Cropping ...............................................................................8 Output Interface .....................................................................10 ITU-R BT.656 .....................................................................10 Horizontal Down Scaling Output........................................10 Vertical Down Scaling Output ............................................11 VBI Data Processing..............................................................12 Raw VBI data output ..........................................................12 VBI Data Slicer ...................................................................12 Sliced VBI Data output format............................................13 Two Wire Serial Bus Interface...............................................20 Test Modes ............................................................................22 Filter Curves...........................................................................23 Anti-alias filter .....................................................................23 Decimation filter..................................................................23 Chroma Band Pass Filter Curves......................................24 Luma Notch Filter Curve for NTSC and PAL/SECAM......24 Chrominance Low-Pass Filter Curve.................................25 Horizontal Scaler Pre- Filter curves ...................................25 Peaking Filter Curves.........................................................25 Peaking Filter Curves.........................................................26 Control Register ........................................................................27 TW9910 Register SUMMARY...........................................27 0x00 - Product ID Code Register (ID)..............................30 0x01 - Chip Status Register I (STATUS1)........................30 0x02 - Input Format (INFORM).........................................31 0x03 - Output Format Control Register (OPFORM) ........32 0x04 - Color Killer Hysteresis and HSYNC Delay Control32 0x05 - Output Control I ......................................................33 0x06 - Analog Control Register (ACNTL) .........................34 0x07 - Cropping Register, High (CROP_HI) ....................34 0x08 - Vertical Delay Register, Low (VDELAY_LO) ........35 0x09 - Vertical Active Register, Low (VACTIVE_LO).......35 0x0A - Horizontal Delay Register, Low (HDELAY_LO) ...35 0x0B - Horizontal Active Register, Low (HACTIVE_LO)..35 0x0C - Control Register I (CNTRL1).................................36 0x0D - Vertical Scaling Register, Low (VSCALE_LO) .....36 0x0E - Scaling Register, High (SCALE_HI)......................36 0x0F - Horizontal Scaling Register, Low (HSCALE_LO).37 0x10 - BRIGHTNESS Control Register (BRIGHT) ..........37 0x11 - CONTRAST Control Register (CONTRAST)........37 0x12 - SHARPNESS Control Register I (SHARPNESS) 37 0x13 - Chroma (U) Gain Register (SAT_U) .....................38 0x14 - Chroma (V) Gain Register (SAT_V)......................38 0x15 - Hue Control Register (HUE) ..................................38 0x16 - Reserved ................................................................38 0x17 - Coring .....................................................................39 0x18 - Coring and IF compensation (CORING) ...............39 0x19 - VBI Control Register (VBICNTL) ...........................40 0x1A - Analog Control II ....................................................41 0x1B - Output Control II ....................................................41 0x1C - Standard Selection (SDT) .....................................42 0x1D - Standard Recognition (SDTR)..............................43 0x1E - Reserved................................................................43 0x1F - Test Control Register (TEST)................................44 0x20 - Clamping Gain (CLMPG) ......................................45 0x21 - Individual AGC Gain (IAGC)..................................45 0x22 - AGC Gain (AGCGAIN) ..........................................45 0x23 - White Peak Threshold (PEAKWT)........................45 0x24- Clamp level (CLMPL)..............................................45 0x25- Sync Amplitude (SYNCT).......................................46 0x26 - Sync Miss Count Register (MISSCNT).................46 0x27 - Clamp Position Register (PCLAMP) .....................46 0x28 - Vertical Control I (VCNTL1)...................................47 0x29 - Vertical Control II (VCNTL2)..................................47 0x2A - Color Killer Level Control (CKILL).........................47 0x2B - Comb Filter Control (COMB).................................48 0x2C - Luma Delay and H Filter Control (LDLY)..............48 0x2D - Miscellaneous Control I (MISC1)..........................49 0x2E - LOOP Control Register (LOOP) ...........................49 0x2F - Miscellaneous Control II (MISC2) .........................50 0x30 - Macrovision Detection (MVSN) .............................51 0x31 - Chip STATUS II (STATUS2) ................................51 0x32 - H monitor (HFREF)................................................52 0x33 - CLAMP MODE (CLMD) ........................................52 0x34 - ID Detection Control (IDCNTL)..............................52 0x35 - Clamp Control I (CLCNTL1) ..................................53 0x4F - WSS3 .....................................................................54 0x50 - FILLDATA ..............................................................54 0x51 - SDID.......................................................................54 0x52 - DID..........................................................................54 0x53 - WSS1 .....................................................................55 0x54 - WSS2 .....................................................................55 0x55 - VVBI .......................................................................55 0x56~6A LCTL6~LCTL26 .................................................56 0x6B - HSGEGIN ..............................................................56 0x6C - HSEND ..................................................................56 0x6D - OVSDLY................................................................56 0x6E - OVSEND................................................................57 0x6F - VBIDELAY .............................................................57 Pin Diagram ...............................................................................58 44 PIN LQFP......................................................................58 Pin Diagram ...............................................................................59 48 PIN QFNPin Description...............................................59 Pin Description ...................................................................60 Power and Ground Pins.....................................................61 Parametric Information ............................................................62 AC/DC Electrical Parameters................................................62 Clock Timing Diagram........................................................64 Mechanical Data ................................................................64 Mechanical Data ................................................................65 44 Pin LQFP.......................................................................65 48 PIN QFN........................................................................67 Application Schematics .........................................................69 PCB Layout Considerations ..............................................70 Copyright Notice.......................................................................71 Disclaimer ..................................................................................71 Life Support Policy ...................................................................71
TECHWELL, INC.
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TW9910
Low Power NTSC/PAL/SECAM Video Decoder with VBI Slicer
TW9910 - Low Power NTSC/PAL/SECAM Video Decoder with VBI Slicer
Features
Video decoder - NTSC (M, 4.43) and PAL (B, D, G, H, I, M, N, N combination), PAL (60), SECAM support with automatic format detection - Software selectable analog inputs allows any of the following combinations, e.g. 4 CVBS or ( 3 CVBS and 1 Y/C ). Video scaler - High quality horizontal filtered scaling with arbitrary scale down ratio - Phase accuracy better than 1/32 pixel - Programmable output cropping Miscellaneous - Two wire MPU serial bus interface - Support Real Time Control interface - Power save and Power down mode - Typical power consumption <100mW - Single 27MHz crystal for all standards - Supports 24.54MHz and 29.5MHz crystal for high resolution square pixel format decoding - 3.3V tolerant I/O - 1.8V/3.3 V power supply - 44pin LQFP, 48pin QFN package
- Built-in analog anti-alias filter - Two 10-bit ADCs and analog clamping circuit. - Fully programmable static gain or automatic gain
control for the Y channel - Programmable white peak control for the Y channel - 4-H adaptive comb filter Y/C separation - PAL delay line for color phase error correction - Image enhancement with peaking and CTI. - Digital sub-carrier PLL for accurate color decoding - Digital Horizontal PLL for processing and pixel sampling synchronization
- Advanced synchronization processing and sync detection for handling non-standard and weak signal - Programmable hue, brightness, contrast, and sharpness. - Automatic color control and color killer - Chroma IF compensation saturation,
- Detection of level of copy protection according to
Macrovision standard
- ITU-R 601 or ITU-R 656 compatible YCbCr(4:2:2)
output format - VBI slicer supporting industrial standard data services - VBI data pass through, raw ADC data output
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TW9910
Low Power NTSC/PAL/SECAM Video Decoder with VBI Slicer
Functional Description
Figure 1: TW9910 Block Diagram
VBI Slicer
VD (15:8)
Analog Video In
Chroma Demodulation
CIN 0
10-bit ADC
U
4H Adaptive Comb Filter
MUX0 MUX1 MUX2 MUX3
10-bit ADC
MUX
AGC
V
Scaling / Video Interface
VD(7:0)
Luma/Chroma processor
HS VS CLKx2 MPOUT
Y
27 Mhz
Line-lock clock Generator
Clock
PDN RSTB
SCLK SDAT
2 Wire Serial Bus
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Sync Processor
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TW9910 Introduction
Low Power NTSC/PAL/SECAM Video Decoder with VBI Slicer
The TW9910 is a low power NTSC/PAL/SECAM video decoder chip that is designed for portable applications. It consumes less than 100mW in typical composite input application. The available power down mode further reduces the power consumption. It uses the 1.8V for both analog and digital supply voltage and 3.3V for I/O power. A single 27MHz crystal is all that needed to decode all analog video standards. The video decoder decodes the base-band analog CVBS or S-video signals into digital 8 or 16-bit 4:2:2 YCbCr for output. It consists of analog front-end with input source selection, variable gain amplifier and analog-to-digital converters, Y/C separation circuit, multi-standard color decoder (PAL BGHI, PAL M, PAL N, combination PAL N, NTSC M, NTSC 4.43 and SECAM) and synchronization circuitry. The Y/C separation is done with high quality adaptive 4H comb filter for reduced cross color and cross luminance. The advanced synchronization processing circuitry can produce stable pictures for nonstandard signal as well as weak signal. A video scaler is provided to arbitrarily scale down the output video in a packed format. The output of the decoder is line-locked and formatted to the ITU-R 656 output with embedded sync. The TW9910 also includes circuits to detect and process vertical blanking interval (VBI) signal. It slices and process VBI data for output through video bus. Some information can also be alternatively retrieved through host interface. It also detects copy-protected signal according to Macrovision standard including AGC and colorstripe pulses. A 2-wire serial host interface is used to simplify system integration. All the functions can be controlled through this interface.
Analog Front End
The analog front-end prepares and digitizes the AC coupled analog signal for further processing. Both channels have built-in anti-aliase filter and 10-bit over-sampling ADCs. The characteristic of the filter is available in the filter curve section. The Y channel has additional 4-input multiplexer, and a variable gain amplifier for automatic gain control (AGC). It can support a maximum input voltage range of 1.4V without attenuation. The C channel has only one input with built-in clamping circuit that restores the DC level. Software selectable analog inputs allow two possible input combinations: 1. Four selectable composite video inputs. 2. Three selectable composites and one S-video input.
Sync Processor
The sync processor of TW9910 detects horizontal synchronization and vertical synchronization signals in the composite video or in the Y signal of an S-video or component signal. The processor contains a digital phase-locked-loop and decision logic to achieve reliable sync detection in stable signal as well as in unstable signals such as those from VCR fast forward or backward. It allows the sampling of the video signal in line-locked fashion.
Y/C separation
For NTSC and PAL standard signals, the luma/chroma separation can be done either by adaptive comb filtering or notch/band-pass filter combination. For SECAM standard signals, only notch/bandpass filter is available. The default selection for NTSC/PAL is comb filter. The characteristics of the band-pass filter are shown in the filter curve section.
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TW9910
Low Power NTSC/PAL/SECAM Video Decoder with VBI Slicer
TW9910 employs high quality 4-H adaptive comb filter to reduce artifacts like hanging dots and crawling dots. Due to the line buffer used in the comb filter, there is always two lines processing delay in the output images no matter what standard or filter option is chosen.
Color demodulation
The color demodulation of NTSC and PAL signal is done by first quadrature down mixing and then lowpass filtering. The low-pass filter characteristic can be selected for optimized transient color performance. For the PAL system, the PAL ID or the burst phase switching is identified to aid the PAL color demodulation. The SECAM decoding process consists of FM demodulator and de-emphasis filtering. During the FM demodulation, the chroma carrier frequency is identified and used to control the SECAM color demodulation. The sub-carrier signal for use in the color demodulator is generated by direct digital synthesis PLL that locks onto the input sub-carrier reference (color burst). This arrangement allows any sub-standard of NTSC and PAL to be demodulated easily with single crystal frequency. Automatic Chroma Gain Control The Automatic Chroma Gain Control (ACC) compensates for reduced amplitudes caused by highfrequency loss in video signal. The range of ACC control is -6db to +26db. Color Killer For low color amplitude signals, black and white video, or very noisy signals, the color will be "killed". The color killer uses the burst amplitude measurement as well as sub-carrier PLL status to switch-off the color. Automatic standard detection The TW9910 has build-in automatic standard discrimination circuitry. The circuit uses burst-phase, burst-frequency and frame rate to identify NTSC, PAL or SECAM color signals. The standards that can be identified are NTSC (M), NTSC (4.43), PAL (B, D, G, H, I), PAL (M), PAL (N), PAL (60) and SECAM (M). Each standard can be included or excluded in the standard recognition process by software control. The identified standard is indicated by the Standard Selection (SDT) register. Automatic standard detection can be overridden by software controlled standard selection. TW9910 supports all common video formats as shown in Table 1. The video decoder needs to be programmed appropriately for each of the composite video input formats.
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TW9910
Low Power NTSC/PAL/SECAM Video Decoder with VBI Slicer
Table 1. Video Input Formats Supported by the TW9910
Format NTSC-M NTSC-Japan (1) PAL-B, G, N PAL-D PAL-H PAL-I PAL-M PAL-CN SECAM PAL-60 NTSC (4.43) Lines 525 525 625 625 625 625 525 625 625 525 525 Fields 60 60 50 50 50 50 60 50 50 60 60 Fsc 3.579545 MHz 3.579545 MHz 4.433619 MHz 4.433619 MHz 4.433619 MHz 4.433619 MHz 3.575612 MHz 3.582056 MHz 4.406MHz 4.250MHz 4.433619 MHz 4.433619 MHz Country U.S., many others Japan Many China Belgium Great Britain, others Brazil Argentina France, Eastern Europe, Middle East, Russia China Transcoding
Notes: (1). NTSC-Japan has 0 IRE setup.
Component Processing
The TW9910 supports the brightness, contrast, color saturation and Hue adjustment for changing the video characteristic. The Cb and Cr gain can be adjusted independently for flexibility. Sharpness The TW9910 also provides a sharpness control function through control registers. It provides the control up to +9db. The center frequency of the enhancement curve is selectable. A coring function is provided to prevent noise enhancement. Color Transient Improvement A programmable Color Transient Improvement circuit is provided to enhance the color bandwidth. Low level noise enhancement can be suppressed by a programmable coring logic. Overshoot and undershoot are also removed by special circuit to prevent false color generation at the color edge.
Power Management
The TW9910 can be put into power-down mode through both software and hardware control. The Y and C path can be separately powered down.
Host Interface
The TW9910 registers are accessed via 2-WIRE SERIAL MPU interface. It operates as a slave device. Serial clock and data lines, SCLK and SDAT, transfer data from the bus master at a rate of 400 Kbits/s. The TW9910 has one serial interface address select pin(VD[0]/SIAD0) to program up to two unique serial addresses TW9910. This allows as many as two TW9910 to share the same serial bus. Reset signals are also available to reset the control registers to their default values.
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TW9910 Down-scaling and Cropping
Low Power NTSC/PAL/SECAM Video Decoder with VBI Slicer
The TW9910 provides two methods to reduce the amount of output video pixel data, downscaling and cropping. The downscaling provides full video image at lower resolution. Cropping provides only a portion of the video image output. All these mechanisms can be controlled independently to yield maximum flexibility in the output stream. The TW9910 can independently reduce the output video image size in both horizontal and vertical directions using arbitrary scaling ratios up to 1/16 in each direction. The horizontal scaling employs a dynamic 6-tap 32-phase interpolation filter for luma and a 2-tap 8-phase interpolation filter for chroma. The vertical scaling uses the simple line dropping method. It is recommended to choose integer vertical scaling ratio for best result. The horizontal scaling factor can be calculated according to following equation: HSCALE = [HACTIVE / Npixel_desired] * 256 Where: Npixel_desired is the number of output pixels per line and HACTIVE is the programmed number of captured pixels per line. The vertical scaling factor is determined as VSCALE = [VACTIVE / Nline_desired] * 256 Where: Nline_desired is the number of active lines output per field and VACTIVE is the programmed number of captured lines per field. Cropping Cropping allows only subsection of a video image to be output. The VACTIVE signal can be programmed to indicate the number of active lines to be displayed in a video field, and the HACTIVE signal can be programmed to indicate the number of active pixels to be displayed in a video line. The start of the field or frame in the vertical direction is indicated by the leading edge of VSYNC. The start of the line in the horizontal direction is indicated by the leading edge of the HSYNC. The start of the active lines from vertical sync edge is indicated by the VDELAY register. The start of the active pixels from the horizontal edge is indicated by the HDELAY register. The sizes and location of the active video are determined by HDELAY, HACTIVE, VDELAY, and VACTIVE registers. These registers are 8-bit wide, the lower 8-bits is, respectively, in HDELAY_LO, HACTIVE_LO, VDELAY_LO, and VACTIVE_LO. Their upper 2-bit shares the same register CROP_HI. In order for the cropping to work properly, the following equation should be satisfied. HDELAY + HACTIVE < Total number of pixels per line. VDELAY + VACTIVE < Total number of lines per field Table 2 shows some popular video formats and its recommended register settings. The CCIR601 format refers to the sampling rate of 13.5 MHz. The SQ format for 60 Hz system refers to the sampling rate of 12.27 MHz, and the SQ format for 50 Hz system refers to the use of sampling rate of 14.75 MHz.
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TW9910
Scaling Ratio Format Total Resolution 780x525 858x525 944x625 864x625 390x262 429x262 472x312 432x312 195x131 214x131 236x156 216x156 Output Resolution 640x480 720x480 768x576 720x576 320x240 360x240 384x288 360x288 160x120 180x120 192x144 180x144
Low Power NTSC/PAL/SECAM Video Decoder with VBI Slicer
HSCALE values 0x0100 0x0100 0x0100 0x0100 0x0200 0x0200 0x0200 0x0200 0x0400 0x0400 0x0400 0x0400
VSCALE (frame) 0x0100 0x0100 0x0100 0x0100 0x0200 0x0200 0x0200 0x0200 0x0400 0x0400 0x0400 0x0400
1:1
2:1 (CIF)
4:1 (QCIF)
NTSC SQ NTSC CCIR601 PAL SQ PAL CCIR601 NTSC SQ NTSC CCIR601 PAL SQ PAL CCIR601 NTSC SQ NTSC CCIR601 PAL SQ PAL CCIR601
Table 2. HSCALE and VSCALE value for some popular video formats.
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TW9910
Low Power NTSC/PAL/SECAM Video Decoder with VBI Slicer
Output Interface
ITU-R BT.656 ITU-R BT.656 defines strict EAV/SAV Code, video data output timing, H blanking timing, and V Blanking timing. In this mode, VD[15:8] pins are only effective and CLKx2 pin should be used for data clock signal. EAV/SAV Code format is shown as follows. Bit 7 of forth byte in EAV/SAV code must be "1" in ITU-R BT.656 standard. For that reason, VIPCFG Register bit must be set to "1". Table3. ITU-R BT.656 SAV and EAV code sequence VD15 VD14 VD13 VD12 VD11 VD10 VD9 1 1 1 1 1 1 1st byte 1 0 0 0 0 0 0 2nd byte 0 0 0 0 0 0 0 3rd byte 0 4th byte *C F V H V XOR H F XOR H F XOR V
VD8 1 0 0 F XOR V XOR H
*C is set by VIPCFG register bit.
For complete IRU-R BT.656 standard, following setting is recommended. Table 4. ITU-R BT.656 Register set up 525 line system 625 line system 1 1 0 0 0x012 0x018 0X0F4 0x120 0x2D0 0x2D0 1 1 1 1 1 0
Register MODE LEN VDELAY VACTIVE HACTIVE HA_EN VIPCFG NTSC656
ITU-R BT.656 for 525-line system has 244 video active lines in odd field and 243 vide active lines in even field. NTSC656 register bit controls this video active line length. Horizontal Down Scaling Output TW9910 generates Horizontal down scaling output data. Figure 2 shows 8 bit mode Horizontal Down Scaling output timing. As shown on Figure 2, Horizontal Down Scaled data are generated by continuous data stream. The trailing edge of DVALID signal changes with the trailing edge of HACTIVE signal. Data value from the leading edge of HACTIVE to the leading edge of DVALID is programmable by CNTL656 register. If CNTL656 is set to "1", all Y and CbCr data will be 0x00. If CNTL656 is set to "0", all Y data will be 0x10 and all CbCr data will be 0x80. VIP application normally uses 0x00 data as invalid data. Figure 2 shows 360 active pixels output timing after horizontal downscaling.
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TW9910
Low Power NTSC/PAL/SECAM Video Decoder with VBI Slicer
VCLK HACTIVE x 2 VCLK HACTIVE DVALID 360x2 VCLK
VD[15:8]
0x00
Cb0
Y0
Cr0
Y1
Cb2
...
Cb358
Y358
Cr358
Y359
Figure 2. 8 bit mode Horizontal Down Scaling Output
Vertical Down Scaling Output TW9910 generates Vertical Down Scaling output data. Figure 3 shows its timing. As shown on Figure 3, HACTIVE is NOT generated on invalid line as default (VSCTL is "0"). If VSCTL is set to "1", HACTIVE is generated on every lines during VACTIVE active period. DVALID is not generated on invalid lines in each setting. Invalid lines for Vertical down scaling are generated during VACTIVE active period. If MODE bit is set to "1" for VIP mode, EAV/SAV codes are not generated on those lines without HACTIVE signal. All CbCr data will be 80H and all Y data will be 10H the same as H-blanking data in ITU-R BT.656 data stream.
HSYNC HACTIVE DVALID VACTIVE LVALID (OPTION)
Figure 3. Vertical Down Scaling Output
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TW9910 VBI Data Processing
Raw VBI data output
Low Power NTSC/PAL/SECAM Video Decoder with VBI Slicer
TW9910 supports raw VBI data output. Raw VBI data output has the same vertical line delay timing as video output. Horizontal output timing is also programmable by VBIDELAY register. Raw VBI data is generated during HACTIVE active period (from SAV to EAV) as Video data output. Total pixel number of raw VBI data per line is twice as many as HACTIVE register value. If VBI EN register is set to "1", all vertical blanking output while VACTIVE is inactive will be raw VBI data output. If VVBI registers are set to more than "1", the VVBI number lines from top video active lines will also be raw VBI data output lines. VBI Data Slicer The following VBI standards are supported by VBI Data slicer. The VBI Data slicing is controlled by the registers LCTL6 to LCTL26. Registers LCTL6 to LCTL26 are controlling the slicing process itself. LCTL6 to LCTL26 defines the Data Type to be decoded. The Data Type can be specified on a line by line basis for line6 to line26 and for even and odd field depending on the detected TV system standard. The setting for LCTL26 is valid for the rest of the corresponding field. Normally no text data 0H (video data) should be selected to render the VBI Data slicer inactive during active video. LCTRL26 is useful for Full-Field Teletext mode in the case of NABTS. NABTS is 525 Teletext-C. Japan's MOJI is 525 Teletext-D. Didon Antiope is 625 Teletext-A. VBI Data slicer supports up to Physical layer, Link layer in ITU-R BT.653-2. Japan's EIAJ CPR-1204 shown as 525 WSS has the same physical layer protocol as that of CGMS. The sliced VBI data is embedded in the ITU-R BT.656 output stream, using the intervals between the End of Active Video (EAV) and the Start of Active Vide(SAV) codes of each line and formatted according to ITU-R BT.1364 Ancillary data packet Type 2.
Table 5. VBI Standard.
STANDARD TYPE 625 Teletext-B 525 Teletext-B 625 Teletext-C 525 Teletext-C 625 Teletext-D 525 Teletext-D 625 CC 525 CC 625 WSS 525 WSS(CGMS) 625 VITC 525 VITC Gemstar 2x Gemstar 1x VPS 625 Teletext-A
TV Systems (lines/freq) 625/50 525/60 625/50 525/60 625/50 525/60 625/50 525/60 626/50 525/60 625/50 525/60 525/60 525/60 625/50 625/50
Bit Rate (Mbits/s) 6.9375 5.727272 5.734375 5.727272 5.6427875 5.727272 0.500 0.503 5 0.447443 1.8125 1.7898 1.007 0.503 5 6.203125
Modulation NRZ NRZ NRZ NRZ NRZ NRZ NRZ NRZ Bi-phase NRZ NRZ NRZ NRZ NRZ Bi-phase NRZ
Data Type 1H 1H 2H 2H 3H 3H 4H 4H 5H 5H 6H 6H 7H 8H 9H AH
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TW9910
Sliced VBI Data output format
Low Power NTSC/PAL/SECAM Video Decoder with VBI Slicer
After 4 bytes of EAV code, sliced VBI ANC data packets are generated by following format. Byte1 to Byte4N+7 data stream is formatted according to ITU-R BT.1364 ANC data packet type2. BC data byte is optional and not included in ANC data packet type 2 BC data byte is inserted after ANC data packet type2.
Table 6. Sliced VBI ANC data packet
BYTE No. D7 MSB D6 D5 D4 D3 D2 D1 D0 LSB DESCRIPTION
Ancillary data flag
1
2 3 4 5 6 7 8 9 10 11 12 13 . . 4N+6 4N+7 4N+8 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14.
0 1 1
NEP NEP NEP OP OP
0 1 1
EP EP EP FID LN2
0 1 1
0 SDID5 DC5 LN8 LN1
0 1 1
DID4 SDID4 DC4 LN7 LN0
0 1 1
DID3 SDID3 DC3 LN6 DT3
0 1 1
DID2 SDID2 DC2 LN5 DT2
0 1 1
DID1 SDID1 DC1 LN4 DT1
0 1 1
DID0 SDID0 DC0 LN3 DT0
Sliced VBI Data byte 1
Sliced VBI Data byte 2 Sliced VBI Data byte 3 Sliced VBI Data byte 4 Sliced VBI Data byte 5
DID SDID DC IDI1. UDW1 IDI2. UDW 2 Sliced VBI Data No.1. UDW3 Sliced VBI Data No.2. UDW4 Sliced VBI Data No.3 UDW5 Sliced VBI Data No.4. UDW6 Sliced VBI Data No.5. UDW7
. . Sliced VBI Data byte last or FILLDATA
NCS6 OP CS6 0 CS5 BC5 CS4 BC4 CS3 BC3 CS2 BC2 CS1 BC1 CS0 BC0
Sliced VBI Data Last or FILLDATA. UDW 4N CS BC
EP is Even Parity of bits 5 to 0 in same 1 byte. NEP is inverted EP in same 1 byte. {DID4,DID3,DID2,DID1,DID0} is DID register value. {SDID5,SDID4,SDID3,SDID2,SDID1,SDID0} is SDID register value. {DC5,DC4,DC3,DC2,DC1,DC0} is the number of DOWRD data length from UDW1 to UDW4N.On this table, {DC5,DC4,DC3,DC2,DC1,DC0} is N(decimal). OP is Odd Parity of bits 6 to 0 in same 1 byte. FID=0: odd field ; FID=1: even field. {LN8,LN7,LN6,LN5,LN4,LN3,LN2,LN1,LN0} is the line number of current sliced VBI data. {DT3,DT2,DT1,DT0} is the Data Type shown on Table NCS6 is inverted CS6. {CS6,CS5,CS4,CS3,CS2,CS1,CS0} is the checksum value calculated from DID to UDW4N. UDW1 to UDW4N are the User data words(UDW) shown on ITU-R BT.1364 ANC data packet type 2. [BC5,BC4,BC3,BC2,BC1,BC0] is the number of valid bytes from UDW1 to UDW4N. FILLDATA is FILLDATA register value. FILLDATA is inserted after last valid bytes to make 4N number byte stream sometimes.
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TW9910
Following shows various type of ANC data packet to be output
Table 7. Closed Captioning ANC data packet
BYTE No. D7 MSB D6 D5 D4 D3 D2 D1 D0 LSB
Low Power NTSC/PAL/SECAM Video Decoder with VBI Slicer
DESCRIPTION
Ancillary data flag
1
2 3 4 5 6 7 8 9 10 11 12
0 1 1
NEP NEP 0 OP OP
0 1 1
EP EP 1 FID LN2
0 1 1
0 SDID5 0 LN8 LN1
0 1 1
DID4 SDID4 0 LN7 LN0
nd
0 1 1
DID3 SDID3 0 LN6 0
0 1 1
DID2 SDID2 0 LN5 1
0 1 1
DID1 SDID1 0 LN4 0
0 1 1
DID0 SDID0 1 LN3 0
1st Character byte
NCS6 0 CS6 0 CS5 0 2 Character byte CS4 CS3 0 0
DID SDID DC IDI1. UDW1 IDI2. UDW 2 UDW3 UDW4 CS BC
CS2
1
CS1 0
CS0 0
Table 8. CGMS ANC data packet
BYTE No. D7 MSB D6 D5 D4 D3 D2 D1 D0 LSB DESCRIPTION
Ancillary dataflag
1
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
0 1 1
NEP NEP 0 OP OP
0 1 1
EP EP 1 FID LN2
0 1 1
0 SDID5 0 LN8 LN1
0 1 1
DID4 SDID4 0 LN7 LN0
0 1 1
DID3 SDID3 0 LN6 0
0 1 1
DID2 SDID2 0 LN5 1
0 1 1
DID1 SDID1 1 LN4 0
0 1 1
DID0 SDID0 0 LN3 1
WSS[7:0]
WSS[15:8] {0H,WSS[19:16]} CRCERRORCODE FILLDATA FILLDATA CS4 CS3 0 0
DID SDID DC IDI1. UDW1 IDI2. UDW 2 UDW3 UDW4 UDW5 UDW6 UDW7 UDW8 CS BC
NCS6 1
CS6 0
CS5 0
CS2
1
CS1 1
CS0 0
1.CRCERRORCODE is optional byte. 41H means "this wss data has CRC Error". 80H means no CRC error.
Table 9. 625 line Wide Screen signaling ANC data packet
BYTE No. D7 MSB D6 D5 D4 D3 D2 D1 D0 LSB DESCRIPTION
Ancillary dataflag
1
2 3 4 5 6 7 8 9 10
0 1 1
NEP NEP 0 OP OP
0 1 1
EP EP 1 FID LN2
0 1 1
0 SDID5 0 LN8 LN1
0 1 1
DID4 SDID4 0 LN7 LN0
0 1 1
DID3 SDID3 0 LN6 0
0 1 1
DID2 SDID2 0 LN5 1
0 1 1
DID1 SDID1 0 LN4 0
0 1 1
DID0 SDID0 1 LN3 1
WSS[7:0]
{00b,WSS[13:8]
DID SDID DC IDI1. UDW1 IDI2. UDW 2 UDW3 UDW4
TECHWELL, INC.
14
REV. A 09/21/2006
TW9910
12 13 NCS6 0 CS6 0 CS5 0 CS4 0 CS3 0 CS1 0 CS0 0 CS BC
Low Power NTSC/PAL/SECAM Video Decoder with VBI Slicer
CS2
1
Table 10. 625 Teletext-A ANC data packet
BYTE No. D7 MSB D6 D5 D4 D3 D2 D1 D0 LSB DESCRIPTION
Ancillary dataflag
1
2 3 4 5 6 7 8 9 10 11 . . 46 47 48 49 50 51 52
0 1 1
NEP NEP 0 OP OP
0 1 1
EP EP 1 FID LN2
0 1 1
0 SDID5 0 LN8 LN1
0 1 1
DID4 SDID4 0 LN7 LN0
0 1 1
DID3 SDID3 1 LN6 1
0 1 1
DID2 SDID2 0 LN5 0
0 1 1
DID1 SDID1 1 LN4 1
0 1 1
DID0 SDID0 1 LN3 0
FRAME CDDE
BYTE4 BYTE5 . . BYTE40 HAMM84ERROR FILLDATA FILLDATA FILLDATA CS4 CS3 0 1
DID SDID DC IDI1. UDW1 IDI2. UDW 2 UDW3 UDW4 UDW5
NCS6 0
CS6 0
CS5 1
CS2
0
CS1 0
CS0 1
UDW40 UDW41 UDW42 UDW43 UDW44 CS BC
1.FRAME CODE is E7H if it's received correctly. 2.HAMM84ERROR is 41H if more than 1 8/4 Hamming code error in this packet,80H means no 8/4 Hamming error.
Table 11. 625 Teletext-B ANC data packet
BYTE No. D7 MSB D6 D5 D4 D3 D2 D1 D0 LSB DESCRIPTION
Ancillary dataflag
1
2 3 4 5 6 7 8 9 10 11 . . 50 51 52 53 54 55 56
0 1 1
NEP NEP 1 OP OP
0 1 1
EP EP 0 FID LN2
0 1 1
0 SDID5 0 LN8 LN1
0 1 1
DID4 SDID4 0 LN7 LN0
0 1 1
DID3 SDID3 1 LN6 0
0 1 1
DID2 SDID2 1 LN5 0
0 1 1
DID1 SDID1 0 LN4 0
0 1 1
DID0 SDID0 0 LN3 1
FRAME CDDE
BYTE4 BYTE5 . . BYTE44 BYTE45 HAMM84ERROR FILLDATA FILLDATA CS4 CS3 0 1
DID SDID DC IDI1. UDW1 IDI2. UDW 2 UDW3 UDW4 UDW5
NCS6 1
CS6 0
CS5 1
CS2
1
CS1 1
CS0 0
UDW44 UDW45 UDW46 UDW47 UDW48 CS BC
1.FRAME CODE is 27H if it's received correctly. 2.HAMM84ERROR is 41H if more than 1 8/4 Hamming code error in this packet,80H means no 8/4 Hamming error.
TECHWELL, INC.
15
REV. A 09/21/2006
TW9910
Low Power NTSC/PAL/SECAM Video Decoder with VBI Slicer
Table 12. 525 Teletext-B ANC data packet
BYTE No. D7 MSB D6 D5 D4 D3 D2 D1 D0 LSB DESCRIPTION
Ancillary dataflag
1
2 3 4 5 6 7 8 9 10 11 . . 30 31 32 33 34 35
0 1 1
NEP NEP 1 OP OP
0 1 1
EP EP 0 FID LN2
0 1 1
0 SDID5 0 LN8 LN1
0 1 1
DID4 SDID4 0 LN7 LN0
0 1 1
DID3 SDID3 1 LN6 0
0 1 1
DID2 SDID2 0 LN5 0
0 1 1
DID1 SDID1 1 LN4 0
0 1 1
DID0 SDID0 0 LN3 1
FRAME CDDE
BYTE4 BYTE5 . . BYTE36 BYTE37 HAMM84ERROR FILLDATA FILLDATA CS4 CS3 0 0
DID SDID DC IDI1. UDW1 IDI2. UDW 2 UDW3 UDW4 UDW5
NCS6 1
CS6 0
CS5 1
CS2
1
CS1 1
CS0 0
UDW36 UDW37 UDW38 UDW39 UDW40 CS BC
36
1.FRAME CODE is 27H if it's received correctly. 2.HAMM84ERROR is 41H if more than 1 8/4 Hamming code error in this packet,80H means no 8/4 Hamming error.
Table 13. 625 Teletext-C and 525 Teletext-C ANC data packet
BYTE No. D7 MSB D6 D5 D4 D3 D2 D1 D0 LSB DESCRIPTION
Ancillary dataflag
1
2 3 4 5 6 7 8 9 10 11 . . 42 43 44 45 46 47
0 1 1
NEP NEP 1 OP OP
0 1 1
EP EP 0 FID LN2
0 1 1
0 SDID5 0 LN8 LN1
0 1 1
DID4 SDID4 0 LN7 LN0
0 1 1
DID3 SDID3 1 LN6 0
0 1 1
DID2 SDID2 0 LN5 0
0 1 1
DID1 SDID1 1 LN4 1
0 1 1
DID0 SDID0 0 LN3 0
FRAME CDDE
BYTE4 BYTE5 . . BYTE36 HAMM84ERROR FILLDATA FILLDATA FILLDATA CS4 CS3 0 0
DID SDID DC IDI1. UDW1 IDI2. UDW 2 UDW3 UDW4 UDW5
NCS6 0
CS6 0
CS5 1
CS2
1
CS1 0
CS0 1
UDW36 UDW37 UDW38 UDW39 UDW40 CS BC
48
1.FRAME CODE is E7H if it's received correctly. 2.HAMM84ERROR is 41H if more than 1 8/4 Hamming code error in this packet,80H means no 8/4 Hamming error.
TECHWELL, INC.
16
REV. A 09/21/2006
TW9910
Low Power NTSC/PAL/SECAM Video Decoder with VBI Slicer
Table 14. 625 Teletext-D and 525 Teletext-D ANC data packet
BYTE No. D7 MSB D6 D5 D4 D3 D2 D1 D0 LSB DESCRIPTION
Ancillary dataflag
1
2 3 4 5 6 7 8 9 10 11 . . 42 43 44 45 46 47
0 1 1
NEP NEP 1 OP OP
0 1 1
EP EP 0 FID LN2
0 1 1
0 SDID5 0 LN8 LN1
0 1 1
DID4 SDID4 0 LN7 LN0
0 1 1
DID3 SDID3 1 LN6 0
0 1 1
DID2 SDID2 0 LN5 0
0 1 1
DID1 SDID1 1 LN4 1
0 1 1
DID0 SDID0 0 LN3 1
FRAME CDDE
BYTE4 BYTE5 . . BYTE36 BYTE37 FILLDATA FILLDATA FILLDATA CS4 CS3 0 0
DID SDID DC IDI1. UDW1 IDI2. UDW 2 UDW3 UDW4 UDW5
NCS6 0
CS6 0
CS5 1
CS2
1
CS1 0
CS0 1
UDW36 UDW37 UDW38 UDW39 UDW40 CS BC
48
1.FRAME CODE is A7H if it's received correctly.
Table 15. Line16 VPS ANC data packet
BYTE No. D7 MSB D6 D5 D4 D3 D2 D1 D0 LSB DESCRIPTION
Ancillary dataflag
1
2 3 4 5 6 7 8 9 10 11 . . 22 23 24 25 26 27
0 1 1
NEP NEP 1 OP OP
0 1 1
EP EP 0 FID LN2
0 1 1
0 SDID5 0 LN8 LN1
0 1 1
DID4 SDID4 0 LN7 LN0
0 1 1
DID3 SDID3 0 LN6 1
0 1 1
DID2 SDID2 1 LN5 0
0 1 1
DID1 SDID1 0 LN4 0
0 1 1
DID0 SDID0 1 LN3 1
START CDDE1(51H)
START CODE2(99H) BYTE3 . . BYTE14 BYTE15 BI-PHASEERROR FILLDATA FILLDATA CS4 CS3 1 0
DID SDID DC IDI1. UDW1 IDI2. UDW 2 UDW3 UDW4 UDW5
NCS6 1
CS6 0
CS5 0
CS2
0
CS1 1
CS0 0
UDW16 UDW17 UDW18 UDW19 UDW20 CS BC
28
1.START CODE1 is the first byte of Start Code by 5Mbps slicing. 2.START CODE2 is the second byte of Start Code by 5Mbps slicing. 3.BYTE3~BYTE15 are data bytes by 5/2 Mbps Bi-phase slicing. 4.BI-PHASEEROOR is Bi-phase coding error detection.80H means No error.41H means Bi-phase coding error is detected.
TECHWELL, INC.
17
REV. A 09/21/2006
TW9910
Low Power NTSC/PAL/SECAM Video Decoder with VBI Slicer
Table 16. VITC ANC data packet
BYTE No. D7 MSB D6 D5 D4 D3 D2 D1 D0 LSB DESCRIPTION
Ancillary dataflag
1
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
0 1 1
NEP NEP 1 OP OP
0 1 1
EP EP 0 FID LN2
0 1 1
0 SDID5 0 LN8 LN1
0 1 1
DID4 SDID4 0 LN7 LN0
0 1 1
DID3 SDID3 0 LN6 0
0 1 1
DID2 SDID2 0 LN5 1
0 1 1
DID1 SDID1 1 LN4 1
0 1 1
DID0 SDID0 1 LN3 0
Bit[9:2]
Bit[19:12] Bit[29:22] .Bit[39:32] .Bit[49:42] Bit[59:52] Bit[69:62] Bit[79:72] Bit[89:82] CRCERROR NCS6 1 CS6 0 CS5 0 CS4 0 CS3 1
DID SDID DC IDI1. UDW1 IDI2. UDW 2 UDW3 UDW4 UDW5 UDW6 UDW7 UDW8 UDW9 UDW10 UDW11 UDW12
18
19
CS2
1
CS1 0
CS0 0
CS BC
20
1.CRCERROR is CRC Error information.41H means CRC Error is deteced.80H means no CRC error.
Table 17. Gemstar 1X ANC data packet
BYTE No. D7 MSB D6 D5 D4 D3 D2 D1 D0 LSB DESCRIPTION
Ancillary dataflag
1
2 3 4 5 6 7 8 9 10 11 12
0 1 1
NEP NEP 0 OP OP
0 1 1
EP EP 1 FID LN2
0 1 1
0 SDID5 0 LN8 LN1
0 1 1
DID4 SDID4 0 LN7 LN0
0 1 1
DID3 SDID3 0 LN6 1
0 1 1
DID2 SDID2 0 LN5 0
0 1 1
DID1 SDID1 0 LN4 0
0 1 1
DID0 SDID0 1 LN3 0
1st Character byte
NCS6 0 CS6 0 CS5 0 2 nd Character byte CS4 CS3 0 0
DID SDID DC IDI1. UDW1 IDI2. UDW 2 UDW3 UDW4 CS BC
CS2
1
CS1 0
CS0 0
TECHWELL, INC.
18
REV. A 09/21/2006
TW9910
Low Power NTSC/PAL/SECAM Video Decoder with VBI Slicer
Table 18. Gemstar 2X ANC data packet
BYTE No. D7 MSB D6 D5 D4 D3 D2 D1 D0 LSB DESCRIPTION
Ancillary dataflag
1
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
0 1 1
NEP NEP 0 OP OP
0 1 1
EP EP 1 FID LN2
0 1 1
0 SDID5 0 LN8 LN1
0 1 1
DID4 SDID4 0 LN7 LN0
0 1 1
DID3 SDID3 0 LN6 0
0 1 1
DID2 SDID2 0 LN5 1
0 1 1
DID1 SDID1 1 LN4 1
0 1 1
DID0 SDID0 0 LN3 1
FRAMECODE1 FRAMECODE2 Data Byte 1 Data Byte 2 Data Byte 3
NCS6 0 CS6 0 CS5 0 Data Byte 4 CS4 CS3 0 1
DID SDID DC IDI1. UDW1 IDI2. UDW 2 UDW3 UDW4 UDW5 UDW6 UDW7
CS2
0
CS1 0
CS0 0
UDW8 CS BC
1.FRAMCODE1 is B9H if Frame Code is correctly received. 2.FRAMCODE2 is 05H if Frame Code is correctly received.
TECHWELL, INC.
19
REV. A 09/21/2006
TW9910 Two Wire Serial Bus Interface
Low Power NTSC/PAL/SECAM Video Decoder with VBI Slicer
Start Condition SDAT
Stop Condition
SCLK
Figure 4. Definition of the serial bus interface bus start and stop
Device ID (1-7) R/W Index (1-8)
SDAT SCLK Start Condition Ack Ack
Device ID (1-7)
R/W
Data (1-8)
Re-start Condition
Ack
Stop Nack Condition
Figure 5. One complete register read sequence via the serial bus interface
Device ID (1-7)
R/W
Index (1-8)
Data (1-8)
SDAT SCLK Start Condition Ack Ack Ack Stop Condition
Figure 6. One complete register write sequence via the serial bus interface
TECHWELL, INC.
20
REV. A 09/21/2006
TW9910
Low Power NTSC/PAL/SECAM Video Decoder with VBI Slicer
The two wire serial bus interface is used to allow an external micro-controller to write control data to, and read control or other information from the TW9910 registers. SCLK is the serial clock and SDAT is the data line. Both lines are pulled high by resistors connected to VDD. ICs communicate on the bus by pulling SCLK and SDAT low through open drain outputs. In normal operation the master generates all clock pulses, but control of the SDAT line alternates back and forth between the master and the slave. For both read and write, each byte is transferred MSB first, and the data bit is valid whenever SCLK is high. The TW9910 is operated as a bus slave device. It can be programmed to respond to one of two 7-bit slave device addresses by tying the SIAD (Serial Interface ADdress) pin ether to VDD or VSS (See Table 19) through a pull-up or pull-down resister. The SIAD pin is multi-purpose pin and must not tied to VDD or VSS directly. If the SIAD pin is tied to VDD, then the least significant bit of the 7-bit address is a "1". If the SIAD pin is tied to VSS then the least significant bit of the 7-bit address is a "0". The most significant 6-bits are fixed. The 7-bit address field is concatenated with the read/write control bit to form the first byte transferred during a new transfer. If the read/write control bit is high the next byte will be read from the slave device. If it is low the next byte will be a write to the slave. When a bus master (the host microprocessor) drives SDAT from high to low, while SCLK is high, this is defined to be a start condition (See Figure 4.). All slaves on the bus listen to determine when a start condition has been asserted. After a start condition, all slave devices listen for the their device addresses. The host then sends a byte consisting of the 7-bit slave device ID and the R/W bit. This is shown in Figure 5. (For the TW9910, the next byte is normally the index to the TW9910 registers and is a write to the TW9910 therefore the first R/W bit is normally low.) After transmitting the device address and the R/W bit, the master must release the SDAT line while holding SCLK low, and wait for an acknowledgement from the slave. If the address matches the device address of a slave, the slave will respond by driving the SDAT line low to acknowledge the condition. The master will then continue with the next 8-bit transfer. If no device on the bus responds, the master transmits a stop condition and ends the cycle. Notice that a successful transfer always includes nine clock pulses. To write to the internal register of theTW9910, the master sends another 8-bits of data, the TW9910 loads this to the register pointed by the internal index register. The TW9910 will acknowledge the 8-bit data transfer and automatically increment the index in preparation for the next data. The master can do multiple writes to the TW9910 if they are in ascending sequential order. After each 8-bit transfer the TW9910 will acknowledge the receipt of the 8-bits with an acknowledge pulse. To end all transfers to the TW9910 the host will issue a stop condition. Serial Bus Interface 7-bit Slave Address 1 0 0 0 1 0 SIAD0 Read/Write bit 1=Read 0=Write
Table 19 TW9910 serial bus interface 7-bit slave address and read write bit A TW9910 read cycle has two phases. The first phase is a write to the internal index register. The second phase is the read from the data register. (See figure 5). The host initiates the first phase by sending the start condition. It then sends the slave device ID together with a 0 in the R/W bit position. The index is then sent followed by either a stop condition or a second start condition. The second phase starts with the second start condition. The master then resends the same slave device ID with a 1 in the R/W bit position to indicate a read. The slave will transfer the contents of the desired register. The master remains in control of the clock. After transferring eight bits, the slave releases and the master takes control of the SDAT line and acknowledges the receipt of data to the slave. To terminate
TECHWELL, INC.
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TW9910
Low Power NTSC/PAL/SECAM Video Decoder with VBI Slicer
the last transfer the master will issue a negative acknowledge (SDAT is left high during a clock pulse) and issue a stop condition.
Test Modes
The input pin TMODE combining with RESET# provide different test modes selection. If this pin is low at the rising edge of the RESET# pin and remaining low afterwards, TW9910 is in the normal operating mode. Other test modes can be obtained as shown in Table 20. Table 20. Test mode selection and description Test mode TMODE before RESET# rising edge 0 0 1 TMODE after RESET# rising edge 0 1 0 Description
Normal Pin tri-state Outputs high
Normal operation mode. In this mode, all pin output drivers are tri-stated. Pin leakage current parameters can be measured. In this mode, all pin output drivers are forced to the high output state. Pin output high voltage, VOH and IOH, can be measured. In this mode, all pin output drivers are forced to the low output state. Pin output low voltage, VOL and IOL, can be measured.
Outputs low
1
1
TECHWELL, INC.
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REV. A 09/21/2006
TW9910 Filter Curves
Anti-alias filter
Low Power NTSC/PAL/SECAM Video Decoder with VBI Slicer
5 0 -5 -10 ) B d ( n i a G -15 -20 -25 -30 -35 -40 0 2 4 6 8 10 12 Frequency (Hertz) 14 16 18 20
Decimation filter
0 -5 -10 ) B d ( e s n o p s e R e d u t i n g a M -15 -20 -25 -30 -35 -40 -45 -50
0
2
4
6 8 Frequency (Hertz)
10
12 x 10
6
TECHWELL, INC.
23
REV. A 09/21/2006
TW9910
Low Power NTSC/PAL/SECAM Video Decoder with VBI Slicer
Chroma Band Pass Filter Curves
0 -5 -10 ) B d ( e s n o p s e R e d u t i n g a M -15
NTSC PAL/SEAM
-20 -25 -30 -35 -40 -45 -50
0
1
2
3
4 5 Frequency (Hertz)
6
7
8 x 10
9
6
Luma Notch Filter Curve for NTSC and PAL/SECAM
0 -10 -20 ) B d ( e s n o p s e R e d u t i n g a M
PAL/SECAM
-30 -40 -50 -60 -70 -80
NTSC
0
1
2
3
4 5 Frequency (Hertz)
6
7
8 x 10
9
6
TECHWELL, INC.
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REV. A 09/21/2006
TW9910
Chrominance Low-Pass Filter Curve
Low Power NTSC/PAL/SECAM Video Decoder with VBI Slicer
0 -5 -10
High
) B d ( e s n o p s e R e d u t i n g a M
-15 -20 -25 -30 -35 -40 -45 -50
Low Med
0
0.5
1
1.5
2 2.5 3 Frequency (Hertz)
3.5
4
4.5 x 10
5
6
Horizontal Scaler Pre- Filter curves
0 -5
HFLT[1:0]=1
-10 ) B d ( e s n o p s e R e d u t i n g a M
HFLT[1:0]=2
-15
HFLT[1:0]=3
-20 -25 -30 -35 -40
0
0.05
0.1
0.15
0.2 0.25 0.3 Fsig/Fsample
0.35
0.4
0.45
0.5
TECHWELL, INC.
25
REV. A 09/21/2006
TW9910
Peaking Filter Curves NTSC
Low Power NTSC/PAL/SECAM Video Decoder with VBI Slicer
16 14 12 ) B d ( e s n o p s e R e d u t i n g a M 10 8 6 4 2 0
0
1
2
3 4 Frequency (Hertz)
5
6 x 10
7
6
PAL
16 14 12 ) B d ( e s n o p s e R e d u t i n g a M 10 8 6 4 2 0
0
1
2
3
4 5 Frequency (Hertz)
6
7
8 x 10
9
6
TECHWELL, INC.
26
REV. A 09/21/2006
TW9910
Low Power NTSC/PAL/SECAM Video Decoder with VBI Slicer
Control Register
TW9910 Register SUMMARY
Index (HEX)
7
6
5
ID
4
3
2
1
REV
0
00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F
VDLOSS YSEL2 MODE GMEN VSP SRESET
HLOCK FC27 LEN CKHY
SLOCK IFSEL LLCMODE VSSL
FIELD AINC
VLOCK YSEL VSCTL HSP
OEN HSDLY
MONO CSEL
DET50 SEL
TRI_SEL HSSL
IREF
VREF
AGC_EN
CLKPDN
Y_PDN
C_PDN HACTIVE_HI
-
VDELAY_HI
VACTIVE_HI VDELAY_LO VACTIVE_LO
HDELAY_HI
HDELAY_LO HACTIVE_LO
PBW DEM PALSW SET7 COMB HCOMP YCOMB PDLY VSCALE_LO VSCALE_HI HSCALE_LO BRIGHTNESS CONTRAST SCURVE CTI SAT_U SAT_V HUE SHCOR CTCOR VBI_EN LLCTEST VBI_BYT PLL_PDN CK2S DTSTUS START PAL60 CCOR VBI_FRAM HA_EN VCOR CTL656 YFLEN ATREG PALM TEST NTSC4 SECAM YSV RTSEL CFLEN STANDARD CSV VSHP CIF SHARPNESS HSCALE_HI
Reset (hex) 58 00 40 04 00 00 00 02 12 F0 0F D0 CC 00 11 00 00 5C 11 80 80 00 00 80 44 58 00 00 07 7F 00 00
CK1S
STDNOW PALCN
-
PALB
NTSC
TECHWELL, INC.
27
REV. A 09/21/2006
TW9910
Low Power NTSC/PAL/SECAM Video Decoder with VBI Slicer
Index (HEX) 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 40 41 42 43 44 45 46 47 48 4E 4F
7
6
CLPEND NMGAIN
5
4
3
2
CLPST WPGAIN
1
0
Agcgain[8]
AGCGAIN[7:0] PEAKWT CLMPLD SYNCTD MISSCNT PCLAMP VLCKI VLCKO VMODE DETV AFLD VINT CLMPL SYNCT HSWIN
BSHT CKILMAX HTL
CKLM
VSHT CKILMIN VTL YDLY PALC
ACCT EVCNT
Reset (hex) 50 22 F0 D8 BC B8 44 38 00 00 78 44 30 14 A5 E0 00 00 X 05 1E 00
HPLC
HPM
-
SDET
TBC_EN
BYPAS S
LCS MCVSN WSSDET
HFLT SYOUT
CBW CCS CSTRIPE EDSDET PSP
HADV
SPM CBAL KF VSTD HFREF FCS
NKILL
SF VCR FRM IDX CTEST
PKILL PF WKAIR
SKILL FF WKAIR1 YNR
BST CTYPE CCDET
CSBAD
NINTL
CLMD NSEN / SSEN / PSEN / WKTH VCLEN GTEST VLPF CKLY
YCLEN
CCLEN
CKLC
-
-
WSS[19:14]
TECHWELL, INC.
28
REV. A 09/21/2006
TW9910
Low Power NTSC/PAL/SECAM Video Decoder with VBI Slicer
Index (HEX) 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F
7
6
5
4
FILLDATA
3
2
1
0
NODAEN ANCEN CRCERR HA656
SYRM TOUTHA WSSFLD WSS[7:0] VIPCFG
SDID DID WSS[13:8] HAMM84 NTSC656 LCTL6 LCTL7 LCTL8 LCTL9 VVBI
EAVSW AP
Reset (hex) A0 22 31 X X 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 2C 60 00 20 24
LCTL10 LCTL11 LCTL12 LCTL13 LCTL14
LCTL15 LCTL16 LCTL17 LCTL18 LCTL19 LCTL20 LCTL21 LCTL22 LCTL23 LCTL24 LCTL25 LCTL26 HSBEGIN
HSEND OVSDLY
HSPIN
OFDLY
VSMODE VBIDELAY
OVSEND
PDNSV BI
TECHWELL, INC.
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REV. A 09/21/2006
TW9910
0x00 - Product ID Code Register (ID) Bit 7-3 2-0 ID Revision Function R/W R R Description The TW9910 Product ID code is 01011. The revision number.
Low Power NTSC/PAL/SECAM Video Decoder with VBI Slicer
Reset B 0
0x01 - Chip Status Register I (STATUS1) Bit 7 Function VDLOSS R/W R Description 1 = Video not present. (Sync is not detected in number of line periods specified by MISSCNT register) 0 = Video detected. 6 HLOCK R 1 = Horizontal sync PLL is locked to the incoming video source. 0 = Horizontal sync PLL is not locked. 5 SLOCK R 1 = Sub-carrier PLL is locked to the incoming video source. 0 = Sub-carrier PLL is not locked. 4 FIELD R 0 = Odd field is being decoded. 1 = Even field is being decoded. 3 VLOCK R 1 = Vertical logic is locked to the incoming video source. 0 = Vertical logic is not locked. 2 1 MONO R Reserved 1 = No color burst signal detected. 0 = Color burst signal detected. 0 DET50 R 0 = 60Hz source detected 1 = 50Hz source detected The actual vertical scanning frequency depends on the current standard invoked. 0 0 0 0 0 0 0 Reset 0
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Low Power NTSC/PAL/SECAM Video Decoder with VBI Slicer
0x02 - Input Format (INFORM) Bit 7 6 FC27 Function R/W R/W R/W Reserved. 1 = Input crystal clock frequency is 27MHz. 0 = Square pixel mode. Must use 24.54MHz for 60Hz field rate source or 29.5MHz for 50Hz field rate source. 5-4 IFSEL R/W 01 = S-video decoding 00 = Composite video decoding 3-2 YSEL R/W These two bits control the Y input video selection. 00 = Mux0 selected 01 = Mux1 selected 10 = Mux2 selected 11 = Mux3 selected 1 0 R/W R/W Reserved Reserved 0 0 0 0 Description Reset 0 1
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Low Power NTSC/PAL/SECAM Video Decoder with VBI Slicer
0x03 - Output Format Control Register (OPFORM) Bit 7 Function MODE R/W Description Reset 0
R/W 0 = CCIR601 compatible YCrCb 4:2:2 format with separate syncs and flags. 1 = ITU-R-656 compatible data sequence format.
6
LEN
R/W 0 = 8-bit YCrCb 4:2:2 output format. 1 = 16-bit YCrCb 4:2:2 output format. R/W 1 = LLC output mode. 0 = free-run output mode
0
5 4
LLCMODE AINC
0 0
R/W Serial interface auto-indexing control 0 = auto-increment 1 = non-auto R/W 1 = Vertical scale-downed output controlled by DVALID only. 0 = Vertical scale-downed output controlled by both HACTIVE and DVALID. R/W 0 = Enable outputs. 1 = Tri-state outputs defined by Tri-state select bits of this register. R/W These bits select the outputs to be tri-stated when the OEN bit is asserted high. There are three major groups that can be independently tri-stated: timing group (HS, VS, DVALID, MPOUT, FLD), data group (VD[15:0]), and clock (CLKX2/CLKX1) according to following definition. 00 = Timing and data group only. 01 = Data group only. 10 = All three groups. 11 = Clock and data group only.
3
VSCTL
0
2
OEN
1
1-0
TRI_SEL
0
0x04 - Color Killer Hysteresis and HSYNC Delay Control Bit 7 6-5 Function GMEN CKHY R/W R/W Reserved for test. R/W Color killer hysteresis. 0 - fastest 4-0 HSDLY 1 - fast 2 - medium 3 - slow 0 R/W Reserved for test. Description Reset 0 0
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Low Power NTSC/PAL/SECAM Video Decoder with VBI Slicer
0x05 - Output Control I Bit 7 Function VSP R/W Description Reset 0
R/W 0 = VS pin output polarity is active low 1 = VS pin output polarity is active high. R/W VS pin output control 0 = VSYNC 1 = VACT 2 = FIELD 3 = VVALID 4 - 7 = Reserved
6-4
VSSL
0
3
HSP
R/W 0 = HS pin output polarity is active low 1 = HS pin output polarity is active high. R/W HS pin output control 0 = HACT 1 = HSYNC 2 = DVALID 3 = HLOCK 4 = ASYNCW 5 - 7 = Reserved
0
2-0
HSSL
0
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Low Power NTSC/PAL/SECAM Video Decoder with VBI Slicer
0x06 - Analog Control Register (ACNTL) Bit 7 6 Function SRESET IREF R/W W Description An 1 written to this bit resets the device to its default state but all register content remain unchanged. This bit is self-resetting. Reset 0 0
R/W 0 = Internal current reference 1. 1 = Internal current reference 2. R/W 1 = Internal voltage reference. 0 = Internal voltage reference shut down. R/W 0 = AGC loop function enabled. 1 = AGC loop function disabled. Gain is set to by AGCGAIN. R/W 0 = Normal clock operation. 1 = System clock in power down mode, but the MPU INTERFACE module and output clocks (CLKX1 and CLKX2) are still active. R/W 0 = Luma ADC in normal operation. 1 = Luma ADC in power down mode. R/W 0 = Chroma ADC in normal operation. 1 = Chroma ADC in power down mode. R/W Reserved for future use
5
VREF
0
4
AGC_EN
0
3
CLK_PDN
0
2
Y_PDN
0
1
C_PDN
0
0
0
0x07 - Cropping Register, High (CROP_HI) Bit 7-6 5-4 3-2 1-0 Function VDELAY_HI VACTIVE_HI HDELAY_HI HACTIVE_HI R/W Description Reset 0 0 0 2
R/W These bits are bit 9 to 8 of the 10-bit Vertical Delay register. R/W These bits are bit 9 to 8 of the 10-bit VACTIVE register. Refer to description on Reg09 for its shadow register. R/W These bits are bit 9 to 8 of the 10-bit Horizontal Delay register. R/W These bits are bit 9 to 8 of the 10-bit HACTIVE register.
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Low Power NTSC/PAL/SECAM Video Decoder with VBI Slicer
0x08 - Vertical Delay Register, Low (VDELAY_LO) Bit 7-0 Function VDELAY_LO R/W Description Reset 12
R/W These bits are bit 7 to 0 of the 10-bit Vertical Delay register. The two MSBs are in the CROP_HI register. It defines the number of lines between the leading edge of VSYNC and the start of the active video.
0x09 - Vertical Active Register, Low (VACTIVE_LO) Bit 7-0 Function VACTIVE_LO R/W Description Reset F0
R/W These bits are bit 7 to 0 of the 10-bit Vertical Active register. The two MSBs are in the CROP_HI register. It defines the number of active video lines per frame output. The VACTIVE register has a shadow register for use with 50Hz source when Atreg of Reg0x1C is not set. This register can be accessed through the same index address by first changing the format standard to any 50Hz standard.
0x0A - Horizontal Delay Register, Low (HDELAY_LO) Bit 7-0 Function HDELAY_LO R/W Description Reset 0F
R/W These bits are bit 7 to 0 of the 10-bit Horizontal Delay register. The two MSBs are in the CROP_HI register. It defines the number of pixels between the leading edge of the HSYNC and the start of the image cropping for active video. The HDELAY_LO register has two shadow registers for use with PAL and SECAM sources respectively. These register can be accessed using the same index address by first changing the decoding format to the corresponding standard.
0x0B - Horizontal Active Register, Low (HACTIVE_LO) Bit 7-0 Function HACTIVE_LO R/W Description Reset D0
R/W These bits are bit 7 to 0 of the 10-bit Horizontal Active register. The two MSBs are in the CROP_HI register. It defines the number of active pixels per line output.
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Low Power NTSC/PAL/SECAM Video Decoder with VBI Slicer
0x0C - Control Register I (CNTRL1) Bit 7 Function PBW R/W R/W 1 = Wide Chroma BPF BW 0 = Normal Chroma BPF BW 6 DEM R/W Secam control 1 = reduction 1 0 = normal 0 Description Reset 1
5
PALSW
R/W 1 = PAL switch sensitivity low. 0 = PAL switch sensitivity normal. R/W 1 = The black level is 7.5 IRE above the blank level. 0 = The black level is the same as the blank level. R/W 1 = Adaptive comb filter on for NTSC 0 = Notch filter R/W 1 = operation mode 1. (Recommended) 0 = mode 0. R/W This bit controls the no color burst output behavior. 1 = No comb 0 = comb.
4
SET7
0
3
COMB
1
2
HCOMP
1
1
YCOMB
0
0
PDLY
R/W PAL delay line control 1 = disable. 0 = enable.
0
0x0D - Vertical Scaling Register, Low (VSCALE_LO) Bit 7-0 Function VSCALE_LO R/W Description Reset 00h
R/W These bits are bit 7 to 0 of the 12-bit vertical scaling ratio register
0x0E - Scaling Register, High (SCALE_HI) Bit 7-4 3-0 Function VSCALE_HI HSCALE_HI R/W Description Reset 1 1
R/W These bits are bit 11 to 8 of the 12-bit vertical scaling ratio register. R/W These bits are bit 11 to 8 of the 12-bit horizontal scaling ratio register.
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0x0F - Horizontal Scaling Register, Low (HSCALE_LO) Bit 7-0 Function HSCALE_LO R/W Description
Low Power NTSC/PAL/SECAM Video Decoder with VBI Slicer
Reset 00
R/W These bits are bit 7 to 0 of the 12-bit horizontal scaling ratio register.
0x10 - BRIGHTNESS Control Register (BRIGHT) Bit 7-0 Function BRIGHT R/W Description Reset 00
R/W These bits control the brightness. They have value of -128 to 127 in 2's complement form. Positive value increases brightness. A value 0 has no effect on the data.
0x11 - CONTRAST Control Register (CONTRAST) Bit 7-0 Function CNTRST R/W Description Reset 5C
R/W These bits control the contrast. They have value of 0 to 3.98 (FFh). A value of 1 (`100_0000`) has no effect on the video data.
0x12 - SHARPNESS Control Register I (SHARPNESS) Bit 7 Function SCURVE R/W Description Reset 0
R/W This bit controls the sharpness filter center frequency. 0 = Normal 1 = High R/W This bit is for internal used. R/W CTI level selection. 0 = lowest. 3 = hightest. R/W These bits control the amount of sharpness enhancement on the luminance signals. There are 16 levels of control with `0' having no effect on the output image. 1 through 15 provides sharpness enhancement with `F' being the strongest.
6 5-4 3-0
VSF CTI SHARP
1 1 1
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Low Power NTSC/PAL/SECAM Video Decoder with VBI Slicer
0x13 - Chroma (U) Gain Register (SAT_U) Bit 7-0 Function SAT_U R/W Description Reset 80
R/W These bits control the digital gain adjustment to the U (or Cb) component of the digital video signal. The color saturation can be adjusted by adjusting the U and V color gain components by the same amount in the normal situation. The U and V can also be adjusted independently to provide greater flexibility. The range of adjustment is 0 to 200%.
0x14 - Chroma (V) Gain Register (SAT_V) Bit 7-0 Function SAT_V R/W Description Reset 80
R/W These bits control the digital gain adjustment to the V (or Cr) component of the digital video signal. The color saturation can be adjusted by adjusting the U and V color gain components by the same amount in the normal situation. The U and V can also be adjusted independently to provide greater flexibility. The range of adjustment is 0 to 200%.
0x15 - Hue Control Register (HUE) Bit 7-0 Function HUE R/W Description Reset 00
R/W These bits control the color hue as 2's complement number. They o o o have value from +36 (7Fh) to -36 (80h) with an increment of 0.28 . The positive value gives greenish tone and negative value gives o purplish tone. The default value is 0 (00h). This is effective only on NTSC system.
0x16 - Reserved Bit 7-4 3-0 Function R/W R/W Reserved for future use. R/W Reserved for future use. Description Reset 0 0
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Low Power NTSC/PAL/SECAM Video Decoder with VBI Slicer
0x17 - Coring Bit 7-4 3 2-0 VSHP Function SHCOR R/W Description Reset 8 0 0
R/W These bits provide coring function for the sharpness control. Reserved R/W Vertical peaking level. 0 = none. 7 = highest.
0x18 - Coring and IF compensation (CORING) Bit 7-6 5-4 3-2 1-0 Function CTCOR CCOR VCOR CIF R/W Description Reset 1 0 1 0 3 = 6dB
R/W These bits control the coring for CTI. R/W These bits control the low level coring function for the Cb/Cr output. R/W These bits control the coring function of vertical peaking. R/W These bits control the IF compensation level. 0 = None 1 = 1.5dB 2 = 3dB
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Low Power NTSC/PAL/SECAM Video Decoder with VBI Slicer
0x19 - VBI Control Register (VBICNTL) Bit 7 Function VBI_EN R/W R/W 0 = VBI capture disabled. 1 = VBI capture enabled. 6 VBI Byte Order R/W If LEN(Reg0x03[6]) is "1" 0 = Pixel 1, 3, 5 ... on the VD[15:8] data bus, and pixel 2, 4, 6, ... on the VD[7:0] data bus. 1 = Pixel 1, 3, 5, ... on the VD[7:0] data bus, and pixel 2, 4, 6, ... on the VD[15:8] data bus. If LEN is "0" 0 = Pixel 2,1,4,3,6,5,.... on the VD[15:8] data bus. 1 = Pixel 1,2,3,4,5,6,.... on the VD[15:8] data bus. 5 VBI_ FRAM R/W 0 = Normal mode 1 = ADC output mode VD[15:8] is Y-ADC data,VD[7:0] pin is C-YADC data 4 HA_EN R/W 0 = HACTIVE output is disabled during vertical blanking period. 1 = HACTIVE output is enabled during vertical blanking period. R/W 0 = 0x80 and 0x10 code will be output as invalid data during active video line. 1 = 0x00 code will be output as invalid data during active video line. 2-0 RTSEL R/W These bits control the real time signal output from the MPOUT pin. 000 = Video loss 001 = H-lock 010 = S-lock 011 = V-lock 100 = MONO 101 = DET50 110 = FIELD 111 = RTCO ( Real Time Control ) 0 1 0 1 Description Reset 0
3
CNTL656
1
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Low Power NTSC/PAL/SECAM Video Decoder with VBI Slicer
0x1A - Analog Control II Bit 7 6 Function LLCTEST PLL_PDN R/W R/W LLC test mode R/W 0 = LLC PLL in normal operation. 1 = PLL in power down mode. Reserved YFLEN R/W Y-Ch anti-alias filter control 1 = enable 0 = disable R/W Y-Ch power saving mode 1 = enable 0 = disable R/W C-Ch anti-alias filter control 1 = enable 0 = disable R/W C-Ch power saving mode 1 = enable 0 = disable Description Reset 0 0
5-4 3
0 0
2
YSV
0
1
CFLEN
0
0
CSV
0
0x1B - Output Control II Bit 7-6 Function CK2S R/W Description Reset 0
R/W CLKX2 pin output control. CK1S[0] together with these two bits (CK1S[0], CK2S) control CLKX2 pin output selection. 000 = VCLK 001 = CLKX1 010 = CLKX2 011 = LLCK 100 = LLCK2 101 = LLCK4
5-4 3 2-0
CK1S
R/W See CK2S R/W Reserved R/W Reserved
0 0 0
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Low Power NTSC/PAL/SECAM Video Decoder with VBI Slicer
0x1C - Standard Selection (SDT) Bit 7 6-4 Function DETSTUS STDNOW R/W R R 0 = Idle Description 1 = detection in progress Reset 0 0
Current standard invoked 0 = NTSC(M) 1 = PAL (B,D,G,H,I) 2 = SECAM 3 = NTSC4.43 4 = PAL (M) 5 = PAL (CN) 6 = PAL 60 7 = Not valid
3
ATREG
R/W 1 = Disable the shadow registers. 0 = Enable VACTIVE and HDELAY shadow registers value depending on standard R/W Standard selection 0 = NTSC(M) 1 = PAL (B,D,G,H,I) 2 = SECAM 3 = NTSC4.43 4 = PAL (M) 5 = PAL (CN) 6 = PAL 60 7 = Auto detection
0
2-0
STD
7
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Low Power NTSC/PAL/SECAM Video Decoder with VBI Slicer
0x1D - Standard Recognition (SDTR) Bit 7 6 Function ATSTART PAL6_EN R/W Description Reset 0 1
R/W Writing 1 to this bit will manually initiate the auto format detection process. This bit is a self-resetting bit. R/W 1 = enable recognition of PAL60. 0 = disable recognition. R/W 1 = enable recognition of PAL (CN). 0 = disable recognition. R/W 1 = enable recognition of PAL (M). 0 = disable recognition. R/W 1 = enable recognition of NTSC 4.43. 0 = disable recognition. R/W 1 = enable recognition of SECAM. 0 = disable recognition. R/W 1 = enable recognition of PAL (B,D,G,H,I). 0 = disable recognition. R/W 1 = enable recognition of NTSC (M). 0 = disable recognition.
5
PALN_EN
1
4
PALM_EN
1
3
NT44_EN
1
2
SEC_EN
1
1
PALB_EN
1
0
NTSC_EN
1
0x1E - Reserved Bit 7-0 Function R/W R Reserved Description Reset 0
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Low Power NTSC/PAL/SECAM Video Decoder with VBI Slicer
0x1F - Test Control Register (TEST) Bit 7-0 Function TEST R/W Description Reset 0
R/W This register is reserved for testing purpose. In normal operation, only 0 should be written into this register. 1 = Analog test mode. Y and C channel portion of the device can be tested in this mode. The Y channel ADC output can be obtained from VD[15-8]. The C channel ADC output can be obtained from VD[7-0]. 2 = Clamp test mode. Clamp control YU, YUX, YD, YDX, CU, CUX, CD, and CDX are mapped to VD[3-0]. 3 = Reserved 4 = Digital test mode1. This is the CVBS test mode. The 8-bit input corresponds to VD[7-0] in the order of bit 7 to 0. 5 = Digital test mode 2. This is the Y/C test mode. Y input is defined by test mode 1. The C channel data is inputted from VD[7-0]. In this mode, only 8/10-bit output format is allowed. 6 = Reserved 7 = Reserved 8 = Reserved 9 = Sync output mode. The 6-bit Sync output corresponds to VD[5-0] in the order of bit 5 to 0. Y and Cb/Cr outputs correspond to VD[15-8] in 422 format
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Low Power NTSC/PAL/SECAM Video Decoder with VBI Slicer
0x20 - Clamping Gain (CLMPG) Bit 7-4 Function CLPEND R/W Description Reset 5
R/W These 4 bits set the end time of the clamping pulse in the increment of 8 system clocks. The clamping period is determined by this and CLPST. R/W These 4 bits set the start time of the clamping pulse in the increment of 8 system clocks. It is referenced to PCLAMP position.
3-0
CLPST
0
0x21 - Individual AGC Gain (IAGC) Bit 7-4 3-1 0 Function NMGAIN WPGAIN AGCGAIN8 R/W Description Reset 2 1 0
R/W These bits control the normal AGC loop maximum correction value. R/W Peak AGC loop gain control. R/W This bit is the MSB of the 9-bit register that controls the AGC gain when AGC loop is disabled.
0x22 - AGC Gain (AGCGAIN) Bit 7-0 Function AGCGAIN R/W Description Reset F0
R/W These bits are the lower 8 bits of the 9-bit register that controls the AGC gain when AGC loop is disabled.
0x23 - White Peak Threshold (PEAKWT) Bit 7-0 Function PEAKWT R/W Description Reset D8
R/W These bits control the white peak detection threshold. Setting `FF' can disable this function.
0x24- Clamp level (CLMPL) Bit 7 Function CLMPLD R/W Description Reset 1
R/W 0 = Clamping level is set by CLMPL. 1 = Clamping level preset at 60d. R/W These bits determine the clamping level of the Y channel.
6-0
CLMPL
3C
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Low Power NTSC/PAL/SECAM Video Decoder with VBI Slicer
0x25- Sync Amplitude (SYNCT) Bit 7 Function SYNCTD R/W Description Reset 1
R/W 0 = Reference sync amplitude is set by SYNCT. 1 = Reference sync amplitude is preset to 38h. R/W These bits determine the standard sync pulse amplitude for AGC reference.
6-0
SYNCT
38
0x26 - Sync Miss Count Register (MISSCNT) Bit 7-4 Function MISSCNT R/W Description Reset 4
R/W MISSCNT[3] controls the speed of VDLOSS detection with `0' being fast and `1' being slow. MISSCNT[2:0] control the threshold of horizontal sync miss detection per field before VDLOSS is flagged. R/W These bits determine the VCR mode Hsync detection window.
3-0
HSWIN
4
0x27 - Clamp Position Register (PCLAMP) Bit 7-0 Function PCLAMP R/W Description Reset 38
R/W These bits set the clamping position from the PLL sync edge
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Low Power NTSC/PAL/SECAM Video Decoder with VBI Slicer
0x28 - Vertical Control I (VCNTL1) Bit 7-6 Function VLCKI R/W R/W Vertical lock in time. 0 = fastest 5-4 VLCKO 3 = slowest. 0 R/W Vertical lock out time. 0 = fastest 3 = slowest. R/W This bit controls the vertical detection window. 1 = search mode. 0 = vertical count down mode. 2 DETV R/W 1 = recommended for special application only. 0 = Normal Vertical sync logic R/W Auto field generation control 0 = Off 1 = On R/W Vertical integration time control. 1 = long 0 = normal 0 Description Reset 0
3
VMODE
0
1
AFLD
0
0
VINT
0
0x29 - Vertical Control II (VCNTL2) Bit 7-5 5-0 Function BSHT VSHT R/W Description Reset 0 00
R/W Burst PLL center frequency control. R/W Vertical sync output delay control in the increment of half line length.
0x2A - Color Killer Level Control (CKILL) Bit 7-6 5-0 Function CKILMAX CKILMIN R/W Description Reset 1 28
R/W These bits control the amount of color killer hysteresis. The hysteresis amount is proportional to the value. R/W These bits control the color killer threshold. Larger value gives lower killer level.
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0x2B - Comb Filter Control (COMB) Bit 7 6-4 3-0 Function HTL HTL VTL R/W Description 0=more.
Low Power NTSC/PAL/SECAM Video Decoder with VBI Slicer
Reset 0 4 4
R/W Comb strength control. 1= less.
R/W Adaptive Comb filter threshold control 1. R/W Adaptive Comb filter threshold control 2.
0x2C - Luma Delay and H Filter Control (LDLY) Bit 7 Function CKLM R/W Description Reset 0
R/W Color Killer mode. 0 = normal 1 = fast ( for special application) R/W Luma delay fine adjustment. This 2's complement number provide -4 to +3 unit delay control. R/W 1 = Even field counter in special mode. 0 = Normal operation R/W Pre-filter selection for horizontal scaler 1** = Horizontal enhancement level control 100 = Bypass 000 = Auto selection based on Horizontal scaling ratio. 001 = Recommended for CIF size image 010 = Recommended for QCIF size image 011 = Recommended for ICON size image
6-4 3
YDLY EVCNT
3 0
2-0
HFLT
0
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Low Power NTSC/PAL/SECAM Video Decoder with VBI Slicer
0x2D - Miscellaneous Control I (MISC1) Bit 7 6 5 4 3 2 1 PALC SDET TBC_EN BYPASS SYOUT Function HPLC R/W R/W Reserved for Internal use. R/W Reserved. R/W Reserved. R/W ID detection sensitivity. A `1' is recommended. R/W 1:TBC enable in freerun clock mode 0:Disable 0 1 0 1 0 Description Reset 0
R/W It controls the standard detection and should be set to `1' in normal use. R/W 1 = Hsync output is disabled when video loss is detected 0 = Hsync output is always enabled R/W This bit advances the HACTIVE and DVALID pin output by one data clock when set.
0
HADV
0
0x2E - LOOP Control Register (LOOP) Bit 7-6 Function HPM R/W Description Reset 2 1 = Auto2 0 = Slow 2 2 = medium 3 = fast 1 2 = Fast 3 = Fastest 1
R/W Horizontal PLL acquisition time. 3 = Fast 2 = Auto1 R/W ACC time constant 0 = No ACC 1 = slow R/W Burst PLL control. 0 = Slowest 1 = Slow
5-4
ACCT
3-2
SPM
1-0
CBW
R/W Chroma low pass filter bandwidth control. Refer to filter curves.
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Low Power NTSC/PAL/SECAM Video Decoder with VBI Slicer
0x2F - Miscellaneous Control II (MISC2) Bit 7 Function NKILL R/W Description Reset 1
R/W 1 = Enable noisy signal color killer function in NTSC mode. 0 = Disabled. R/W 1 = Enable automatic noisy color killer function in PAL mode. 0 = Disabled. R/W 1 = Enable automatic noisy color killer function in SECAM mode. 0 = Disabled. R/W 0 = Normal output 1 = special output mode. R/W 1 = Force decoder output value determined by CCS. 0 = Disabled. R/W 1 = Enable pre-determined output value indicated by CCS when video loss is detected. 0 = Disabled.
6
PKILL
1
5
SKILL
1
4
CBAL
0
3
FCS
0
2
LCS
0
1
CCS
R/W When FCS is set high or video loss condition is detected when LCS is set high, one of two colors display can be selected. 1 = Blue color. 0 = Black.
0
0
BST
R/W 1 = Enable blue stretch. 0 = Disabled.
0
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Low Power NTSC/PAL/SECAM Video Decoder with VBI Slicer
0x30 - Macrovision Detection (MVSN) Bit 7 6 5 4 3 2 SF PF FF KF CSBAD MCVSN Function R/W R R R R R R Set when Macrovision color stripe detection may be un-reliable 1 = Macrovision AGC pulse detected. 0 = Not detected. 1 CSTRIPE R 1 = Macrovision color stripe protection burst detected. 0 = Not detected. 0 CTYPE R This bit is valid only when color stripe protection is detected, i.e. Cstripe=1. 1 = Type 2 color stripe protection 0 = Type 3 color stripe protection 0 0 Description Reset 0 0 0 0 0 0
0x31 - Chip STATUS II (STATUS2) Bit 7 6 5 4 3 2 1 0 Function VCR WKAIR WKAIR1 VSTD NINTL WSSDET EDSDET CCDET R/W R R R R R R R R VCR signal indicator Weak signal indicator 2. weak signal indicator controlled by WKTH. 1 = 525/625 line signal 1 = Non-interlaced signal 0 = Non-standard signal 0 = interlaced signal Description Reset 0 0 0 0 0 0 0 0
1 = WSS data detected. 0 = Not detected. 1 = EDS data detected. 0 = Not detected. 1 = CC data detected. 0 = Not detected.
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Low Power NTSC/PAL/SECAM Video Decoder with VBI Slicer
0x32 - H monitor (HFREF) Bit 7-0 Function HFREF R/W R Description Horizontal line frequency indicator Reset X
0x33 - CLAMP MODE (CLMD) Bit 7-6 Function FRM R/W R/W Free run mode control 0 = Auto 5-4 YNR 2 = default to 60Hz 3 = default to 50Hz 0 2 = small 3 = medium 1 2 = Pedestal 3 = N/A 1 2 = high R/W Y HF noise reduction 0 = None 1 = smallest R/W Clamping mode control. 0 = Sync top 1 = Auto R/W Slice level control 0 = low 1 = medium Description Reset 0
3-2
CLMD
1-0
PSP
0x34 - ID Detection Control (IDCNTL) Bit 7-6 Function IDX R/W Description Reset 0
R/W These two bits indicate which of the four lower 6-bit registers is currently be controlled. The write sequence is a two steps process unless the same register is written. A write of {ID,000000} selects one of the four registers to be written. A subsequent write will actually write into the register.
5-0
NSEN / SSEN / R/W IDX = 0 controls the NTSC ID detection sensitivity (NSEN). PSEN / WKTH IDX = 1 controls the SECAM ID detection sensitivity (SSEN). IDX = 2 controls the PAL ID detection sensitivity (PSEN). IDX = 3 controls the weak signal detection sensitivity (WKTH).
1A / 20 / 1C / 11
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Low Power NTSC/PAL/SECAM Video Decoder with VBI Slicer
0x35 - Clamp Control I (CLCNTL1) Bit 7 6 Function CTEST YCLEN R/W Description Reset 0 0
R/W Clamping control for debugging use. R/W 1 = Y channel clamp disabled 0 = Enabled. R/W 1 = C channel clamp disabled 0 = Enabled. R/W Reserved R/W 1 = Test. 0 = Normal operation. R/W Sync filter control R/W Clamping current control 1. R/W Clamping current control 2.
5
CCLEN
0
4 3
VCLEN GTEST
0 0
2 1 0
VLPF CKLY CKLC
0 0 0
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Low Power NTSC/PAL/SECAM Video Decoder with VBI Slicer
0x4F - WSS3 Bit 7-0 Function WSS[19:14] R/W R Description CGMS(WSS525) Bit19-14 in 525 line video system. These bits show CRC 6bits in CGMS(WSS525). These bits are only valid in 525 line video system. Reset X
0x50 - FILLDATA Bit 7-0 Function FILLDATA R/W Description Reset A0
R/W Filled data as dummy data in ANC Dword data packet.
0x51 - SDID Bit 7 Function NODAEN R/W Description Reset 0
th R/W 1:Bit7 in 4 byte of EAV/SAV code will be 0 when sync lost(No Video input.)
0: Bit7 in 4 byte of EAV/SAV is always VIPCFG register bit. 6 SYRM R/W 1: Minimum value in raw VBI will be 0x10 for Sync Level remove. 0:none. R/W Secondary data ID in ANC data packet type 2 0
th
5-0
SDID
22
0x52 - DID Bit 7 6 Function ANCEN TOUTHA R/W Description 0:disable. Reset 0 0
R/W ANC data packet output control. 1 = enable. R/W 1: reserved 0:should be "0" in normal mode.
th R/W Set up Bit7 in 4 byte of EAV/SAV code.
5 4-0
VIPCFG DID
1 11
R/W Data ID in ANC data packet type 2.
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Low Power NTSC/PAL/SECAM Video Decoder with VBI Slicer
0x53 - WSS1 Bit 7 Function CRCERR R/W R Description This bit is only valid in 525 line video system. 1: CGMS(WSS525) CRC error detected in current field. 0:No CRC error 6 WSSFLD R 0:current WSS data is received in Odd field. 1: current WSS data is received in Even field. 5-0 WSS[13:8] R CGMS(WSS525) Bit13-8 in 525 line video system. Wide Screen Signaling Bit13-8 in 625 line video system. X X Reset X
0x54 - WSS2 Bit 7-0 Function WSS[7:8] R/W R Description CGMS(WSS525) Bit7-0 in 525 line video system. Wide Screen Signaling Bit7-0 in 625 line video system. 0x55 - VVBI Bit 7 Function HA656 R/W Description Reset 0 Reset X
R/W 1:HACTIVE signal is same as DVALID signal in H Down scaled video output. 0:HACTIVE signal is always HACTIVE register's length.
6
EAVSWAP
R/W 1:EAV-SAV code is swapped. 0:EAV-SAV code is not swapped(standard 656 output mode) R/W 1:enable 84 Hamming Code checking BI Slicer.0: disable. R/W 1:Number of Even Field Video output line is (the number of Odd field Video output line - 1). This bit is required for ITU-R BT.656 output for 525-line system standard. 0: Number of Even Field Video output line is same as the number of Odd field Video output line.
0
5 4
HAMM84 NTSC656
0 0
3-0
VVBI
R/W The number of raw VBI data output line counted from top video active line signal timing.
0
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Low Power NTSC/PAL/SECAM Video Decoder with VBI Slicer
0x56~6A LCTL6~LCTL26 Bit 7-4 Function LCTLn R/W Description Reset 0
R/W Set up VBI Data Slicer Decoding mode on Line-n. Value is set up by upper bit7-4 meaning for Line-n in odd field. R/W Value is set up by below bit3-0 meaning for Line-n in even field. 0h:disable decoding. 1h:Teletext-B 2h:Teletext-C 3h:Teletext-D 4h:Closed Captioning and Extended Data service. (EIA-608 type). 5h:CGMS (WSS525) in 525 line system or WSS625 in 625 line system. 6h:VITC 7h:Gemstar 1x 8h:Gemstar 2x 9h:VPS (Line16 VPS type) Ah: Teletext-A Bh~Fh: reserved
3-0
0
0x6B - HSGEGIN Bit 7-0 Function HSBEGIN R/W R/W HSYNC Start position. Description Reset 2C
0x6C - HSEND Bit 7-0 Function HSEND R/W R/W HSYNC End position. Description Reset 60
0x6D - OVSDLY Bit 7-0 Function OVSDLY R/W R/W VSYNC Start position. Description Reset 00
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0x6E - OVSEND Bit 7 Function HSPIN R/W Description
Low Power NTSC/PAL/SECAM Video Decoder with VBI Slicer
Reset 0
R/W 1:HSYNC output is HACTIVE. 0:HSYNC output is HSYNC. R/W FIELD output delay. 0h:0H line delay FIELD output. (601 mode only) 1h-6h: 1-H to 6-H line delay FIELD output. 7h:FIELD output is synchronized to the leading edge of VACTIVE.
6-4
OFDLY
2
3
VSMODE
R/W 1:VSYNC output is HACTIVE-VSYNC mode. 0:VSYNC output is HSYNC-VSYNC mode. R/W Line delay for VSYNC end position.
0
2-0
OVSEND
0
0x6F - VBIDELAY Bit 7 Function PDNSVBI R/W Description Reset 0
R/W 1:VBI data slicer enable 0: VBI data slicer is in reset and power-down mode R/W R/W Raw VBI output delay
6 5-0
Reserved VBIDELAY
0 24
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Low Power NTSC/PAL/SECAM Video Decoder with VBI Slicer
Pin Diagram
44 PIN LQFP
XTO XTI VSSE VD[0]/SIAD0 VD[1]
44 43 42 41 40 39 38 VDDE SCLK SDAT PDN RSTB TMODE AVD YMUX3 YMUX2 YGND YMUX1
37 36 35 34 33 32 31 30
VSS VD[2] VD[3] VD[4] VD[5] VD[6]
1 2 3 4 5 6 7 8 9 10 11
TW9910
29 28 27 26 25 24 23 20 21 22
VD[7] VD[8] VD[9] VD[10] VDD VD[11] VD[12] VD[13] VD[14] VD[15] VDDE
12 13 14 15 16 17 18 19
YMUX0 AVS
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CIN0 AVD AVS VSS VS HS MPOUT CLKX2
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Low Power NTSC/PAL/SECAM Video Decoder with VBI Slicer
Pin Diagram
48 PIN QFN
XTO XTI VSSE VD[0]/SIAD0 VD[1] NC VSS 48 47 46 45
44 43 42 41 40 39 38 37
VD[2] VD[3] VD[4] VD[5] VD[6]
VDDE SCLK SDAT PDN RSTB TMODE NC AVD YMUX3 YMUX2 YGND YMUX1
1 2 3 4 5 6 7 8 9 10 11 12 13 14
36 35 34 33 32 31 30 29 28 27 26 25 15 16 17 18 19 20 21 22 23 24
TW9910
VD[7] VD[8] VD[9] VD[10] VDD NC VD[11] VD[12] VD[13] VD[14] VD[15] VDDE
YMUX0 AVS CIN0 AVD AVS NC VSS
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Pin Description
Pin# LQFP QFN I/O Pin Name Description
Low Power NTSC/PAL/SECAM Video Decoder with VBI Slicer
Analog video signals 12 11 9 8 10 14 13 12 10 9 11 15 I I I I I MUX0 MUX1 MUX2 MUX3 YGND CIN0 Analog CVBS or Y input. Connect unused input to AGND through 0.1uF capacitor. Analog CVBS or Y input. Connect unused input to AGND through 0.1uF capacitor. Analog CVBS or Y input. Connect unused input to AGND through 0.1uF capacitor. Analog CVBS or Y input. Connect unused input to AGND through 0.1uF capacitor. Analog Differential input for Y-ADC. Analog chroma input. Connect unused input to AGND through 0.1uF capacitor.
Clock Signals 43 44 47 48 I O XTI XTO Clock input. A 27Mhz fundamental (or 3rd overtone) crystal or a single-ended oscillator can be connected. Clock output. For connecting a crystal.
Host Interface 2 3 2 3 I I/O SCLK SDAT The MPU Serial interface Clock Line. The MPU Serial interface Data Line.
General signals 5 4 6 5 4 6 7,18, 31,43 Video output Signals 19 18 21 20 24,25, 26,27, 28,30, 31,32 33,34, 35,36, 37,38, 40 41 21 20 23 22 26,27, 28,29, 30,33, 34,35 36,37, 38,39, 40,41, 44 45 O O O O O HS VS CLK2 MPOUT VD[15:8] Horizontal sync and multi-purpose output pin. See register for control information. Vertical Sync and multi-purpose output. See register for control information. Data Clock output. See register for control information. Multi-purpose output pin. The output function can be selected by RTSEL of register 0x19 Digitized Video Data Outputs of Y/YCbCr. VD[8] is the LSB and VD[15] is the MSB. I I I RSTB PDN TMODE NC Reset input. Low active. Power down control pin. It is high active. Test pin. It should be low for normal operation. NC pin.
I/O
VD[7:1]
Digitized video data output of CbCr. VD[7] is the MSB.
I/O
VD[0]/ SIAD0
LSB of digitized video data output of CbCr. SIAD0 : The MPU interface address select pin 0. A pullup or pulldown resister is needed for select one of the two addresses that chip will respond.
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Low Power NTSC/PAL/SECAM Video Decoder with VBI Slicer
Power and Ground Pins
Pin# 29 17,39 1,23 22,42 7,15 13,16 32 19,42 1,25 24,46 8,16 14,17 I/O I I I I I I Pin Name VDD VSS VDDE VSSE AVD AVS 1.8V digital core power. 1.8V digital core return 3.3V digital I/O power. 3.3V digital I/O return 1.8V analog ADC supply 1.8V analog ADC return Description
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Low Power NTSC/PAL/SECAM Video Decoder with VBI Slicer
Parametric Information
AC/DC Electrical Parameters
Table 21. Absolute Maximum Ratings
Parameter AVD (measured to AVS) V DD (measured to VSS) V DDE (measured to VSSE) Voltage on any signal pin (See the note below) Analog Input Voltage Storage Temperature Junction Temperature Vapor Phase Soldering(15 Seconds) Symbol VDDAM VDDM VDDEM TS TJ T VSOL Min Typ Max 2.0 2.0 3.6 VDDEM + 0.5 VDDAM + 0.5 +150 +125 +220 Units V V V V V C C C
VSSE - 0.5 AVS - 0.5 -65 -
NOTE: Stresses above those listed may cause permanent damage to the device. This is a stress rating only, and functional operation at these or any other conditions above those listed in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
This device employs high-impedance CMOS devices on all signal pins. It must be handled as an ESDsensitive device. Voltage on any signal pin that exceeds the power supply voltage by more than +0.5 V or drops below ground by more than 0.5 V can induce destructive latch-up. Table 22. characteristics
Parameter Supply Power Supply -- IO Power Supply -- Analog Power Supply -- Digital Maximum |V DD - AVDD| MUX0, MUX1 , MUX2 and MUX3 Input Range (AC coupling required) CIN0 Amplitude Range (AC coupling required) Ambient Operating Temperature Analog Supply current : CVBS S-video Digital I/O Supply current Digital Core Supply Current Digital Inputs Input High Voltage (TTL) Input Low Voltage (TTL) Input High Voltage (XTI) Input Low Voltage (XTI) Symbol Min Typ Max Units
VDDE VDDA VDD
3.15 1.6 1.6 0.5 0.5 0 -
3.3 1.8 1.8 1.00 1.00 12 20 9 24
3.6 2.0 2.0 0.3 1.40 1.40 +70 -
V V V V V V C mA mA mA mA
TA Iaa Idde Idd
V IH V IL V IH V IL 62
2.0 2.0 VSS -0.5
-
V DDE + 0.5 0.8 V DDE + 0.5 1.0
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TECHWELL, INC.
TW9910
Input High Current (V IN =V DD ) Input Low Current (V IN =VSS) Input Capacitance (f=1 MHz, V IN =2.4 V) I IH I IL C IN -
Low Power NTSC/PAL/SECAM Video Decoder with VBI Slicer
5
10 -10 -
A A pF
Parameter Digital Outputs Output High Voltage (I OH = -2 mA) Output Low Voltage (I OL = 2 mA) 3-State Current Output Capacitance Analog Input Analog Pin Input voltage Analog Pin Input Capacitance ADCs ADC resolution ADC integral Non-linearity ADC differential non-linearity ADC clock rate Video bandwidth (-3db) Horizontal PLL Line frequency (50Hz) Line frequency (60Hz) static deviation Subcarrier PLL subcarrier frequency (NTSC-M) subcarrier frequency (PAL-BDGHI) subcarrier frequency (PAL-M) subcarrier frequency (PAL-N) lock in range Crystal spec nominal frequency (fundamental) deviation Temperature range load capacitance series resistor Oscillator Input nominal frequency deviation duty cycle
Symbol
Min
Typ
Max
Units
V OH V OL I OZ CO
2.4 -
0.2 5
V DDE 0.4 10 -
V V A pF
Vi CA
-
1 7
-
Vpp pF
ADCR AINL ADNL fADC BW
24 -
10 1 1 27 10
30 -
bits LSB LSB MHz MHz
fLN fLN fH
-
15.625 15.734 -
6.2
KHz KHz %
fSC fSC fSC fSC fH
450
3579545 4433619 3575612 3582056 -
-
Hz Hz Hz Hz Hz
Ta CL RS 0 -
27 20 80
50 70 -
MHz ppm C pF Ohm
o
63
27 -
50 55
MHz ppm %
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Low Power NTSC/PAL/SECAM Video Decoder with VBI Slicer
Parameter Output CLK CLKX1 CLKX2 CLKX1 Duty Cycle CLKX2 Duty Cycle CLKX2 to CLKX1 Delay CLKX1 to Data Delay CLKX2 to Data Delay CLKX1 (Falling Edge) to VCLK (Rising Edge) CLKX2 (Falling Edge) to VCLK (Rising Edge) Output Video Data 8-bit Mode (1) Data to VCLK (Rising Edge) Delay VCLK (Rising Edge) to Data Delay 16-bit Mode (1) Data to VCLK (Rising Edge) Delay VCLK (Rising Edge) to Data Delay
Symbol
Min
Typ
Max
Units
4 5 6 41 42
12 24 -
13.5 27 5 5 0 0
15 30 55 55 2 -
MHz MHz % % ns ns ns ns ns
7b 8b 7a 8a
-
18 18 37 37
-
ns ns ns ns
Clock Timing Diagram
1 XT 3 2
(8-bit output mode)
VCLK
Data 6 CLKX2 4 7b 8b 42
(16-bit output mode)
41 CLKX1
VCLK Data
5
7a
8a
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Mechanical Data 44 Pin LQFP A A1 A2 E E1 E2
Low Power NTSC/PAL/SECAM Video Decoder with VBI Slicer
TW9910
D2 D1 D Top View
L1 b e
c
2 R1 R2 Gage Plane
0.25mm
1
S
3
L
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Low Power NTSC/PAL/SECAM Video Decoder with VBI Slicer
SYMBOL
MILLIMETER MIN NOM ----1.40 9.00 BSC. 7.00 BSC. 9.00 BSC. 7.00 BSC. 0.08 0.08 0 0 11 11 0.09 0.45 0.20 0.17 ----3.5 --12 12 --0.60 1.00 REF --0.20 0.50 BSC. 5.00 5.00 --0.27 0.008 0.007 0.20 --7 --13 13 0.20 0.75 MAX 1.60 0.15 1.45 MIN --0.002 0.053
INCH NOM ----0.055 MAX 0.063 0.006 0.057
A A1 A2 D D1 E E1 R2 R1 1 2 3 c L L1 S b e D2 E2
--0.05 1.35
0.354 BSC. 0.276 BSC. 0.354 BSC. 0.276 BSC. 0.003 0.003 0 0 11 11 0.004 0.018 ----3.5 --12 12 --0.024 0.039 REF --0.008 0.197 0.197 --0.011 0.008 --7 --13 13 0.008 0.030
0.020 BSC.
NOTES: 1. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25mm per side. D1 and E1 are maximum plastic body size dimensions including mold mismatch. 2. Dimension b does not include dambar protrusion. Allowable dambar protrusion shall not cause the lead width to exceed the maximum b dimension by more than 0.08mm. Dambar can not be located on the lower radius or the foot. Minimum space between protrusion and a adjacent lead is 0.07mm for 0.4mm and 0.5mm pitch packages.
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Low Power NTSC/PAL/SECAM Video Decoder with VBI Slicer
48 PIN QFN
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Low Power NTSC/PAL/SECAM Video Decoder with VBI Slicer
SYMBOL
MILLIMETER MIN NOM --0.01 0.65 0.2 REF. 0.20 0.25 7.00 BSC. 6.75 BSC. 5.00 5.20 7.00 BSC. 6.75 BSC. 5.00 0.30 0 0.09 5.20 0.40 0.50 BSC. ----0.10 0.10 12 --0 0.004 5.40 0.50 0.197 0.012 5.40 0.197 0.32 0.008 MAX 0.90 0.05 0.70 MIN --0.00 ---
INCH NOM --0.0004
MAX 0.035 0.002 0.028 0.013
A A1 A2 A3 b D D1 D2 E E1 E2 L e 1 R aaa bbb
--0.00 ---
0.026 0.008 REF. 0.010 0.276 BSC. 0.266 BSC. 0.205 0.276 BSC. 0.266 BSC. 0.205 0.016 0.020 BSC. ----0.004 0.004 0.002
0.213
0.213 0.020 12 ---
TOLERANCES OF FORM AND POSITION
ccc 0.05 * CONTROLLING DIMENSION : MM
NOTES: 1. All dimensions are in millimeters. 2. Dimension applies to plated terminal and is measured between 0.20 and 0.25mm from terminal tip. 3. Package warpage MAX 0.08mm. 4. Package corners unless otherwise specified are R0.175 0.025mm
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TW9910 Application Schematics
Low Power NTSC/PAL/SECAM Video Decoder with VBI Slicer
3.3/5V
4.7k
CVBS1
75 ohm 0.1uF
MUX0
SCL
4.7k
MUX1
75 ohm
SDA
S-Video
0.1uF
CIN0
75 ohm 0.1uF
VD1-15 3.3V
10k
** option
VD0 / SIAD0
Video Timing
TW9910
TMODE PDN
RST# DVDD
0.1uF
1.8V 3.3V GND Filtered 1.8V
0.1uF
*
C1, 220pf
L1, 3.3uH
DGND AVDD XTI AGND XTO
22pf
1Mohm 22pf
27M
AGND Note: All unused digital input pins should be tied to DGND. * For 3rd overtone crystal Typical TW9910 External Circuitry DGND
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PCB Layout Considerations
Low Power NTSC/PAL/SECAM Video Decoder with VBI Slicer
The PCB layout should be done to minimize the power and ground noise on the TW9910. This is done by good power de-coupling with minimum lead length on the de-coupling capacitors; wellfiltered and regulated analog power input shielding and ground plane isolation. The ground plane should cover most of the PCB area with separated digital and analog ground planes surrounding the chip. These two planes should be at the same electrical potential and connected together under TW9910. The following figure shows a ground plane layout example.
DGND TW9910
AGND
To minimize crosstalk, the digital signals of TW9910 should be separated from the analog circuitry. Moreover, the digital signals should not cross over the analog power and ground plane. Parallel running of digital lines for long distance should also be avoided. For QFN Package, the Exposed die pad (Ground bond) can be either floating or soldered to PCB Ground to enhance thermal performance.
QFN
E x p o s e d D ie P a d
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Low Power NTSC/PAL/SECAM Video Decoder with VBI Slicer
Copyright Notice
This manual is copyrighted by Techwell, Inc. Do not reproduce, transform to any other format, or send/transmit any part of this documentation without the express written permission of Techwell, Inc.
Disclaimer
This document provides technical information for the user. Techwell, Inc. reserves the right to modify the information in this document as necessary. The customer should make sure that they have the most recent data sheet version. Techwell, Inc. holds no responsibility for any errors that may appear in this document. Customers should take appropriate action to ensure their use of the products does not infringe upon any patents. Techwell, Inc. respects valid patent rights of third parties and does not infringe upon or assist others to infringe upon such rights.
Life Support Policy
Techwell, Inc. products are not authorized for use as critical components in life support devices or systems.
Datasheet revision history Date
12/14/2005 12/27/2005 01/24/2006 02/20/2006 03/08/2006 09/21/2006 First draft. Add MPOUT pin description. Change Oscillator Input deviation +/25 to +/- 50 Add LQFP. Pg61, Fix pin number, LQFP pin17 to pin16. Pg27 Reg. Table 0x1E. Pg28 Reg. Table 0x4F. Pg62, change symbols. AVD, AVS. Pg27. Reg 0x16, reset:00. P70, add exposed die pad info.
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