View APL531712BI-TRG_4565667.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

APL5317
Selectable Adjustable/Fixed Low Dropout 300mA Linear Regulator
Features
* * * *
Wide Operating Voltage: 2.8~6V Low Dropout Voltage: 230mV(Typical) @ 300mA Guaranteed 300mA Output Current Two Modes for Setting Output Voltage - Fixed Output Voltage: 1~5V - Adjustable Output Voltage: 0.8~5.5V
General Description
The APL5317 is a low dropout linear regulator which only needs a single input voltage supply from 2.8 to 6V, and it can deliver current up to 300mA to a set output voltage. It can work with low ESR ceramic capacitors that make it ideal for using in the battery-powered applications, such as notebook computers and cellular phones. Its typical dropout voltage is only 230mV at 300mA loading. The APL5317 provides two output voltage operation modes, the fixed output voltage mode and the adjustable output voltage, controlled by the SET pin for setting the output voltage. The fixed output voltage mode sets the output to a preset voltage (only 1.2V available now) in the chip by connecting SET pin to the ground, and the adjustable output voltage mode needs two resistors as a voltage divider connected to SET pin to define the output. The current-limit with current foldback and thermal shutdown functions protect the device against current over-loads and over temperature. The APL5317 is available in a SOT23-5 package.
* * * * * *
Current-Limit Protection with Foldback Current Internal Soft-Start Over-Temperature Protection Stable with Low ESR Ceramic Capacitor SOT-23-5 Package Lead Free and Green Devices Available (RoHS Compliant)
Applications
* * *
Cellular Phones
Pin Configuration
VIN 1 5 VOUT 4 SET SOT-23-5 GND 2 SHDN 3
Portable and Battery-Powered Equipment Notebook and Personal Computers
Simplified Application Circuit
1. Fixed Output Voltage Mode
VIN APL5317 1 VIN VOUT SET 5 4 COUT VOUT
2. Adjustable Output Voltage Mode
APL5317 VIN 1 VIN VOUT SET GND 2 5 4 COUT VOUT
CIN
3 SHDN GND 2
CIN
3 SHDN
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. Copyright (c) ANPEC Electronics Corp. Rev. A.4 - Mar., 2009 1 www.anpec.com.tw
APL5317
Ordering and Marking Information
APL5317 Assembly Material Handling Code Temperature Range Package Code Voltage Code APL5317 B: APL5317-12 B: 375X 375X Package Code B : SOT-23-5 Operating Junction Temperature Range I : -40 to 85 oC Handling Code TR : Tape & Reel Voltage Code (Note 1) 12 : 1.2V Assembly Material G: Halogen and Lead Free Device X - Date code X - Date code
Note : ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020C for MSL classification at lead-free peak reflow temperature. ANPEC defines "Green" to mean lead-free (RoHS compliant) and halogen free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by weight). Note 1: For other voltage versions, please contact ANPEC for details. Note 2: Because APL5317 and APL5317-12 are identical, the marking of APL5317 is same as APL5317-12.
Absolute Maximum Ratings
Symbol VIN VSHDN PD TJ TSTG TSDR VIN Supply Voltage (VIN to GND) SHDN Input Voltage (SHDN to GND) Power Dissipation Junction Temperature Storage Temperature
(Note 3)
Rating -0.3 ~ 6.5 -0.3 ~ 6.5 Internally Limited -40 ~ 150 -65 ~ 150 260 Unit V V W
o o o
Parameter
C
C C
Maximum Lead Soldering Temperature, 10 Seconds
Note 3: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Thermal Characteristics
Symbol JA JC Parameter Thermal Resistance-Junction to Ambient Thermal Resistance-Junction to Case SOT-23-5
(Note 4)
Typical Value SOT-23-5 240 130
Unit
o
C/W C/W
o
Note 4 : JA is measured with the component mounted on a high effective thermal conductivity test board in free air.
Recommended Operating Conditions
Symbol VIN VOUT IOUT VIN Supply Voltage Output Voltage VOUT Output Current Parameter Range 2.8 ~ 6 0.8 ~ 5.5 0 ~ 300 Unit V V mA
Copyright (c) ANPEC Electronics Corp. Rev. A.4 - Mar., 2009
2
www.anpec.com.tw
APL5317
Recommended Operating Conditions (Cont.)
Symbol CIN COUT TJ Input Capacitor Output Capacitor Junction Temperature Parameter Range 0.22 ~ 100 1.5 ~ 33 -40 ~ 125 Unit F F
o
C
Electrical Characteristics
Unless otherwise specified, these specifications apply over VIN = VOUT+1V (min VIN=2.8V), IOUT=0~300mA, CIN = 1F, COUT = 2.2F, TA = -40 to 85oC. Typical values are at TA = 25oC.
Symbol VIN VOUT IQ VREF Parameter Input Voltage Output Voltage Range Quiescent Current Reference Voltage IOUT =10mA ~300mA Measured on SET, VIN=VOUT+1V(min VIN=2.8V), IOUT=10mA TA=25X C, VIN=VOUT+1V(min VIN=2.8V), IOUT=10mA TA=-40X ~ 85X C C, VIN=VOUT+1V(min VIN=2.8V), IOUT=0~300mA VOUT = 2.5V, IOUT = 300mA VOUT = 3.3V, IOUT = 300mA Power Supply Ripple Rejection Ratio Noise Current-Limit Foldback Current SHDN Input Voltage High SHDN Input Voltage Low Shutdown VIN Supply Current SHDN Pull Low Resistance VOUT Discharge MOSFET RDS(ON) Over Temperature Threshold Over Temperature Hysteresis SET Input Threshold for Fixed/Adjustable Output Voltage Mode SET Input Bias Current TSS Soft-Start Interval VSET=0.8V SHDN = Low SHDN = Low, VIN = 6V VOUT = 0V f = 10kHz, IOUT = 300mA f = 80Hz to 100kHz, IOUT = 300mA Test Conditions Min. 2.8 0.8 APL5317 Typ. 135 0.8 Max. 6 5.5 160 V V A V Unit
Output Voltage Accuracy
-1
-
+1
%
Output Voltage Accuracy
-2 450 1.6 -100 -
230 170 45 160 600 80 0.1 3 60 160 40 100 60
+2 360 300 0.4 1 100 -
%
VDROP PSRR
Dropout Voltage
mV dB VRMS mA mA V A M X C X C mV nA s
ILIMIT ISHORT
Copyright (c) ANPEC Electronics Corp. Rev. A.4 - Mar., 2009
3
www.anpec.com.tw
APL5317
Typical Operating Characteristics
Quiescent Current vs. Supply Voltage
160 140 Quiescent Current, IQ (A) 120 100 80 60 40 20 0 0 1 2 3 4 5 6 7 Supply Voltage, VIN (V) IOUT= 0mV
Quiescent Current vs. Junction Temperature
138 136 Quiescent Current, IQ (A) 134 132 130 128 126 -50 -25 0 25 50 75 100 125
Junction Temperature, T J (X C)
Quiescent Current vs. Output Current
180 160 Quiescent Current, IQ (A) 140 VIN=5.5V
PSRR (dB) 0 -10 -20
PSRR vs. Frequency
VIN=3.3V, VOUT=1.2V CIN=1F, COUT=2.2F IOUT=300mA
120 100 80 60 0 50 100
-30 -40 -50 -60
VIN=4.5V
150
200
250
300
1000
10000
100000
1000000
Output Current, I OUT (mA)
Frequency (Hz)
Dropout Voltage vs. Output Current
300 VOUT=2.5V Dropout Voltage, VDROP (mV) 250 200 150 TJ=25X C TJ=75X C TJ=125X C
Dropout Voltage vs. Output Current
250 VOUT=3.3V Dropout Voltage, VDROP (mV) 200 TJ=125X C TJ=25X C TJ=75X C
150
100 TJ=0X C TJ=-50X C
100 TJ=-50X C 50
TJ=0X C
50
0 0 100 200 Output Current, I OUT (mA) 300
0 0 100 200 Output Current, IOUT (mA) 300
Copyright (c) ANPEC Electronics Corp. Rev. A.4 - Mar., 2009
4
www.anpec.com.tw
APL5317
Typical Operating Characteristics (Cont.)
Loop Gain vs. Frequency
50 40 30 20 Loop Gain (dB) 10 0 -10 -20 -30 -40 1000 10000 100000 1000000 Frequency (Hz) IOUT=300mA
40 20 0 1000 10000 100000 Frequency (Hz) 1000000 IOUT=100mA 160
Phase vs. Frequency
140 120 Phase (degree) 100 80 60 VIN=3.3V, VOUT=1.2V, CIN=1F, C OUT=2.2F IOUT=300mA
VIN=3.3V, VOUT=1.2V, CIN=1F, COUT=2.2F IOUT=100mA
Current Limit vs. Junction Temperature
650 VIN=5V
Current Limit, ILIMIT (mA)
600
550
500
450 -50 -25 0 25 50 75 Junction Temperature, TJ (X C) 100 125
Copyright (c) ANPEC Electronics Corp. Rev. A.4 - Mar., 2009
5
www.anpec.com.tw
APL5317
Operating Waveforms
Load Transient
VIN=3.3V, CIN=1F, COUT=2.2F, TR=1s
Line Transient
CIN=1F, COUT=2.2F, TR=10s, IOUT=10mA
V OUT
V IN
V OUT
IOUT
CH1 : VOUT, 50mV/div, AC CH2 : IOUT, 100mA/div, DC Time : 100s/div
CH1 : VIN, 1V/div, DC CH2 : VOUT, 20mV/div, AC Time : 100s/div
Enable
Shutdown
V OUT
V OUT
V SHDN
V SHDN
I OUT
I OUT
CH1 : VOUT, 500mV/div CH2 : VSHDN, 5V/div CH3 : IOUT, 200mA/div Time : 50s/div
CH1 : VOUT, 500mV/Div CH2 : VSHDN, 5V/Div CH3 : IOUT, 200mA/Div DC Time : 10s/Div
Copyright (c) ANPEC Electronics Corp. Rev. A.4 - Mar., 2009
6
www.anpec.com.tw
APL5317
Operating Waveforms (Cont.)
Power on
Power off
V IN
V IN
V OUT
V OUT
I OUT
I OUT
CH1 : VIN, 2V/div CH2 : VOUT, 500mV/div CH3 : IOUT, 100mA/div Time : 200s/Div
CH1 : VIN, 2V/div CH2 : VOUT,, 500mV/div, CH3 : IOUT, 100mA/div Time : 50ms/Div
Pin Description
PIN NO. 1 2 3 4 5 NAME VIN GND SHDN SET VOUT Voltage supply input pin Ground pin Shutdown control pin, logic high: enable; logic low: shutdown Connect this pin to the ground for fixed output voltage operation. Connect this pin to an external resistor divider for adjustable output voltage mode operation. Regulator output pin FUNCTION
Copyright (c) ANPEC Electronics Corp. Rev. A.4 - Mar., 2009
7
www.anpec.com.tw
APL5317
Block Diagram
SHDN
Shutdown Logic Thermal Shutdown + Foldback Current Limit
VIN
VOUT 3M Low SET High + GND 0.8V 100mV
Typical Application Circuits
1. Fixed Output Voltage Mode
VIN
APL5317 1 3 VIN SHDN GND 2 VOUT SET 5 4
VOUT
CIN 1F
COUT 2.2F
Enable
Shutdown
2.2F/GRM155R60J225M Murata
Copyright (c) ANPEC Electronics Corp. Rev. A.4 - Mar., 2009
8
www.anpec.com.tw
APL5317
Typical Application Circuits (Cont.)
2. Adjustable Output Voltage Mode
APL5317 1 3 VIN SHDN GND 2 Enable R2 VOUT SET 5 4 R1
VIN
VOUT
CIN 1F
COUT 2.2F
Shutdown
R1 VOUT = 0.8 1 + R2
Copyright (c) ANPEC Electronics Corp. Rev. A.4 - Mar., 2009
9
www.anpec.com.tw
APL5317
Function Description
Internal Soft-Start An internal soft-start function controls rising rate of the output voltage to limit the surge current at start-up. The typical soft-start interval is about 80s. Output Voltage Regulation The APL5317 can work in either fixed or adjustable mode by connecting the SET to GND or a resistor-divider which receives the feedback voltage of the regulator. The output voltage set by the resistor-divider is determined by:
R1 VOUT = 0.8 1 + R2
Under-Voltage Lock Out (UVLO) The APL5317 monitors the input voltage to prevent wrong logic control. The UVLO function initiates a soft-start process after input voltage exceeds its rising UVLO threshold during power on. The UVLO function also shuts off the output when the input voltage falls below its falling threshold. Typical UVLO hysteresis voltage is 0.8V. Shutdown Control The APL5317 has an active-low shutdown function. Force SHDN high (>1.6V) enables the VOUT; force SHDN low (<0.4V) disables the VOUT. SHDN is internally pulled low by a resistor (3M typical). If SHDN is not used, it will connect to VIN for normal operation.
Where R1 is connected from VOUT to SET with Kelvin sensing and R2 is connected from SET to GND. The recommended value of R2 is in the range of 100 to 100k. An error amplifier works with a temperature compensated 0.8V reference and an output PMOS regulates the output to the presetting voltage. The error amplifier is designed with high bandwidth and DC gain provides very fast transient response and less load regulation. It compares the reference with the feedback voltage and amplifies the difference to drive the output PMOS which provides load current from VIN to VOUT. Thermal Shutdown A thermal shutdown circuit limits the junction temperature of APL5317. When the junction temperature exceeds +160C, a thermal sensor turns off the output PMOS, allowing the device to cool down. The regulator regulates the output again through initiation of a new soft-start cycle after the junction temperature is cooled by 40C.The thermal shutdown is designed with a 40C hysteresis to lower the average junction temperature during continuous thermal overload conditions, extending lifetime of the device. For normal operation, device power dissipation should be externally limited, so that junction temperature will not exceed 125C.
Copyright (c) ANPEC Electronics Corp. Rev. A.4 - Mar., 2009
10
www.anpec.com.tw
APL5317
Application Information
Input Capacitor The APL5317 requires proper input capacitors to supply surge current during stepping load transients to prevent the input rail from dropping. Because the parasitic inductor from the voltage sources or other bulk capacitors to the VIN limit the slew rate of the surge current, place the Input capacitors near VIN as close as possible. Input capacitors should be larger than 1F and a minimum ceramic capacitor of 1F is necessary. Output Capacitor The APL5317 needs a proper output capacitor to maintain circuit stability and improve transient response over temperature and current. In order to insure the circuit stability, the proper output capacitor value should be larger than 2.2F. With X5R and X7R dielectrics, 2.2F is sufficient at all operating temperatures. Large output capacitor value can reduce noise and improve load-transient response and PSRR, however, it also affects power on issue. Equation (1) shows the relationship between the maximum COUT value and VOUT.
COUT(max) = 31 6 VOUT ...............................(1)
Operation Region and Power Dissipation The APL5317 maximum power dissipation depends on the thermal resistance and temperature difference between the die junction and ambient air. The power dissipation PD across the device is: PD = (TJ - TA) / JA where (TJ-TA) is the temperature difference between the junction and ambient air. JA is the thermal resistance between junction and ambient air. Assuming the TA=25oC and maximum TJ=160oC (typical thermal limit threshold), the maximum power dissipation is calculated as: PD(max)=(160-25)/240 = 0.56(W) For normal operation, do not exceed the maximum junction temperature rating of TJ = 125 oC. The calculated power dissipation should less than: PD =(125-25)/240 = 0.41(W) The GND provides an electrical connection to ground and channels heat away. Connect the GND to the ground by using a large pad or a ground plane. Layout Consideration Figure 2 illustrates the layout. Below is a checklist for your layout: 1. Please place the input capacitors close to the VIN. 2. Ceramic capacitors for load must be placed near the load as close as possible. 3. To place APL5317 and output capacitors near the load is good for performance. 4. Large current paths, the bold lines in figure 2, must have wide tracks. 5. Divider resistor R1 and R2 must be placed near the SET as close as possible.
Where the unit of COUT is F and VOUT is V, Figure 1 shows the curve of maximum output capacitor over the output voltage. The output voltage range is from 0.8 to 5.5V and the output capacitor value should be under the line. Output capacitors must be placed at the load and the ground pin as close as possible and the impedance of the layout must be minimized.
31
Output Capacitor (F)
28
25
22 0 1 2 3 4 5 6
Output voltage (V) Figure 1
Copyright (c) ANPEC Electronics Corp. Rev. A.4 - Mar., 2009
11
www.anpec.com.tw
APL5317
Application Information (Cont.)
PCB Layout Consideration (Cont.)
CIN APL5317 VIN VOUT SET GND 2 R2 LOAD 1 5 4 R1 VOUT VIN
COUT
Figure 2 Recommended Minimum Footprint
SOT-23-5
0.076
0.1
0.038
0.02 Unit : Inch
Copyright (c) ANPEC Electronics Corp. Rev. A.4 - Mar., 2009
0.05
12
www.anpec.com.tw
APL5317
Package Information
SOT-23-5
D e
SEE VIEW A E1 b e1 E
c
0.25 GAUGE PLANE SEATING PLANE VIEW A
0
A2 A1
A
L
S Y M B O L A A1 A2 b c D E E1 e e1 L 0
SOT-23-5 MILLIMETERS MIN. MAX. 1.45 0.00 0.90 0.30 0.08 2.70 2.60 1.40 0.95 BSC 1.90 BSC 0.30 0 0.60 8 0.012 0 0.15 1.30 0.50 0.22 3.10 3.00 1.80 0.000 0.035 0.012 0.003 0.016 0.102 0.055 0.037 BSC 0.075 BSC 0.024 8 MIN. INCHES MAX. 0.057 0.006 0.051 0.020 0.009 0.122 0.118 0.071
Note : 1. Follow JEDEC TO-178 AA. 2. Dimension D and E1 do not include mold flash, protrusions or gate burrs. Mold flash, protrusion or gate burrs shall not exceed 10 mil per side.
Copyright (c) ANPEC Electronics Corp. Rev. A.4 - Mar., 2009
13
www.anpec.com.tw
APL5317
Carrier Tape & Reel Dimensions
OD0 P0 P2 P1 A E1 F K0 B SECTION A-A T B0 A0 OD1 B A SECTION B-B
d
Application
A 178.0O .00 2
H 50 MIN. P1 4.0O .10 0
H A
T1
T1 8.4+2.00 -0.00 P2 2.0O .05 0
C 13.0+0.50 -0.20 D0 1.5+0.10 -0.00
d 1.5 MIN. D1 1.0 MIN.
D 20.2 MIN. T 0.6+0.00 -0.40
W 8.0O .30 0 A0 3.20O .20 0
W
E1 1.75O .10 0 B0 3.10O .20 0
F 3.5O .05 0 K0 1.50O .20 0 (mm)
SOT-23-5
P0 4.0O .10 0
Devices Per Unit
Package Type SOT-23-5 Unit Tape & Reel Quantity 3000
Copyright (c) ANPEC Electronics Corp. Rev. A.4 - Mar., 2009
14
www.anpec.com.tw
APL5317
Taping Direction Information
SOT-23-5
USER DIRECTION OF FEED
Classification Profile
Copyright (c) ANPEC Electronics Corp. Rev. A.4 - Mar., 2009
15
www.anpec.com.tw
APL5317
Classification Reflow Profiles
Profile Feature Preheat & Soak Temperature min (Tsmin) Temperature max (Tsmax) Time (Tsmin to Tsmax) (ts) Average ramp-up rate (Tsmax to TP) Liquidous temperature (TL) Time at liquidous (tL) Peak package body Temperature (Tp)* Time (tP)** within 5C of the specified classification temperature (Tc) Average ramp-down rate (Tp to Tsmax) Time 25C to peak temperature Sn-Pb Eutectic Assembly 100 C 150 C 60-120 seconds 3 C/second max. 183 C 60-150 seconds See Classification Temp in table 1 20** seconds 6 C/second max. 6 minutes max. Pb-Free Assembly 150 C 200 C 60-120 seconds 3C/second max. 217 C 60-150 seconds See Classification Temp in table 2 30** seconds 6 C/second max. 8 minutes max.
* Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum. ** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum.
Table 1. SnPb Eutectic Process - Classification Temperatures (Tc) Package Thickness <2.5 mm 2.5 mm Package Thickness <1.6 mm 1.6 mm - 2.5 mm 2.5 mm Volume mm <350 260 C 260 C 250 C
3
Volume mm <350 235 C 220 C
3
Volume mm 350 220 C 220 C Volume mm 350-2000 260 C 250 C 245 C
3
3
Table 2. Pb-free Process - Classification Temperatures (Tc) Volume mm >2000 260 C 245 C 245 C
3
Reliability Test Program
Test item SOLDERABILITY HOLT PCT TCT ESD Latch-Up Method JESD-22, B102 JESD-22, A108 JESD-22, A102 JESD-22, A104 MIL-STD-883-3015.7 JESD 78 Description 5 Sec, 245C 1000 Hrs, Bias @ 125C 168 Hrs, 100%RH, 2atm, 121C 500 Cycles, -65C~150C VHBMU2KV, VMMU200V 10ms, 1trU 100mA
Copyright (c) ANPEC Electronics Corp. Rev. A.4 - Mar., 2009
16
www.anpec.com.tw
APL5317
Customer Service
Anpec Electronics Corp. Head Office : No.6, Dusing 1st Road, SBIP, Hsin-Chu, Taiwan, R.O.C. Tel : 886-3-5642000 Fax : 886-3-5642050 Taipei Branch : 2F, No. 11, Lane 218, Sec 2 Jhongsing Rd., Sindian City, Taipei County 23146, Taiwan Tel : 886-2-2910-3838 Fax : 886-2-2917-3838
Copyright (c) ANPEC Electronics Corp. Rev. A.4 - Mar., 2009
17
www.anpec.com.tw

▲Up To Search▲

Price & Availability of APL531712BI-TRG

	To Download APL531712BI-TRG Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .