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PIC16F688 Data Sheet
14-Pin Flash-Based, 8-Bit CMOS Microcontrollers with nanoWatt Technology
(c) 2009 Microchip Technology Inc.
DS41203E
Note the following details of the code protection feature on Microchip devices: * * Microchip products meet the specification contained in their particular Microchip Data Sheet. Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable."
*
* *
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Trademarks The Microchip name and logo, the Microchip logo, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, rfPIC and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Octopus, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, PIC32 logo, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. (c) 2009, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper.
Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company's quality system processes and procedures are for its PIC(R) MCUs and dsPIC(R) DSCs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001:2000 certified.
DS41203E-page ii
(c) 2009 Microchip Technology Inc.
PIC16F688
14-Pin Flash-Based, 8-Bit CMOS Microcontrollers with nanoWatt Technology
High-Performance RISC CPU:
* Only 35 Instructions to Learn: - All single-cycle instructions except branches * Operating Speed: - DC - 20 MHz oscillator/clock input - DC - 200 ns instruction cycle * Interrupt Capability * 8-level Deep Hardware Stack * Direct, Indirect and Relative Addressing modes
Low-Power Features:
* Standby Current: - 50 nA @ 2.0V, typical * Operating Current: - 11 A @ 32 kHz, 2.0V, typical - 220 A @ 4 MHz, 2.0V, typical * Watchdog Timer Current: - 1 A @ 2.0V, typical
Peripheral Features: Special Microcontroller Features:
* Precision Internal Oscillator: - Factory calibrated to 1% - Software selectable frequency range of 8 MHz to 125 kHz - Software tunable - Two-Speed Start-Up mode - Crystal fail detect for critical applications - Clock mode switching during operation for power savings * Power-Saving Sleep mode * Wide Operating Voltage Range (2.0V-5.5V) * Industrial and Extended Temperature Range * Power-on Reset (POR) * Power-up Timer (PWRT) and Oscillator Start-up Timer (OST) * Brown-out Reset (BOR) with Software Control Option * Enhanced Low-Current Watchdog Timer (WDT) with on-chip oscillator (software selectable nominal 268 seconds with full prescaler) with software enable * Multiplexed Master Clear with Weak Pull-up or Input Only Pin * Programmable Code Protection * High-Endurance Flash/EEPROM Cell: - 100,000 write Flash endurance - 1,000,000 write EEPROM endurance - Flash/Data EEPROM retention: > 40 years * 12 I/O Pins with Individual Direction Control: - High-current source/sink for direct LED drive - Interrupt-on-change pin - Individually programmable weak pull-ups - Ultra Low-Power Wake-up * Analog Comparator module with: - Two analog comparators - Programmable On-chip Voltage Reference (CVREF) module (% of VDD) - Comparator inputs and outputs externally accessible * A/D Converter: - 10-bit resolution and 8 channels * Timer0: 8-bit Timer/Counter with 8-bit Programmable Prescaler * Enhanced Timer1: - 16-bit timer/counter with prescaler - External Timer1 Gate (count enable) - Option to use OSC1 and OSC2 in LP mode as Timer1 oscillator if INTOSC mode selected * Enhanced USART Module: - Supports RS-485, RS-232, LIN 2.0/2.1 and J2602 - Auto-Baud Detect - Auto-wake-up on Start bit * In-Circuit Serial ProgrammingTM (ICSPTM) via two pins
(c) 2009 Microchip Technology Inc.
DS41203E-page 1
PIC16F688
Program Memory Device Flash (words) PIC16F688 4096 SRAM (bytes) 256 EEPROM (bytes) 256 12 Data Memory I/O 10-bit A/D (ch) 8 Comparators Timers 8/16-bit 1/1
2
Pin Diagram (PDIP, SOIC, TSSOP)
14-pin PDIP, SOIC, TSSOP
VDD RA5/T1CKI/OSC1/CLKIN RA4/AN3/T1G/OSC2/CLKOUT RA3/MCLR/VPP RC5/RX/DT RC4/C2OUT/TX/CK RC3/AN7
1 2 PIC16F688 3 4 5 6 7
14 13 12 11 10 9 8
VSS RA0/AN0/C1IN+/ICSPDAT/ULPWU RA1/AN1/C1IN-/VREF/ICSPCLK RA2/AN2/T0CKI/INT/C1OUT RC0/AN4/C2IN+ RC1/AN5/C2INRC2/AN6
TABLE 1:
I/O RA0 RA1 RA2 RA3 RA4 RA5 RC0 RC1 RC2 RC3 RC4 RC5 -- -- Note 1: Pin 13 12 11 4 3 2 10 9 8 7 6 5 1 14
PIC16F688 14-PIN SUMMARY (PDIP, SOIC, TSSOP)
Analog AN0/ULPWU AN1 AN2 -- AN3 -- AN4 AN5 AN6 AN7 -- -- -- -- Comparators C1IN+ C1INC1OUT -- -- -- C2IN+ C2IN-- -- C2OUT -- -- -- Timers -- -- T0CKI -- T1G T1CKI -- -- -- -- -- -- -- -- EUSART -- -- -- -- -- -- -- -- -- -- TX/CK RX/DT -- -- Interrupt IOC IOC IOC/INT IOC IOC IOC -- -- -- -- -- -- -- -- Pull-up Y Y Y Y(1) Y Y -- -- -- -- -- -- -- -- Basic ICSPDAT VREF/ICSPCLK -- MCLR/VPP OSC2/CLKOUT OSC1/CLKIN -- -- -- -- -- -- VDD VSS
Pull-up activated only with external MCLR configuration.
DS41203E-page 2
(c) 2009 Microchip Technology Inc.
PIC16F688
Pin Diagram (QFN)
16-pin QFN VDD VSS 13 NC 15 NC 14
RA5/T1CKI/OSC1/CLKIN RA4/AN3/T1G/OSC2/CLKOUT RA3/MCLR/VPP RC5/RX/DT
16
1 2 3 4 5 6 7 PIC16F688
12 11 10 9
RA0/AN0/C1IN+/ICSPDAT/ULPWU RA1/AN1/C1IN-/VREF/ICSPCLK RA2/AN2/T0CKI/INT/C1OUT RC0/AN4/C2IN+
RC3/AN7
RC4/C2OUT/TX/CK
RC2/AN6
TABLE 2:
I/O RA0 RA1 RA2 RA3 RA4 RA5 RC0 RC1 RC2 RC3 RC4 RC5 -- -- -- -- Note 1: Pin 12 11 10 3 2 1 9 8 7 6 5 4 16 13 14 15
PIC16F688 16-PIN SUMMARY (QFN)
Analog AN0/ULPWU AN1 AN2 -- AN3 -- AN4 AN5 AN6 AN7 -- -- -- -- -- -- Comparators C1IN+ C1INC1OUT -- -- -- C2IN+ C2IN-- -- C2OUT -- -- -- -- -- Timers -- -- T0CKI -- T1G T1CKI -- -- -- -- -- -- -- -- -- -- EUSART -- -- -- -- -- -- -- -- -- -- TX/CK RX/DT -- -- -- -- Interrupt IOC IOC IOC/INT IOC IOC IOC -- -- -- -- -- -- -- -- -- -- Pull-up Y Y Y Y(1) Y Y -- -- -- -- -- -- -- -- -- -- Basic ICSPDAT VREF/ICSPCLK -- MCLR/VPP OSC2/CLKOUT OSC1/CLKIN -- -- -- -- -- -- VDD VSS NC NC
Pull-up activated only with external MCLR configuration.
(c) 2009 Microchip Technology Inc.
RC1/AN5/C2IN-
8
DS41203E-page 3
PIC16F688
Table of Contents
1.0 Device Overview ......................................................................................................................................................................... 5 2.0 Memory Organization .................................................................................................................................................................. 7 3.0 Clock Sources ........................................................................................................................................................................... 21 4.0 I/O Ports .................................................................................................................................................................................... 33 5.0 Timer0 Module .......................................................................................................................................................................... 45 6.0 Timer1 Module with Gate Control.............................................................................................................................................. 49 7.0 Comparator Module................................................................................................................................................................... 55 8.0 Analog-to-Digital Converter (A/D) Module ................................................................................................................................. 65 9.0 Data EEPROM and Flash Program Memory Control ................................................................................................................ 77 10.0 Enhanced Universal Asynchronous Receiver Transmitter (EUSART) ...................................................................................... 83 11.0 Special Features of the CPU ................................................................................................................................................... 109 12.0 Instruction Set Summary ......................................................................................................................................................... 129 13.0 Development Support .............................................................................................................................................................. 139 14.0 Electrical Specifications........................................................................................................................................................... 143 15.0 DC and AC Characteristics Graphs and Tables ...................................................................................................................... 163 16.0 Packaging Information............................................................................................................................................................. 185 Appendix A: Data Sheet Revision History......................................................................................................................................... 193 Appendix B: Migrating from other PIC(R) Devices............................................................................................................................... 193 Index ................................................................................................................................................................................................. 195 On-line Support ................................................................................................................................................................................. 199 Systems Information and Upgrade Hot Line ..................................................................................................................................... 199 Reader Response ............................................................................................................................................................................. 200 Product Identification System............................................................................................................................................................ 201
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DS41203E-page 4
(c) 2009 Microchip Technology Inc.
PIC16F688
1.0 DEVICE OVERVIEW
The PIC16F688 is covered by this data sheet. It is available in 14-pin PDIP, SOIC, TSSOP and QFN packages. Figure 1-1 shows a block diagram of the PIC16F688 device. Table 1-1 shows the pinout description.
FIGURE 1-1:
PIC16F688 BLOCK DIAGRAM
INT Configuration 13 Program Counter Flash 4k x 14 Program Memory Data Bus 8 PORTA RA0 RA1 8-Level Stack (13 bit) RAM 256 bytes File Registers RAM Addr 9 Addr MUX Direct Addr 7 Indirect Addr PORTC RC0 RC1 RC2 RC3 RC4 RC5 3 Power-up Timer Instruction Decode & Control Oscillator Start-up Timer Power-on Reset Watchdog Timer Brown-out Reset Internal Oscillator Block 8 W Reg MUX RA2 RA3 RA4 RA5
Program Bus
14
Instruction Reg
8
FSR Reg STATUS Reg 8
ALU
OSC1/CLKIN OSC2/CLKOUT
Timing Generation
RX/DT MCLR VDD VSS
TX/CK
T1G T1CKI Timer0 T0CKI
Timer1
EUSART
Analog-to-Digital Converter
2 Analog Comparators and Reference
EEDAT 8 256 bytes DATA EEPROM EEADDR
VREF
AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 C1IN- C1IN+ C1OUT C2IN- C2IN+ C2OUT
(c) 2009 Microchip Technology Inc.
DS41203E-page 5
PIC16F688
TABLE 1-1: PIC16F688 PINOUT DESCRIPTION
Name RA0/AN0/C1IN+/ICSPDAT/ULPWU Function RA0 AN0 C1IN+ ICSPDAT ULPWU RA1/AN1/C1IN-/VREF/ICSPCLK RA1 AN1 C1INVREF ICSPCLK RA2/AN2/T0CKI/INT/C1OUT RA2 AN2 T0CKI INT C1OUT RA3/MCLR/VPP RA3 MCLR VPP RA4/AN3/T1G/OSC2/CLKOUT RA4 AN3 T1G OSC2 CLKOUT RA5/T1CKI/OSC1/CLKIN RA5 T1CKI OSC1 CLKIN RC0/AN4/C2IN+ RC0 AN4 C2IN+ RC1/AN5/C2INRC1 AN5 C2INRC2/AN6 RC3/AN7 RC4/C2OUT/TX/CK RC2 AN6 RC3 AN7 RC4 C2OUT TX CK RC5/RX/DT RC5 RX DT VSS VDD Legend: AN TTL HV VSS VDD = Analog input or output = TTL compatible input = High Voltage Input Type TTL AN AN TTL AN TTL AN AN AN ST ST AN ST ST -- TTL ST HV TTL AN ST -- -- TTL ST XTAL ST TTL AN AN TTL AN AN TTL AN TTL AN TTL -- -- ST TTL ST ST Power Power CMOS -- CMOS -- CMOS CMOS CMOS CMOS CMOS CMOS CMOS -- -- CMOS -- Output Type CMOS -- -- CMOS -- CMOS -- -- -- -- CMOS -- -- -- CMOS -- -- -- CMOS -- -- XTAL CMOS CMOS -- -- -- CMOS -- A/D Channel 0 input Comparator 1 input Serial Programming Data I/O Ultra Low-Power Wake-up input PORTA I/O w/prog pull-up and interrupt-on-change A/D Channel 1 input Comparator 1 input External Voltage Reference for A/D Serial Programming Clock PORTA I/O w/prog pull-up and interrupt-on-change A/D Channel 2 input Timer0 clock input External Interrupt Comparator 1 output PORTA input with interrupt-on-change Master Clear w/internal pull-up Programming voltage PORTA I/O w/prog pull-up and interrupt-on-change A/D Channel 3 input Timer1 gate Crystal/Resonator FOSC/4 output PORTA I/O w/prog pull-up and interrupt-on-change Timer1 clock Crystal/Resonator External clock input/RC oscillator connection PORTC I/O A/D Channel 4 input Comparator 2 input PORTC I/O A/D Channel 5 input Comparator 2 input PORTC I/O A/D Channel 6 input PORTC I/O A/D Channel 7 input PORTC I/O Comparator 2 output USART asynchronous output USART asynchronous clock Port C I/O USART asynchronous input USART asynchronous data Ground reference Positive supply OC = Open collector output Description PORTA I/O w/prog pull-up and interrupt-on-change
CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels XTAL = Crystal
DS41203E-page 6
(c) 2009 Microchip Technology Inc.
PIC16F688
2.0
2.1
MEMORY ORGANIZATION
Program Memory Organization
2.2
Data Memory Organization
The PIC16F688 has a 13-bit program counter capable of addressing a 4K x 14 program memory space. Only the first 4K x 14 (0000h-01FFF) for the PIC16F688 is physically implemented. Accessing a location above these boundaries will cause a wrap-around within the first 4K x 14 space. The Reset vector is at 0000h and the interrupt vector is at 0004h (see Figure 2-1).
The data memory is partitioned into multiple banks, which contain the General Purpose Registers (GPR) and the Special Function Registers (SFR). Bits RP0 and RP1 are bank select bits. RP1 0 0 1 1 RP0 0 1 0 1 Bank 0 is selected Bank 1 is selected Bank 2 is selected Bank 3 is selected
FIGURE 2-1:
PROGRAM MEMORY MAP AND STACK FOR THE PIC16F688
PC<12:0>
CALL, RETURN RETFIE, RETLW
13
Stack Level 1 Stack Level 2
Each bank extends up to 7Fh (128 bytes). The lower locations of each bank are reserved for the Special Function Registers. Above the Special Function Registers are the General Purpose Registers, implemented as static RAM. All implemented banks contain Special Function Registers. Some frequently used Special Function Registers from one bank are mirrored in another bank for code reduction and quicker access.
2.2.1
GENERAL PURPOSE REGISTER FILE
Stack Level 8 Reset Vector
0000h
The register file is organized as 256 x 8 in the PIC16F688. Each register is accessed, either directly or indirectly, through the File Select Register (FSR) (see Section 2.4 "Indirect Addressing, INDF and FSR Registers").
Interrupt Vector
0004h 0005h
2.2.2
SPECIAL FUNCTION REGISTERS
On-chip Program Memory 01FFh 02000h Wraps to 0000h-07FFh 1FFFh
The Special Function Registers are registers used by the CPU and peripheral functions for controlling the desired operation of the device (see Tables 2-1, 2-2, 2-3 and 2-4). These registers are static RAM. The special registers can be classified into two sets: core and peripheral. The Special Function Registers associated with the "core" are described in this section. Those related to the operation of the peripheral features are described in the section of that peripheral feature.
(c) 2009 Microchip Technology Inc.
DS41203E-page 7
PIC16F688
FIGURE 2-2: PIC16F688 SPECIAL FUNCTION REGISTERS
File Address Indirect addr. (1) 80h OPTION_REG 81h PCL 82h STATUS 83h FSR 84h TRISA 85h 86h TRISC 87h 88h 89h PCLATH 8Ah INTCON 8Bh PIE1 8Ch 8Dh PCON 8Eh OSCCON 8Fh OSCTUNE 90h ANSEL 91h 92h 93h 94h WPUA 95h IOCA 96h EEDATH 97h EEADRH 98h VRCON 99h EEDAT 9Ah EEADR 9Bh EECON1 9Ch EECON2(1) 9Dh ADRESL 9Eh ADCON1 9Fh A0h General Purpose Register 80 Bytes 96 Bytes 7Fh Bank 0 accesses Bank 0 Bank 1 EFh F0h FFh File Address Indirect addr. (1) 100h TMR0 101h PCL 102h STATUS 103h FSR 104h PORTA 105h 106h PORTC 107h 108h 109h PCLATH 10Ah INTCON 10Bh 10Ch 10Dh 10Eh 10Fh 110h 111h 112h 113h 114h 115h 116h 117h 118h 119h 11Ah 11Bh 11Ch 11Dh 11Eh 11Fh 120h General Purpose Register 80 Bytes accesses Bank 0 Bank 2 16Fh 170h 17Fh accesses Bank 0 Bank 3 1EFh 1F0h 1FFh File Address Indirect addr. (1) 180h OPTION_REG 181h PCL 182h STATUS 183h FSR 184h TRISA 185h 186h TRISC 187h 188h 189h PCLATH 18Ah INTCON 18Bh 18Ch 18Dh 18Eh 18Fh 190h 191h 192h 193h 194h 195h 196h 197h 198h 199h 19Ah 19Bh 19Ch 19Dh 19Eh 19Fh 1A0h File Address Indirect addr. (1) 00h TMR0 01h PCL 02h STATUS 03h FSR 04h PORTA 05h 06h PORTC 07h 08h 09h PCLATH 0Ah INTCON 0Bh PIR1 0Ch 0Dh TMR1L 0Eh TMR1H 0Fh T1CON 10h BAUDCTL 11h SPBRGH 12h SPBRG 13h RCREG 14h TXREG 15h TXSTA 16h RCSTA 17h WDTCON 18h CMCON0 19h CMCON1 1Ah 1Bh 1Ch 1Dh ADRESH 1Eh ADCON0 1Fh 20h
General Purpose Register
Unimplemented data memory locations, read as `0'. Note 1: Not a physical register.
DS41203E-page 8
(c) 2009 Microchip Technology Inc.
PIC16F688
TABLE 2-1:
Addr Bank 0 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh INDF TMR0 PCL STATUS FSR PORTA -- PORTC -- -- PCLATH INTCON PIR1 -- TMR1L TMR1H T1CON BAUDCTL SPBRGH SPBRG RCREG TXREG TXSTA RCSTA WDTCON CMCON0 CMCON1 -- -- -- ADRESH ADCON0 Addressing this location uses contents of FSR to address data memory (not a physical register) Timer0 Module's register Program Counter's (PC) Least Significant Byte IRP RP1 RP0 TO PD Z DC C xxxx xxxx xxxx xxxx 0000 0000 0001 1xxx xxxx xxxx RA4 RA3 RA2 RA1 RA0 --x0 x000 -- RC5 RC4 RC3 RC2 RC1 RC0 --xx 0000 -- -- -- T0IE RCIF Write Buffer for upper 5 bits of Program Counter INTE C2IF RAIE C1IF T0IF OSFIF INTF TXIF RAIF(2) TMR1IF ---0 0000 0000 000x 0000 0000 -- xxxx xxxx xxxx xxxx TMR1CS WUE TMR1ON ABDEN 0000 0000 01-0 0-00 0000 0000 0000 0000 0000 0000 0000 0000 SYNC CREN WDTPS3 C1INV -- SENDB ADDEN WDTPS2 CIS -- BRGH FERR WDTPS1 CM2 -- TRMT OERR WDTPS0 CM1 T1GSS TX9D RX9D SWDTEN CM0 C2SYNC 0000 0010 0000 000x ---0 1000 0000 0000 ---- --10 -- -- -- xxxx xxxx ADON 00-0 0000 20, 117 45, 117 19, 117 13, 117 20, 117 33, 117 -- 42, 117 -- -- 19, 117 15, 117 17, 117 -- 48, 117 48, 117 51, 117 94, 117 95, 117 95, 117 87, 117 87, 117 92, 117 93, 117 124, 117 61, 117 62, 117 -- -- -- 72, 117 71, 117 Name
PIC16F688 SPECIAL REGISTERS SUMMARY BANK 0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR/BOR Page
Indirect Data Memory Address Pointer -- -- RA5
Unimplemented -- --
Unimplemented Unimplemented -- GIE EEIF -- PEIE ADIF
Unimplemented Holding Register for the Least Significant Byte of the 16-bit TMR1 Holding Register for the Most Significant Byte of the 16-bit TMR1 T1GINV ABDOVF TMR1GE RCIDL T1CKPS1 -- T1CKPS0 SCKP T1OSCEN BRG16 T1SYNC --
USART Baud Rate High Generator USART Baud Rate Generator USART Receive Register USART Transmit Register CSRC SPEN -- C2OUT -- TX9 RX9 -- C1OUT -- TXEN SREN -- C2INV --
Unimplemented Unimplemented Unimplemented Most Significant 8 bits of the left shifted A/D result or 2 bits of right shifted result ADFM VCFG -- CHS2 CHS1 CHS0 GO/DONE
Legend: Note 1: 2:
- = Unimplemented locations read as `0', u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation. MCLR and WDT Reset does not affect the previous value data latch. The RAIF bit will be cleared upon Reset but will set again if the mismatched exists.
(c) 2009 Microchip Technology Inc.
DS41203E-page 9
PIC16F688
TABLE 2-2:
Addr Bank 1 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch 8Dh 8Eh 8Fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9Ah 9Bh 9Ch 9Dh 9Eh 9Fh IOCA EEDATH EEADRH VRCON EEDAT EEADR EECON1 EECON2 ADRESL ADCON1 INDF OPTION_REG PCL STATUS FSR TRISA -- TRISC -- -- PCLATH INTCON PIE1 -- PCON OSCCON OSCTUNE ANSEL -- -- -- WPUA(2) Addressing this location uses contents of FSR to address data memory (not a physical register) RAPU IRP -- -- INTEDG RP1 -- -- T0CS RP0 TRISA5 TRISC5 T0SE TO TRISA4 TRISC4 PSA PD TRISA3 TRISC3 PS2 Z TRISA2 TRISC2 PS1 DC TRISA1 TRISC1 PS0 C TRISA0 TRISC0 Program Counter's (PC) Least Significant Byte Indirect Data Memory Address Pointer Unimplemented Unimplemented Unimplemented -- GIE EEIE -- -- -- ANS7 -- PEIE ADIE -- IRCF2 -- ANS6 -- T0IE RCIE ULPWUE IRCF1 -- ANS5 Write Buffer for upper 5 bits of Program Counter INTE C2IE SBOREN IRCF0 TUN4 ANS4 RAIE C1IE -- OSTS TUN3 ANS3 T0IF OSFIE -- HTS TUN2 ANS2 INTF TXIE POR LTS TUN1 ANS1 RAIF(3) TMR1IE BOR SCS TUN0 ANS0 xxxx xxxx 1111 1111 0000 0000 0001 1xxx xxxx xxxx --11 1111 -- --11 1111 -- -- ---0 0000 0000 000x 0000 0000 -- --01 --qq -110 x000 ---0 0000 1111 1111 -- -- -- WPUA5 IOCA5 EEDATH5 -- VRR EEDAT5 EEADR5 -- WPUA4 IOCA4 EEDATH4 -- -- EEDAT4 EEADR4 -- -- IOCA3 EEDATH3 VR3 EEDAT3 EEADR3 WRERR WPUA2 IOCA2 EEDATH2 VR2 EEDAT2 EEADR2 WREN WPUA1 IOCA1 EEDATH1 VR1 EEDAT1 EEADR1 WR WPUA0 IOCA0 EEDATH0 VR0 EEDAT0 EEADR0 RD --11 -111 --00 0000 --00 0000 20, 117 14, 117 19, 117 13, 117 20, 117 33, 117 -- 42, 117 -- -- 19, 117 15, 117 16, 117 -- 18, 117 22, 118 26, 118 34, 118 -- -- -- 35, 118 35, 118 78, 118 78, 118 63, 118 78, 118 78, 118 79, 118 77, 118 72, 118 71, 118 Name
PIC16F688 SPECIAL FUNCTION REGISTERS SUMMARY BANK 1
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR/BOR Page
Unimplemented
Unimplemented Unimplemented Unimplemented -- -- -- -- VREN EEDAT7 EEADR7 EEPGD -- -- -- -- -- EEDAT6 EEADR6 --
EEADRH3 EEADRH2 EEADRH1 EEADRH0 ---- 0000 0-0- 0000 0000 0000 0000 0000 x--- x000 ---- ---xxxx xxxx -- -000 ----- --
EEPROM Control 2 Register (not a physical register) Least Significant 2 bits of the left shifted result or 8 bits of the right shifted result -- ADCS2 ADCS1 ADCS0 --
Legend: Note 1: 2: 3:
- = Unimplemented locations read as `0', u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation. RA3 pull-up is enabled when pin is configured as MCLR in the Configuration Word register. MCLR and WDT Reset does not affect the previous value data latch. The RAIF bit will be cleared upon Reset but will set again if the mismatched exists.
DS41203E-page 10
(c) 2009 Microchip Technology Inc.
PIC16F688
TABLE 2-3:
Addr Bank 2 100h 101h 102h 103h 104h 105h 106h 107h 108h 109h 10Ah 10Bh 10Ch 10Dh 10Eh 10Fh 110h 111h 112h 113h 114h 115h 116h 117h 118h 119h 11Ah 11Bh 11Ch 11Dh 11Eh 11Fh Legend: Note 1: 2: INDF TMR0 PCL STATUS FSR PORTA -- PORTC -- -- PCLATH INTCON -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Addressing this location uses contents of FSR to address data memory (not a physical register) Timer0 Module's register Program Counter's (PC) Least Significant Byte IRP RP1 RP0 TO PD Z DC C xxxx xxxx xxxx xxxx 0000 0000 0001 1xxx xxxx xxxx RA4 RA3 RA2 RA1 RA0 --x0 x000 -- -- RC5 RC4 RC3 RC2 RC1 RC0 --xx 0000 -- -- -- PEIE -- T0IE Write Buffer for upper 5 bits of Program Counter INTE RAIE T0IF INTF RAIF(2) ---0 0000 0000 000x -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 20, 117 45, 117 19, 117 13, 117 20, 117 33, 117 -- 42, 117 -- -- 19, 117 15, 117 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Name
PIC16F688 SPECIAL REGISTERS SUMMARY BANK 2
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR/BOR Page
Indirect Data Memory Address Pointer -- Unimplemented -- Unimplemented Unimplemented -- GIE -- RA5
Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented
- = Unimplemented locations read as `0', u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation. MCLR and WDT Reset does not affect the previous value data latch. The RAIF bit will be cleared upon Reset but will set again if the mismatched exists.
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TABLE 2-4:
Addr Bank 3 180h 181h 182h 183h 184h 185h 186h 187h 188h 189h 18Ah 18Bh 18Ch 18Dh 190h 191h 192h 193h 194h 195h 196h 19Ah 19Bh 199h 19Ah 19Bh 19Ch 19Dh 19Eh 19Fh Legend: Note 1: 2: INDF OPTION_REG PCL STATUS FSR TRISA -- TRISC -- -- PCLATH INTCON -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Addressing this location uses contents of FSR to address data memory (not a physical register) RAPU IRP -- Unimplemented -- Unimplemented Unimplemented -- GIE Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented -- PEIE -- T0IE Write Buffer for upper 5 bits of Program Counter INTE RAIE T0IF INTF RAIF(2) -- TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 INTEDG RP1 -- T0CS RP0 TRISA5 T0SE TO TRISA4 PSA PD TRISA3 PS2 Z TRISA2 PS1 DC TRISA1 PS0 C TRISA0 Program Counter's (PC) Least Significant Byte Indirect Data Memory Address Pointer xxxx xxxx 1111 1111 0000 0000 0001 1xxx xxxx xxxx --11 1111 -- --11 1111 -- -- ---0 0000 0000 000x -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 20, 117 14, 117 19, 117 13, 117 20, 117 33, 117 -- 42, 117 -- -- 19, 117 15, 117 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Name
PIC16F688 SPECIAL FUNCTION REGISTERS SUMMARY BANK 3
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR/BOR Page
- = Unimplemented locations read as `0', u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation. MCLR and WDT Reset does not affect the previous value data latch. The RAIF bit will be cleared upon Reset but will set again if the mismatched exists.
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PIC16F688
2.2.2.1 STATUS Register
The STATUS register, shown in Register 2-1, contains: * the arithmetic status of the ALU * the Reset status * the bank select bits for data memory (SRAM) The STATUS register can be the destination for any instruction, like any other register. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic. Furthermore, the TO and PD bits are not writable. Therefore, the result of an instruction with the STATUS register as destination may be different than intended. For example, CLRF STATUS will clear the upper three bits and set the Z bit. This leaves the STATUS register as `000u u1uu' (where u = unchanged). It is recommended, therefore, that only BCF, BSF, SWAPF and MOVWF instructions are used to alter the STATUS register, because these instructions do not affect any Status bits. For other instructions not affecting any Status bits (see Section 12.0 "Instruction Set Summary"). Note 1: The C and DC bits operate as a Borrow and Digit Borrow out bit, respectively, in subtraction.
REGISTER 2-1:
R/W-0 IRP bit 7 Legend: R = Readable bit -n = Value at POR bit 7
STATUS: STATUS REGISTER
R/W-0 RP1 R/W-0 RP0 R-1 TO R-1 PD R/W-x Z R/W-x DC(1) R/W-x C(1) bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
IRP: Register Bank Select bit (used for indirect addressing) 1 = Bank 2, 3 (100h-1FFh) 0 = Bank 0, 1 (00h-FFh) RP<1:0>: Register Bank Select bits (used for direct addressing) 00 = Bank 0 (00h-7Fh) 01 = Bank 1 (80h-FFh) 10 = Bank 2 (100h-17Fh) 11 = Bank 3 (180h-1FFh) TO: Time-out bit 1 = After power-up, CLRWDT instruction or SLEEP instruction 0 = A WDT time-out occurred PD: Power-down bit 1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero DC: Digit Carry/Borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)(1) 1 = A carry-out from the 4th low-order bit of the result occurred 0 = No carry-out from the 4th low-order bit of the result C: Carry/Borrow bit(1) (ADDWF, ADDLW, SUBLW, SUBWF instructions)(1) 1 = A carry-out from the Most Significant bit of the result occurred 0 = No carry-out from the Most Significant bit of the result occurred For Borrow, the polarity is reversed. A subtraction is executed by adding the two's complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high-order or low-order bit of the source register.
bit 6-5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
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2.2.2.2 OPTION Register
Note: To achieve a 1:1 prescaler assignment for Timer0, assign the prescaler to the WDT by setting PSA bit of the OPTION register to `1'. See Section 5.1.3 "Software Programmable Prescaler". The OPTION register is a readable and writable register, which contains various control bits to configure: * * * * Timer0/WDT prescaler External RA2/INT interrupt Timer0 Weak pull-ups on PORTA
REGISTER 2-2:
R/W-1 RAPU bit 7 Legend: R = Readable bit -n = Value at POR bit 7
OPTION_REG: OPTION REGISTER
R/W-1 INTEDG R/W-1 T0CS R/W-1 T0SE R/W-1 PSA R/W-1 PS2 R/W-1 PS1 R/W-1 PS0 bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
RAPU: PORTA Pull-up Enable bit 1 = PORTA pull-ups are disabled 0 = PORTA pull-ups are enabled by individual PORT latch values INTEDG: Interrupt Edge Select bit 1 = Interrupt on rising edge of RA2/INT pin 0 = Interrupt on falling edge of RA2/INT pin T0CS: Timer0 Clock Source Select bit 1 = Transition on RA2/T0CKI pin 0 = Internal instruction cycle clock (FOSC/4) T0SE: Timer0 Source Edge Select bit 1 = Increment on high-to-low transition on RA2/T0CKI pin 0 = Increment on low-to-high transition on RA2/T0CKI pin PSA: Prescaler Assignment bit 1 = Prescaler is assigned to the WDT 0 = Prescaler is assigned to the Timer0 module PS<2:0>: Prescaler Rate Select bits
Bit Value 000 001 010 011 100 101 110 111 Timer0 Rate 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256 WDT Rate 1:1 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128
bit 6
bit 5
bit 4
bit 3
bit 2-0
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PIC16F688
2.2.2.3 INTCON Register
Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, GIE of the INTCON register. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. The INTCON register is a readable and writable register, which contains the various enable and flag bits for TMR0 register overflow, PORTA change and external RA2/INT pin interrupts.
REGISTER 2-3:
R/W-0 GIE bit 7 Legend: R = Readable bit -n = Value at POR bit 7
INTCON: INTERRUPT CONTROL REGISTER
R/W-0 PEIE R/W-0 T0IE R/W-0 INTE R/W-0 RAIE R/W-0 T0IF R/W-0 INTF R/W-x RAIF bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
GIE: Global Interrupt Enable bit 1 = Enables all unmasked interrupts 0 = Disables all interrupts PEIE: Peripheral Interrupt Enable bit 1 = Enables all unmasked peripheral interrupts 0 = Disables all peripheral interrupts T0IE: Timer0 Overflow Interrupt Enable bit 1 = Enables the Timer0 interrupt 0 = Disables the Timer0 interrupt INTE: RA2/INT External Interrupt Enable bit 1 = Enables the RA2/INT external interrupt 0 = Disables the RA2/INT external interrupt RAIE: PORTA Change Interrupt Enable bit(1) 1 = Enables the PORTA change interrupt 0 = Disables the PORTA change interrupt T0IF: Timer0 Overflow Interrupt Flag bit(2) 1 = Timer0 register has overflowed (must be cleared in software) 0 = Timer0 register did not overflow INTF: RA2/INT External Interrupt Flag bit 1 = The RA2/INT external interrupt occurred (must be cleared in software) 0 = The RA2/INT external interrupt did not occur RAIF: PORTA Change Interrupt Flag bit 1 = When at least one of the PORTA <5:0> pins changed state (must be cleared in software) 0 = None of the PORTA <5:0> pins have changed state IOCA register must also be enabled. T0IF bit is set when TMR0 rolls over. TMR0 is unchanged on Reset and should be initialized before clearing T0IF bit.
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1: 2:
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2.2.2.4 PIE1 Register
Note: Bit PEIE of the INTCON register must be set to enable any peripheral interrupt. The PIE1 register contains the interrupt enable bits, as shown in Register 2-4.
REGISTER 2-4:
R/W-0 EEIE bit 7 Legend: R = Readable bit -n = Value at POR bit 7
PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1
R/W-0 ADIE R/W-0 RCIE R/W-0 C2IE R/W-0 C1IE R/W-0 OSFIE R/W-0 TXIE R/W-0 TMR1IE bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
EEIE: EE Write Complete Interrupt Enable bit 1 = Enables the EE write complete interrupt 0 = Disables the EE write complete interrupt ADIE: A/D Converter (ADC) Interrupt Enable bit 1 = Enables the ADC interrupt 0 = Disables the ADC interrupt RCIE: EUSART Receive Interrupt Enable bit 1 = Enables the EUSART receive interrupt 0 = Disables the EUSART receive interrupt C2IE: Comparator 2 Interrupt Enable bit 1 = Enables the Comparator C2 interrupt 0 = Disables the Comparator C2 interrupt C1IE: Comparator 1 Interrupt Enable bit 1 = Enables the Comparator C1 interrupt 0 = Disables the Comparator C1 interrupt OSFIE: Oscillator Fail Interrupt Enable bit 1 = Enables the oscillator fail interrupt 0 = Disables the oscillator fail interrupt TXIE: EUSART Transmit Interrupt Enable bit 1 = Enables the EUSART transmit interrupt 0 = Disables the EUSART transmit interrupt TMR1IE: Timer1 Overflow Interrupt Enable bit 1 = Enables the Timer1 overflow interrupt 0 = Disables the Timer1 overflow interrupt
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
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PIC16F688
2.2.2.5 PIR1 Register
Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, GIE bit of the INTCON register. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. The PIR1 register contains the interrupt flag bits, as shown in Register 2-5.
REGISTER 2-5:
R/W-0 EEIF bit 7 Legend: R = Readable bit -n = Value at POR bit 7
PIR1: PERIPHERAL INTERRUPT REQUEST REGISTER 1
R/W-0 ADIF R-0 RCIF R/W-0 C2IF R/W-0 C1IF R/W-0 OSFIF R-0 TXIF R/W-0 TMR1IF bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
EEIF: EEPROM Write Operation Interrupt Flag bit 1 = The write operation completed (must be cleared in software) 0 = The write operation has not completed or has not been started ADIF: A/D Converter Interrupt Flag bit 1 = A/D conversion complete (must be cleared in software) 0 = A/D conversion has not completed or has not been started RCIF: EUSART Receive Interrupt Flag bit 1 = The EUSART receive buffer is full (cleared by reading RCREG) 0 = The EUSART receive buffer is not full C2IF: Comparator C2 Interrupt Flag bit 1 = Comparator output (C2OUT bit) has changed (must be cleared in software) 0 = Comparator output (C2OUT bit) has not changed C1IF: Comparator C1 Interrupt Flag bit 1 = Comparator output (C1OUT bit) has changed (must be cleared in software) 0 = Comparator output (C1OUT bit) has not changed OSFIF: Oscillator Fail Interrupt Flag bit 1 = System oscillator failed, clock input has changed to INTOSC (must be cleared in software) 0 = System clock operating TXIF: EUSART Transmit Interrupt Flag bit 1 = The EUSART transmit buffer is empty (cleared by writing to TXREG) 0 = The EUSART transmit buffer is full TMR1IF: Timer1 Overflow Interrupt Flag bit 1 = The TMR1 register overflowed (must be cleared in software) 0 = The TMR1 register did not overflow
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
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2.2.2.6 PCON Register
The Power Control (PCON) register (see Register 2-6) contains flag bits to differentiate between a: * * * * Power-on Reset (POR) Brown-out Reset (BOR) Watchdog Timer Reset (WDT) External MCLR Reset
The PCON register also controls the Ultra Low-Power Wake-up and software enable of the BOR.
REGISTER 2-6:
U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7-6 bit 5
PCON: POWER CONTROL REGISTER
U-0 -- R/W-0 ULPWUE R/W-1 SBOREN(1) U-0 -- U-0 -- R/W-0 POR R/W-x BOR bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
Unimplemented: Read as `0' ULPWUE: Ultra Low-Power Wake-up Enable bit 1 = Ultra low-power wake-up enabled 0 = Ultra low-power wake-up disabled SBOREN: Software BOR Enable bit(1) 1 = BOR enabled 0 = BOR disabled Unimplemented: Read as `0' POR: Power-on Reset Status bit 1 = No Power-on Reset occurred 0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs) BOR: Brown-out Reset Status bit 1 = No Brown-out Reset occurred 0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs) BOREN<1:0> = 01 in the Configuration Word register for this bit to control the BOR.
bit 4
bit 3-2 bit 1
bit 0
Note 1:
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PIC16F688
2.3 PCL and PCLATH
2.3.2 STACK
The Program Counter (PC) is 13 bits wide. The low byte comes from the PCL register, which is a readable and writable register. The high byte (PC<12:8>) is not directly readable or writable and comes from PCLATH. On any Reset, the PC is cleared. Figure 2-3 shows the two situations for the loading of the PC. The upper example in Figure 2-3 shows how the PC is loaded on a write to PCL (PCLATH<4:0> PCH). The lower example in Figure 2-3 shows how the PC is loaded during a CALL or GOTO instruction (PCLATH<4:3> PCH). The PIC16F688 family has an 8-level x 13-bit wide hardware stack (see Figure 2-1). The stack space is not part of either program or data space and the Stack Pointer is not readable or writable. The PC is PUSHed onto the stack when a CALL instruction is executed or an interrupt causes a branch. The stack is POPed in the event of a RETURN, RETLW or a RETFIE instruction execution. PCLATH is not affected by a PUSH or POP operation. The stack operates as a circular buffer. This means that after the stack has been PUSHed eight times, the ninth push overwrites the value that was stored from the first push. The tenth push overwrites the second push (and so on). Note 1: There are no Status bits to indicate Stack Overflow or Stack Underflow conditions. 2: There are no instructions/mnemonics called PUSH or POP. These are actions that occur from the execution of the CALL, RETURN, RETLW and RETFIE instructions or the vectoring to an interrupt address.
FIGURE 2-3:
PCH 12 PC 5 8 7
LOADING OF PC IN DIFFERENT SITUATIONS
PCL 0 Instruction with PCL as Destination ALU Result
PCLATH<4:0>
8
PCLATH PCH 12 PC 2 PCLATH<4:3> 11 OPCODE<10:0> PCLATH 11 10 8 7 PCL 0 GOTO, CALL
2.3.1
COMPUTED GOTO
A computed GOTO is accomplished by adding an offset to the program counter (ADDWF PCL). When performing a table read using a computed GOTO method, care should be exercised if the table location crosses a PCL memory boundary (each 256-byte block). Refer to the Application Note AN556, "Implementing a Table Read" (DS00556).
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2.4 Indirect Addressing, INDF and FSR Registers
A simple program to clear RAM location 20h-2Fh using indirect addressing is shown in Example 2-1.
The INDF register is not a physical register. Addressing the INDF register will cause indirect addressing. Indirect addressing is possible by using the INDF register. Any instruction using the INDF register actually accesses data pointed to by the File Select Register (FSR). Reading INDF itself indirectly will produce 00h. Writing to the INDF register indirectly results in a no operation (although Status bits may be affected). An effective 9-bit address is obtained by concatenating the 8-bit FSR register and the IRP bit of the STATUS register, as shown in Figure 2-4.
EXAMPLE 2-1:
MOVLW MOVWF NEXT CLRF INCF BTFSS GOTO CONTINUE 0x20 FSR INDF FSR FSR,4 NEXT
INDIRECT ADDRESSING
;initialize pointer ;to RAM ;clear INDF register ;inc pointer ;all done? ;no clear next ;yes continue
FIGURE 2-4:
DIRECT/INDIRECT ADDRESSING PIC16F688
Indirect Addressing 0 IRP 7 File Select Register 0
Direct Addressing RP1 RP0 6 From Opcode
Bank Select
Location Select 00 00h 01 10 11
Bank Select 180h
Location Select
Data Memory
7Fh Bank 0 Note: Bank 1 Bank 2 Bank 3
1FFh
For memory map detail, see Figure 2-2.
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PIC16F688
3.0
3.1
OSCILLATOR MODULE (WITH FAIL-SAFE CLOCK MONITOR)
Overview
The oscillator module can be configured in one of eight clock modes. 1. 2. 3. 4. 5. 6. 7. 8. EC - External clock with I/O on OSC2/CLKOUT. LP - 32 kHz Low-Power Crystal mode. XT - Medium Gain Crystal or Ceramic Resonator Oscillator mode. HS - High Gain Crystal or Ceramic Resonator mode. RC - External Resistor-Capacitor (RC) with FOSC/4 output on OSC2/CLKOUT. RCIO - External Resistor-Capacitor (RC) with I/O on OSC2/CLKOUT. INTOSC - Internal oscillator with FOSC/4 output on OSC2 and I/O on OSC1/CLKIN. INTOSCIO - Internal oscillator with I/O on OSC1/CLKIN and OSC2/CLKOUT.
The oscillator module has a wide variety of clock sources and selection features that allow it to be used in a wide range of applications while maximizing performance and minimizing power consumption. Figure 3-1 illustrates a block diagram of the oscillator module. Clock sources can be configured from external oscillators, quartz crystal resonators, ceramic resonators and Resistor-Capacitor (RC) circuits. In addition, the system clock source can be configured from one of two internal oscillators, with a choice of speeds selectable via software. Additional clock features include: * Selectable system clock source between external or internal via software. * Two-Speed Start-Up mode, which minimizes latency between external oscillator start-up and code execution. * Fail-Safe Clock Monitor (FSCM) designed to detect a failure of the external clock source (LP, XT, HS, EC or RC modes) and switch automatically to the internal oscillator.
Clock source modes are configured by the FOSC<2:0> bits in the Configuration Word register (CONFIG). The internal clock can be generated from two internal oscillators. The HFINTOSC is a calibrated highfrequency oscillator. The LFINTOSC is an uncalibrated low-frequency oscillator.
FIGURE 3-1:
PIC(R) MCU CLOCK SOURCE BLOCK DIAGRAM
FOSC<2:0> (Configuration Word Register) SCS<0> (OSCCON Register)
External Oscillator OSC2 Sleep OSC1
LP, XT, HS, RC, RCIO, EC MUX INTOSC
IRCF<2:0> (OSCCON Register) 8 MHz Internal Oscillator 4 MHz 2 MHz Postscaler 101 100 500 kHz 250 kHz 125 kHz LFINTOSC 31 kHz 31 kHz 011 010 001 000 MUX 1 MHz HFINTOSC 8 MHz 111 110
System Clock (CPU and Peripherals)
Power-up Timer (PWRT) Watchdog Timer (WDT) Fail-Safe Clock Monitor (FSCM)
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3.2 Oscillator Control
The Oscillator Control (OSCCON) register (Figure 3-1) controls the system clock and frequency selection options. The OSCCON register contains the following bits: * Frequency selection bits (IRCF) * Frequency Status bits (HTS, LTS) * System clock control bits (OSTS, SCS)
REGISTER 3-1:
U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7 bit 6-4
OSCCON: OSCILLATOR CONTROL REGISTER
R/W-1 IRCF2 R/W-1 IRCF1 R/W-0 IRCF0 R-1 OSTS(1) R-0 HTS R-0 LTS R/W-0 SCS bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
Unimplemented: Read as `0' IRCF<2:0>: Internal Oscillator Frequency Select bits 111 = 8 MHz 110 = 4 MHz (default) 101 = 2 MHz 100 = 1 MHz 011 = 500 kHz 010 = 250 kHz 001 = 125 kHz 000 = 31 kHz (LFINTOSC) OSTS: Oscillator Start-up Time-out Status bit(1) 1 = Device is running from the external clock defined by FOSC<2:0> of the Configuration Word 0 = Device is running from the internal oscillator (HFINTOSC or LFINTOSC) HTS: HFINTOSC Status bit (High Frequency - 8 MHz to 125 kHz) 1 = HFINTOSC is stable 0 = HFINTOSC is not stable LTS: LFINTOSC Stable bit (Low Frequency - 31 kHz) 1 = LFINTOSC is stable 0 = LFINTOSC is not stable SCS: System Clock Select bit 1 = Internal oscillator is used for system clock 0 = Clock source defined by FOSC<2:0> of the Configuration Word Bit resets to `0' with Two-Speed Start-up and LP, XT or HS selected as the Oscillator mode or Fail-Safe mode is enabled.
bit 3
bit 2
bit 1
bit 0
Note 1:
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PIC16F688
3.3 Clock Source Modes 3.4
3.4.1
External Clock Modes
OSCILLATOR START-UP TIMER (OST)
Clock source modes can be classified as external or internal. * External Clock modes rely on external circuitry for the clock source. Examples are: oscillator modules (EC mode), quartz crystal resonators or ceramic resonators (LP, XT and HS modes) and Resistor-Capacitor (RC) mode circuits. * Internal clock sources are contained internally within the oscillator module. The oscillator module has two internal oscillators: the 8 MHz HighFrequency Internal Oscillator (HFINTOSC) and the 31 kHz Low-Frequency Internal Oscillator (LFINTOSC). The system clock can be selected between external or internal clock sources via the System Clock Select (SCS) bit of the OSCCON register. See Section 3.6 "Clock Switching" for additional information.
If the oscillator module is configured for LP, XT or HS modes, the Oscillator Start-up Timer (OST) counts 1024 oscillations from OSC1. This occurs following a Power-on Reset (POR) and when the Power-up Timer (PWRT) has expired (if configured), or a wake-up from Sleep. During this time, the program counter does not increment and program execution is suspended. The OST ensures that the oscillator circuit, using a quartz crystal resonator or ceramic resonator, has started and is providing a stable system clock to the oscillator module. When switching between clock sources, a delay is required to allow the new clock to stabilize. These oscillator delays are shown in Table 3-1. In order to minimize latency between external oscillator start-up and code execution, the Two-Speed Clock Start-up mode can be selected (see Section 3.7 "TwoSpeed Clock Start-up Mode").
TABLE 3-1:
OSCILLATOR DELAY EXAMPLES
Switch To LFINTOSC HFINTOSC EC, RC EC, RC LP, XT, HS HFINTOSC Frequency 31 kHz 125 kHz to 8 MHz DC - 20 MHz DC - 20 MHz 32 kHz to 20 MHz 125 kHz to 8 MHz Oscillator Delay Oscillator Warm-Up Delay (TWARM) 2 instruction cycles 1 cycle of each 1024 Clock Cycles (OST) 1 s (approx.)
Switch From Sleep/POR Sleep/POR LFINTOSC (31 kHz) Sleep/POR LFINTOSC (31 kHz)
3.4.2
EC MODE
FIGURE 3-2:
The External Clock (EC) mode allows an externally generated logic level as the system clock source. When operating in this mode, an external clock source is connected to the OSC1 input and the OSC2 is available for general purpose I/O. Figure 3-2 shows the pin connections for EC mode. The Oscillator Start-up Timer (OST) is disabled when EC mode is selected. Therefore, there is no delay in operation after a Power-on Reset (POR) or wake-up from Sleep. Because the PIC(R) MCU design is fully static, stopping the external clock input will have the effect of halting the device while leaving all data intact. Upon restarting the external clock, the device will resume operation as if no time had elapsed.
EXTERNAL CLOCK (EC) MODE OPERATION
OSC1/CLKIN PIC(R) MCU I/O OSC2/CLKOUT(1)
Clock from Ext. System
Note 1:
Alternate pin functions are listed in Section 1.0 "Device Overview".
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PIC16F688
3.4.3 LP, XT, HS MODES
The LP, XT and HS modes support the use of quartz crystal resonators or ceramic resonators connected to OSC1 and OSC2 (Figure 3-3). The mode selects a low, medium or high gain setting of the internal inverteramplifier to support various resonator types and speed. LP Oscillator mode selects the lowest gain setting of the internal inverter-amplifier. LP mode current consumption is the least of the three modes. This mode is best suited to drive resonators with a low drive level specification, for example, tuning fork type crystals. This mode is designed to drive only 32.768 kHz tuning fork type crystals (watch crystals). XT Oscillator mode selects the intermediate gain setting of the internal inverter-amplifier. XT mode current consumption is the medium of the three modes. This mode is best suited to drive resonators with a medium drive level specification. HS Oscillator mode selects the highest gain setting of the internal inverter-amplifier. HS mode current consumption is the highest of the three modes. This mode is best suited for resonators that require a high drive setting. Figure 3-3 and Figure 3-4 show typical circuits for quartz crystal and ceramic resonators, respectively. Note 1: Quartz crystal characteristics vary according to type, package and manufacturer. The user should consult the manufacturer data sheets for specifications and recommended application. 2: Always verify oscillator performance over the VDD and temperature range that is expected for the application. 3: For oscillator design assistance, reference the following Microchip Applications Notes: * AN826, "Crystal Oscillator Basics and Crystal Selection for rfPIC(R) and PIC(R) Devices" (DS00826) * AN849, "Basic PIC(R) Oscillator Design" (DS00849) * AN943, "Practical PIC(R) Oscillator Analysis and Design" (DS00943) * AN949, "Making Your Oscillator Work" (DS00949)
FIGURE 3-4:
CERAMIC RESONATOR OPERATION (XT OR HS MODE)
PIC(R) MCU
OSC1/CLKIN
FIGURE 3-3:
QUARTZ CRYSTAL OPERATION (LP, XT OR HS MODE)
C1
PIC(R) MCU
RP(3) OSC1/CLKIN C1 Quartz Crystal To Internal Logic RF(2) Sleep RF(2)
To Internal Logic Sleep
C2 Ceramic RS(1) Resonator
OSC2/CLKOUT
Note 1:
C2 RS(1) OSC2/CLKOUT
A series resistor (RS) may be required for ceramic resonators with low drive level.
2: The value of RF varies with the Oscillator mode selected (typically between 2 M to 10 M). 3: An additional parallel feedback resistor (RP) may be required for proper ceramic resonator operation.
Note 1: 2:
A series resistor (RS) may be required for quartz crystals with low drive level. The value of RF varies with the Oscillator mode selected (typically between 2 M to 10 M).
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3.4.4 EXTERNAL RC MODES
3.5
Internal Clock Modes
The external Resistor-Capacitor (RC) modes support the use of an external RC circuit. This allows the designer maximum flexibility in frequency choice while keeping costs to a minimum when clock accuracy is not required. There are two modes: RC and RCIO. In RC mode, the RC circuit connects to OSC1. OSC2/ CLKOUT outputs the RC oscillator frequency divided by 4. This signal may be used to provide a clock for external circuitry, synchronization, calibration, test or other application requirements. Figure 3-5 shows the external RC mode connections.
The oscillator module has two independent, internal oscillators that can be configured or selected as the system clock source. 1. The HFINTOSC (High-Frequency Internal Oscillator) is factory calibrated and operates at 8 MHz. The frequency of the HFINTOSC can be user-adjusted via software using the OSCTUNE register (Register 3-2). The LFINTOSC (Low-Frequency Internal Oscillator) is uncalibrated and operates at 31 kHz.
2.
FIGURE 3-5:
VDD REXT
EXTERNAL RC MODES
PIC(R) MCU
The system clock speed can be selected via software using the Internal Oscillator Frequency Select bits IRCF<2:0> of the OSCCON register. The system clock can be selected between external or internal clock sources via the System Clock Selection (SCS) bit of the OSCCON register. See Section 3.6 "Clock Switching" for more information.
OSC1/CLKIN CEXT VSS FOSC/4 or I/O(2) OSC2/CLKOUT(1)
Internal Clock
3.5.1
INTOSC AND INTOSCIO MODES
Recommended values: 10 k REXT 100 k, <3V 3 k REXT 100 k, 3-5V CEXT > 20 pF, 2-5V Note 1: 2: Alternate pin functions are listed in Section 1.0 "Device Overview". Output depends upon RC or RCIO clock mode.
The INTOSC and INTOSCIO modes configure the internal oscillators as the system clock source when the device is programmed using the oscillator selection or the FOSC<2:0> bits in the Configuration Word register (CONFIG). See Section 11.0 "Special Features of the CPU" for more information. In INTOSC mode, OSC1/CLKIN is available for general purpose I/O. OSC2/CLKOUT outputs the selected internal oscillator frequency divided by 4. The CLKOUT signal may be used to provide a clock for external circuitry, synchronization, calibration, test or other application requirements. In INTOSCIO mode, OSC1/CLKIN and OSC2/CLKOUT are available for general purpose I/O.
In RCIO mode, the RC circuit is connected to OSC1. OSC2 becomes an additional general purpose I/O pin. The RC oscillator frequency is a function of the supply voltage, the resistor (REXT) and capacitor (CEXT) values and the operating temperature. Other factors affecting the oscillator frequency are: * threshold voltage variation * component tolerances * packaging variations in capacitance The user also needs to take into account variation due to tolerance of external RC components used.
3.5.2
HFINTOSC
The High-Frequency Internal Oscillator (HFINTOSC) is a factory calibrated 8 MHz internal clock source. The frequency of the HFINTOSC can be altered via software using the OSCTUNE register (Register 3-2). The output of the HFINTOSC connects to a postscaler and multiplexer (see Figure 3-1). One of seven frequencies can be selected via software using the IRCF<2:0> bits of the OSCCON register. See Section 3.5.4 "Frequency Select Bits (IRCF)" for more information. The HFINTOSC is enabled by selecting any frequency between 8 MHz and 125 kHz by setting the IRCF<2:0> bits of the OSCCON register 000. Then, set the System Clock Source (SCS) bit of the OSCCON register to `1' or enable Two-Speed Start-up by setting the IESO bit in the Configuration Word register (CONFIG) to `1'. The HF Internal Oscillator (HTS) bit of the OSCCON register indicates whether the HFINTOSC is stable or not.
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3.5.2.1 OSCTUNE Register
The HFINTOSC is factory calibrated but can be adjusted in software by writing to the OSCTUNE register (Register 3-2). The default value of the OSCTUNE register is `0'. The value is a 5-bit two's complement number. When the OSCTUNE register is modified, the HFINTOSC frequency will begin shifting to the new frequency. Code execution continues during this shift. There is no indication that the shift has occurred. OSCTUNE does not affect the LFINTOSC frequency. Operation of features that depend on the LFINTOSC clock source frequency, such as the Power-up Timer (PWRT), Watchdog Timer (WDT), Fail-Safe Clock Monitor (FSCM) and peripherals, are not affected by the change in frequency.
REGISTER 3-2:
U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7-5 bit 4-0
OSCTUNE: OSCILLATOR TUNING REGISTER
U-0 -- U-0 -- R/W-0 TUN4 R/W-0 TUN3 R/W-0 TUN2 R/W-0 TUN1 R/W-0 TUN0 bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
Unimplemented: Read as `0' TUN<4:0>: Frequency Tuning bits 01111 = Maximum frequency 01110 = * * * 00001 = 00000 = Oscillator module is running at the calibrated frequency. 11111 = * * * 10000 = Minimum frequency
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3.5.3 LFINTOSC 3.5.5
The Low-Frequency Internal Oscillator (LFINTOSC) is an uncalibrated 31 kHz internal clock source. The output of the LFINTOSC connects to a postscaler and multiplexer (see Figure 3-1). Select 31 kHz, via software, using the IRCF<2:0> bits of the OSCCON register. See Section 3.5.4 "Frequency Select Bits (IRCF)" for more information. The LFINTOSC is also the frequency for the Power-up Timer (PWRT), Watchdog Timer (WDT) and Fail-Safe Clock Monitor (FSCM). The LFINTOSC is enabled by selecting 31 kHz (IRCF<2:0> bits of the OSCCON register = 000) as the system clock source (SCS bit of the OSCCON register = 1), or when any of the following are enabled: * Two-Speed Start-up IESO bit of the Configuration Word register = 1 and IRCF<2:0> bits of the OSCCON register = 000 * Power-up Timer (PWRT) * Watchdog Timer (WDT) * Fail-Safe Clock Monitor (FSCM) The LF Internal Oscillator (LTS) bit of the OSCCON register indicates whether the LFINTOSC is stable or not.
HF AND LF INTOSC CLOCK SWITCH TIMING
When switching between the LFINTOSC and the HFINTOSC, the new oscillator may already be shut down to save power (see Figure 3-6). If this is the case, there is a delay after the IRCF<2:0> bits of the OSCCON register are modified before the frequency selection takes place. The LTS and HTS bits of the OSCCON register will reflect the current active status of the LFINTOSC and HFINTOSC oscillators. The timing of a frequency selection is as follows: 1. 2. 3. 4. 5. IRCF<2:0> bits of the OSCCON register are modified. If the new clock is shut down, a clock start-up delay is started. Clock switch circuitry waits for a falling edge of the current clock. CLKOUT is held low and the clock switch circuitry waits for a rising edge in the new clock. CLKOUT is now connected with the new clock. LTS and HTS bits of the OSCCON register are updated as required. Clock switch is complete.
6.
See Figure 3-1 for more details. If the internal oscillator speed selected is between 8 MHz and 125 kHz, there is no start-up delay before the new frequency is selected. This is because the old and new frequencies are derived from the HFINTOSC via the postscaler and multiplexer. Start-up delay specifications are located in the Section 14.0 "Electrical Specifications", under the AC Specifications (Oscillator Module).
3.5.4
FREQUENCY SELECT BITS (IRCF)
The output of the 8 MHz HFINTOSC and 31 kHz LFINTOSC connects to a postscaler and multiplexer (see Figure 3-1). The Internal Oscillator Frequency Select bits IRCF<2:0> of the OSCCON register select the frequency output of the internal oscillators. One of eight frequencies can be selected via software: * * * * * * * * 8 MHz 4 MHz (Default after Reset) 2 MHz 1 MHz 500 kHz 250 kHz 125 kHz 31 kHz (LFINTOSC) Note: Following any Reset, the IRCF<2:0> bits of the OSCCON register are set to `110' and the frequency selection is set to 4 MHz. The user can modify the IRCF bits to select a different frequency.
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FIGURE 3-6:
LF(1) HF HFINTOSC HFINTOSC
Start-up Time 2-cycle Sync Running
INTERNAL OSCILLATOR SWITCH TIMING
LFINTOSC (FSCM and WDT disabled)
LFINTOSC IRCF <2:0> System Clock Note 1: When going from LF to HF. 0 =0
HFINTOSC HFINTOSC
LFINTOSC (Either FSCM or WDT enabled)
2-cycle Sync
Running
LFINTOSC IRCF <2:0> System Clock
0
=0
LFINTOSC LFINTOSC
HFINTOSC
LFINTOSC turns off unless WDT or FSCM is enabled
Start-up Time 2-cycle Sync
Running
HFINTOSC IRCF <2:0> System Clock =0
0
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3.6 Clock Switching
The system clock source can be switched between external and internal clock sources via software using the System Clock Select (SCS) bit of the OSCCON register. When the oscillator module is configured for LP, XT or HS modes, the Oscillator Start-up Timer (OST) is enabled (see Section 3.4.1 "Oscillator Start-up Timer (OST)"). The OST will suspend program execution until 1024 oscillations are counted. Two-Speed Start-up mode minimizes the delay in code execution by operating from the internal oscillator as the OST is counting. When the OST count reaches 1024 and the OSTS bit of the OSCCON register is set, program execution switches to the external oscillator.
3.6.1
SYSTEM CLOCK SELECT (SCS) BIT
The System Clock Select (SCS) bit of the OSCCON register selects the system clock source that is used for the CPU and peripherals. * When the SCS bit of the OSCCON register = 0, the system clock source is determined by configuration of the FOSC<2:0> bits in the Configuration Word register (CONFIG). * When the SCS bit of the OSCCON register = 1, the system clock source is chosen by the internal oscillator frequency selected by the IRCF<2:0> bits of the OSCCON register. After a Reset, the SCS bit of the OSCCON register is always cleared. Note: Any automatic clock switch, which may occur from Two-Speed Start-up or Fail-Safe Clock Monitor, does not update the SCS bit of the OSCCON register. The user can monitor the OSTS bit of the OSCCON register to determine the current system clock source.
3.7.1
TWO-SPEED START-UP MODE CONFIGURATION
Two-Speed Start-up mode is configured by the following settings: * IESO (of the Configuration Word register) = 1; Internal/External Switchover bit (Two-Speed Startup mode enabled). * SCS (of the OSCCON register) = 0. * FOSC<2:0> bits in the Configuration Word register (CONFIG) configured for LP, XT or HS mode. Two-Speed Start-up mode is entered after: * Power-on Reset (POR) and, if enabled, after Power-up Timer (PWRT) has expired, or * Wake-up from Sleep. If the external clock oscillator is configured to be anything other than LP, XT or HS mode, then TwoSpeed Start-up is disabled. This is because the external clock oscillator does not require any stabilization time after POR or an exit from Sleep.
3.6.2
OSCILLATOR START-UP TIME-OUT STATUS (OSTS) BIT
The Oscillator Start-up Time-out Status (OSTS) bit of the OSCCON register indicates whether the system clock is running from the external clock source, as defined by the FOSC<2:0> bits in the Configuration Word register (CONFIG), or from the internal clock source. In particular, OSTS indicates that the Oscillator Start-up Timer (OST) has timed out for LP, XT or HS modes.
3.7.2
1. 2.
TWO-SPEED START-UP SEQUENCE
3.7
Two-Speed Clock Start-up Mode
3. 4. 5. 6. 7.
Two-Speed Start-up mode provides additional power savings by minimizing the latency between external oscillator start-up and code execution. In applications that make heavy use of the Sleep mode, Two-Speed Start-up will remove the external oscillator start-up time from the time spent awake and can reduce the overall power consumption of the device. This mode allows the application to wake-up from Sleep, perform a few instructions using the INTOSC as the clock source and go back to Sleep without waiting for the primary oscillator to become stable. Note: Executing a SLEEP instruction will abort the oscillator start-up time and will cause the OSTS bit of the OSCCON register to remain clear.
Wake-up from Power-on Reset or Sleep. Instructions begin execution by the internal oscillator at the frequency set in the IRCF<2:0> bits of the OSCCON register. OST enabled to count 1024 clock cycles. OST timed out, wait for falling edge of the internal oscillator. OSTS is set. System clock held low until the next falling edge of new clock (LP, XT or HS mode). System clock is switched to external clock source.
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3.7.3 CHECKING TWO-SPEED CLOCK STATUS
Checking the state of the OSTS bit of the OSCCON register will confirm if the microcontroller is running from the external clock source, as defined by the FOSC<2:0> bits in the Configuration Word register (CONFIG), or the internal oscillator.
FIGURE 3-7:
TWO-SPEED START-UP
HFINTOSC T TOST OSC1 0 1 1022 1023
OSC2 Program Counter PC - N PC PC + 1
System Clock
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3.8 Fail-Safe Clock Monitor
3.8.3 FAIL-SAFE CONDITION CLEARING
The Fail-Safe Clock Monitor (FSCM) allows the device to continue operating should the external oscillator fail. The FSCM can detect oscillator failure any time after the Oscillator Start-up Timer (OST) has expired. The FSCM is enabled by setting the FCMEN bit in the Configuration Word register (CONFIG). The FSCM is applicable to all external oscillator modes (LP, XT, HS, EC, RC and RCIO). The Fail-Safe condition is cleared after a Reset, executing a SLEEP instruction or toggling the SCS bit of the OSCCON register. When the SCS bit is toggled, the OST is restarted. While the OST is running, the device continues to operate from the INTOSC selected in OSCCON. When the OST times out, the Fail-Safe condition is cleared and the device will be operating from the external clock source. The Fail-Safe condition must be cleared before the OSFIF flag can be cleared.
FIGURE 3-8:
FSCM BLOCK DIAGRAM
Clock Monitor Latch S Q
3.8.4
RESET OR WAKE-UP FROM SLEEP
External Clock
LFINTOSC Oscillator 31 kHz (~32 s)
/ 64 488 Hz (~2 ms)
R
Q
The FSCM is designed to detect an oscillator failure after the Oscillator Start-up Timer (OST) has expired. The OST is used after waking up from Sleep and after any type of Reset. The OST is not used with the EC or RC Clock modes so that the FSCM will be active as soon as the Reset or wake-up has completed. When the FSCM is enabled, the Two-Speed Start-up is also enabled. Therefore, the device will always be executing code while the OST is operating. Note:
Clock Failure Detected
Sample Clock
3.8.1
FAIL-SAFE DETECTION
The FSCM module detects a failed oscillator by comparing the external oscillator to the FSCM sample clock. The sample clock is generated by dividing the LFINTOSC by 64. See Figure 3-8. Inside the fail detector block is a latch. The external clock sets the latch on each falling edge of the external clock. The sample clock clears the latch on each rising edge of the sample clock. A failure is detected when an entire halfcycle of the sample clock elapses before the primary clock goes low.
Due to the wide range of oscillator start-up times, the Fail-Safe circuit is not active during oscillator start-up (i.e., after exiting Reset or Sleep). After an appropriate amount of time, the user should check the OSTS bit of the OSCCON register to verify the oscillator start-up and that the system clock switchover has successfully completed.
3.8.2
FAIL-SAFE OPERATION
When the external clock fails, the FSCM switches the device clock to an internal clock source and sets the bit flag OSFIF of the PIR2 register. Setting this flag will generate an interrupt if the OSFIE bit of the PIE2 register is also set. The device firmware can then take steps to mitigate the problems that may arise from a failed clock. The system clock will continue to be sourced from the internal clock source until the device firmware successfully restarts the external oscillator and switches back to external operation. The internal clock source chosen by the FSCM is determined by the IRCF<2:0> bits of the OSCCON register. This allows the internal oscillator to be configured before a failure occurs.
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FIGURE 3-9:
Sample Clock System Clock Output Clock Monitor Output (Q) Failure Detected OSCFIF Oscillator Failure
FSCM TIMING DIAGRAM
Test Note:
Test
Test
The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in this example have been chosen for clarity.
TABLE 3-2:
Name CONFIG(2) INTCON OSCCON OSCTUNE PIE1 PIR1 Legend: Note 1: 2:
SUMMARY OF REGISTERS ASSOCIATED WITH CLOCK SOURCES
Bit 7 CPD GIE -- -- EEIE EEIF Bit 6 CP PEIE IRCF2 -- ADIE ADIF Bit 5 MCLRE T0IE IRCF1 -- RCIE RCIF Bit 4 PWRTE INTE IRCF0 TUN4 C2IE C2IF Bit 3 WDTE RAIE OSTS TUN3 C1IE C1IF Bit 2 FOSC2 T0IF HTS TUN2 OSFIE OSFIF Bit 1 FOSC1 INTF LTS TUN1 TXIE TXIF Bit 0 FOSC0 RAIF SCS TUN0 TMR1IE TMR1IF Value on POR, BOR -- 0000 000x -110 x000 ---0 0000 0000 0000 0000 0000 Value on all other Resets(1) -- 0000 000x -110 x000 ---u uuuu 0000 0000 0000 0000
x = unknown, u = unchanged, - = unimplemented locations read as `0'. Shaded cells are not used by oscillators. Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation. See Configuration Word register (CONFIG) for operation of all register bits.
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4.0 I/O PORTS
There are as many as twelve general purpose I/O pins available. Depending on which peripherals are enabled, some or all of the pins may not be available as general purpose I/O. In general, when a peripheral is enabled, the associated pin may not be used as a general purpose I/O pin. Therefore, a write to a port implies that the port pins are read, this value is modified and then written to the PORT data latch. RA3 reads `0' when MCLRE = 1. The TRISA register controls the direction of the PORTA pins, even when they are being used as analog inputs. The user must ensure the bits in the TRISA register are maintained set when using them as analog inputs. I/O pins configured as analog input always read `0'. Note: The ANSEL and CMCON0 registers must be initialized to configure an analog channel as a digital input. Pins configured as analog inputs will read `0'.
4.1
PORTA and the TRISA Registers
PORTA is a 6-bit wide, bidirectional port. The corresponding data direction register is TRISA. Setting a TRISA bit (= 1) will make the corresponding PORTA pin an input (i.e., put the corresponding output driver in a High-Impedance mode). Clearing a TRISA bit (= 0) will make the corresponding PORTA pin an output (i.e., put the contents of the output latch on the selected pin). The exception is RA3, which is input only and its TRISA bit will always read as `1'. Example 4-1 shows how to initialize PORTA. Reading the PORTA register reads the status of the pins, whereas writing to it will write to the PORT latch. All write operations are read-modify-write operations.
EXAMPLE 4-1:
BANKSEL CLRF MOVLW MOVWF BANKSEL CLRF MOVLW MOVWF PORTA PORTA 07h CMCON0 ANSEL ANSEL 0Ch TRISA
INITIALIZING PORTA
; ;Init PORTA ;Set RA<2:0> to ;digital I/O ; ;digital I/O ;Set RA<3:2> as inputs ;and set RA<5:4,1:0> ;as outputs
REGISTER 4-1:
U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7-6 bit 5-0
PORTA: PORTA REGISTER
U-0 -- R/W-x RA5 R/W-0 RA4 R-x RA3 R/W-0 RA2 R/W-0 RA1
R/W-0
RA0
bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
Unimplemented: Read as `0' RA<5:0>: PORTA I/O Pin bit 1 = Port pin is > VIH 0 = Port pin is < VIL
REGISTER 4-2:
U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7-6 bit 5-0
TRISA: PORTA TRI-STATE REGISTER
U-0 -- R/W-1 TRISA5 R/W-1 TRISA4 R-1 TRISA3 R/W-1 TRISA2 R/W-1 TRISA1 R/W-1 TRISA0 bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
Unimplemented: Read as `0' TRISA<5:0>: PORTA Tri-State Control bits 1 = PORTA pin configured as an input (tri-stated) 0 = PORTA pin configured as an output TRISA<3> always reads `1'. TRISA<5:4> always reads `1' in XT, HS and LP Oscillator modes.
Note 1: 2:
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4.2 Additional Pin Functions
4.2.3 INTERRUPT-ON-CHANGE
Every PORTA pin on the PIC16F688 has an interrupton-change option and a weak pull-up option. PORTA also provides an Ultra Low-Power Wake-up option. The next three sections describe these functions. Each of the PORTA pins is individually configurable as an interrupt-on-change pin. Control bits IOCAx enable or disable the interrupt function for each pin. Refer to Register 4-5. The interrupt-on-change is disabled on a Power-on Reset. For enabled interrupt-on-change pins, the values are compared with the old value latched on the last read of PORTA. The `mismatch' outputs of the last read are OR'd together to set the PORTA Change Interrupt Flag bit (RAIF) in the INTCON register. This interrupt can wake the device from Sleep. The user, in the Interrupt Service Routine, clears the interrupt by: a) b) Any read or write of PORTA. This will end the mismatch condition, then Clear the flag bit RAIF.
4.2.1
ANSEL REGISTER
The ANSEL register is used to configure the Input mode of an I/O pin to analog. Refer to Register 4-3. Setting the appropriate ANSEL bit high will cause all digital reads on the pin to be read as `0' and allow analog functions on the pin to operate correctly. The state of the ANSEL bits has no affect on digital output functions. A pin with TRIS clear and ANSEL set will still operate as a digital output, but the Input mode will be analog. This can cause unexpected behavior when executing read-modify-write instructions on the affected port.
4.2.2
WEAK PULL-UPS
Each of the PORTA pins, except RA3, has an individually configurable internal weak pull-up. Control bits WPUAx enable or disable each pull-up. Refer to Register 4-4. Each weak pull-up is automatically turned off when the port pin is configured as an output. The pull-ups are disabled on a Power-on Reset by the RAPU bit of the OPTION register. A weak pull-up is automatically enabled for RA3 when configured as MCLR and disabled when RA3 is an I/O. There is no software control of the MCLR pull-up.
A mismatch condition will continue to set flag bit RAIF. Reading PORTA will end the mismatch condition and allow flag bit RAIF to be cleared. The latch holding the last read value is not affected by a MCLR nor BOR Reset. After these Resets, the RAIF flag will continue to be set if a mismatch is present. Note: If a change on the I/O pin should occur when the read operation is being executed (start of the Q2 cycle), then the RAIF interrupt flag may not get set.
REGISTER 4-3:
R/W-1 ANS7 bit 7 Legend: R = Readable bit -n = Value at POR bit 7-0
ANSEL: ANALOG SELECT REGISTER
R/W-1 ANS6 R/W-1 ANS5 R/W-1 ANS4 R/W-1 ANS3 R/W-1 ANS2 R/W-1 ANS1 R/W-1 ANS0 bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
ANS<7:0>: Analog Select bits Analog select between analog or digital function on pins AN<7:0>, respectively. 1 = Analog input. Pin is assigned as analog input(1). 0 = Digital I/O. Pin is assigned to port or special function. Setting a pin to an analog input automatically disables the digital input circuitry, weak pull-ups and interrupt-on-change, if available. The corresponding TRIS bit must be set to Input mode in order to allow external control of the voltage on the pin.
Note 1:
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REGISTER 4-4:
U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7-6 bit 5-4 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
WPUA: WEAK PULL-UP PORTA REGISTER
U-0 -- R/W-1 WPUA5 R/W-1 WPUA4 U-0 -- R/W-1 WPUA2 R/W-1 WPUA1 R/W-1 WPUA0 bit 0
Unimplemented: Read as `0' WPUA<5:4>: Weak Pull-up Control bits 1 = Pull-up enabled 0 = Pull-up disabled Unimplemented: Read as `0' WPUA<2:0>: Weak Pull-up Control bits 1 = Pull-up enabled 0 = Pull-up disabled Global RAPU must be enabled for individual pull-ups to be enabled. The weak pull-up device is automatically disabled if the pin is in Output mode (TRISA = 0). The RA3 pull-up is enabled when configured as MCLR and disabled as an I/O in the Configuration Word. WPUA<5:4> always reads `1' in XT, HS and LP OSC modes.
bit 3 bit 2-0
Note 1: 2: 3: 4:
REGISTER 4-5:
U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7-6 bit 5-0
IOCA: INTERRUPT-ON-CHANGE PORTA REGISTER
U-0 -- R/W-0 IOCA5 R/W-0 IOCA4 R/W-0 IOCA3 R/W-0 IOCA2 R/W-0 IOCA1 R/W-0 IOCA0 bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
Unimplemented: Read as `0' IOCA<5:0>: Interrupt-on-change PORTA Control bits 1 = Interrupt-on-change enabled 0 = Interrupt-on-change disabled Global Interrupt Enable (GIE) must be enabled for individual interrupts to be recognized. IOCA<5:4> always reads `1' in XT, HS and LP OSC modes.
Note 1: 2:
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PIC16F688
4.2.4 ULTRA LOW-POWER WAKE-UP EXAMPLE 4-2:
BANKSEL BSF MOVLW MOVWF BANKSEL BCF BANKSEL BCF CALL BSF BSF BSF MOVLW MOVWF SLEEP NOP
The Ultra Low-Power Wake-up (ULPWU) on RA0 allows a slow falling voltage to generate an interrupton-change on RA0 without excess current consumption. The mode is selected by setting the ULPWUE bit of the PCON register. This enables a small current sink which can be used to discharge a capacitor on RA0. To use this feature, the RA0 pin is configured to output `1' to charge the capacitor, interrupt-on-change for RA0 is enabled, and RA0 is configured as an input. The ULPWUE bit is set to begin the discharge and a SLEEP instruction is performed. When the voltage on RA0 drops below VIL, an interrupt will be generated which will cause the device to wake-up. Depending on the state of the GIE bit of the INTCON register, the device will either jump to the interrupt vector (0004h) or execute the next instruction when the interrupt event occurs. See Section 4.2.3 "INTERRUPT-ONCHANGE" and Section 11.3.3 "PORTA Interrupt" for more information. This feature provides a low-power technique for periodically waking up the device from Sleep. The time-out is dependent on the discharge time of the RC circuit on RA0. See Example 4-2 for initializing the Ultra Low-Power Wake-up module. The series resistor provides overcurrent protection for the RA0 pin and can allow for software calibration of the time-out. (see Figure 4-1). A timer can be used to measure the charge time and discharge time of the capacitor. The charge time can then be adjusted to provide the desired interrupt delay. This technique will compensate for the affects of temperature, voltage and component accuracy. The Ultra Low-Power Wake-up peripheral can also be configured as a simple programmable low voltage detect or temperature sensor. Note: For more information, refer to Application Note AN879, "Using the Microchip Ultra Low-Power Wake-up Module" (DS00879).
ULTRA LOW-POWER WAKE-UP INITIALIZATION
; ;Set RA0 data latch ;Turn off ; comparators ; ;RA0 to digital I/O ; ;Output high to ; charge capacitor ;Enable ULP Wake-up ;Select RA0 IOC ;RA0 to input ;Enable interrupt ; and clear flag ;Wait for IOC ;
PORTA PORTA,0 H'7' CMCON0 ANSEL ANSEL,0 TRISA TRISA,0 CapDelay PCON,ULPWUE IOCA,0 TRISA,0 B'10001000' INTCON
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4.2.5 PIN DESCRIPTIONS AND DIAGRAMS 4.2.5.1 RA0/AN0/C1IN+/ICSPDAT/ULPWU
Each PORTA pin is multiplexed with other functions. The pins and their combined functions are briefly described here. For specific information about individual functions such as the comparator or the A/D, refer to the appropriate section in this data sheet. Figure 4-1 shows the diagram for this pin. The RA0 pin is configurable to function as one of the following: * * * * * a general purpose I/O an analog input for the A/D an analog input to the comparator an analog input to the Ultra Low-Power Wake-up In-Circuit Serial ProgrammingTM data
FIGURE 4-1:
BLOCK DIAGRAM OF RA0
Analog(1) Input Mode VDD
Data Bus D WR WPUDA RD WPUDA Q Weak RAPU CK Q
VDD
D WR PORTA
Q I/O PIN
CK Q
VSS
+ D WR TRISA RD TRISA RD PORTA D WR IOCA RD IOCA Q Q D EN Q D EN Interrupt-onChange RD PORTA To Comparator To A/D Converter Q3 Q IULP 0 Analog(1) Input Mode 1 Vss ULPWUE
VT
CK Q
CK Q
Note
1:
Comparator mode and ANSEL determines analog Input mode.
(c) 2009 Microchip Technology Inc.
DS41203E-page 37
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4.2.5.2 RA1/AN1/C1IN-/VREF/ICSPCLK 4.2.5.3 RA2/AN2/T0CKI/INT/C1OUT
Figure 4-2 shows the diagram for this pin. The RA1 pin is configurable to function as one of the following: * * * * * a general purpose I/O an analog input for the A/D an analog input to the comparator a voltage reference input for the A/D In-Circuit Serial ProgrammingTM clock Figure 4-3 shows the diagram for this pin. The RA2 pin is configurable to function as one of the following: * * * * * a general purpose I/O an analog input for the A/D the clock input for Timer0 an external edge triggered interrupt a digital output from the comparator
FIGURE 4-2:
Data Bus WR WPUA RD WPUA
BLOCK DIAGRAM OF RA1
Analog(1) Input Mode VDD Weak RAPU
FIGURE 4-3:
Data Bus WR WPUA RD WPUA
BLOCK DIAGRAM OF RA2
Analog(1) Input Mode VDD Weak RAPU C1OUT Enable
D
Q
D CK
Q Q
CK Q
D WR PORTA
Q
VDD WR PORTA I/O pin
D CK
Q Q C1OUT 1 0
VDD
CK Q
I/O pin
D WR TRISA RD TRISA RD PORTA D WR IOCA RD IOCA
Q VSS Analog Input Mode
(1)
D WR TRISA RD TRISA RD PORTA CK
Q Q Analog(1) Input Mode VSS
CK Q
Q Q D EN Q D EN Q3 WR IOCA RD IOCA
D CK
Q Q Q EN Q D EN Q3 D
CK Q
Interrupt-onchange RD PORTA To Comparator To A/D Converter
Interrupt-onchange
RD PORTA
To Timer0 To INT To A/D Converter
Note
1:
Comparator mode and ANSEL determines analog Input mode.
Note
1:
Analog Input mode is based upon ANSEL.
DS41203E-page 38
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PIC16F688
4.2.5.4 RA3/MCLR/VPP 4.2.5.5 RA4/AN3/T1G/OSC2/CLKOUT
Figure 4-4 shows the diagram for this pin. The RA3 pin is configurable to function as one of the following: * a general purpose input * as Master Clear Reset with weak pull-up Figure 4-5 shows the diagram for this pin. The RA4 pin is configurable to function as one of the following: * * * * * a general purpose I/O an analog input for the A/D a Timer1 gate input a crystal/resonator connection a clock output
FIGURE 4-4:
BLOCK DIAGRAM OF RA3
VDD MCLRE Weak
FIGURE 4-5:
BLOCK DIAGRAM OF RA4
Analog(3) Input Mode
Data Bus
Reset VSS
MCLRE
Input pin
RD TRISA RD PORTA D WR IOCA RD IOCA CK Q
Data Bus WR WPUA RD WPUA
CLK(1) Modes VDD Weak
D CK
Q Q RAPU Oscillator Circuit OSC1 CLKOUT Enable
MCLRE
VSS
Q Q
D EN Q3
VDD
Q
D EN WR PORTA D CK Q Q CLKOUT Enable VSS D WR TRISA RD TRISA RD PORTA D WR IOCA RD IOCA CK Q Q Q EN Q D EN Q3 D CK Q Q INTOSC/ RC/EC(2) CLKOUT Enable Analog(3) Input Mode Fosc/4 1 0 I/O pin
Interrupt-onchange
RD PORTA
Interrupt-onchange
RD PORTA To T1G To A/D Converter Note 1: CLK modes are XT, HS, LP, LPTMR1 and CLKOUT Enable. 2: With CLKOUT option. 3: Analog Input mode is ANSEL.
(c) 2009 Microchip Technology Inc.
DS41203E-page 39
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4.2.5.6 RA5/T1CKI/OSC1/CLKIN FIGURE 4-6: BLOCK DIAGRAM OF RA5
INTOSC Mode Data Bus WR WPUA RD WPUA D CK Q Q RAPU Oscillator Circuit OSC2 D WR PORTA CK Q Q VDD TMR1LPEN(1) VDD Weak
Figure 4-6 shows the diagram for this pin. The RA5 pin is configurable to function as one of the following: * * * * a general purpose I/O a Timer1 clock input a crystal/resonator connection a clock input
D WR TRISA RD TRISA RD PORTA D WR IOCA RD IOCA CK CK
Q Q INTOSC Mode VSS
I/O pin
(2) Q Q Q EN Q3 D
Q
D EN
Interrupt-onchange
RD PORTA To Timer1 or CLKGEN Note 1: Timer1 LP oscillator enabled.
2: When using Timer1 with LP oscillator, the Schmitt Trigger is bypassed.
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PIC16F688
TABLE 4-1:
Name ANSEL CMCON0 PCON INTCON IOCA OPTION_REG PORTA TRISA WPUA Legend:
SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Bit 7 ANS7 C2OUT -- GIE -- RAPU -- -- -- Bit 6 ANS6 C1OUT -- PEIE -- INTEDG -- -- -- Bit 5 ANS5 C2INV ULPWUE T0IE IOCA5 T0CS RA5 TRISA5 WPUA5 Bit 4 ANS4 C1INV SBOREN INTE IOCA4 T0SE RA4 TRISA4 WPUA4 Bit 3 ANS3 CIS -- RAIE IOCA3 PSA RA3 TRISA3 -- Bit 2 ANS2 CM2 -- T0IF IOCA2 PS2 RA2 TRISA2 WPUA2 Bit 1 ANS1 CM1 POR INTF IOCA1 PS1 RA1 TRISA1 WPUA1 Bit 0 ANS0 CM0 BOR RAIF IOCA0 PS0 RA0 TRISA0 WPUA0 Value on POR, BOR 1111 1111 0000 0000 --01 --qq 0000 000x --00 0000 1111 1111 --x0 x000 --11 1111 --11 -111 Value on all other Resets 1111 1111 0000 0000 --0u --uu 0000 000x --00 0000 1111 1111 --x0 x000 --11 1111 --11 -111
x = unknown, u = unchanged, - = unimplemented locations read as `0'. Shaded cells are not used by PORTA.
(c) 2009 Microchip Technology Inc.
DS41203E-page 41
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4.3 PORTC
EXAMPLE 4-3:
BANKSEL CLRF MOVLW MOVWF BANKSEL CLRF MOVLW MOVWF PORTC PORTC 07h CMCON0 ANSEL ANSEL 0Ch TRISC
INITIALIZING PORTC
; ;Init PORTC ;Set RC<4,1:0> to ;digital I/O ; ;digital I/O ;Set RC<3:2> as inputs ;and set RC<5:4,1:0> ;as outputs
PORTC is a general purpose I/O port consisting of 6 bidirectional pins. The pins can be configured for either digital I/O or analog input to A/D converter or comparator. For specific information about individual functions such as the EUSART or the A/D converter, refer to the appropriate section in this data sheet. Note: The ANSEL and CMCON0 registers must be initialized to configure an analog channel as a digital input. Pins configured as analog inputs will read `0'.
REGISTER 4-6:
U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7-6 bit 5-0
PORTC: PORTC REGISTER
U-0 -- R/W-x RC5 R/W-x RC4 R/W-0 RC3 R/W-0 RC2 R/W-0 RC1 R/W-0 RC0 bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
Unimplemented: Read as `0' RC<5:0>: PORTC I/O Pin bit 1 = PORTC pin is > VIH 0 = PORTC pin is < VIL
REGISTER 4-7:
U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7-6 bit 5-0
TRISC: PORTC TRI-STATE REGISTER
U-0 -- R/W-1 TRISC5 R/W-1 TRISC4 R/W-1 TRISC3 R/W-1 TRISC2 R/W-1 TRISC1 R/W-1 TRISC0 bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
Unimplemented: Read as `0' TRISC<5:0>: PORTC Tri-State Control bits 1 = PORTC pin configured as an input (tri-stated) 0 = PORTC pin configured as an output
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4.3.1 RC0/AN4/C2IN+ 4.3.3 RC2/AN6
Figure 4-7 shows the diagram for this pin. The RC0 is configurable to function as one of the following: * a general purpose I/O * an analog input for the A/D Converter * an analog input to the comparator Figure 4-8 shows the diagram for this pin. The RC2 is configurable to function as one of the following: * a general purpose I/O * an analog input for the A/D Converter
4.3.4
RC3/AN7
4.3.2
RC1/AN5/C2IN-
Figure 4-7 shows the diagram for this pin. The RC1 is configurable to function as one of the following: * a general purpose I/O * an analog input for the A/D Converter * an analog input to the comparator
Figure 4-8 shows the diagram for this pin. The RC3 is configurable to function as one of the following: * a general purpose I/O * an analog input for the A/D Converter
FIGURE 4-8:
Data Bus
BLOCK DIAGRAM OF RC2 AND RC3
FIGURE 4-7:
Data Bus
BLOCK DIAGRAM OF RC0 AND RC1
D VDD WR PORTC CK
Q Q
VDD
D WR PORTC CK
Q Q
I/O Pin D I/O Pin WR TRISC RD TRISC RD PORTC To A/D Converter CK Q Q Analog Input Mode(1) VSS
D WR TRISC RD TRISC RD PORTC CK
Q Q Analog Input Mode(1) VSS
To Comparators To A/D Converter Note 1: Analog Input mode is based upon Comparator mode and ANSEL.
Note
1:
Analog Input mode comes from ANSEL.
(c) 2009 Microchip Technology Inc.
DS41203E-page 43
PIC16F688
4.3.5 RC4/C2OUT/TX/CK 4.3.6 RC5/RX/DT
Figure 4-9 shows the diagram for this pin. The RC4 is configurable to function as one of the following: * a general purpose I/O * a digital output from the comparator * a digital I/O for the EUSART The RC5 is configurable to function as one of the following: * a general purpose I/O * a digital I/O for the EUSART
FIGURE 4-10: FIGURE 4-9:
USART Select(1) C2OUT EN
BLOCK DIAGRAM OF RC4
Data Bus
BLOCK DIAGRAM OF RC5 PIN
EUSART Out Enable
D VDD 0 0 1 1 D WR PORTC Q I/O Pin VSS WR TRISC RD TRISC RD PORTC D CK WR PORTC CK
Q Q EUSART DT Out 1 0 Q Q
VDD
EUSART TX/CLKOUT Data Bus C2OUT
I/O Pin
VSS
CK Q
D WR TRISC RD TRISC RD PORTC
Q
CK Q
To EUSART RX/DT In
To EUSART CLK Input
Note
1:
USART Select signals selects between port data and peripheral output.
TABLE 4-2:
Name ANSEL CMCON0 PORTC TRISC Legend: Bit 7 ANS7
SUMMARY OF REGISTERS ASSOCIATED WITH PORTC
Bit 6 ANS6 C1OUT -- -- Bit 5 ANS5 C2INV RC5 TRISC5 Bit 4 ANS4 C1INV RC4 TRISC4 Bit 3 ANS3 CIS RC3 TRISC3 Bit 2 ANS2 CM2 RC2 TRISC2 Bit 1 ANS1 CM1 RC1 TRISC1 Bit 0 ANS0 CM0 RC0 TRISC0 Value on POR, BOR 1111 1111 0000 0000 --xx 0000 --11 1111 Value on all other Resets 1111 1111 0000 0000 --xx 0000 --11 1111
C2OUT -- --
x = unknown, u = unchanged, - = unimplemented locations read as `0'. Shaded cells are not used by PORTC.
DS41203E-page 44
(c) 2009 Microchip Technology Inc.
PIC16F688
5.0 TIMER0 MODULE
5.1 Timer0 Operation
The Timer0 module is an 8-bit timer/counter with the following features: * * * * * 8-bit timer/counter register (TMR0) 8-bit prescaler (shared with Watchdog Timer) Programmable internal or external clock source Programmable external clock edge selection Interrupt on overflow When used as a timer, the Timer0 module can be used as either an 8-bit timer or an 8-bit counter.
5.1.1
8-BIT TIMER MODE
When used as a timer, the Timer0 module will increment every instruction cycle (without prescaler). Timer mode is selected by clearing the T0CS bit of the OPTION register to `0'. When TMR0 is written, the increment is inhibited for two instruction cycles immediately following the write. Note: The value written to the TMR0 register can be adjusted, in order to account for the two instruction cycle delay when TMR0 is written.
Figure 5-1 is a block diagram of the Timer0 module.
5.1.2
8-BIT COUNTER MODE
When used as a counter, the Timer0 module will increment on every rising or falling edge of the T0CKI pin. The incrementing edge is determined by the T0SE bit of the OPTION register. Counter mode is selected by setting the T0CS bit of the OPTION register to `1'.
FIGURE 5-1:
FOSC/4
BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER
Data Bus 0 1 1 T0CKI pin T0SE T0CS 1 8 0 0 8-bit Prescaler PSA Set Flag bit T0IF on Overflow Sync 2 Tcy TMR0 8
WDTE SWDTEN
PSA
PS<2:0> 16-bit Prescaler 31 kHz INTOSC Watchdog Timer WDTPS<3:0>
Note 1: 2: 3: T0SE, T0CS, PSA, PS<2:0> are bits in the OPTION register. SWDTEN and WDTPS<3:0> are bits in the WDTCON register. WDTE bit is in the Configuration Word register.
1 WDT Time-out 0
16 PSA
(c) 2009 Microchip Technology Inc.
DS41203E-page 45
PIC16F688
5.1.3 SOFTWARE PROGRAMMABLE PRESCALER
A single software programmable prescaler is available for use with either Timer0 or the Watchdog Timer (WDT), but not both simultaneously. The prescaler assignment is controlled by the PSA bit of the OPTION register. To assign the prescaler to Timer0, the PSA bit must be cleared to a `0'. There are 8 prescaler options for the Timer0 module ranging from 1:2 to 1:256. The prescale values are selectable via the PS<2:0> bits of the OPTION register. In order to have a 1:1 prescaler value for the Timer0 module, the prescaler must be assigned to the WDT module. The prescaler is not readable or writable. When assigned to the Timer0 module, all instructions writing to the TMR0 register will clear the prescaler. When the prescaler is assigned to WDT, a CLRWDT instruction will clear the prescaler along with the WDT. When changing the prescaler assignment from the WDT to the Timer0 module, the following instruction sequence must be executed (see Example 5-2).
EXAMPLE 5-2:
CLRWDT
CHANGING PRESCALER (WDT TIMER0)
;Clear WDT and ;prescaler BANKSEL OPTION_REG ; MOVLW b'11110000' ;Mask TMR0 select and ANDWF OPTION_REG,W ;prescaler bits IORLW b'00000011' ;Set prescale to 1:16 MOVWF OPTION_REG ;
5.1.4
TIMER0 INTERRUPT
5.1.3.1
Switching Prescaler Between Timer0 and WDT Modules
Timer0 will generate an interrupt when the TMR0 register overflows from FFh to 00h. The T0IF interrupt flag bit of the INTCON register is set every time the TMR0 register overflows, regardless of whether or not the Timer0 interrupt is enabled. The T0IF bit must be cleared in software. The Timer0 interrupt enable is the T0IE bit of the INTCON register. Note: The Timer0 interrupt cannot wake the processor from Sleep since the timer is frozen during Sleep.
As a result of having the prescaler assigned to either Timer0 or the WDT, it is possible to generate an unintended device Reset when switching prescaler values. When changing the prescaler assignment from Timer0 to the WDT module, the instruction sequence shown in Example 5-1, must be executed.
5.1.5
USING TIMER0 WITH AN EXTERNAL CLOCK
EXAMPLE 5-1:
BANKSEL CLRWDT CLRF BANKSEL BSF CLRWDT MOVLW ANDWF IORLW MOVWF TMR0
CHANGING PRESCALER (TIMER0 WDT)
; ;Clear WDT TMR0 ;Clear TMR0 and ;prescaler OPTION_REG ; OPTION_REG,PSA ;Select WDT ; ; b'11111000' ;Mask prescaler OPTION_REG,W ;bits b'00000101' ;Set WDT prescaler OPTION_REG ;to 1:32
When Timer0 is in Counter mode, the synchronization of the T0CKI input and the Timer0 register is accomplished by sampling the prescaler output on the Q2 and Q4 cycles of the internal phase clocks. Therefore, the high and low periods of the external clock source must meet the timing requirements as shown in Section 14.0 "Electrical Specifications".
DS41203E-page 46
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REGISTER 5-1:
R/W-1 RAPU bit 7 Legend: R = Readable bit -n = Value at POR bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
OPTION_REG: OPTION REGISTER
R/W-1 INTEDG R/W-1 T0CS R/W-1 T0SE R/W-1 PSA R/W-1 PS2 R/W-1 PS1 R/W-1 PS0 bit 0
RAPU: PORTA Pull-up Enable bit 1 = PORTA pull-ups are disabled 0 = PORTA pull-ups are enabled by individual PORT latch values INTEDG: Interrupt Edge Select bit 1 = Interrupt on rising edge of INT pin 0 = Interrupt on falling edge of INT pin T0CS: TMR0 Clock Source Select bit 1 = Transition on T0CKI pin 0 = Internal instruction cycle clock (FOSC/4) T0SE: TMR0 Source Edge Select bit 1 = Increment on high-to-low transition on T0CKI pin 0 = Increment on low-to-high transition on T0CKI pin PSA: Prescaler Assignment bit 1 = Prescaler is assigned to the WDT 0 = Prescaler is assigned to the Timer0 module PS<2:0>: Prescaler Rate Select bits
BIT VALUE 000 001 010 011 100 101 110 111 TMR0 RATE 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256 WDT RATE 1:1 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128
bit 6
bit 5
bit 4
bit 3
bit 2-0
Note 1:
A dedicated 16-bit WDT postscaler is available. See Section 11.5 "Watchdog Timer (WDT)" for more information.
TABLE 5-1:
Name TMR0 INTCON OPTION_REG TRISA
SUMMARY OF REGISTERS ASSOCIATED WITH TIMER0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets
Timer0 Module Register GIE -- PEIE -- T0IE T0CS INTE T0SE RAIE PSA T0IF PS2 INTF PS1 RAIF PS0 RAPU INTEDG
xxxx xxxx uuuu uuuu 0000 000x 0000 000x 1111 1111 1111 1111
TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 --11 1111 --11 1111
Legend: - = Unimplemented locations, read as `0', u = unchanged, x = unknown. Shaded cells are not used by the Timer0 module.
(c) 2009 Microchip Technology Inc.
DS41203E-page 47
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6.0 TIMER1 MODULE WITH GATE CONTROL
6.1 Timer1 Operation
The Timer1 module is a 16-bit incrementing counter which is accessed through the TMR1H:TMR1L register pair. Writes to TMR1H or TMR1L directly update the counter. When used with an internal clock source, the module is a timer. When used with an external clock source, the module can be used as either a timer or counter.
The Timer1 module is a 16-bit timer/counter with the following features: 16-bit timer/counter register pair (TMR1H:TMR1L) Programmable internal or external clock source 3-bit prescaler Optional LP oscillator Synchronous or asynchronous operation Timer1 gate (count enable) via comparator or T1G pin * Interrupt on overflow * Wake-up on overflow (external clock, Asynchronous mode only) Figure 6-1 is a block diagram of the Timer1 module. * * * * * *
6.2
Clock Source Selection
The TMR1CS bit of the T1CON register is used to select the clock source. When TMR1CS = 0, the clock source is FOSC/4. When TMR1CS = 1, the clock source is supplied externally. Clock Source FOSC/4 T1CKI pin TMR1CS 0 1 Clock Source FOSC/4 T1CKI pin
FIGURE 6-1:
TIMER1 BLOCK DIAGRAM
TMR1GE TMR1ON Set flag bit TMR1IF on Overflow To C2 Comparator Module Timer1 Clock EN 0 Synchronized clock input
T1GINV
TMR1(2) TMR1H TMR1L
1
Oscillator
(1)
T1SYNC 1 FOSC/4 Internal Clock Prescaler 1, 2, 4, 8 0 2 T1CKPS<1:0> TMR1CS 1 Synchronize(3) det
OSC1/T1CKI
OSC2/T1G
INTOSC Without CLKOUT T1OSCEN
C2OUT
0 T1GSS
Note 1: 2: 3:
ST Buffer is low power type when using LP oscillator, or high speed type when using T1CKI. Timer1 register increments on rising edge. Synchronize does not operate while in Sleep.
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6.2.1 INTERNAL CLOCK SOURCE
6.5
When the internal clock source is selected the TMR1H:TMR1L register pair will increment on multiples of TCY as determined by the Timer1 prescaler.
Timer1 Operation in Asynchronous Counter Mode
6.2.2
EXTERNAL CLOCK SOURCE
When the external clock source is selected, the Timer1 module may work as a timer or a counter. When counting, Timer1 is incremented on the rising edge of the external clock input T1CKI. In addition, the Counter mode clock can be synchronized to the microcontroller system clock or run asynchronously. If an external clock oscillator is needed (and the microcontroller is using the INTOSC without CLKOUT), Timer1 can use the LP oscillator as a clock source. Note: In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge.
If control bit T1SYNC of the T1CON register is set, the external clock input is not synchronized. The timer continues to increment asynchronous to the internal phase clocks. The timer will continue to run during Sleep and can generate an interrupt on overflow, which will wake-up the processor. However, special precautions in software are needed to read/write the timer (see Section 6.5.1 "Reading and Writing Timer1 in Asynchronous Counter Mode"). Note: When switching from synchronous to asynchronous operation, it is possible to skip an increment. When switching from asynchronous to synchronous operation, it is possible to produce a single spurious increment.
6.5.1
6.3
Timer1 Prescaler
READING AND WRITING TIMER1 IN ASYNCHRONOUS COUNTER MODE
Timer1 has four prescaler options allowing 1, 2, 4 or 8 divisions of the clock input. The T1CKPS bits of the T1CON register control the prescale counter. The prescale counter is not directly readable or writable; however, the prescaler counter is cleared upon a write to TMR1H or TMR1L.
Reading TMR1H or TMR1L while the timer is running from an external asynchronous clock will ensure a valid read (taken care of in hardware). However, the user should keep in mind that reading the 16-bit timer in two 8-bit values itself, poses certain problems, since the timer may overflow between the reads. For writes, it is recommended that the user simply stop the timer and write the desired values. A write contention may occur by writing to the timer registers, while the register is incrementing. This may produce an unpredictable value in the TMR1H:TTMR1L register pair.
6.4
Timer1 Oscillator
A low-power 32.768 kHz crystal oscillator is built-in between pins OSC1 (input) and OSC2 (amplifier output). The oscillator is enabled by setting the T1OSCEN control bit of the T1CON register. The oscillator will continue to run during Sleep. The Timer1 oscillator is shared with the system LP oscillator. Thus, Timer1 can use this mode only when the primary system clock is derived from the internal oscillator or when in LP oscillator mode. The user must provide a software time delay to ensure proper oscillator start-up. TRISA5 and TRISA4 bits are set when the Timer1 oscillator is enabled. RA5 and RA4 bits read as `0' and TRISA5 and TRISA4 bits read as `1'. Note: The oscillator requires a start-up and stabilization time before use. Thus, T1OSCEN should be set and a suitable delay observed prior to enabling Timer1.
6.6
Timer1 Gate
Timer1 gate source is software configurable to be the T1G pin or the output of Comparator 2. This allows the device to directly time external events using T1G or analog events using Comparator 2. See the CMCON1 register (Register 7-2) for selecting the Timer1 gate source. This feature can simplify the software for a Delta-Sigma A/D converter and many other applications. For more information on Delta-Sigma A/D converters, see the Microchip web site (www.microchip.com). Note: TMR1GE bit of the T1CON register must be set to use either T1G or C2OUT as the Timer1 gate source. See Register 7-2 for more information on selecting the Timer1 gate source.
Timer1 gate can be inverted using the T1GINV bit of the T1CON register, whether it originates from the T1G pin or Comparator 2 output. This configures Timer1 to measure either the active-high or active-low time between events.
(c) 2009 Microchip Technology Inc.
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PIC16F688
6.7 Timer1 Interrupt 6.8 Timer1 Operation During Sleep
The Timer1 register pair (TMR1H:TMR1L) increments to FFFFh and rolls over to 0000h. When Timer1 rolls over, the Timer1 interrupt flag bit of the PIR1 register is set. To enable the interrupt on rollover, you must set these bits: * Timer1 interrupt enable bit of the PIE1 register * PEIE bit of the INTCON register * GIE bit of the INTCON register The interrupt is cleared by clearing the TMR1IF bit in the Interrupt Service Routine. Note: The TMR1H:TTMR1L register pair and the TMR1IF bit should be cleared before enabling interrupts. Timer1 can only operate during Sleep when setup in Asynchronous Counter mode. In this mode, an external crystal or clock source can be used to increment the counter. To set up the timer to wake the device: * TMR1ON bit of the T1CON register must be set * TMR1IE bit of the PIE1 register must be set * PEIE bit of the INTCON register must be set The device will wake-up on an overflow and execute the next instruction. If the GIE bit of the INTCON register is set, the device will call the Interrupt Service Routine (0004h).
FIGURE 6-2:
T1CKI = 1 when TMR1 Enabled
TIMER1 INCREMENTING EDGE
T1CKI = 0 when TMR1 Enabled Note 1: 2: Arrows indicate counter increments. In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of the clock.
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6.9 Timer1 Control Register
The Timer1 Control register (T1CON), shown in Register 6-1, is used to control Timer1 and select the various features of the Timer1 module.
REGISTER 6-1:
R/W-0 T1GINV bit 7 Legend: R = Readable bit -n = Value at POR bit 7
(1)
T1CON: TIMER 1 CONTROL REGISTER
R/W-0 R/W-0
(2)
R/W-0 T1CKPS0
R/W-0 T1OSCEN
R/W-0 T1SYNC
R/W-0 TMR1CS
R/W-0 TMR1ON bit 0
TMR1GE
T1CKPS1
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
T1GINV: Timer1 Gate Invert bit(1) 1 = Timer1 gate is active high (Timer1 counts when gate is high) 0 = Timer1 gate is active low (Timer1 counts when gate is low) TMR1GE: Timer1 Gate Enable bit(2) If TMR1ON = 0: This bit is ignored If TMR1ON = 1: 1 = Timer1 is on if Timer1 gate is active 0 = Timer1 is on T1CKPS<1:0>: Timer1 Input Clock Prescale Select bits 11 = 1:8 Prescale Value 10 = 1:4 Prescale Value 01 = 1:2 Prescale Value 00 = 1:1 Prescale Value T1OSCEN: LP Oscillator Enable Control bit If INTOSC without CLKOUT oscillator is active: 1 = LP oscillator is enabled for Timer1 clock 0 = LP oscillator is off Else: This bit is ignored. LP oscillator is disabled. T1SYNC: Timer1 External Clock Input Synchronization Control bit TMR1CS = 1: 1 = Do not synchronize external clock input 0 = Synchronize external clock input TMR1CS = 0: This bit is ignored. Timer1 uses the internal clock TMR1CS: Timer1 Clock Source Select bit 1 = External clock from T1CKI pin (on the rising edge) 0 = Internal clock (FOSC/4) TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1 T1GINV bit inverts the Timer1 gate logic, regardless of source. TMR1GE bit must be set to use either T1G pin or C2OUT, as selected by the T1GSS bit of the CM2CON1 register, as a Timer1 gate source.
bit 6
bit 5-4
bit 3
bit 2
bit 1
bit 0
Note 1: 2:
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TABLE 6-1:
Name CMCON1 INTCON PIE1 PIR1 TMR1H TMR1L T1CON Legend: Bit 7 -- GIE EEIE EEIF
SUMMARY OF REGISTERS ASSOCIATED WITH TIMER1
Bit 6 -- PEIE ADIE ADIF Bit 5 -- T0IE RCIE RCIF Bit 4 -- INTE C2IE C2IF Bit 3 -- RAIE C1IE C1IF Bit 2 -- T0IF OSFIE OSFIF Bit 1 T1GSS INTF TXIE TXIF Bit 0 C2SYNC RAIF TMR1IE TMR1IF Value on POR, BOR ---- --10 0000 000x 0000 0000 0000 0000 xxxx xxxx xxxx xxxx TMR1CS TMR1ON 0000 0000 Value on all other Resets 00-- --10 0000 000x 0000 0000 0000 0000 uuuu uuuu uuuu uuuu uuuu uuuu
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register Holding Register for the Least Significant Byte of the 16-bit TMR1 Register T1GINV TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC
x = unknown, u = unchanged, - = unimplemented, read as `0'. Shaded cells are not used by the Timer1 module.
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PIC16F688
7.0 COMPARATOR MODULE
7.1 Comparator Overview
Comparators are used to interface analog circuits to a digital circuit by comparing two analog voltages and providing a digital indication of their relative magnitudes. The comparators are very useful mixed signal building blocks because they provide analog functionality independent of the program execution. The analog comparator module includes the following features: * Dual comparators * Multiple comparator configurations * Comparator outputs are available internally/externally * Programmable output polarity * Interrupt-on-change * Wake-up from Sleep * Timer1 gate (count enable) * Output synchronization to Timer1 clock input * Programmable voltage reference Note: Only Comparator C2 can be linked to Timer1. Output A comparator is shown in Figure 7-1 along with the relationship between the analog input levels and the digital output. When the analog voltage at VIN+ is less than the analog voltage at VIN-, the output of the comparator is a digital low level. When the analog voltage at VIN+ is greater than the analog voltage at VIN-, the output of the comparator is a digital high level.
FIGURE 7-1:
VIN+ VIN-
SINGLE COMPARATOR
+ - Output
VINVIN+
Note:
The black areas of the output of the comparator represents the uncertainty due to input offsets and response time.
This device contains two comparators as shown in Figure 7-2 and Figure 7-3. The comparators are not independently configurable.
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FIGURE 7-2: COMPARATOR C1 OUTPUT BLOCK DIAGRAM
MULTIPLEX
C1INV C1
FIGURE 7-3:
DS41203E-page 54
Port Pins Port Pins
To C1OUT pin
D Q1 EN
Q
To Data Bus
RD CMCON0 Set C1IF bit
D Q3*RD CMCON0 EN
Q
CL
Reset Note 1: 2: Q1 and Q3 are phases of the four-phase system clock (FOSC). Q1 is held high during Sleep mode.
COMPARATOR C2 OUTPUT BLOCK DIAGRAM
C2SYNC C2INV C2 D Timer1 clock source(1) Q 0 To C2OUT pin 1 To Timer1 Gate MULTIPLEX Note 1: 2: 3:
D Q1 EN
Q
To Data Bus
RD CMCON0 Set C2IF bit
D Q3*RD CMCON0 EN
Q
CL
Reset
Comparator output is latched on falling edge of Timer1 clock source. Q1 and Q3 are phases of the four-phase system clock (FOSC). Q1 is held high during Sleep mode.
(c) 2009 Microchip Technology Inc.
PIC16F688
7.1.1 ANALOG INPUT CONNECTION CONSIDERATIONS
A simplified circuit for an analog input is shown in Figure 7-4. Since the analog input pins share their connection with a digital input, they have reverse biased ESD protection diodes to VDD and VSS. The analog input, therefore, must be between VSS and VDD. If the input voltage deviates from this range by more than 0.6V in either direction, one of the diodes is forward biased and a latch-up may occur. A maximum source impedance of 10 k is recommended for the analog sources. Also, any external component connected to an analog input pin, such as a capacitor or a Zener diode, should have very little leakage current to minimize inaccuracies introduced. Note 1: When reading a PORT register, all pins configured as analog inputs will read as a `0'. Pins configured as digital inputs will convert as an analog input, according to the input specification. 2: Analog levels on any pin defined as a digital input, may cause the input buffer to consume more current than is specified.
FIGURE 7-4:
ANALOG INPUT MODEL
VDD
Rs < 10K AIN VA CPIN 5 pF
VT 0.6V
RIC To ADC Input
VT 0.6V
ILEAKAGE 500 nA
Vss Legend: CPIN = Input Capacitance ILEAKAGE = Leakage Current at the pin due to various junctions = Interconnect Resistance RIC = Source Impedance RS VA = Analog Voltage = Threshold Voltage VT
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7.2 Comparator Configuration
There are eight modes of operation for the comparator. The CM<2:0> bits of the CMCON0 register are used to select these modes as shown in Figure 7-5. I/O lines change as a function of the mode and are designated as follows: * Analog function (A): digital input buffer is disabled * Digital function (D): comparator digital output, overrides port function * Normal port function (I/O): independent of comparator The port pins denoted as "A" will read as a `0' regardless of the state of the I/O pin or the I/O control TRIS bit. Pins used as analog inputs should also have the corresponding TRIS bit set to `1' to disable the digital output driver. Pins denoted as "D" should have the corresponding TRIS bit set to `0' to enable the digital output driver. Note: Comparator interrupts should be disabled during a Comparator mode change to prevent unintended interrupts.
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PIC16F688
FIGURE 7-5: COMPARATOR I/O OPERATING MODES
Two Independent Comparators CM<2:0> = 100 VINC1IN- A
C1IN+ C2INC2 Off
(1)
Comparators Reset (POR Default Value) CM<2:0> = 000 A VINC1INC1IN+ A C2INA
VIN+ VINVIN+
C1
Off(1)
A
VIN+ VINVIN+
C1
C1OUT
A A
C2IN+ A
C2IN+
C2
C2OUT
Three Inputs Multiplexed to Two Comparators CM<2:0> = 001
C1INC1IN+
A A
CIS = 0 CIS = 1
VINVIN+ VINVIN+
C2 C2OUT C1 C1OUT
One Independent Comparator CM<2:0> = 101 I/O VINC1INC1IN+
I/O
VIN+
C1
Off(1)
C2INC2IN+
A A
C2INC2IN+
A A
VINVIN+
C2 C2OUT
Four Inputs Multiplexed to Two Comparators CM<2:0> = 010
C1INC1IN+ C2INC2IN+
A A
CIS = 0 CIS = 1
VINVIN+ VINVIN+
C2 C2OUT C1 C1OUT
Two Common Reference Comparators with Outputs CM<2:0> = 110 A VINC1INVIN+
C1OUT(pin)
D A A D
C1
C1OUT
A A
CIS = 0 CIS = 1
C2INC2IN+ C2OUT(pin)
VINVIN+
C2 C2OUT
From CVREF Module
Two Common Reference Comparators CM<2:0> = 011 A VINC1INC1IN+
I/O
Comparators Off (Lowest Power) CM<2:0> = 111
C1INI/O
VINVIN+
C1 Off(1)
VIN+
C1
C1OUT
C1IN+ I/O
C2INC2IN+
A A
VINVIN+
C2 C2OUT
C2INC2IN+
I/O I/O
VINVIN+
C2 Off(1)
Legend: A = Analog Input, ports always reads `0' I/O = Normal port I/O Note 1: Reads as `0', unless CxINV = 1.
CIS = Comparator Input Switch (CMCON0<3>) D = Comparator Digital Output
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7.3 Comparator Control
The CMCON0 register (Register 7-1) provides access to the following comparator features: * * * * Mode selection Output state Output polarity Input switch
7.3.1
COMPARATOR OUTPUT STATE
Each comparator state can always be read internally via the associated CxOUT bit of the CMCON0 register. The comparator outputs are directed to the CxOUT pins when CM<2:0> = 110. When this mode is selected, the TRIS bits for the associated CxOUT pins must be cleared to enable the output drivers.
7.3.2
COMPARATOR OUTPUT POLARITY
Inverting the output of a comparator is functionally equivalent to swapping the comparator inputs. The polarity of a comparator output can be inverted by setting the CxINV bits of the CMCON0 register. Clearing CxINV results in a non-inverted output. A complete table showing the output state versus input conditions and the polarity bit is shown in Table 7-1.
TABLE 7-1:
OUTPUT STATE VS. INPUT CONDITIONS
CxINV 0 0 1 1 CxOUT 0 1 1 0
Input Conditions VIN- > VIN+ VIN- < VIN+ VIN- > VIN+ VIN- < VIN+ Note:
CxOUT refers to both the register bit and output pin.
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7.3.3 COMPARATOR INPUT SWITCH
7.5
Comparator Interrupt Operation
The inverting input of the comparators may be switched between two analog pins in the following modes: * CM<2:0> = 001 (Comparator C1 only) * CM<2:0> = 010 (Comparators C1 and C2) In the above modes, both pins remain in analog mode regardless of which pin is selected as the input. The CIS bit of the CMCON0 register controls the comparator input switch.
7.4
Comparator Response Time
The comparator output is indeterminate for a period of time after the change of an input source or the selection of a new reference voltage. This period is referred to as the response time. The response time of the comparator differs from the settling time of the voltage reference. Therefore, both of these times must be considered when determining the total response time to a comparator input change. See the Comparator and Voltage Reference specifications in Section 14.0 "Electrical Specifications" for more details.
The comparator interrupt flag is set whenever there is a change in the output value of the comparator. Changes are recognized by means of a mismatch circuit which consists of two latches and an exclusiveor gate (see Figure 7-2 and Figure 7-3). One latch is updated with the comparator output level when the CMCON0 register is read. This latch retains the value until the next read of the CMCON0 register or the occurrence of a Reset. The other latch of the mismatch circuit is updated on every Q1 system clock. A mismatch condition will occur when a comparator output change is clocked through the second latch on the Q1 clock cycle. The mismatch condition will persist, holding the CxIF bit of the PIR1 register true, until either the CMCON0 register is read or the comparator output returns to the previous state. Note: A write operation to the CMCON0 register will also clear the mismatch condition because all writes include a read operation at the beginning of the write cycle.
Software will need to maintain information about the status of the comparator output to determine the actual change that has occurred. The CxIF bit of the PIR1 register is the comparator interrupt flag. This bit must be reset in software by clearing it to `0'. Since it is also possible to write a `1' to this register, a simulated interrupt may be initiated. The CxIE bit of the PIE1 register and the PEIE and GIE bits of the INTCON register must all be set to enable comparator interrupts. If any of these bits are cleared, the interrupt is not enabled, although the CxIF bit of the PIR1 register will still be set if an interrupt condition occurs. The user, in the Interrupt Service Routine, can clear the interrupt in the following manner: a) b) Any read or write of CMCON0. This will end the mismatch condition. See Figures 7-6 and 7-7 Clear the CxIF interrupt flag.
A persistent mismatch condition will preclude clearing the CxIF interrupt flag. Reading CMCON0 will end the mismatch condition and allow the CxIF bit to be cleared.
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FIGURE 7-6: COMPARATOR INTERRUPT TIMING W/O CMCON0 READ
7.6
Operation During Sleep
Q1 Q3 CIN+ COUT Set CMIF (level) CMIF reset by software TRT
The comparator, if enabled before entering Sleep mode, remains active during Sleep. The additional current consumed by the comparator is shown separately in Section 14.0 "Electrical Specifications". If the comparator is not used to wake the device, power consumption can be minimized while in Sleep mode by turning off the comparator. The comparator is turned off by selecting mode CM<2:0> = 000 or CM<2:0> = 111 of the CMCON0 register. A change to the comparator output can wake-up the device from Sleep. To enable the comparator to wake the device from Sleep, the CxIE bit of the PIE1 register and the PEIE bit of the INTCON register must be set. The instruction following the Sleep instruction always executes following a wake from Sleep. If the GIE bit of the INTCON register is also set, the device will then execute the Interrupt Service Routine.
FIGURE 7-7:
COMPARATOR INTERRUPT TIMING WITH CMCON0 READ
Q1 Q3 CIN+ COUT Set CMIF (level) CMIF cleared by CMCON0 read reset by software TRT
7.7
Effects of a Reset
Note 1: If a change in the CM1CON0 register (CxOUT) occurs when a read operation is being executed (start of the Q2 cycle), then the CxIF Interrupt Flag bit of the PIR1 register may not get set. 2: When either comparator is first enabled, bias circuitry in the comparator module may cause an invalid output from the comparator until the bias circuitry is stable. Allow about 1 s for bias settling then clear the mismatch condition and interrupt flags before enabling comparator interrupts.
A device Reset forces the CMCON0 and CMCON1 registers to their Reset states. This forces the comparator module to be in the Comparator Reset mode (CM<2:0> = 000). Thus, all comparator inputs are analog inputs with the comparator disabled to consume the smallest current possible.
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PIC16F688
REGISTER 7-1:
R-0 C2OUT bit 7 Legend: R = Readable bit -n = Value at POR bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
CMCON0: COMPARATOR CONFIGURATION REGISTER
R-0 C1OUT R/W-0 C2INV R/W-0 C1INV R/W-0 CIS R/W-0 CM2 R/W-0 CM1 R/W-0 CM0 bit 0
C2OUT: Comparator 2 Output bit When C2INV = 0: 1 = C2 VIN+ > C2 VIN0 = C2 VIN+ < C2 VINWhen C2INV = 1: 1 = C2 VIN+ < C2 VIN0 = C2 VIN+ > C2 VINC1OUT: Comparator 1 Output bit When C1INV = 0: 1 = C1 VIN+ > C1 VIN0 = C1 VIN+ < C1 VINWhen C1INV = 1: 1 = C1 VIN+ < C1 VIN0 = C1 VIN+ > C1 VINC2INV: Comparator 2 Output Inversion bit 1 = C2 output inverted 0 = C2 output not inverted C1INV: Comparator 1 Output Inversion bit 1 = C1 Output inverted 0 = C1 Output not inverted CIS: Comparator Input Switch bit When CM<2:0> = 010: 1 = C1IN+ connects to C1 VINC2IN+ connects to C2 VIN0 = C1IN- connects to C1 VINC2IN- connects to C2 VINWhen CM<2:0> = 001: 1 = C1IN+ connects to C1 VIN0 = C1IN- connects to C1 VINCM<2:0>: Comparator Mode bits (See Figure 7-5) 000 = Comparators off. CxIN pins are configured as analog 001 = Three inputs multiplexed to two comparators 010 = Four inputs multiplexed to two comparators 011 = Two common reference comparators 100 = Two independent comparators 101 = One independent comparator 110 = Two common reference comparators with outputs 111 = Comparators off. CxIN pins are configured as digital I/O
bit 6
bit 5
bit 4
bit 3
bit 2-0
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7.8 Comparator C2 Gating Timer1 7.9
This feature can be used to time the duration or interval of analog events. Clearing the T1GSS bit of the CMCON1 register will enable Timer1 to increment based on the output of Comparator C2. This requires that Timer1 is on and gating is enabled. See Section 6.0 "Timer1 Module with Gate Control" for details. It is recommended to synchronize Comparator C2 with Timer1 by setting the C2SYNC bit when the comparator is used as the Timer1 gate source. This ensures Timer1 does not miss an increment if the comparator changes during an increment.
Synchronizing Comparator C2 Output to Timer1
The output of Comparator C2 can be synchronized with Timer1 by setting the C2SYNC bit of the CMCON1 register. When enabled, the comparator output is latched on the falling edge of the Timer1 clock source. If a prescaler is used with Timer1, the comparator output is latched after the prescaling function. To prevent a race condition, the comparator output is latched on the falling edge of the Timer1 clock source and Timer1 increments on the rising edge of its clock source. Reference the comparator block diagrams (Figure 7-2 and Figure 7-3) and the Timer1 Block Diagram (Figure 6-1) for more information.
REGISTER 7-2:
U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7-2 bit 1
CMCON1: COMPARATOR CONFIGURATION REGISTER
U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- R/W-1 T1GSS R/W-0 C2SYNC bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
Unimplemented: Read as `0' T1GSS: Timer1 Gate Source Select bit(1) 1 = Timer1 gate source is T1G pin (pin should be configured as digital input) 0 = Timer1 gate source is Comparator C2 output C2SYNC: Comparator C2 Output Synchronization bit(2) 1 = Output is synchronized with falling edge of Timer1 clock 0 = Output is asynchronous Refer to Section 6.6 "Timer1 Gate". Refer to Figure 7-3.
bit 0
Note 1: 2:
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PIC16F688
7.10 Comparator Voltage Reference
EQUATION 7-1: CVREF OUTPUT VOLTAGE
The Comparator Voltage Reference module provides an internally generated voltage reference for the comparators. The following features are available: * * * * Independent from Comparator operation Two 16-level voltage ranges Output clamped to VSS Ratiometric with VDD VRR = 1 (low range): CVREF = (VR<3:0>/24) x VDD VRR = 0 (high range): CVREF = (VDD/4) + (VR<3:0> x VDD/32) The full range of VSS to VDD cannot be realized due to the construction of the module. See Figure 7-8.
The VRCON register (Figure 7-3) controls the Voltage Reference module shown in Figure 7-8.
7.10.3
OUTPUT CLAMPED TO VSS
7.10.1
INDEPENDENT OPERATION
The CVREF output voltage can be set to Vss with no power consumption by configuring VRCON as follows: * VREN = 0 * VRR = 1 * VR<3:0> = 0000 This allows the comparator to detect a zero-crossing while not consuming additional CVREF module current.
The comparator voltage reference is independent of the comparator configuration. Setting the VREN bit of the VRCON register will enable the voltage reference.
7.10.2
OUTPUT VOLTAGE SELECTION
The CVREF voltage reference has 2 ranges with 16 voltage levels in each range. Range selection is controlled by the VRR bit of the VRCON register. The 16 levels are set with the VR<3:0> bits of the VRCON register.
7.10.4
OUTPUT RATIOMETRIC TO VDD
The CVREF output voltage is determined by the following equations: REGISTER 7-3:
R/W-0 VREN bit 7 Legend: R = Readable bit -n = Value at POR bit 7 W = Writable bit `1' = Bit is set
The comparator voltage reference is VDD derived and therefore, the CVREF output changes with fluctuations in VDD. The tested absolute accuracy of the Comparator Voltage Reference can be found in Section 14.0 "Electrical Specifications".
VRCON: VOLTAGE REFERENCE CONTROL REGISTER
U-0 -- R/W-0 VRR U-0 -- R/W-0 VR3 R/W-0 VR2 R/W-0 VR1 R/W-0 VR0 bit 0
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
VREN: CVREF Enable bit 1 = CVREF circuit powered on 0 = CVREF circuit powered down, no IDD drain and CVREF = VSS. Unimplemented: Read as `0' VRR: CVREF Range Selection bit 1 = Low range 0 = High range Unimplemented: Read as `0' VR<3:0>: CVREF Value Selection bits (0 VR<3:0> 15) When VRR = 1: CVREF = (VR<3:0>/24) * VDD When VRR = 0: CVREF = VDD/4 + (VR<3:0>/32) * VDD
bit 6 bit 5
bit 4 bit 3-0
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FIGURE 7-8: COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM
16 Stages 8R VDD 8R 16-1 Analog MUX VREN CVREF to Comparator Input
15 14 2 1 0
R
R
R
R
VRR
VR<3:0>(1)
VREN VR<3:0> = 0000 VRR
Note 1:
Care should be taken to ensure VREF remains within the comparator common mode input range. See Section 14.0 "Electrical Specifications" for more detail.
TABLE 7-2:
SUMMARY OF REGISTERS ASSOCIATED WITH THE COMPARATOR AND VOLTAGE REFERENCE MODULES
Bit 7 ANS7 C2OUT -- GIE EEIE EEIF -- -- -- -- VREN Bit 6 ANS6 C1OUT -- PEIE ADIE ADIF -- -- -- -- -- Bit 5 ANS5 C2INV -- T0IE RCIE RCIF RA5 RC5 Bit 4 ANS4 C1INV -- INTE C2IE C2IF RA4 RC4 Bit 3 ANS3 CIS -- RAIE C1IE C1IF RA3 RC3 Bit 2 ANS2 CM2 -- T0IF OSFIE OSFIF RA2 RC2 Bit 1 ANS1 CM1 T1GSS INTF TXIE TXIF RA1 RC1 TRISA1 TRISC1 VR1 Bit 0 ANS0 CM0 C2SYNC RAIF TMR1IE TMR1IF RA0 RC0 TRISA0 TRISC0 VR0 Value on POR, BOR 1111 1111 0000 0000 ---- --10 0000 000x 0000 0000 0000 0000 --x0 x000 --xx 0000 --11 1111 --11 1111 0-0- 0000 Value on all other Resets 1111 1111 0000 0000 ---- --10 0000 000x 0000 0000 0000 0000 --x0 x000 --xx 0000 --11 1111 --11 1111 0-0- 0000
Name ANSEL CMCON0 CMCON1 INTCON PIE1 PIR1 PORTA PORTC TRISA TRISC VRCON Legend:
TRISA5 TRISA4 TRISA3 TRISA2 TRISC5 TRISC4 TRISC3 TRISC2 VRR -- VR3 VR2
x = unknown, u = unchanged, - = unimplemented, read as `0'. Shaded cells are not used for comparator.
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PIC16F688
8.0 ANALOG-TO-DIGITAL CONVERTER (ADC) MODULE
The Analog-to-Digital Converter (ADC) allows conversion of an analog input signal to a 10-bit binary representation of that signal. This device uses analog inputs, which are multiplexed into a single sample and hold circuit. The output of the sample and hold is connected to the input of the converter. The converter generates a 10-bit binary result via successive approximation and stores the conversion result into the ADC result registers (ADRESL and ADRESH). The ADC voltage reference is software selectable to either VDD or a voltage applied to the external reference pins. The ADC can generate an interrupt upon completion of a conversion. This interrupt can be used to wake-up the device from Sleep. Figure 8-1 shows the block diagram of the ADC.
FIGURE 8-1:
ADC BLOCK DIAGRAM
VDD
VCFG = 0
VREF
VCFG = 1
RA0/AN0 RA1/AN1/VREF RA2/AN2 RA4/AN3 RC0/AN4 RC1/AN5 RC2/AN6 RC3/AN7
000 001 010 011 100 101 110 111 ADFM ADON VSS CHS ADRESH A/D GO/DONE 10 0 = Left Justify 1 = Right Justify 10 ADRESL
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8.1 ADC Configuration
When configuring and using the ADC the following functions must be considered: * * * * * * Port configuration Channel selection ADC voltage reference selection ADC conversion clock source Interrupt control Results formatting For correct conversion, the appropriate TAD specification must be met. See A/D conversion requirements in Section 14.0 "Electrical Specifications" for more information. Table 8-1 gives examples of appropriate ADC clock selections. Note: Unless using the FRC, any changes in the system clock frequency will change the ADC clock frequency, which may adversely affect the ADC result.
8.1.1
PORT CONFIGURATION
The ADC can be used to convert both analog and digital signals. When converting analog signals, the I/O pin should be configured for analog by setting the associated TRIS and ANSEL bits. See the corresponding Port section for more information. Note: Analog voltages on any pin that is defined as a digital input may cause the input buffer to conduct excess current.
8.1.2
CHANNEL SELECTION
The CHS bits of the ADCON0 register determine which channel is connected to the sample and hold circuit. When changing channels, a delay is required before starting the next conversion. Refer to Section 8.2 "ADC Operation" for more information.
8.1.3
ADC VOLTAGE REFERENCE
The VCFG bit of the ADCON0 register provides control of the positive voltage reference. The positive voltage reference can be either VDD or an external voltage source. The negative voltage reference is always connected to the ground reference.
8.1.4
CONVERSION CLOCK
The source of the conversion clock is software selectable via the ADCS bits of the ADCON1 register. There are seven possible clock options: * * * * * * * FOSC/2 FOSC/4 FOSC/8 FOSC/16 FOSC/32 FOSC/64 FRC (dedicated internal oscillator)
The time to complete one bit conversion is defined as TAD. One full 10-bit conversion requires 11 TAD periods as shown in Figure 8-3.
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TABLE 8-1: ADC CLOCK PERIOD (TAD) VS. DEVICE OPERATING FREQUENCIES (VDD > 3.0V)
Device Frequency (FOSC) 20 MHz 100 ns 400 ns 800 ns
(2)
ADC Clock Period (TAD) ADC Clock Source FOSC/2 FOSC/4 FOSC/8 FOSC/16 FOSC/32 FOSC/64 FRC Legend: Note 1: 2: 3: 4: ADCS<2:0> 000 100 001 101 010 110 x11
8 MHz 250 ns 1.0 s
(2)
4 MHz 500 ns
(2)
1 MHz 2.0 s 4.0 s 8.0 s(3) 16.0 s(3) 32.0 s(3) 64.0 s(3) 2-6 s(1,4)
200 ns(2)
(2) (2)
500 ns(2)
(2)
1.0 s(2) 2.0 s 4.0 s 8.0 s(3) 16.0 s
(3)
2.0 s 4.0 s 8.0 s
(3)
1.6 s 3.2 s 2-6 s(1,4)
2-6 s(1,4)
2-6 s(1,4)
Shaded cells are outside of recommended range. The FRC source has a typical TAD time of 4 s for VDD > 3.0V. These values violate the minimum required TAD time. For faster conversion times, the selection of another clock source is recommended. When the device frequency is greater than 1 MHz, the FRC clock source is only recommended if the conversion will be performed during Sleep.
FIGURE 8-2:
ANALOG-TO-DIGITAL CONVERSION TAD CYCLES
TCY to TAD TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9 TAD10 TAD11 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
Conversion Starts Holding Capacitor is Disconnected from Analog Input (typically 100 ns) Set GO/DONE bit ADRESH and ADRESL registers are loaded, GO bit is cleared, ADIF bit is set, Holding capacitor is connected to analog input
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8.1.5 INTERRUPTS 8.1.6 RESULT FORMATTING
The ADC module allows for the ability to generate an interrupt upon completion of an Analog-to-Digital Conversion. The ADC interrupt flag is the ADIF bit in the PIR1 register. The ADC interrupt enable is the ADIE bit in the PIE1 register. The ADIF bit must be cleared in software. Note: The ADIF bit is set at the completion of every conversion, regardless of whether or not the ADC interrupt is enabled. The 10-bit A/D Conversion result can be supplied in two formats, left justified or right justified. The ADFM bit of the ADCON0 register controls the output format. Figure 8-4 shows the two output formats.
This interrupt can be generated while the device is operating or while in Sleep. If the device is in Sleep, the interrupt will wake-up the device. Upon waking from Sleep, the next instruction following the SLEEP instruction is always executed. If the user is attempting to wake-up from Sleep and resume in-line code execution, the global interrupt must be disabled. If the global interrupt is enabled, execution will switch to the Interrupt Service Routine. Please see Section 8.1.5 "Interrupts" for more information.
FIGURE 8-3:
10-BIT A/D CONVERSION RESULT FORMAT
ADRESH ADRESL LSB bit 0 10-bit A/D Result bit 7 bit 0 Unimplemented: Read as `0' LSB bit 0 bit 7 10-bit A/D Result bit 0
(ADFM = 0)
MSB bit 7
(ADFM = 1) bit 7 Unimplemented: Read as `0'
MSB
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8.2
8.2.1
ADC Operation
STARTING A CONVERSION
8.2.5
A/D CONVERSION PROCEDURE
This is an example procedure for using the ADC to perform an Analog-to-Digital Conversion: 1. Configure Port: * Disable pin output driver (See TRIS register) * Configure pin as analog Configure the ADC module: * Select ADC conversion clock * Configure voltage reference * Select ADC input channel * Select result format * Turn on ADC module Configure ADC interrupt (optional): * Clear ADC interrupt flag * Enable ADC interrupt * Enable peripheral interrupt * Enable global interrupt(1) Wait the required acquisition time(2). Start conversion by setting the GO/DONE bit. Wait for ADC conversion to complete by one of the following: * Polling the GO/DONE bit * Waiting for the ADC interrupt (interrupts enabled) Read ADC Result Clear the ADC interrupt flag (required if interrupt is enabled).
To enable the ADC module, the ADON bit of the ADCON0 register must be set to a `1'. Setting the GO/ DONE bit of the ADCON0 register to a `1' will start the Analog-to-Digital Conversion. Note: The GO/DONE bit should not be set in the same instruction that turns on the ADC. Refer to Section 8.2.5 "A/D Conversion Procedure".
2.
8.2.2
COMPLETION OF A CONVERSION
3.
When the conversion is complete, the ADC module will: * Clear the GO/DONE bit * Set the ADIF flag bit * Update the ADRESH:ADRESL registers with new conversion result
8.2.3
TERMINATING A CONVERSION
If a conversion must be terminated before completion, the GO/DONE bit can be cleared in software. The ADRESH:ADRESL registers will not be updated with the partially complete Analog-to-Digital Conversion sample. Instead, the ADRESH:ADRESL register pair will retain the value of the previous conversion. Additionally, a 2 TAD delay is required before another acquisition can be initiated. Following this delay, an input acquisition is automatically started on the selected channel. Note: A device Reset forces all registers to their Reset state. Thus, the ADC module is turned off and any pending conversion is terminated.
4. 5. 6.
7. 8.
Note 1: The global interrupt can be disabled if the user is attempting to wake-up from Sleep and resume in-line code execution. 2: See Section 8.3 Requirements". "A/D Acquisition
8.2.4
ADC OPERATION DURING SLEEP
The ADC module can operate during Sleep. This requires the ADC clock source to be set to the FRC option. When the FRC clock source is selected, the ADC waits one additional instruction before starting the conversion. This allows the SLEEP instruction to be executed, which can reduce system noise during the conversion. If the ADC interrupt is enabled, the device will wake-up from Sleep when the conversion completes. If the ADC interrupt is disabled, the ADC module is turned off after the conversion completes, although the ADON bit remains set. When the ADC clock source is something other than FRC, a SLEEP instruction causes the present conversion to be aborted and the ADC module is turned off, although the ADON bit remains set.
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EXAMPLE 8-1: A/D CONVERSION
;This code block configures the ADC ;for polling, Vdd reference, Frc clock ;and AN0 input. ; ;Conversion start & polling for completion ; are included. ; BANKSEL ADCON1 ; MOVLW B'01110000' ;ADC Frc clock MOVWF ADCON1 ; BANKSEL TRISA ; BSF TRISA,0 ;Set RA0 to input BANKSEL ANSEL ; BSF ANSEL,0 ;Set RA0 to analog BANKSEL ADCON0 ; MOVLW B'10000001' ;Right justify, MOVWF ADCON0 ;Vdd Vref, AN0, On CALL SampleTime ;Acquisiton delay BSF ADCON0,GO ;Start conversion BTFSC ADCON0,GO ;Is conversion done? GOTO $-1 ;No, test again BANKSEL ADRESH ; MOVF ADRESH,W ;Read upper 2 bits MOVWF RESULTHI ;store in GPR space BANKSEL ADRESL ; MOVF ADRESL,W ;Read lower 8 bits MOVWF RESULTLO ;Store in GPR space
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8.2.6 ADC REGISTER DEFINITIONS ADCON0: A/D CONTROL REGISTER 0
R/W-0 VCFG U-0 R/W-0 CHS2 R/W-0 CHS1 R/W-0 CHS0 R/W-0 GO/DONE R/W-0 ADON bit 0
The following registers are used to control the operation of the ADC.
REGISTER 8-1:
R/W-0 ADFM bit 7 Legend: R = Readable bit -n = Value at POR bit 7
--
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
ADFM: A/D Conversion Result Format Select bit 1 = Right justified 0 = Left justified VCFG: Voltage Reference bit 1 = VREF pin 0 = VDD Unimplemented: Read as `0' CHS<2:0>: Analog Channel Select bits
bit 6
bit 5 bit 4-2
000 = AN0 001 = AN1 010 = AN2 011 = AN3 100 = AN4 101 = AN5 110 = AN6 111 = AN7
bit 1 GO/DONE: A/D Conversion Status bit 1 = A/D Conversion cycle in progress. Setting this bit starts an A/D Conversion cycle. This bit is automatically cleared by hardware when the A/D Conversion has completed. 0 = A/D Conversion completed/not in progress ADON: ADC Enable bit 1 = ADC is enabled 0 = ADC is disabled and consumes no operating current
bit 0
REGISTER 8-2:
U-0
ADCON1: A/D CONTROL REGISTER 1
R/W-0 ADCS2 R/W-0 ADCS1 R/W-0 ADCS0 U-0 U-0 U-0 U-0
--
bit 7 Legend: R = Readable bit -n = Value at POR bit 7 bit 6-4
--
--
--
--
bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
Unimplemented: Read as `0'
ADCS<2:0>: A/D Conversion Clock Select bits 000 = FOSC/2 001 = FOSC/8 010 = FOSC/32 x11 = FRC (clock derived from a dedicated internal oscillator = 500 kHz max) 100 = FOSC/4 101 = FOSC/16 110 = FOSC/64
Unimplemented: Read as `0'
bit 3-0
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REGISTER 8-3:
R/W-x ADRES9 bit 7 Legend: R = Readable bit -n = Value at POR bit 7-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 0
R/W-x ADRES8 R/W-x ADRES7 R/W-x ADRES6 R/W-x ADRES5 R/W-x ADRES4 R/W-x ADRES3 R/W-x ADRES2 bit 0
ADRES<9:2>: ADC Result Register bits Upper 8 bits of 10-bit conversion result
REGISTER 8-4:
R/W-x ADRES1 bit 7 Legend: R = Readable bit -n = Value at POR bit 7-6 bit 5-0
ADRESL: ADC RESULT REGISTER LOW (ADRESL) ADFM = 0
R/W-x ADRES0 R/W-x -- R/W-x -- R/W-x -- R/W-x -- R/W-x -- R/W-x -- bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
ADRES<1:0>: ADC Result Register bits Lower 2 bits of 10-bit conversion result Reserved: Do not use.
REGISTER 8-5:
R/W-x -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7-2 bit 1-0
ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 1
R/W-x -- R/W-x -- R/W-x -- R/W-x -- R/W-x -- R/W-x ADRES9 R/W-x ADRES8 bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
Reserved: Do not use. ADRES<9:8>: ADC Result Register bits Upper 2 bits of 10-bit conversion result
REGISTER 8-6:
R/W-x ADRES7 bit 7 Legend: R = Readable bit -n = Value at POR bit 7-0
ADRESL: ADC RESULT REGISTER LOW (ADRESL) ADFM = 1
R/W-x ADRES6 R/W-x ADRES5 R/W-x ADRES4 R/W-x ADRES3 R/W-x ADRES2 R/W-x ADRES1 R/W-x ADRES0 bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
ADRES<7:0>: ADC Result Register bits Lower 8 bits of 10-bit conversion result
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8.3 A/D Acquisition Requirements
For the ADC to meet its specified accuracy, the charge holding capacitor (CHOLD) must be allowed to fully charge to the input channel voltage level. The Analog Input model is shown in Figure 8-4. The source impedance (RS) and the internal sampling switch (RSS) impedance directly affect the time required to charge the capacitor CHOLD. The sampling switch (RSS) impedance varies over the device voltage (VDD), see Figure 8-4. The maximum recommended impedance for analog sources is 10 k. As the source impedance is decreased, the acquisition time may be decreased. After the analog input channel is selected (or changed), an A/D acquisition must be done before the conversion can be started. To calculate the minimum acquisition time, Equation 8-1 may be used. This equation assumes that 1/2 LSb error is used (1024 steps for the ADC). The 1/2 LSb error is the maximum error allowed for the ADC to meet its specified resolution.
EQUATION 8-1: Assumptions:
ACQUISITION TIME EXAMPLE Temperature = 50C and external impedance of 10k 5.0V VDD
TACQ = Amplifier Settling Time + Hold Capacitor Charging Time + Temperature Coefficient = TAMP + TC + TCOFF = 2s + TC + [ ( Temperature - 25C ) ( 0.05s/C ) ] The value for TC can be approximated with the following equations:
1 VAPPLIED 1 - ----------- = VCHOLD 2047
--------- RC VAPPLIED 1 - e = VCHOLD -------- 1 RC VAPPLIED 1 - e = VAPPLIED 1 - ----------- 2047 - Tc - TC
;[1] VCHOLD charged to within 1/2 lsb
;[2] VCHOLD charge response to VAPPLIED
;combining [1] and [2]
Solving for TC:
TC = - CHOLD ( RIC + RSS + RS ) ln(1/2047) = - 10pF ( 1k + 7k + 10k ) ln(0.0004885) = 1.37 s
Therefore: TACQ = 2S + 1.37S + [ ( 50C- 25C ) ( 0.05S/C ) ] = 4.67S
Note 1: The reference voltage (VREF) has no effect on the equation, since it cancels itself out. 2: The charge holding capacitor (CHOLD) is not discharged after each conversion. 3: The maximum recommended impedance for analog sources is 10 k. This is required to meet the pin leakage specification.
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FIGURE 8-4: ANALOG INPUT MODEL
VDD Rs VA ANx CPIN 5 pF VT = 0.6V RIC 1k I LEAKAGE 500 nA Sampling Switch SS Rss
VT = 0.6V
CHOLD = 10 pF VSS/VREF-
Legend: CPIN = Input Capacitance = Threshold Voltage VT I LEAKAGE = Leakage current at the pin due to various junctions RIC = Interconnect Resistance SS = Sampling Switch CHOLD = Sample/Hold Capacitance
6V 5V VDD 4V 3V 2V
RSS
5 6 7 8 9 10 11 Sampling Switch (k)
FIGURE 8-5:
ADC TRANSFER FUNCTION
Full-Scale Range
3FFh 3FEh 3FDh ADC Output Code 3FCh 3FBh Full-Scale Transition 1 LSB ideal
004h 003h 002h 001h 000h 1 LSB ideal
Analog Input Voltage
VSS/VREF-
Zero-Scale Transition
VDD/VREF+
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TABLE 8-2:
Name ADCON0 ADCON1 ANSEL ADRESH ADRESL INTCON PIE1 PIR1 PORTA PORTC TRISA TRISC Legend: Bit 7 ADFM -- ANS7
SUMMARY OF ASSOCIATED ADC REGISTERS
Bit 6 VCFG ADCS2 ANS6 Bit 5 -- ADCS1 ANS5 Bit 4 CHS2 ADCS0 ANS4 Bit 3 CHS1 -- ANS3 Bit 2 CHS0 -- ANS2 Bit 1 GO/DONE -- ANS1 Bit 0 ADON -- ANS0 Value on POR, BOR 00-0 0000 -000 ---1111 1111 xxxx xxxx xxxx xxxx INTE C2IE C2IF RA4 RC4 TRISA4 TRISC4 RAIE C1IE C1IF RA3 RC3 TRISA3 TRISC3 T0IF OSFIE OSFIF RA2 RC2 TRISA2 TRISC2 INTF TXIE TXIF RA1 RC1 TRISA1 TRISC1 RAIF TMR1IE TMR1IF RA0 RC0 TRISA0 TRISC0 0000 000x 0000 0000 0000 0000 --x0 x000 --xx 0000 --11 1111 --11 1111 Value on all other Resets 00-0 0000 -000 ---1111 1111 uuuu uuuu uuuu uuuu 0000 000x 0000 0000 0000 0000 --x0 x000 --xx 0000 --11 1111 --11 1111
A/D Result Register High Byte A/D Result Register Low Byte GIE EEIE EEIF -- -- -- -- PEIE ADIE ADIF -- -- -- -- T0IE RCIE RCIF RA5 RC5 TRISA5 TRISC5
x = unknown, u = unchanged, -- = unimplemented read as `0'. Shaded cells are not used for ADC module.
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NOTES:
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9.0 DATA EEPROM AND FLASH PROGRAM MEMORY CONTROL
9.1 EEADR and EEADRH Registers
The EEADR and EEADRH registers can address up to a maximum of 256 bytes of data EEPROM or up to a maximum of 4K words of program EEPROM. When selecting a program address value, the MSB of the address is written to the EEADRH register and the LSB is written to the EEADR register. When selecting a data address value, only the LSB of the address is written to the EEADR register.
Data EEPROM memory is readable and writable and the Flash program memory is readable during normal operation (full VDD range). These memories are not directly mapped in the register file space. Instead, they are indirectly addressed through the Special Function Registers. There are six SFRs used to access these memories: * * * * * * EECON1 EECON2 EEDAT EEDATH EEADR EEADRH
9.1.1
EECON1 AND EECON2 REGISTERS
EECON1 is the control register for EE memory accesses. Control bit EEPGD determines if the access will be a program or data memory access. When clear, as it is when reset, any subsequent operations will operate on the data memory. When set, any subsequent operations will operate on the program memory. Program memory can only be read. Control bits RD and WR initiate read and write, respectively. These bits cannot be cleared, only set, in software. They are cleared in hardware at completion of the read or write operation. The inability to clear the WR bit in software prevents the accidental, premature termination of a write operation. The WREN bit, when set, will allow a write operation to data EEPROM. On power-up, the WREN bit is clear. The WRERR bit is set when a write operation is interrupted by a MCLR or a WDT Time-out Reset during normal operation. In these situations, following Reset, the user can check the WRERR bit and rewrite the location. The data and address will be unchanged in the EEDAT and EEADR registers. Interrupt flag bit EEIF of the PIR1 register is set when write is complete. It must be cleared in the software. EECON2 is not a physical register. Reading EECON2 will read all `0's. The EECON2 register is used exclusively in the data EEPROM write sequence.
When interfacing the data memory block, EEDAT holds the 8-bit data for read/write, and EEADR holds the address of the EE data location being accessed. This device has 256 bytes of data EEPROM with an address range from 0h to 0FFh. When interfacing the program memory block, the EEDAT and EEDATH registers form a 2-byte word that holds the 14-bit data for read/write, and the EEADR and EEADRH registers form a 2-byte word that holds the 12-bit address of the EEPROM location being accessed. This device has 4K words of program EEPROM with an address range from 0h to 0FFFh. The program memory allows one word reads. The EEPROM data memory allows byte read and write. A byte write automatically erases the location and writes the new data (erase before write). The write time is controlled by an on-chip timer. The write/erase voltages are generated by an on-chip charge pump rated to operate over the voltage range of the device for byte or word operations. When the device is code-protected, the CPU may continue to read and write the data EEPROM memory and read the program memory. When code-protected, the device programmer can no longer access data or program memory.
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REGISTER 9-1:
R/W-0 EEDAT7 bit 7 Legend: R = Readable bit -n = Value at POR bit 7-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
EEDAT: EEPROM DATA REGISTER
R/W-0 EEDAT6 R/W-0 EEDAT5 R/W-0 EEDAT4 R/W-0 EEDAT3 R/W-0 EEDAT2 R/W-0 EEDAT1 R/W-0 EEDAT0 bit 0
EEDATn: Byte Value to Write to or Read from Data EEPROM bits
REGISTER 9-2:
R/W-0 EEADR7 bit 7 Legend: R = Readable bit -n = Value at POR bit 7-0
EEADR: EEPROM ADDRESS REGISTER
R/W-0 EEADR6 R/W-0 EEADR5 R/W-0 EEADR4 R/W-0 EEADR3 R/W-0 EEADR2 R/W-0 EEADR1 R/W-0 EEADR0 bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
EEADR<7:0>: 8 Least Significant Address bits for EEPROM Read/Write Operation(1) or Read from program memory
REGISTER 9-3:
U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7-6 bit 5-0
EEDATH: EEPROM DATA HIGH BYTE REGISTER
U-0 -- R/W-0 EEDATH5 R/W-0 EEDATH4 R/W-0 EEDATH3 R/W-0 EEDATH2 R/W-0 EEDATH1 R/W-0 EEDATH0 bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
Unimplemented: Read as `0' EEDATH<5:0>: 6 Most Significant Data bits from program memory
REGISTER 9-4:
U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7-4 bit 3-0
EEADRH: EEPROM ADDRESS HIGH BYTE REGISTER
U-0 -- U-0 -- U-0 -- R/W-0 EEADRH3 R/W-0 EEADRH2 R/W-0 EEADRH1 R/W-0 EEADRH0 bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
Unimplemented: Read as `0' EEADRH<3:0>: Specifies the 4 Most Significant Address bits or high bits for program memory reads
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REGISTER 9-5:
R/W-x EEPGD bit 7 Legend: S = Bit can only be set R = Readable bit -n = Value at POR bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
EECON1: EEPROM CONTROL REGISTER
U-0 -- U-0 -- U-0 -- R/W-x WRERR R/W-0 WREN R/S-0 WR R/S-0 RD bit 0
EEPGD: Program/Data EEPROM Select bit 1 = Accesses program memory 0 = Accesses data memory Unimplemented: Read as `0' WRERR: EEPROM Error Flag bit 1 = A write operation is prematurely terminated (any MCLR Reset, any WDT Reset during normal operation or BOR Reset) 0 = The write operation completed WREN: EEPROM Write Enable bit 1 = Allows write cycles 0 = Inhibits write to the data EEPROM WR: Write Control bit EEPGD = 1: This bit is ignored EEPGD = 0: 1 = Initiates a write cycle (The bit is cleared by hardware once write is complete. The WR bit can only be set, not cleared, in software.) 0 = Write cycle to the data EEPROM is complete RD: Read Control bit 1 = Initiates a memory read (the RD is cleared in hardware and can only be set, not cleared, in software.) 0 = Does not initiate a memory read
bit 6-4 bit 3
bit 2
bit 1
bit 0
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9.1.2 READING THE DATA EEPROM MEMORY 9.1.3 WRITING TO THE DATA EEPROM MEMORY
To read a data memory location, the user must write the address to the EEADR register, clear the EEPGD control bit of the EECON1 register, and then set control bit RD of the EECON1 register. The data is available in the very next cycle, in the EEDAT register; therefore, it can be read in the next instruction. EEDAT will hold this value until another read or until it is written to by the user (during a write operation). To write an EEPROM data location, the user must first write the address to the EEADR register and the data to the EEDAT register. Then the user must follow a specific sequence to initiate the write for each byte. The write will not initiate if the above sequence is not followed exactly (write 55h to EECON2, write AAh to EECON2, then set WR bit) for each byte. Interrupts should be disabled during this code segment. Additionally, the WREN bit in EECON1 must be set to enable write. This mechanism prevents accidental writes to data EEPROM due to errant (unexpected) code execution (i.e., lost programs). The user should keep the WREN bit clear at all times, except when updating EEPROM. The WREN bit is not cleared by hardware. After a write sequence has been initiated, clearing the WREN bit will not affect this write cycle. The WR bit will be inhibited from being set unless the WREN bit is set. At the completion of the write cycle, the WR bit is cleared in hardware and the EE Write Complete Interrupt Flag bit (EEIF) is set. The user can either enable this interrupt or poll this bit. EEIF must be cleared by software.
EXAMPLE 9-1:
DATA EEPROM READ
; ; ;Data Memory ;Address to read ;Point to DATA ;memory ;EE Read ;W = EEDAT
BANKSEL EEADR MOVLW DATA_EE_ADDR MOVWF EEADR BCF BSF MOVF EECON1, EEPGD EECON1, RD EEDAT, W
EXAMPLE 9-2:
BANKSEL MOVLW MOVWF MOVLW MOVWF BANKSEL BCF BSF BCF BTFSC GOTO MOVLW MOVWF MOVLW MOVWF BSF BSF SLEEP BCF
DATA EEPROM WRITE
EEADR DATA_EE_ADDR EEADR DATA_EE_DATA EEDAT EECON1 EECON1, EEPGD EECON1, WREN INTCON, INTCON, $-2 55h EECON2 AAh EECON2 EECON1, INTCON, GIE GIE ; ; ;Data Memory Address to write ; ;Data Memory Value to write ; ;Point to DATA memory ;Enable writes ;Disable INTs. ;SEE AN576 ; ;Write 55h ; ;Write AAh ;Set WR bit to begin write ;Enable INTs. ;Wait for interrupt to signal write complete ;Disable writes
Required Sequence
WR GIE
EECON1, WREN
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9.1.4 READING THE FLASH PROGRAM MEMORY
To read a program memory location, the user must write two bytes of the address to the EEADR and EEADRH registers, set the EEPGD control bit of the EECON1 register, and then set control bit RD of the EECON1 register. Once the read control bit is set, the program memory Flash controller will use the second instruction cycle to read the data. This causes the second instruction immediately following the "BSF EECON1,RD" instruction to be ignored. The data is available in the very next cycle, in the EEDAT and EEDATH registers; therefore, it can be read as two bytes in the following instructions. EEDAT and EEDATH registers will hold this value until another read or until it is written to by the user (during a write operation). Note 1: The two instructions following a program memory read are required to be NOP's. This prevents the user from executing a two-cycle instruction on the next instruction after the RD bit is set. 2: If the WR bit is set when EEPGD = 1, it will be immediately reset to `0' and no operation will take place.
EXAMPLE 9-3:
BANKSEL MOVLW MOVWF MOVLW MOVWF BANKSEL BSF BSF
FLASH PROGRAM READ
EEADR MS_PROG_EE_ADDR EEADRH LS_PROG_EE_ADDR EEADR EECON1 EECON1, EEPGD EECON1, RD ; ; ;MS Byte of Program Address to read ; ;LS Byte of Program Address to read ; ;Point to PROGRAM memory ;EE Read ;First instruction after BSF EECON1,RD executes normally
Required Sequence
;
NOP NOP
;Any instructions here are ignored as program ;memory is read in second cycle after BSF EECON1,RD EEDAT EEDAT, W LOWPMBYTE EEDATH, W HIGHPMBYTE STATUS, RP1 ; ;W = LS Byte of Program Memory ; ;W = MS Byte of Program EEDAT ; ;Bank 0
; BANKSEL MOVF MOVWF MOVF MOVWF BCF
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FIGURE 9-1: FLASH PROGRAM MEMORY READ CYCLE EXECUTION
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Flash ADDR
PC
PC + 1
EEADRH,EEADR
PC + 3 PC+3
PC + 4
PC + 5
Flash Data
INSTR (PC)
INSTR (PC + 1)
EEDATH,EEDAT
INSTR (PC + 3)
INSTR (PC + 4)
INSTR(PC - 1) executed here
BSF EECON1,RD executed here
INSTR(PC + 1) executed here
Forced NOP executed here
INSTR(PC + 3) executed here
INSTR(PC + 4) executed here
RD bit
EEDATH EEDAT Register
EERHLT
TABLE 9-1:
Name EECON1 EECON2 EEADR EEADRH EEDAT EEDATH INTCON PIE1 PIR1
SUMMARY OF REGISTERS ASSOCIATED WITH DATA EEPROM
Bit 7 Bit 6 -- Bit 5 -- Bit 4 -- Bit 3 WRERR Bit 2 WREN Bit 1 WR Bit 0 RD Value on POR, BOR x--- x000 ---- ---EEADR2 EEADRH2 EEDAT2 EEDATH2 T0IF EEADR1 EEADRH1 EEDAT1 EEDATH1 INTF EEADR0 EEADRH0 EEDAT0 EEDATH0 RABIF 0000 0000 ---- 0000 0000 0000 --00 0000 0000 000x 0000 0000 0000 0000 Value on all other Resets 0--- q000 ---- ---0000 0000 ---- 0000 0000 0000 --00 0000 0000 000x 0000 0000 0000 0000
EEPGD
EEPROM Control Register 2 (not a physical register) EEADR7 -- EEDAT7 -- GIE EEADR6 -- EEDAT6 -- PEIE EEADR5 -- EEDAT5 EEDATH5 T0IE EEADR4 -- EEDAT4 EEDATH4 INTE EEADR3 EEADRH3 EEDAT3 EEDATH3 RABIE
EEIE EEIF
ADIE ADIF
RCIE RCIF
C2IE C2IF
C1IE C1IF
OSFIE OSFIF
TXIE TXIF
TMR1IE TMR1IF
Legend:
x = unknown, u = unchanged, -- = unimplemented read as `0', q = value depends upon condition. Shaded cells are not used by data EEPROM module.
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(c) 2009 Microchip Technology Inc.
PIC16F688
10.0 ENHANCED UNIVERSAL SYNCHRONOUS ASYNCHRONOUS RECEIVER TRANSMITTER (EUSART)
The EUSART module includes the following capabilities: * * * * * * * * * * Full-duplex asynchronous transmit and receive Two-character input buffer One-character output buffer Programmable 8-bit or 9-bit character length Address detection in 9-bit mode Input buffer overrun error detection Received character framing error detection Half-duplex synchronous master Half-duplex synchronous slave Programmable clock polarity in synchronous modes
The Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) module is a serial I/O communications peripheral. It contains all the clock generators, shift registers and data buffers necessary to perform an input or output serial data transfer independent of device program execution. The EUSART, also known as a Serial Communications Interface (SCI), can be configured as a full-duplex asynchronous system or half-duplex synchronous system. Full-Duplex mode is useful for communications with peripheral systems, such as CRT terminals and personal computers. Half-Duplex Synchronous mode is intended for communications with peripheral devices, such as A/D or D/A integrated circuits, serial EEPROMs or other microcontrollers. These devices typically do not have internal clocks for baud rate generation and require the external clock signal provided by a master synchronous device.
The EUSART module implements the following additional features, making it ideally suited for use in Local Interconnect Network (LIN) bus systems: * Automatic detection and calibration of the baud rate * Wake-up on Break reception * 13-bit Break character transmit Block diagrams of the EUSART transmitter and receiver are shown in Figure 10-1 and Figure 10-2.
FIGURE 10-1:
EUSART TRANSMIT BLOCK DIAGRAM
Data Bus TXIE Interrupt TXREG Register 8 MSb (8) LSb TX/CK pin Pin Buffer and Control TXIF
***
Transmit Shift Register (TSR)
0
TXEN Baud Rate Generator TRMT FOSC /n n +1 Multiplier SYNC SPBRGH SPBRG BRGH BRG16 x4 x16 x64 0 0 0 TX9D TX9 SPEN
BRG16
1X00 X110 X101
(c) 2009 Microchip Technology Inc.
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FIGURE 10-2: EUSART RECEIVE BLOCK DIAGRAM
SPEN CREN OERR RCIDL
RX/DT pin Pin Buffer and Control Baud Rate Generator FOSC Data Recovery
MSb Stop (8) 7
RSR Register
LSb 0 START
***
RX9
1
/n
BRG16 +1 Multiplier SYNC SPBRGH SPBRG BRGH BRG16 x4 x16 x64 0 0 0 1X00 X110 X101
n
FERR
RX9D
RCREG Register 8 Data Bus RCIF RCIE
FIFO
Interrupt
The operation of the EUSART module is controlled through three registers: * Transmit Status and Control (TXSTA) * Receive Status and Control (RCSTA) * Baud Rate Control (BAUDCTL) These registers are detailed in Register 10-1, Register 10-2 and Register 10-3, respectively.
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10.1 EUSART Asynchronous Mode
Note 1: When the SPEN bit is set, the RX/DT I/O pin is automatically configured as an input, regardless of the state of the corresponding TRIS bit and whether or not the EUSART receiver is enabled. The RX/DT pin data can be read via a normal PORT read but PORT latch data output is precluded. 2: The TXIF transmitter interrupt flag is set when the TXEN enable bit is set. The EUSART transmits and receives data using the standard non-return-to-zero (NRZ) format. NRZ is implemented with two levels: a VOH mark state which represents a `1' data bit, and a VOL space state which represents a `0' data bit. NRZ refers to the fact that consecutively transmitted data bits of the same value stay at the output level of that bit without returning to a neutral level between each bit transmission. An NRZ transmission port idles in the mark state. Each character transmission consists of one Start bit followed by eight or nine data bits and is always terminated by one or more Stop bits. The Start bit is always a space and the Stop bits are always marks. The most common data format is 8 bits. Each transmitted bit persists for a period of 1/(Baud Rate). An on-chip dedicated 8-bit/16-bit Baud Rate Generator is used to derive standard baud rate frequencies from the system oscillator. See Table 10-5 for examples of baud rate configurations. The EUSART transmits and receives the LSb first. The EUSART's transmitter and receiver are functionally independent, but share the same data format and baud rate. Parity is not supported by the hardware, but can be implemented in software and stored as the ninth data bit.
10.1.1.2
Transmitting Data
10.1.1
EUSART ASYNCHRONOUS TRANSMITTER
A transmission is initiated by writing a character to the TXREG register. If this is the first character, or the previous character has been completely flushed from the TSR, the data in the TXREG is immediately transferred to the TSR register. If the TSR still contains all or part of a previous character, the new character data is held in the TXREG until the Stop bit of the previous character has been transmitted. The pending character in the TXREG is then transferred to the TSR in one TCY immediately following the Stop bit transmission. The transmission of the Start bit, data bits and Stop bit sequence commences immediately following the transfer of the data to the TSR from the TXREG.
10.1.1.3
Transmit Interrupt Flag
The EUSART transmitter block diagram is shown in Figure 10-1. The heart of the transmitter is the serial Transmit Shift Register (TSR), which is not directly accessible by software. The TSR obtains its data from the transmit buffer, which is the TXREG register.
10.1.1.1
Enabling the Transmitter
The EUSART transmitter is enabled for asynchronous operations by configuring the following three control bits: * TXEN = 1 * SYNC = 0 * SPEN = 1 All other EUSART control bits are assumed to be in their default state. Setting the TXEN bit of the TXSTA register enables the transmitter circuitry of the EUSART. Clearing the SYNC bit of the TXSTA register configures the EUSART for asynchronous operation. Setting the SPEN bit of the RCSTA register enables the EUSART and automatically configures the TX/CK I/O pin as an output. If the TX/CK pin is shared with an analog peripheral the analog I/O function must be disabled by clearing the corresponding ANSEL bit.
The TXIF interrupt flag bit of the PIR1 register is set whenever the EUSART transmitter is enabled and no character is being held for transmission in the TXREG. In other words, the TXIF bit is only clear when the TSR is busy with a character and a new character has been queued for transmission in the TXREG. The TXIF flag bit is not cleared immediately upon writing TXREG. TXIF becomes valid in the second instruction cycle following the write execution. Polling TXIF immediately following the TXREG write will return invalid results. The TXIF bit is read-only, it cannot be set or cleared by software. The TXIF interrupt can be enabled by setting the TXIE interrupt enable bit of the PIE1 register. However, the TXIF flag bit will be set whenever the TXREG is empty, regardless of the state of TXIE enable bit. To use interrupts when transmitting data, set the TXIE bit only when there is more data to send. Clear the TXIE interrupt enable bit upon writing the last character of the transmission to the TXREG.
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10.1.1.4 TSR Status 10.1.1.6
1.
Asynchronous Transmission Set-up:
The TRMT bit of the TXSTA register indicates the status of the TSR register. This is a read-only bit. The TRMT bit is set when the TSR register is empty and is cleared when a character is transferred to the TSR register from the TXREG. The TRMT bit remains clear until all bits have been shifted out of the TSR register. No interrupt logic is tied to this bit, so the user has to poll this bit to determine the TSR status. Note: The TSR register is not mapped in data memory, so it is not available to the user.
2. 3.
10.1.1.5
Transmitting 9-Bit Characters
4.
The EUSART supports 9-bit character transmissions. When the TX9 bit of the TXSTA register is set the EUSART will shift 9 bits out for each character transmitted. The TX9D bit of the TXSTA register is the ninth, and Most Significant, data bit. When transmitting 9-bit data, the TX9D data bit must be written before writing the 8 Least Significant bits into the TXREG. All nine bits of data will be transferred to the TSR shift register immediately after the TXREG is written. A special 9-bit Address mode is available for use with multiple receivers. See Section 10.1.2.7 "Address Detection" for more information on the Address mode.
5.
6. 7.
Initialize the SPBRGH, SPBRG register pair and the BRGH and BRG16 bits to achieve the desired baud rate (see Section 10.3 "EUSART Baud Rate Generator (BRG)"). Enable the asynchronous serial port by clearing the SYNC bit and setting the SPEN bit. If 9-bit transmission is desired, set the TX9 control bit. A set ninth data bit will indicate that the 8 Least Significant data bits are an address when the receiver is set for address detection. Enable the transmission by setting the TXEN control bit. This will cause the TXIF interrupt bit to be set. If interrupts are desired, set the TXIE interrupt enable bit. An interrupt will occur immediately provided that the GIE and PEIE bits of the INTCON register are also set. If 9-bit transmission is selected, the ninth bit should be loaded into the TX9D data bit. Load 8-bit data into the TXREG register. This will start the transmission.
FIGURE 10-3:
Write to TXREG BRG Output (Shift Clock) RC4/C2OUT/TX/CK pin TXIF bit (Transmit Buffer Reg. Empty Flag)
ASYNCHRONOUS TRANSMISSION
Word 1
Start bit
bit 0
bit 1 Word 1
bit 7/8
Stop bit
1 TCY
TRMT bit (Transmit Shift Reg. Empty Flag)
Word 1 Transmit Shift Reg
FIGURE 10-4:
Write to TXREG BRG Output (Shift Clock) RC4/C2OUT/TX/CK pin TXIF bit (Interrupt Reg. Flag) TRMT bit (Transmit Shift Reg. Empty Flag)
ASYNCHRONOUS TRANSMISSION (BACK-TO-BACK)
Word 1 Word 2
Start bit 1 TCY
bit 0
bit 1 Word 1
bit 7/8
Stop bit
Start bit Word 2
bit 0
1 TCY Word 1 Transmit Shift Reg. Word 2 Transmit Shift Reg.
Note:
This timing diagram shows two consecutive transmissions.
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TABLE 10-1:
Name BAUDCTL INTCON PIE1 PIR1 RCREG RCSTA SPBRG SPBRGH TRISC TXREG TXSTA Legend:
REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION
Bit 6 RCIDL
PEIE ADIE ADIF
Bit 7 ABDOVF
GIE EEIE EEIF
Bit 5 --
T0IE RCIE RCIF
Bit 4 SCKP
INTE C2IE C2IF
Bit 3 BRG16
RAIE C1IE C1IF
Bit 2 --
T0IF OSFIE OSFIF
Bit 1 WUE
INTF TXIE TXIF
Bit 0 ABDEN
RAIF TMR1IE TMR1IF
Value on POR, BOR 01-0 0-00 0000 000x 0000 0000 0000 0000 0000 0000 0000 000x 0000 0000 0000 0000
--11 1111
Value on all other Resets 01-0 0-00 0000 000x 0000 0000 0000 0000 0000 0000 0000 000x 0000 0000 0000 0000
--11 1111
EUSART Receive Data Register SPEN BRG7 BRG15
--
RX9 BRG6 BRG14
--
SREN BRG5 BRG13
TRISC5
CREN BRG4 BRG12
TRISC4
ADDEN BRG3 BRG11
TRISC3
FERR BRG2 BRG10
TRISC2
OERR BRG1 BRG9
TRISC1
RX9D BRG0 BRG8
TRISC0
EUSART Transmit Data Register CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D
0000 0000 0000 0010
0000 0000 0000 0010
x = unknown, - = unimplemented read as `0'. Shaded cells are not used for Asynchronous Transmission.
(c) 2009 Microchip Technology Inc.
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10.1.2 EUSART ASYNCHRONOUS RECEIVER 10.1.2.2 Receiving Data
The Asynchronous mode would typically be used in RS-232 systems. The receiver block diagram is shown in Figure 10-2. The data is received on the RX/DT pin and drives the data recovery block. The data recovery block is actually a high-speed shifter operating at 16 times the baud rate, whereas the serial Receive Shift Register (RSR) operates at the bit rate. When all 8 or 9 bits of the character have been shifted in, they are immediately transferred to a two character First-InFirst-Out (FIFO) memory. The FIFO buffering allows reception of two complete characters and the start of a third character before software must start servicing the EUSART receiver. The FIFO and RSR registers are not directly accessible by software. Access to the received data is via the RCREG register. The receiver data recovery circuit initiates character reception on the falling edge of the first bit. The first bit, also known as the Start bit, is always a zero. The data recovery circuit counts one-half bit time to the center of the Start bit and verifies that the bit is still a zero. If it is not a zero then the data recovery circuit aborts character reception, without generating an error, and resumes looking for the falling edge of the Start bit. If the Start bit zero verification succeeds then the data recovery circuit counts a full bit time to the center of the next bit. The bit is then sampled by a majority detect circuit and the resulting `0' or `1' is shifted into the RSR. This repeats until all data bits have been sampled and shifted into the RSR. One final bit time is measured and the level sampled. This is the Stop bit, which is always a `1'. If the data recovery circuit samples a `0' in the Stop bit position then a framing error is set for this character, otherwise the framing error is cleared for this character. See Section 10.1.2.4 "Receive Framing Error" for more information on framing errors. Immediately after all data bits and the Stop bit have been received, the character in the RSR is transferred to the EUSART receive FIFO and the RCIF interrupt flag bit of the PIR1 register is set. The top character in the FIFO is transferred out of the FIFO by reading the RCREG register. Note: If the receive FIFO is overrun, no additional characters will be received until the overrun condition is cleared. See Section 10.1.2.5 "Receive Overrun Error" for more information on overrun errors.
10.1.2.1
Enabling the Receiver
The EUSART receiver is enabled for asynchronous operation by configuring the following three control bits: * CREN = 1 * SYNC = 0 * SPEN = 1 All other EUSART control bits are assumed to be in their default state. Setting the CREN bit of the RCSTA register enables the receiver circuitry of the EUSART. Clearing the SYNC bit of the TXSTA register configures the EUSART for asynchronous operation. Setting the SPEN bit of the RCSTA register enables the EUSART and automatically configures the RX/DT I/O pin as an input. If the RX/DT pin is shared with an analog peripheral the analog I/O function must be disabled by clearing the corresponding ANSEL bit. Note: When the SPEN bit is set the TX/CK I/O pin is automatically configured as an output, regardless of the state of the corresponding TRIS bit and whether or not the EUSART transmitter is enabled. The PORT latch is disconnected from the output driver so it is not possible to use the TX/CK pin as a general purpose output.
10.1.2.3
Receive Interrupts
The RCIF interrupt flag bit of the PIR1 register is set whenever the EUSART receiver is enabled and there is an unread character in the receive FIFO. The RCIF interrupt flag bit is read-only, it cannot be set or cleared by software. RCIF interrupts are enabled by setting the following bits: * RCIE interrupt enable bit of the PIE1 register * PEIE peripheral interrupt enable bit of the INTCON register * GIE global interrupt enable bit of the INTCON register The RCIF interrupt flag bit will be set when there is an unread character in the FIFO, regardless of the state of interrupt enable bits.
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10.1.2.4 Receive Framing Error 10.1.2.7 Address Detection
Each character in the receive FIFO buffer has a corresponding framing error Status bit. A framing error indicates that a Stop bit was not seen at the expected time. The framing error status is accessed via the FERR bit of the RCSTA register. The FERR bit represents the status of the top unread character in the receive FIFO. Therefore, the FERR bit must be read before reading the RCREG. The FERR bit is read-only and only applies to the top unread character in the receive FIFO. A framing error (FERR = 1) does not preclude reception of additional characters. It is not necessary to clear the FERR bit. Reading the next character from the FIFO buffer will advance the FIFO to the next character and the next corresponding framing error. The FERR bit can be forced clear by clearing the SPEN bit of the RCSTA register which resets the EUSART. Clearing the CREN bit of the RCSTA register does not affect the FERR bit. A framing error by itself does not generate an interrupt. Note: If all receive characters in the receive FIFO have framing errors, repeated reads of the RCREG will not clear the FERR bit. A special Address Detection mode is available for use when multiple receivers share the same transmission line, such as in RS-485 systems. Address detection is enabled by setting the ADDEN bit of the RCSTA register. Address detection requires 9-bit character reception. When address detection is enabled, only characters with the ninth data bit set will be transferred to the receive FIFO buffer, thereby setting the RCIF interrupt bit. All other characters will be ignored. Upon receiving an address character, user software determines if the address matches its own. Upon address match, user software must disable address detection by clearing the ADDEN bit before the next Stop bit occurs. When user software detects the end of the message, determined by the message protocol used, software places the receiver back into the Address Detection mode by setting the ADDEN bit.
10.1.2.5
Receive Overrun Error
The receive FIFO buffer can hold two characters. An overrun error will be generated If a third character, in its entirety, is received before the FIFO is accessed. When this happens the OERR bit of the RCSTA register is set. The characters already in the FIFO buffer can be read but no additional characters will be received until the error is cleared. The error must be cleared by either clearing the CREN bit of the RCSTA register or by resetting the EUSART by clearing the SPEN bit of the RCSTA register.
10.1.2.6
Receiving 9-bit Characters
The EUSART supports 9-bit character reception. When the RX9 bit of the RCSTA register is set the EUSART will shift 9 bits into the RSR for each character received. The RX9D bit of the RCSTA register is the ninth and Most Significant data bit of the top unread character in the receive FIFO. When reading 9-bit data from the receive FIFO buffer, the RX9D data bit must be read before reading the 8 Least Significant bits from the RCREG.
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10.1.2.8
1.
Asynchronous Reception Set-up:
10.1.2.9
9-bit Address Detection Mode Set-up
2.
3.
4. 5. 6.
7.
8.
9.
Initialize the SPBRGH, SPBRG register pair and the BRGH and BRG16 bits to achieve the desired baud rate (see Section 10.3 "EUSART Baud Rate Generator (BRG)"). Enable the serial port by setting the SPEN bit. The SYNC bit must be clear for asynchronous operation. If interrupts are desired, set the RCIE interrupt enable bit and set the GIE and PEIE bits of the INTCON register. If 9-bit reception is desired, set the RX9 bit. Enable reception by setting the CREN bit. The RCIF interrupt flag bit will be set when a character is transferred from the RSR to the receive buffer. An interrupt will be generated if the RCIE interrupt enable bit was also set. Read the RCSTA register to get the error flags and, if 9-bit data reception is enabled, the ninth data bit. Get the received 8 Least Significant data bits from the receive buffer by reading the RCREG register. If an overrun occurred, clear the OERR flag by clearing the CREN receiver enable bit.
This mode would typically be used in RS-485 systems. To set up an Asynchronous Reception with Address Detect Enable: 1. Initialize the SPBRGH, SPBRG register pair and the BRGH and BRG16 bits to achieve the desired baud rate (see Section 10.3 "EUSART Baud Rate Generator (BRG)"). 2. Enable the serial port by setting the SPEN bit. The SYNC bit must be clear for asynchronous operation. 3. If interrupts are desired, set the RCIE interrupt enable bit and set the GIE and PEIE bits of the INTCON register. 4. Enable 9-bit reception by setting the RX9 bit. 5. Enable address detection by setting the ADDEN bit. 6. Enable reception by setting the CREN bit. 7. The RCIF interrupt flag bit will be set when a character with the ninth bit set is transferred from the RSR to the receive buffer. An interrupt will be generated if the RCIE interrupt enable bit was also set. 8. Read the RCSTA register to get the error flags. The ninth data bit will always be set. 9. Get the received 8 Least Significant data bits from the receive buffer by reading the RCREG register. Software determines if this is the device's address. 10. If an overrun occurred, clear the OERR flag by clearing the CREN receiver enable bit. 11. If the device has been addressed, clear the ADDEN bit to allow all received data into the receive buffer and generate interrupts.
FIGURE 10-5:
RX/DT pin Rcv Shift Reg Rcv Buffer Reg RCIDL Read Rcv Buffer Reg RCREG RCIF (Interrupt Flag) OERR bit CREN
ASYNCHRONOUS RECEPTION
Start bit bit 0 bit 1 bit 7/8 Stop bit Start bit bit 0 bit 7/8 Stop bit Start bit bit 7/8 Stop bit
Word 1 RCREG
Word 2 RCREG
Note:
This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word, causing the OERR (overrun) bit to be set.
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TABLE 10-2:
Name BAUDCTL INTCON PIE1 PIR1 RCREG RCSTA SPBRG SPBRGH TRISC TXREG TXSTA Legend:
REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Bit 6 RCIDL
PEIE ADIE ADIF
Bit 7 ABDOVF
GIE EEIE EEIF
Bit 5 --
T0IE RCIE RCIF
Bit 4 SCKP
INTE C2IE C2IF
Bit 3 BRG16
RAIE C1IE C1IF
Bit 2 --
T0IF OSFIE OSFIF
Bit 1 WUE
INTF TXIE TXIF
Bit 0 ABDEN
RAIF TMR1IE TMR1IF
Value on POR, BOR 01-0 0-00 0000 000x 0000 0000 0000 0000 0000 0000 0000 000x 0000 0000 0000 0000
--11 1111
Value on all other Resets 01-0 0-00 0000 000x 0000 0000 0000 0000 0000 0000 0000 000x 0000 0000 0000 0000
--11 1111
EUSART Receive Data Register SPEN BRG7 BRG15
--
RX9 BRG6 BRG14
--
SREN BRG5 BRG13
TRISC5
CREN BRG4 BRG12
TRISC4
ADDEN BRG3 BRG11
TRISC3
FERR BRG2 BRG10
TRISC2
OERR BRG1 BRG9
TRISC1
RX9D BRG0 BRG8
TRISC0
EUSART Transmit Data Register CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D
0000 0000 0000 0010
0000 0000 0000 0010
x = unknown, - = unimplemented read as `0'. Shaded cells are not used for Asynchronous Reception.
(c) 2009 Microchip Technology Inc.
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10.2 Clock Accuracy with Asynchronous Operation
The first (preferred) method uses the OSCTUNE register to adjust the INTOSC output. Adjusting the value in the OSCTUNE register allows for fine resolution changes to the system clock source. See Section 3.5 "Internal Clock Modes" for more information. The other method adjusts the value in the Baud Rate Generator. This can be done automatically with the Auto-Baud Detect feature (see Section 10.3.1 "AutoBaud Detect"). There may not be fine enough resolution when adjusting the Baud Rate Generator to compensate for a gradual change in the peripheral clock frequency.
The factory calibrates the internal oscillator block output (INTOSC). However, the INTOSC frequency may drift as VDD or temperature changes, and this directly affects the asynchronous baud rate. Two methods may be used to adjust the baud rate clock, but both require a reference clock source of some kind.
REGISTER 10-1:
R/W-0 CSRC bit 7 Legend: R = Readable bit -n = Value at POR bit 7
TXSTA: TRANSMIT STATUS AND CONTROL REGISTER
R/W-0 TX9 R/W-0 TXEN(1) R/W-0 SYNC R/W-0 SENDB R/W-0 BRGH R-1 TRMT R/W-0 TX9D bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
CSRC: Clock Source Select bit Asynchronous mode: Don't care Synchronous mode: 1 = Master mode (clock generated internally from BRG) 0 = Slave mode (clock from external source) TX9: 9-bit Transmit Enable bit 1 = Selects 9-bit transmission 0 = Selects 8-bit transmission TXEN: Transmit Enable bit(1) 1 = Transmit enabled 0 = Transmit disabled SYNC: EUSART Mode Select bit 1 = Synchronous mode 0 = Asynchronous mode SENDB: Send Break Character bit Asynchronous mode: 1 = Send Sync Break on next transmission (cleared by hardware upon completion) 0 = Sync Break transmission completed Synchronous mode: Don't care BRGH: High Baud Rate Select bit Asynchronous mode: 1 = High speed 0 = Low speed Synchronous mode: Unused in this mode TRMT: Transmit Shift Register Status bit 1 = TSR empty 0 = TSR full TX9D: Ninth bit of Transmit Data Can be address/data bit or a parity bit. SREN/CREN overrides TXEN in Sync mode.
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
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REGISTER 10-2:
R/W-0 SPEN bit 7 Legend: R = Readable bit -n = Value at POR bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
RCSTA: RECEIVE STATUS AND CONTROL REGISTER(1)
R/W-0 RX9 R/W-0 SREN R/W-0 CREN R/W-0 ADDEN R-0 FERR R-0 OERR R-x RX9D bit 0
SPEN: Serial Port Enable bit 1 = Serial port enabled (configures RX/DT and TX/CK pins as serial port pins) 0 = Serial port disabled (held in Reset) RX9: 9-bit Receive Enable bit 1 = Selects 9-bit reception 0 = Selects 8-bit reception SREN: Single Receive Enable bit Asynchronous mode: Don't care Synchronous mode - Master: 1 = Enables single receive 0 = Disables single receive This bit is cleared after reception is complete. Synchronous mode - Slave Don't care CREN: Continuous Receive Enable bit Asynchronous mode: 1 = Enables receiver 0 = Disables receiver Synchronous mode: 1 = Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN) 0 = Disables continuous receive ADDEN: Address Detect Enable bit Asynchronous mode 9-bit (RX9 = 1): 1 = Enables address detection, enable interrupt and load the receive buffer when RSR<8> is set 0 = Disables address detection, all bytes are received and ninth bit can be used as parity bit Asynchronous mode 8-bit (RX9 = 0): Don't care FERR: Framing Error bit 1 = Framing error (can be updated by reading RCREG register and receive next valid byte) 0 = No framing error OERR: Overrun Error bit 1 = Overrun error (can be cleared by clearing bit CREN) 0 = No overrun error RX9D: Ninth bit of Received Data This can be address/data bit or a parity bit and must be calculated by user firmware.
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
(c) 2009 Microchip Technology Inc.
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REGISTER 10-3:
R-0 ABDOVF bit 7 Legend: R = Readable bit -n = Value at POR bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
BAUDCTL: BAUD RATE CONTROL REGISTER
R-1 RCIDL U-0 -- R/W-0 SCKP R/W-0 BRG16 U-0 -- R/W-0 WUE R/W-0 ABDEN bit 0
ABDOVF: Auto-Baud Detect Overflow bit Asynchronous mode: 1 = Auto-baud timer overflowed 0 = Auto-baud timer did not overflow Synchronous mode: Don't care RCIDL: Receive Idle Flag bit Asynchronous mode: 1 = Receiver is Idle 0 = Start bit has been received and the receiver is receiving Synchronous mode: Don't care Unimplemented: Read as `0' SCKP: Synchronous Clock Polarity Select bit Asynchronous mode: 1 = Transmit inverted data to the RB7/TX/CK pin 0 = Transmit non-inverted data to the RB7/TX/CK pin Synchronous mode: 1 = Data is clocked on rising edge of the clock 0 = Data is clocked on falling edge of the clock BRG16: 16-bit Baud Rate Generator bit 1 = 16-bit Baud Rate Generator is used 0 = 8-bit Baud Rate Generator is used Unimplemented: Read as `0' WUE: Wake-up Enable bit Asynchronous mode: 1 = Receiver is waiting for a falling edge. No character will be received byte RCIF will be set. WUE will automatically clear after RCIF is set. 0 = Receiver is operating normally Synchronous mode: Don't care ABDEN: Auto-Baud Detect Enable bit Asynchronous mode: 1 = Auto-Baud Detect mode is enabled (clears when auto-baud is complete) 0 = Auto-Baud Detect mode is disabled Synchronous mode: Don't care
bit 6
bit 5 bit 4
bit 3
bit 2 bit 1
bit 0
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10.3 EUSART Baud Rate Generator (BRG)
If the system clock is changed during an active receive operation, a receive error or data loss may result. To avoid this problem, check the status of the RCIDL bit to make sure that the receive operation is Idle before changing the system clock.
The Baud Rate Generator (BRG) is an 8-bit or 16-bit timer that is dedicated to the support of both the asynchronous and synchronous EUSART operation. By default, the BRG operates in 8-bit mode. Setting the BRG16 bit of the BAUDCTL register selects 16-bit mode. The SPBRGH, SPBRG register pair determines the period of the free running baud rate timer. In Asynchronous mode the multiplier of the baud rate period is determined by both the BRGH bit of the TXSTA register and the BRG16 bit of the BAUDCTL register. In Synchronous mode, the BRGH bit is ignored. Table 10-3 contains the formulas for determining the baud rate. Example 10-1 provides a sample calculation for determining the baud rate and baud rate error. Typical baud rates and error values for various asynchronous modes have been computed for your convenience and are shown in Table 10-3. It may be advantageous to use the high baud rate (BRGH = 1), or the 16-bit BRG (BRG16 = 1) to reduce the baud rate error. The 16-bit BRG mode is used to achieve slow baud rates for fast oscillator frequencies. Writing a new value to the SPBRGH, SPBRG register pair causes the BRG timer to be reset (or cleared). This ensures that the BRG does not wait for a timer overflow before outputting the new baud rate.
EXAMPLE 10-1:
CALCULATING BAUD RATE ERROR
For a device with FOSC of 16 MHz, desired baud rate of 9600, Asynchronous mode, 8-bit BRG:
FOSC Desired Baud Rate = -------------------------------------------------------------------64 ( [SPBRGH:SPBRG] + 1 )
Solving for SPBRGH:SPBRG:
FOSC -------------------------------------------Desired Baud Rate X = --------------------------------------------- - 1 64 16000000 ----------------------9600 = ----------------------- - 1 64 = [ 25.042 ] = 25 16000000 Calculated Baud Rate = -------------------------64 ( 25 + 1 ) = 9615 Calc. Baud Rate - Desired Baud Rate Error = ------------------------------------------------------------------------------------------Desired Baud Rate ( 9615 - 9600 ) = ---------------------------------- = 0.16% 9600
TABLE 10-3:
SYNC 0 0 0 0 1 1 Legend:
BAUD RATE FORMULAS
BRG/EUSART Mode BRG16 0 0 1 1 0 1 BRGH 0 1 0 1 x x 8-bit/Asynchronous 8-bit/Asynchronous FOSC/[16 (n+1)] 16-bit/Asynchronous 16-bit/Asynchronous 8-bit/Synchronous 16-bit/Synchronous FOSC/[4 (n+1)] FOSC/[64 (n+1)] Baud Rate Formula
Configuration Bits
x = Don't care, n = value of SPBRGH, SPBRG register pair
TABLE 10-4:
Name BAUDCTL RCSTA SPBRG SPBRGH TXSTA Legend:
REGISTERS ASSOCIATED WITH THE BAUD RATE GENERATOR
Bit 6 RCIDL RX9 BRG6 BRG14 TX9 Bit 5 -- SREN BRG5 BRG13 TXEN Bit 4 SCKP CREN BRG4 BRG12 SYNC Bit 3 BRG16 ADDEN BRG3 BRG11 SENDB Bit 2 -- FERR BRG2 BRG10 BRGH Bit 1 WUE OERR BRG1 BRG9 TRMT Bit 0 ABDEN RX9D BRG0 BRG8 TX9D Value on POR, BOR 01-0 0-00 0000 000x 0000 0000 0000 0000 0000 0010 Value on all other Resets 01-0 0-00 0000 000x 0000 0000 0000 0000 0000 0010
Bit 7 ABDOVF SPEN BRG7 BRG15 CSRC
x = unknown, - = unimplemented read as `0'. Shaded cells are not used for the Baud Rate Generator.
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TABLE 10-5: BAUD RATES FOR ASYNCHRONOUS MODES
SYNC = 0, BRGH = 0, BRG16 = 0 BAUD RATE FOSC = 20.000 MHz Actual Rate -- 1221 2404 9470 10417 19.53k -- -- % Error -- 1.73 0.16 -1.36 0.00 1.73 -- -- SPBRG value (decimal) -- 255 129 32 29 15 -- -- FOSC = 18.432 MHz Actual Rate -- 1200 2400 9600 10286 19.20k 57.60k -- % Error -- 0.00 0.00 0.00 -1.26 0.00 0.00 -- SPBRG value (decimal) -- 239 119 29 27 14 7 -- FOSC = 11.0592 MHz Actual Rate -- 1200 2400 9600 10165 19.20k 57.60k -- % Error -- 0.00 0.00 0.00 -2.42 0.00 0.00 -- SPBRG value (decimal) -- 143 71 17 16 8 2 -- FOSC = 8.000 MHz Actual Rate -- 1202 2404 9615 10417 -- -- -- % Error -- 0.16 0.16 0.16 0.00 -- -- -- SPBRG value (decimal) -- 103 51 12 11 -- -- --
300 1200 2400 9600 10417 19.2k 57.6k 115.2k
SYNC = 0, BRGH = 0, BRG16 = 0 BAUD RATE FOSC = 4.000 MHz Actual Rate 300 1202 2404 -- 10417 -- -- -- % Error 0.16 0.16 0.16 -- 0.00 -- -- -- SPBRG value (decimal) 207 51 25 -- 5 -- -- -- FOSC = 3.6864 MHz Actual Rate 300 1200 2400 9600 -- 19.20k 57.60k -- % Error 0.00 0.00 0.00 0.00 -- 0.00 0.00 -- SPBRG value (decimal) 191 47 23 5 -- 2 0 -- FOSC = 2.000 MHz Actual Rate 300 1202 2404 -- 10417 -- -- -- % Error 0.16 0.16 0.16 -- 0.00 -- -- -- SPBRG value (decimal) 103 25 12 -- 2 -- -- -- FOSC = 1.000 MHz Actual Rate 300 1202 -- -- -- -- -- -- % Error 0.16 0.16 -- -- -- -- -- -- SPBRG value (decimal) 51 12 -- -- -- -- -- --
300 1200 2400 9600 10417 19.2k 57.6k 115.2k
SYNC = 0, BRGH = 1, BRG16 = 0 BAUD RATE FOSC = 20.000 MHz Actual Rate -- -- -- 9615 10417 19.23k 56.82k 113.64k % Error -- -- -- 0.16 0.00 0.16 -1.36 -1.36 SPBRG value (decimal) -- -- -- 129 119 64 21 10 FOSC = 18.432 MHz Actual Rate -- -- -- 9600 10378 19.20k 57.60k 115.2k % Error -- -- -- 0.00 -0.37 0.00 0.00 0.00 SPBRG value (decimal) -- -- -- 119 110 59 19 9 FOSC = 11.0592 MHz Actual Rate -- -- -- 9600 10473 19.20k 57.60k 115.2k % Error -- -- -- 0.00 0.53 0.00 0.00 0.00 SPBRG value (decimal) -- -- -- 71 65 35 11 5 FOSC = 8.000 MHz Actual Rate -- -- 2404 9615 10417 19231 55556 -- % Error -- -- 0.16 0.16 0.00 0.16 -3.55 -- SPBRG value (decimal) -- -- 207 51 47 25 8 --
300 1200 2400 9600 10417 19.2k 57.6k 115.2k
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TABLE 10-5: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED)
SYNC = 0, BRGH = 1, BRG16 = 0 BAUD RATE FOSC = 4.000 MHz Actual Rate -- 1202 2404 9615 10417 19.23k -- -- % Error -- 0.16 0.16 0.16 0.00 0.16 -- -- SPBRG value (decimal) -- 207 103 25 23 12 -- -- FOSC = 3.6864 MHz Actual Rate -- 1200 2400 9600 10473 19.2k 57.60k 115.2k % Error -- 0.00 0.00 0.00 0.53 0.00 0.00 0.00 SPBRG value (decimal) -- 191 95 23 21 11 3 1 FOSC = 2.000 MHz Actual Rate -- 1202 2404 9615 10417 -- -- -- % Error -- 0.16 0.16 0.16 0.00 -- -- -- SPBRG value (decimal) -- 103 51 12 11 -- -- -- FOSC = 1.000 MHz Actual Rate 300 1202 2404 -- 10417 -- -- -- % Error 0.16 0.16 0.16 -- 0.00 -- -- -- SPBRG value (decimal) 207 51 25 -- 5 -- -- --
300 1200 2400 9600 10417 19.2k 57.6k 115.2k
SYNC = 0, BRGH = 0, BRG16 = 1 BAUD RATE FOSC = 20.000 MHz Actual Rate 300.0 1200 2399 9615 10417 19.23k 56.818 113.636 % Error -0.01 -0.03 -0.03 0.16 0.00 0.16 -1.36 -1.36 SPBRG value (decimal) 4166 1041 520 129 119 64 21 10 FOSC = 18.432 MHz Actual Rate 300.0 1200 2400 9600 10378 19.20k 57.60k 115.2k % Error 0.00 0.00 0.00 0.00 -0.37 0.00 0.00 0.00 SPBRG value (decimal) 3839 959 479 119 110 59 19 9 FOSC = 11.0592 MHz Actual Rate 300.0 1200 2400 9600 10473 19.20k 57.60k 115.2k % Error 0.00 0.00 0.00 0.00 0.53 0.00 0.00 0.00 SPBRG value (decimal) 2303 575 287 71 65 35 11 5 FOSC = 8.000 MHz Actual Rate 299.9 1199 2404 9615 10417 19.23k 55556 -- % Error -0.02 -0.08 0.16 0.16 0.00 0.16 -3.55 -- SPBRG value (decimal) 1666 416 207 51 47 25 8 --
300 1200 2400 9600 10417 19.2k 57.6k 115.2k
SYNC = 0, BRGH = 0, BRG16 = 1 BAUD RATE FOSC = 4.000 MHz Actual Rate 300.1 1202 2404 9615 10417 19.23k -- -- % Error 0.04 0.16 0.16 0.16 0.00 0.16 -- -- SPBRG value (decimal) 832 207 103 25 23 12 -- -- FOSC = 3.6864 MHz Actual Rate 300.0 1200 2400 9600 10473 19.20k 57.60k 115.2k % Error 0.00 0.00 0.00 0.00 0.53 0.00 0.00 0.00 SPBRG value (decimal) 767 191 95 23 21 11 3 1 FOSC = 2.000 MHz Actual Rate 299.8 1202 2404 9615 10417 -- -- -- % Error -0.108 0.16 0.16 0.16 0.00 -- -- -- SPBRG value (decimal) 416 103 51 12 11 -- -- -- FOSC = 1.000 MHz Actual Rate 300.5 1202 2404 -- 10417 -- -- -- % Error 0.16 0.16 0.16 -- 0.00 -- -- -- SPBRG value (decimal) 207 51 25 -- 5 -- -- --
300 1200 2400 9600 10417 19.2k 57.6k 115.2k
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TABLE 10-5: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED)
SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1 BAUD RATE FOSC = 20.000 MHz Actual Rate 300.0 1200 2400 9597 10417 19.23k 57.47k 116.3k % Error 0.00 -0.01 0.02 -0.03 0.00 0.16 -0.22 0.94 SPBRG value (decimal) 16665 4166 2082 520 479 259 86 42 FOSC = 18.432 MHz Actual Rate 300.0 1200 2400 9600 10425 19.20k 57.60k 115.2k % Error 0.00 0.00 0.00 0.00 0.08 0.00 0.00 0.00 SPBRG value (decimal) 15359 3839 1919 479 441 239 79 39 FOSC = 11.0592 MHz Actual Rate 300.0 1200 2400 9600 10433 19.20k 57.60k 115.2k % Error 0.00 0.00 0.00 0.00 0.16 0.00 0.00 0.00 SPBRG value (decimal) 9215 2303 1151 287 264 143 47 23 FOSC = 8.000 MHz Actual Rate 300.0 1200 2401 9615 10417 19.23k 57.14k 117.6k % Error 0.00 -0.02 0.04 0.16 0 0.16 -0.79 2.12 SPBRG value (decimal) 6666 1666 832 207 191 103 34 16
300 1200 2400 9600 10417 19.2k 57.6k 115.2k
SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1 BAUD RATE FOSC = 4.000 MHz Actual Rate 300.0 1200 2398 9615 10417 19.23k 58.82k 111.1k % Error 0.01 0.04 0.08 0.16 0.00 0.16 2.12 -3.55 SPBRG value (decimal) 3332 832 416 103 95 51 16 8 FOSC = 3.6864 MHz Actual Rate 300.0 1200 2400 9600 10473 19.20k 57.60k 115.2k % Error 0.00 0.00 0.00 0.00 0.53 0.00 0.00 0.00 SPBRG value (decimal) 3071 767 383 95 87 47 15 7 FOSC = 2.000 MHz Actual Rate 299.9 1199 2404 9615 10417 19.23k 55.56k -- % Error -0.02 -0.08 0.16 0.16 0.00 0.16 -3.55 -- SPBRG value (decimal) 1666 416 207 51 47 25 8 -- FOSC = 1.000 MHz Actual Rate 300.1 1202 2404 9615 10417 19.23k -- -- % Error 0.04 0.16 0.16 0.16 0.00 0.16 -- -- SPBRG value (decimal) 832 207 103 25 23 12 -- --
300 1200 2400 9600 10417 19.2k 57.6k 115.2k
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10.3.1 AUTO-BAUD DETECT
The EUSART module supports automatic detection and calibration of the baud rate. In the Auto-Baud Detect (ABD) mode, the clock to the BRG is reversed. Rather than the BRG clocking the incoming RX signal, the RX signal is timing the BRG. The Baud Rate Generator is used to time the period of a received 55h (ASCII "U") which is the Sync character for the LIN bus. The unique feature of this character is that it has five rising edges including the Stop bit edge. Setting the ABDEN bit of the BAUDCTL register starts the auto-boot sequence (Figure 10-6). While the ABD sequence takes place, the EUSART state machine is held in Idle. On the first rising edge of the receive line, after the Start bit, the SPBRG begins counting up using the BRG counter clock as shown in Table 10-6. The fifth rising edge will occur on the RX pin at the end of the eighth bit period. At that time, an accumulated value totaling the proper BRG period is left in SPBRGH, SPBRG register pair, the ABDEN bit is automatically cleared and the RCIF interrupt flag is set. The value in the RCREG needs to be read to clear the RCIF interrupt. RCREG content should be discarded. When calibrating for modes that do not use the SPBRGH register the user can verify that the SPBRG register did not overflow by checking for 00h in the SPBRGH register. The BRG auto-baud clock is determined by the BRG16 and BRGH bits as shown in Table 10-6. During ABD, both the SPBRGH and SPBRG registers are used as a 16-bit counter, independent of the BRG16 bit setting. While calibrating the baud rate period, the SPBRGH and SPBRG registers are clocked at 1/8th the BRG base clock rate. The resulting byte measurement is the average bit time when clocked at full speed. Note 1: If the WUE bit is set with the ABDEN bit, auto-baud detection will occur on the byte following the Break character (see Section 10.3.3 "Auto-Wake-up on Break"). 2: It is up to the user to determine that the incoming character baud rate is within the range of the selected BRG clock source. Some combinations of oscillator frequency and EUSART baud rates are not possible due to bit error rates. Overall system timing and communication baud rates must be taken into consideration when using the Auto-Baud Detect feature. 3: During the auto-baud process, the autobaud counter starts counting at 1. Upon completion of the auto-baud sequence, to achieve maximum accuracy, subtract 1 from the SPBRGH:SPBRG register pair.
TABLE 10-6:
BRG16 0 0 1 1 Note: BRGH 0 1 0 1
BRG COUNTER CLOCK RATES
BRG Base Clock FOSC/64 FOSC/16 FOSC/16 FOSC/4 BRG ABD Clock FOSC/512 FOSC/128 FOSC/128 FOSC/32
During the ABD sequence, SPBRG and SPBRGH registers are both used as a 16-bit counter, independent of BRG16 setting.
FIGURE 10-6:
BRG Value RX pin
AUTOMATIC BAUD RATE CALCULATION
XXXXh 0000h Edge #1 bit 1 bit 0 Edge #2 bit 3 bit 2 Edge #3 bit 5 bit 4 Edge #4 bit 7 bit 6 001Ch Edge #5 Stop bit
Start
BRG Clock Set by User ABDEN bit RCIDL RCIF bit (Interrupt) Read RCREG SPBRG SPBRGH Note 1: XXh XXh The ABD sequence requires the EUSART module to be configured in Asynchronous mode. 1Ch 00h Auto Cleared
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10.3.2 AUTO-BAUD OVERFLOW
During the course of automatic baud detection, the ABDOVF bit of the BAUDCTL register will be set if the baud rate counter overflows before the fifth rising edge is detected on the RX pin. The ABDOVF bit indicates that the counter has exceeded the maximum count that can fit in the 16 bits of the SPBRGH:SPBRG register pair. After the ABDOVF has been set, the counter continues to count until the fifth rising edge is detected on the RX pin. Upon detecting the fifth RX edge, the hardware will set the RCIF interrupt flag and clear the ABDEN bit of the BAUDCTL register. The RCIF flag can be subsequently cleared by reading the RCREG. The ABDOVF flag can be cleared by software directly. To terminate the auto-baud process before the RCIF flag is set, clear the ABDEN bit then clear the ABDOVF bit. The ABDOVF bit will remain set if the ABDEN bit is not cleared first. The WUE bit is automatically cleared by the low-to-high transition on the RX line at the end of the Break. This signals to the user that the Break event is over. At this point, the EUSART module is in Idle mode waiting to receive the next character.
10.3.3.1
Special Considerations
Break Character To avoid character errors or character fragments during a wake-up event, the wake-up character must be all zeros. When the wake-up is enabled the function works independent of the low time on the data stream. If the WUE bit is set and a valid non-zero character is received, the low time from the Start bit to the first rising edge will be interpreted as the wake-up event. The remaining bits in the character will be received as a fragmented character and subsequent characters can result in framing or overrun errors. Therefore, the initial character in the transmission must be all `0's. This must be 10 or more bit times, 13-bit times recommended for LIN bus, or any number of bit times for standard RS-232 devices. Oscillator Start-up Time Oscillator start-up time must be considered, especially in applications using oscillators with longer start-up intervals (i.e., LP, XT or HS mode). The Sync Break (or wake-up signal) character must be of sufficient length, and be followed by a sufficient interval, to allow enough time for the selected oscillator to start and provide proper initialization of the EUSART. WUE Bit The wake-up event causes a receive interrupt by setting the RCIF bit. The WUE bit is cleared in hardware by a rising edge on RX/DT. The interrupt condition is then cleared in software by reading the RCREG register and discarding its contents. To ensure that no actual data is lost, check the RCIDL.
10.3.3
AUTO-WAKE-UP ON BREAK
During Sleep mode, all clocks to the EUSART are suspended. Because of this, the Baud Rate Generator is inactive and a proper character reception cannot be performed. The Auto-Wake-up feature allows the controller to wake-up due to activity on the RX/DT line. This feature is available only in Asynchronous mode. The Auto-Wake-up feature is enabled by setting the WUE bit of the BAUDCTL register. Once set, the normal receive sequence on RX/DT is disabled, and the EUSART remains in an Idle state, monitoring for a wakeup event independent of the CPU mode. A wake-up event consists of a high-to-low transition on the RX/DT line. (This coincides with the start of a Sync Break or a wake-up signal character for the LIN protocol.) The EUSART module generates an RCIF interrupt coincident with the wake-up event. The interrupt is generated synchronously to the Q clocks in normal CPU operating modes (Figure 10-7), and asynchronously if the device is in Sleep mode (Figure 10-8). The interrupt condition is cleared by reading the RCREG register.
FIGURE 10-7:
OSC1
AUTO-WAKE-UP BIT (WUE) TIMING DURING NORMAL OPERATION
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Bit set by user WUE bit RX/DT Line RCIF Auto Cleared
Cleared due to User Read of RCREG The EUSART remains in Idle while the WUE bit is set.
Note 1:
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FIGURE 10-8:
OSC1 Bit Set by User WUE bit RX/DT Line RCIF Sleep Command Executed Note 1: 2: Sleep Ends Note 1 Cleared due to User Read of RCREG Auto Cleared
AUTO-WAKE-UP BIT (WUE) TIMINGS DURING SLEEP
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4
Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4
If the wake-up event requires long oscillator warm-up time, the automatic clearing of the WUE bit can occur while the stposc signal is still active. This sequence should not depend on the presence of Q clocks. The EUSART remains in Idle while the WUE bit is set.
10.3.4
BREAK CHARACTER SEQUENCE
10.3.5
RECEIVING A BREAK CHARACTER
The EUSART module has the capability of sending the special Break character sequences that are required by the LIN bus standard. A Break character consists of a Start bit, followed by 12 `0' bits and a Stop bit. To send a Break character, set the SENDB and TXEN bits of the TXSTA register. The Break character transmission is then initiated by a write to the TXREG. The value of data written to TXREG will be ignored and all `0's will be transmitted. The SENDB bit is automatically reset by hardware after the corresponding Stop bit is sent. This allows the user to preload the transmit FIFO with the next transmit byte following the Break character (typically, the Sync character in the LIN specification). The TRMT bit of the TXSTA register indicates when the transmit operation is active or Idle, just as it does during normal transmission. See Figure 10-9 for the timing of the Break character sequence.
The Enhanced EUSART module can receive a Break character in two ways. The first method to detect a Break character uses the FERR bit of the RCSTA register and the Received data as indicated by RCREG. The Baud Rate Generator is assumed to have been initialized to the expected baud rate. A Break character has been received when; * RCIF bit is set * FERR bit is set * RCREG = 00h The second method uses the Auto-Wake-up feature described in Section 10.3.3 "Auto-Wake-up on Break". By enabling this feature, the EUSART will sample the next two transitions on RX/DT, cause an RCIF interrupt, and receive the next data byte followed by another interrupt. Note that following a Break character, the user will typically want to enable the Auto-Baud Detect feature. For both methods, the user can set the ABDEN bit of the BAUDCTL register before placing the EUSART in Sleep mode.
10.3.4.1
Break and Sync Transmit Sequence
The following sequence will start a message frame header made up of a Break, followed by an auto-baud Sync byte. This sequence is typical of a LIN bus master. 1. 2. 3. 4. 5. Configure the EUSART for the desired mode. Set the TXEN and SENDB bits to enable the Break sequence. Load the TXREG with a dummy character to initiate transmission (the value is ignored). Write `55h' to TXREG to load the Sync character into the transmit FIFO buffer. After the Break has been sent, the SENDB bit is reset by hardware and the Sync character is then transmitted.
When the TXREG becomes empty, as indicated by the TXIF, the next data byte can be written to TXREG.
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FIGURE 10-9:
Write to TXREG BRG Output (Shift Clock) TX (pin) Start bit bit 0 bit 1 Break TXIF bit (Transmit interrupt Flag) TRMT bit (Transmit Shift Reg. Empty Flag) SENDB Sampled Here SENDB (send Break control bit) Auto Cleared bit 11 Stop bit
SEND BREAK CHARACTER SEQUENCE
Dummy Write
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10.4 EUSART Synchronous Mode
Synchronous serial communications are typically used in systems with a single master and one or more slaves. The master device contains the necessary circuitry for baud rate generation and supplies the clock for all devices in the system. Slave devices can take advantage of the master clock by eliminating the internal clock generation circuitry. There are two signal lines in Synchronous mode: a bidirectional data line and a clock line. Slaves use the external clock supplied by the master to shift the serial data into and out of their respective receive and transmit shift registers. Since the data line is bidirectional, synchronous operation is half-duplex only. Half-duplex refers to the fact that master and slave devices can receive and transmit data but not both simultaneously. The EUSART can operate as either a master or slave device. Start and Stop bits are not used in synchronous transmissions. the clock Idle state as high. When the SCKP bit is set, the data changes on the falling edge of each clock. Clearing the SCKP bit sets the Idle state as low. When the SCKP bit is cleared, the data changes on the rising edge of each clock.
10.4.1.3
Synchronous Master Transmission
Data is transferred out of the device on the RX/DT pin. The RX/DT and TX/CK pin output drivers are automatically enabled when the EUSART is configured for synchronous master transmit operation. A transmission is initiated by writing a character to the TXREG register. If the TSR still contains all or part of a previous character, the new character data is held in the TXREG until the last bit of the previous character has been transmitted. If this is the first character, or the previous character has been completely flushed from the TSR, the data in the TXREG is immediately transferred to the TSR. The transmission of the character commences immediately following the transfer of the data to the TSR from the TXREG. Each data bit changes on the leading edge of the master clock and remains valid until the subsequent leading clock edge. Note: The TSR register is not mapped in data memory, so it is not available to the user.
10.4.1
SYNCHRONOUS MASTER MODE
The following bits are used to configure the EUSART for Synchronous Master operation: * * * * * SYNC = 1 CSRC = 1 SREN = 0 (for transmit); SREN = 1 (for receive) CREN = 0 (for transmit); CREN = 1 (for receive) SPEN = 1
10.4.1.4
1.
Synchronous Master Transmission Set-up:
Setting the SYNC bit of the TXSTA register configures the device for synchronous operation. Setting the CSRC bit of the TXSTA register configures the device as a master. Clearing the SREN and CREN bits of the RCSTA register ensures that the device is in the Transmit mode, otherwise the device will be configured to receive. Setting the SPEN bit of the RCSTA register enables the EUSART. If the RX/DT or TX/CK pins are shared with an analog peripheral the analog I/O functions must be disabled by clearing the corresponding ANSEL bits.
2. 3. 4. 5. 6. 7. 8.
10.4.1.1
Master Clock
Synchronous data transfers use a separate clock line, which is synchronous with the data. A device configured as a master transmits the clock on the TX/ CK line. The TX/CK pin is automatically configured as an output when the EUSART is configured for synchronous transmit operation. Serial data bits change on the leading edge to ensure they are valid at the trailing edge of each clock. One clock cycle is generated for each data bit. Only as many clock cycles are generated as there are data bits.
Initialize the SPBRGH, SPBRG register pair and the BRGH and BRG16 bits to achieve the desired baud rate (see Section 10.3 "EUSART Baud Rate Generator (BRG)"). Enable the synchronous master serial port by setting bits SYNC, SPEN and CSRC. Disable Receive mode by clearing bits SREN and CREN. Enable Transmit mode by setting the TXEN bit. If 9-bit transmission is desired, set the TX9 bit. If interrupts are desired, set the TXIE, GIE and PEIE interrupt enable bits. If 9-bit transmission is selected, the ninth bit should be loaded in the TX9D bit. Start transmission by loading data to the TXREG register.
10.4.1.2
Clock Polarity
A clock polarity option is provided for Microwire compatibility. Clock polarity is selected with the SCKP bit of the BAUDCTL register. Setting the SCKP bit sets
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PIC16F688
FIGURE 10-10: SYNCHRONOUS TRANSMISSION
RX/DT pin TX/CK pin (SCKP = 0) TX/CK pin (SCKP = 1) Write to TXREG Reg TXIF bit (Interrupt Flag) TRMT bit Write Word 1
bit 0
bit 1 Word 1
bit 2
bit 7
bit 0
bit 1 Word 2
bit 7
Write Word 2
TXEN bit Note:
`1' Sync Master mode, SPBRG = 0, continuous transmission of two 8-bit words.
`1'
FIGURE 10-11:
SYNCHRONOUS TRANSMISSION (THROUGH TXEN)
RX/DT pin bit 0 bit 1 bit 2 bit 6 bit 7
TX/CK pin Write to TXREG reg
TXIF bit
TRMT bit
TXEN bit
TABLE 10-7:
Name BAUDCTL INTCON PIE1 PIR1 RCREG RCSTA SPBRG SPBRGH TRISC TXREG TXSTA Legend:
REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION
Bit 6 RCIDL
PEIE ADIE ADIF
Bit 7 ABDOVF
GIE EEIE EEIF
Bit 5 --
T0IE RCIE RCIF
Bit 4 SCKP
INTE C2IE C2IF
Bit 3 BRG16
RAIE C1IE C1IF
Bit 2 --
T0IF OSFIE OSFIF
Bit 1 WUE
INTF TXIE TXIF
Bit 0 ABDEN
RAIF TMR1IE TMR1IF
Value on POR, BOR 01-0 0-00 0000 000x 0000 0000 0000 0000 0000 0000
Value on all other Resets 01-0 0-00 0000 000x 0000 0000 0000 0000 0000 0000 0000 000x 0000 0000 0000 0000
--11 1111
EUSART Receive Data Register SPEN BRG7 BRG15
--
RX9 BRG6 BRG14
--
SREN BRG5 BRG13
TRISC5
CREN BRG4 BRG12
TRISC4
ADDEN BRG3 BRG11
TRISC3
FERR BRG2 BRG10
TRISC2
OERR BRG1 BRG9
TRISC1
RX9D BRG0 BRG8
TRISC0
0000 000x 0000 0000 0000 0000
--11 1111
EUSART Transmit Data Register CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D
0000 0000 0000 0010
0000 0000 0000 0010
x = unknown, - = unimplemented read as `0'. Shaded cells are not used for Synchronous Master Transmission.
DS41203E-page 104
(c) 2009 Microchip Technology Inc.
PIC16F688
10.4.1.5 Synchronous Master Reception 10.4.1.8
1. Data is received at the RX/DT pin. The RX/DT and TX/ CK pin output drivers are automatically disabled when the EUSART is configured for synchronous master receive operation. In Synchronous mode, reception is enabled by setting either the Single Receive Enable bit (SREN of the RCSTA register) or the Continuous Receive Enable bit (CREN of the RCSTA register). When SREN is set and CREN is clear, only as many clock cycles are generated as there are data bits in a single character. The SREN bit is automatically cleared at the completion of one character. When CREN is set, clocks are continuously generated until CREN is cleared. If CREN is cleared in the middle of a character the CK clock stops immediately and the partial character is discarded. If SREN and CREN are both set, then SREN is cleared at the completion of the first character and CREN takes precedence. To initiate reception, set either SREN or CREN. Data is sampled at the RX/DT pin on the trailing edge of the TX/CK clock pin and is shifted into the Receive Shift Register (RSR). When a complete character is received into the RSR, the RCIF bit is set and the character is automatically transferred to the two character receive FIFO. The Least Significant eight bits of the top character in the receive FIFO are available in RCREG. The RCIF bit remains set as long as there are un-read characters in the receive FIFO.
Synchronous Master Reception Setup:
Initialize the SPBRGH, SPBRG register pair for the appropriate baud rate. Set or clear the BRGH and BRG16 bits, as required, to achieve the desired baud rate. 2. Enable the synchronous master serial port by setting bits SYNC, SPEN and CSRC. 3. Ensure bits CREN and SREN are clear. 4. If using interrupts, set the GIE and PEIE bits of the INTCON register and set RCIE. 5. If 9-bit reception is desired, set bit RX9. 6. Start reception by setting the SREN bit or for continuous reception, set the CREN bit. 7. Interrupt flag bit RCIF will be set when reception of a character is complete. An interrupt will be generated if the enable bit RCIE was set. 8. Read the RCSTA register to get the ninth bit (if enabled) and determine if any error occurred during reception. 9. Read the 8-bit received data by reading the RCREG register. 10. If an overrun error occurs, clear the error by either clearing the CREN bit of the RCSTA register or by clearing the SPEN bit which resets the EUSART.
10.4.1.6
Receive Overrun Error
The receive FIFO buffer can hold two characters. An overrun error will be generated if a third character, in its entirety, is received before RCREG is read to access the FIFO. When this happens the OERR bit of the RCSTA register is set. Previous data in the FIFO will not be overwritten. The two characters in the FIFO buffer can be read, however, no additional characters will be received until the error is cleared. The OERR bit can only be cleared by clearing the overrun condition. If the overrun error occurred when the SREN bit is set and CREN is clear then the error is cleared by reading RCREG. If the overrun occurred when the CREN bit is set then the error condition is cleared by either clearing the CREN bit of the RCSTA register or by clearing the SPEN bit which resets the EUSART.
10.4.1.7
Receiving 9-bit Characters
The EUSART supports 9-bit character reception. When the RX9 bit of the RCSTA register is set the EUSART will shift 9-bits into the RSR for each character received. The RX9D bit of the RCSTA register is the ninth, and Most Significant, data bit of the top unread character in the receive FIFO. When reading 9-bit data from the receive FIFO buffer, the RX9D data bit must be read before reading the 8 Least Significant bits from the RCREG.
(c) 2009 Microchip Technology Inc.
DS41203E-page 105
PIC16F688
FIGURE 10-12:
RX/DT pin TX/CK pin (SCKP = 0) TX/CK pin (SCKP = 1) Write to bit SREN SREN bit CREN bit `0' RCIF bit (Interrupt) Read RXREG Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0. `0'
SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
bit 0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
TABLE 10-8:
Name BAUDCTL INTCON PIE1 PIR1 RCREG RCSTA SPBRG SPBRGH TRISC TXREG TXSTA Legend:
REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION
Bit 6 RCIDL
PEIE ADIE ADIF
Bit 7 ABDOVF
GIE EEIE EEIF
Bit 5 --
T0IE RCIE RCIF
Bit 4 SCKP
INTE C2IE C2IF
Bit 3 BRG16
RAIE C1IE C1IF
Bit 2 --
T0IF OSFIE OSFIF
Bit 1 WUE
INTF TXIE TXIF
Bit 0 ABDEN
RAIF TMR1IE TMR1IF
Value on POR, BOR 01-0 0-00 0000 000x 0000 0000 0000 0000 0000 0000 0000 000x 0000 0000 0000 0000
--11 1111
Value on all other Resets 01-0 0-00 0000 000x 0000 0000 0000 0000 0000 0000 0000 000x 0000 0000 0000 0000
--11 1111
EUSART Receive Data Register SPEN BRG7 BRG15
--
RX9 BRG6 BRG14
--
SREN BRG5 BRG13
TRISC5
CREN BRG4 BRG12
TRISC4
ADDEN BRG3 BRG11
TRISC3
FERR BRG2 BRG10
TRISC2
OERR BRG1 BRG9
TRISC1
RX9D BRG0 BRG8
TRISC0
EUSART Transmit Data Register CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D
0000 0000 0000 0010
0000 0000 0000 0010
x = unknown, - = unimplemented read as `0'. Shaded cells are not used for Synchronous Master Reception.
DS41203E-page 106
(c) 2009 Microchip Technology Inc.
PIC16F688
10.4.2 SYNCHRONOUS SLAVE MODE
The following bits are used to configure the EUSART for Synchronous slave operation: * * * * * SYNC = 1 CSRC = 0 SREN = 0 (for transmit); SREN = 1 (for receive) CREN = 0 (for transmit); CREN = 1 (for receive) SPEN = 1 If two words are written to the TXREG and then the SLEEP instruction is executed, the following will occur: 1. 2. 3. 4. The first character will immediately transfer to the TSR register and transmit. The second word will remain in TXREG register. The TXIF bit will not be set. After the first character has been shifted out of TSR, the TXREG register will transfer the second character to the TSR and the TXIF bit will now be set. If the PEIE and TXIE bits are set, the interrupt will wake the device from Sleep and execute the next instruction. If the GIE bit is also set, the program will call the Interrupt Service Routine.
Setting the SYNC bit of the TXSTA register configures the device for synchronous operation. Clearing the CSRC bit of the TXSTA register configures the device as a slave. Clearing the SREN and CREN bits of the RCSTA register ensures that the device is in the Transmit mode, otherwise the device will be configured to receive. Setting the SPEN bit of the RCSTA register enables the EUSART. If the RX/DT or TX/CK pins are shared with an analog peripheral the analog I/O functions must be disabled by clearing the corresponding ANSEL bits.
5.
10.4.2.2
1. 2. 3.
Synchronous Slave Transmission Set-up:
10.4.2.1
EUSART Synchronous Slave Transmit
The operation of the Synchronous Master and Slave modes are identical (see Section 10.4.1.3 "Synchronous Master Transmission"), except in the case of the Sleep mode.
4. 5. 6. 7.
Set the SYNC and SPEN bits and clear the CSRC bit. Clear the CREN and SREN bits. If using interrupts, ensure that the GIE and PEIE bits of the INTCON register are set and set the TXIE bit. If 9-bit transmission is desired, set the TX9 bit. Enable transmission by setting the TXEN bit. If 9-bit transmission is selected, insert the Most Significant bit into the TX9D bit. Start transmission by writing the Least Significant 8 bits to the TXREG register.
TABLE 10-9:
Name BAUDCTL INTCON PIE1 PIR1 RCREG RCSTA SPBRG SPBRGH TRISC TXREG TXSTA Legend:
REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION
Bit 6 RCIDL PEIE ADIE ADIF RX9 BRG6 BRG14 -- TX9 Bit 5 -- T0IE RCIE RCIF SREN BRG5 BRG13 TRISC5 TXEN Bit 4 SCKP INTE C2IE C2IF CREN BRG4 BRG12 TRISC4 SYNC Bit 3 BRG16 RAIE C1IE C1IF ADDEN BRG3 BRG11 TRISC3 SENDB Bit 2 -- T0IF OSFIE OSFIF FERR BRG2 BRG10 TRISC2 BRGH Bit 1 WUE INTF TXIE TXIF OERR BRG1 BRG9 TRISC1 TRMT Bit 0 ABDEN RAIF TMR1IE TMR1IF RX9D BRG0 BRG8 TRISC0 TX9D Value on POR, BOR 01-0 0-00 0000 000x 0000 0000 0000 0000 0000 0000 0000 000x 0000 0000 0000 0000 --11 1111 0000 0000 0000 0010 Value on all other Resets 01-0 0-00 0000 000x 0000 0000 0000 0000 0000 0000 0000 000x 0000 0000 0000 0000 --11 1111 0000 0000 0000 0010
Bit 7 ABDOVF GIE EEIE EEIF SPEN BRG7 BRG15 -- CSRC
EUSART Receive Data Register
EUSART Transmit Data Register
x = unknown, - = unimplemented read as `0'. Shaded cells are not used for Synchronous Slave Transmission.
(c) 2009 Microchip Technology Inc.
DS41203E-page 107
PIC16F688
10.4.2.3 EUSART Synchronous Slave Reception 10.4.2.4
1. 2.
Synchronous Slave Reception Setup:
The operation of the Synchronous Master and Slave modes is identical (Section 10.4.1.5 "Synchronous Master Reception"), with the following exceptions: * Sleep * CREN bit is always set, therefore the receiver is never Idle * SREN bit, which is a "don't care" in Slave mode A character may be received while in Sleep mode by setting the CREN bit prior to entering Sleep. Once the word is received, the RSR register will transfer the data to the RCREG register. If the RCIE enable bit is set, the interrupt generated will wake the device from Sleep and execute the next instruction. If the GIE bit is also set, the program will branch to the interrupt vector.
3. 4. 5.
6.
7. 8.
Set the SYNC and SPEN bits and clear the CSRC bit. If using interrupts, ensure that the GIE and PEIE bits of the INTCON register are set and set the RCIE bit. If 9-bit reception is desired, set the RX9 bit. Set the CREN bit to enable reception. The RCIF bit will be set when reception is complete. An interrupt will be generated if the RCIE bit was set. If 9-bit mode is enabled, retrieve the Most Significant bit from the RX9D bit of the RCSTA register. Retrieve the 8 Least Significant bits from the receive FIFO by reading the RCREG register. If an overrun error occurs, clear the error by either clearing the CREN bit of the RCSTA register or by clearing the SPEN bit which resets the EUSART.
TABLE 10-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION
Name BAUDCTL INTCON PIE1 PIR1 RCREG RCSTA SPBRG SPBRGH TRISC TXREG TXSTA Legend: Bit 7 ABDOVF
GIE EEIE EEIF
Bit 6 RCIDL
PEIE ADIE ADIF
Bit 5 --
T0IE RCIE RCIF
Bit 4 SCKP
INTE C2IE C2IF
Bit 3 BRG16
RAIE C1IE C1IF
Bit 2 --
T0IF OSFIE OSFIF
Bit 1 WUE
INTF TXIE TXIF
Bit 0 ABDEN
RAIF TMR1IE TMR1IF
Value on POR, BOR 01-0 0-00 0000 000x 0000 0000 0000 0000 0000 0000
Value on all other Resets 01-0 0-00 0000 000x 0000 0000 0000 0000 0000 0000 0000 000x 0000 0000 0000 0000
--11 1111
EUSART Receive Data Register SPEN BRG7 BRG15
--
RX9 BRG6 BRG14
--
SREN BRG5 BRG13
TRISC5
CREN BRG4 BRG12
TRISC4
ADDEN BRG3 BRG11
TRISC3
FERR BRG2 BRG10
TRISC2
OERR BRG1 BRG9
TRISC1
RX9D BRG0 BRG8
TRISC0
0000 000x 0000 0000 0000 0000
--11 1111
EUSART Transmit Data Register CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D
0000 0000 0000 0010
0000 0000 0000 0010
x = unknown, - = unimplemented read as `0'. Shaded cells are not used for Synchronous Slave Reception.
DS41203E-page 108
(c) 2009 Microchip Technology Inc.
PIC16F688
11.0 SPECIAL FEATURES OF THE CPU
The PIC16F688 has two timers that offer necessary delays on power-up. One is the Oscillator Start-up Timer (OST), intended to keep the chip in Reset until the crystal oscillator is stable. The other is the Power-up Timer (PWRT), which provides a fixed delay of 64 ms (nominal) on power-up only, designed to keep the part in Reset while the power supply stabilizes. There is also circuitry to reset the device if a brown-out occurs, which can use the Power-up Timer to provide at least a 64 ms Reset. With these three functions-on-chip, most applications need no external Reset circuitry. The Sleep mode is designed to offer a very low-current Power-Down mode. The user can wake-up from Sleep through: * External Reset * Watchdog Timer Wake-up * An interrupt Several oscillator options are also made available to allow the part to fit the application. The INTOSC option saves system cost while the LP crystal option saves power. A set of Configuration bits are used to select various options (see Register 11-1).
The PIC16F688 has a host of features intended to maximize system reliability, minimize cost through elimination of external components, provide power-saving features and offer code protection. These features are: * Reset - Power-on Reset (POR) - Power-up Timer (PWRT) - Oscillator Start-up Timer (OST) - Brown-out Reset (BOR) * Interrupts * Watchdog Timer (WDT) * Oscillator Selection * Sleep * Code Protection * ID Locations * In-Circuit Serial ProgrammingTM
(c) 2009 Microchip Technology Inc.
DS41203E-page 109
PIC16F688
11.1 Configuration Bits
The Configuration bits can be programmed (read as `0'), or left unprogrammed (read as `1') to select various device configurations as shown in Register 11-1. These bits are mapped in program memory location 2007h. Note: Address 2007h is beyond the user program memory space. It belongs to the special configuration memory space (2000h-3FFFh), which can be accessed only during programming. See "PIC12F6XX/16F6XX Memory Programming Specification" (DS41204) for more information.
DS41203E-page 110
(c) 2009 Microchip Technology Inc.
PIC16F688
REGISTER 11-1:
Reserved bit 15
CONFIG: CONFIGURATION WORD REGISTER
Reserved Reserved FCMEN IESO BOREN1(1) BOREN0(1) bit 8
Reserved
CPD(2) bit 7 Legend: R = Readable bit -n = Value at POR bit 15-12 bit 11
CP(3)
MCLRE(4)
PWRTE
WDTE
FOSC2
FOSC1
FOSC0 bit 0
W = Writable bit `1' = Bit is set
P = Programmable' `0' = Bit is cleared
U = Unimplemented bit, read as `0' x = Bit is unknown
Reserved: Reserved bits. Do Not Use. FCMEN: Fail-Safe Clock Monitor Enabled bit 1 = Fail-Safe Clock Monitor is enabled 0 = Fail-Safe Clock Monitor is disabled IESO: Internal External Switchover bit 1 = Internal External Switchover mode is enabled 0 = Internal External Switchover mode is disabled BOREN<1:0>: Brown-out Reset Selection bits(1) 11 = BOR enabled 10 = BOR enabled during operation and disabled in Sleep 01 = BOR controlled by SBOREN bit of the PCON register 00 = BOR disabled CPD: Data Code Protection bit(2) 1 = Data memory code protection is disabled 0 = Data memory code protection is enabled CP: Code Protection bit(2) 1 = Program memory code protection is disabled 0 = Program memory code protection is enabled MCLRE: MCLR Pin Function Select bit(3) 1 = MCLR pin function is MCLR 0 = MCLR pin function is digital input, MCLR internally tied to VDD PWRTE: Power-up Timer Enable bit 1 = PWRT disabled 0 = PWRT enabled WDTE: Watchdog Timer Enable bit 1 = WDT enabled 0 = WDT disabled FOSC<2:0>: Oscillator Selection bits 111 = EXTRC oscillator: External RC on RA5/OSC1/CLKIN, CLKOUT function on RA4/OSC2/CLKOUT pin 110 = EXTRCIO oscillator: External RC on RA5/OSC1/CLKIN, I/O function on RA4/OSC2/CLKOUT pin 101 = INTOSC oscillator: CLKOUT function on RA4/OSC2/CLKOUT pin, I/O function on RA5/OSC1/CLKIN 100 = INTOSCIO oscillator: I/O function on RA4/OSC2/CLKOUT pin, I/O function on RA5/OSC1/CLKIN 011 = EC: I/O function on RA4/OSC2/CLKOUT pin, CLKIN on RA5/OSC1/CLKIN 010 = HS oscillator: High-speed crystal/resonator on RA4/OSC2/CLKOUT and RA5/OSC1/CLKIN 001 = XT oscillator: Crystal/resonator on RA4/OSC2/CLKOUT and RA5/OSC1/CLKIN 000 = LP oscillator: Low-power crystal on RA4/OSC2/CLKOUT and RA5/OSC1/CLKIN Enabling Brown-out Reset does not automatically enable Power-up Timer. The entire data EEPROM will be erased when the code protection is turned off. The entire program memory will be erased when the code protection is turned off. When MCLR is asserted in INTOSC or RC mode, the internal clock oscillator is disabled.
bit 10
bit 9-8
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2-0
Note 1: 2: 3: 4:
(c) 2009 Microchip Technology Inc.
DS41203E-page 111
PIC16F688
11.2 Reset
The PIC16F688 differentiates between various kinds of Reset: a) b) c) d) e) f) Power-on Reset (POR) WDT Reset during normal operation WDT Reset during Sleep MCLR Reset during normal operation MCLR Reset during Sleep Brown-out Reset (BOR) They are not affected by a WDT wake-up since this is viewed as the resumption of normal operation. TO and PD bits are set or cleared differently in different Reset situations, as indicated in Table 11-2. These bits are used in software to determine the nature of the Reset. See Table 11-4 for a full description of Reset states of all registers. A simplified block diagram of the On-Chip Reset Circuit is shown in Figure 11-1. The MCLR Reset path has a noise filter to detect and ignore small pulses. See Section 14.0 "Electrical Specifications" for pulse width specifications.
Some registers are not affected in any Reset condition; their status is unknown on POR and unchanged in any other Reset. Most other registers are reset to a "Reset state" on: * * * * * Power-on Reset MCLR Reset MCLR Reset during Sleep WDT Reset Brown-out Reset (BOR)
FIGURE 11-1:
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
External Reset
MCLR/VPP pin Sleep WDT Module VDD Rise Detect VDD Brown-out(1) Reset Power-on Reset BOREN SBOREN WDT Time-out Reset
S
OST/PWRT OST 10-bit Ripple Counter OSC1/ CLKI pin PWRT LFINTOSC 11-bit Ripple Counter R Q Chip_Reset
Enable PWRT Enable OST
Note
1:
Refer to the Configuration Word register (Register 11-1).
DS41203E-page 112
(c) 2009 Microchip Technology Inc.
PIC16F688
11.2.1 POWER-ON RESET FIGURE 11-2:
VDD PIC16F688 R1 1 k (or greater)
The on-chip POR circuit holds the chip in Reset until VDD has reached a high enough level for proper operation. To take advantage of the POR, simply connect the MCLR pin through a resistor to VDD. This will eliminate external RC components usually needed to create Power-on Reset. A maximum rise time for VDD is required. See Section 14.0 "Electrical Specifications" for details. If the BOR is enabled, the maximum rise time specification does not apply. The BOR circuitry will keep the device in Reset until VDD reaches VBOD (see Section 11.2.4 "Brown-Out Reset (BOR)"). Note: The POR circuit does not produce an internal Reset when VDD declines. To re-enable the POR, VDD must reach Vss for a minimum of 100 s.
RECOMMENDED MCLR CIRCUIT
MCLR C1 0.1 F (optional, not critical)
11.2.3
POWER-UP TIMER (PWRT)
When the device starts normal operation (exits the Reset condition), device operating parameters (i.e., voltage, frequency, temperature, etc.) must be met to ensure operation. If these conditions are not met, the device must be held in Reset until the operating conditions are met. For additional information, refer to Application Note AN607, "Power-up Trouble Shooting" (DS00607).
11.2.2
MCLR
The Power-up Timer provides a fixed 64 ms (nominal) time-out on power-up only, from POR or Brown-out Reset. The Power-up Timer operates from the 31 kHz LFINTOSC oscillator. For more information, see Section 3.5 "Internal Clock Modes". The chip is kept in Reset as long as PWRT is active. The PWRT delay allows the VDD to rise to an acceptable level. A Configuration bit, PWRTE, can disable (if set) or enable (if cleared or programmed) the Power-up Timer. The Power-up Timer should be enabled when Brown-out Reset is enabled, although it is not required. The Power-up Timer delay will vary from chip-to-chip and vary due to: * VDD variation * Temperature variation * Process variation See DC parameters for details "Electrical Specifications"). Note: (Section 14.0
PIC16F688 has a noise filter in the MCLR Reset path. The filter will detect and ignore small pulses. It should be noted that a WDT Reset does not drive MCLR pin low. The behavior of the ESD protection on the MCLR pin has been altered from early devices of this family. Voltages applied to the pin that exceed its specification can result in both MCLR Resets and excessive current beyond the device specification during the ESD event. For this reason, Microchip recommends that the MCLR pin no longer be tied directly to VDD. The use of an RC network, as shown in Figure 11-2, is suggested. An internal MCLR option is enabled by clearing the MCLRE bit in the Configuration Word register. When MCLRE = 0, the Reset signal to the chip is generated internally. When the MCLRE = 1, the RA3/MCLR pin becomes an external Reset input. In this mode, the RA3/MCLR pin has a weak pull-up to VDD.
Voltage spikes below VSS at the MCLR pin, inducing currents greater than 80 mA, may cause latch-up. Thus, a series resistor of 50-100 should be used when applying a "low" level to the MCLR pin, rather than pulling this pin directly to VSS.
(c) 2009 Microchip Technology Inc.
DS41203E-page 113
PIC16F688
11.2.4 BROWN-OUT RESET (BOR)
The BOREN0 and BOREN1 bits in the Configuration Word register selects one of four BOR modes. Two modes have been added to allow software or hardware control of the BOR enable. When BOREN<1:0> = 01, the SBOREN bit of the PCON register enables/disables the BOR, allowing it to be controlled in software. By selecting BOREN<1:0>, the BOR is automatically disabled in Sleep to conserve power and enabled on wake-up. In this mode, the SBOREN bit is disabled. See Register 11-1 for the Configuration Word definition. If VDD falls below VBOD for greater than parameter (TBOD) (see Section 14.0 "Electrical Specifications"), the Brown-out situation will reset the device. This will occur regardless of VDD slew rate. A Reset is not insured to occur if VDD falls below VBOD for less than parameter (TBOD). On any Reset (Power-on, Brown-out Reset, Watchdog Timer, etc.), the chip will remain in Reset until VDD rises above VBOD (see Figure 11-3). The Power-up Timer will now be invoked, if enabled and will keep the chip in Reset an additional 64 ms. Note: The Power-up Timer is enabled by the PWRTE bit in the Configuration Word register.
If VDD drops below VBOD while the Power-up Timer is running, the chip will go back into a Brown-out Reset and the Power-up Timer will be re-initialized. Once VDD rises above VBOD, the Power-up Timer will execute a 64 ms Reset.
FIGURE 11-3:
VDD
BROWN-OUT SITUATIONS
VBOD
Internal Reset VDD
64 ms(1)
VBOD < 64 ms
Internal Reset
64 ms(1)
VDD
VBOD
Internal Reset Note 1: 64 ms delay only if PWRTE bit is programmed to `0'.
64 ms(1)
DS41203E-page 114
(c) 2009 Microchip Technology Inc.
PIC16F688
11.2.5 TIME-OUT SEQUENCE 11.2.6
On power-up, the time-out sequence is as follows: first, PWRT time-out is invoked after POR has expired, then OST is activated after the PWRT time-out has expired. The total time-out will vary based on oscillator configuration and PWRTE bit status. For example, in EC mode with PWRTE bit erased (PWRT disabled), there will be no time-out at all. Figure 11.2.1, Figure 11-5 and Figure 11-6 depict time-out sequences. The device can execute code from the INTOSC while OST is active by enabling Two-Speed Start-up or Fail-Safe Monitor (see Section 3.7.2 "Two-Speed Start-up Sequence" and Section 3.8 "Fail-Safe Clock Monitor"). Since the time-outs occur from the POR pulse, if MCLR is kept low long enough, the time-outs will expire. Then, bringing MCLR high will begin execution immediately (see Figure 11-5). This is useful for testing purposes or to synchronize more than one PIC16F688 device operating in parallel. Table 11-5 shows the Reset conditions for some special registers, while Table 11-4 shows the Reset conditions for all the registers.
POWER CONTROL (PCON) REGISTER
The Power Control (PCON) register (address 8Eh) has two Status bits to indicate what type of Reset that last occurred. Bit 0 is BOR (Brown-out). BOR is unknown on Power-on Reset. It must then be set by the user and checked on subsequent Resets to see if BOR = 0, indicating that a Brown-out has occurred. The BOR Status bit is a "don't care" and is not necessarily predictable if the brown-out circuit is disabled (BOREN<1:0> = 00 in the Configuration Word register). Bit 1 is POR (Power-on Reset). It is a `0' on Power-on Reset and unaffected otherwise. The user must write a `1' to this bit following a Power-on Reset. On a subsequent Reset, if POR is `0', it will indicate that a Power-on Reset has occurred (i.e., VDD may have gone too low). For more information, see Section 4.2.4 "Ultra Low-Power Wake-up" and Section 11.2.4 "Brown-Out Reset (BOR)".
TABLE 11-1:
TIME-OUT IN VARIOUS SITUATIONS
Power-up Brown-out Reset PWRTE = 0 TPWRT + 1024 * TOSC TPWRT PWRTE = 1 1024 * TOSC -- Wake-up from Sleep 1024 * TOSC --
Oscillator Configuration PWRTE = 0 XT, HS, LP RC, EC, INTOSC TPWRT + 1024 * TOSC TPWRT PWRTE = 1 1024 * TOSC --
TABLE 11-2:
POR 0 1 u u u u
PCON BITS AND THEIR SIGNIFICANCE
TO 1 1 0 0 u 1 PD 1 1 u 0 u 0 Power-on Reset Brown-out Reset WDT Reset WDT Wake-up MCLR Reset during normal operation MCLR Reset during Sleep Condition
BOR u 0 u u u u
Legend: u = unchanged, x = unknown
TABLE 11-3:
Name CONFIG(2) PCON STATUS Legend: Note 1: 2: Bit 9
SUMMARY OF REGISTERS ASSOCIATED WITH BROWN-OUT RESET
Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR -- --01 --qq 0001 1xxx Value on all other Resets(1) -- --0u --uu 000q quuu
BOREN1
BOREN0
CPD -- IRP
CP -- RP1
MCLRE
PWRTE
WDTE -- PD
FOSC2 -- Z
FOSC1 POR DC
FOSC0 BOR C
ULPWUE SBOREN RP0 TO
u = unchanged, x = unknown, - = unimplemented bit, reads as `0', q = value depends on condition. Shaded cells are not used by BOR. Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation. See Configuration Word register (Register 11-1) for operation of all register bits.
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FIGURE 11-4: TIME-OUT SEQUENCE ON POWER-UP (DELAYED MCLR)
VDD MCLR Internal POR TPWRT PWRT Time-out
TOST
OST Time-out
Internal Reset
FIGURE 11-5:
TIME-OUT SEQUENCE ON POWER-UP (DELAYED MCLR)
VDD MCLR Internal POR TPWRT PWRT Time-out
TOST
OST Time-out
Internal Reset
FIGURE 11-6:
VDD MCLR Internal POR
TIME-OUT SEQUENCE ON POWER-UP (MCLR WITH VDD)
TPWRT PWRT Time-out
TOST
OST Time-out
Internal Reset
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TABLE 11-4:
Register
INITIALIZATION CONDITION FOR REGISTERS
Address Power-on Reset xxxx xxxx xxxx xxxx xxxx xxxx 0000 0000 0001 1xxx xxxx xxxx --x0 x000 --xx 0000 ---0 0000 0000 000x 0000 0000 xxxx xxxx xxxx xxxx 0000 0000 01-0 0-00 -000 0000 0000 0000 0000 0000 0000 0000 0000 0010 000x 000x ---0 1000 0000 0000 ---- --10 xxxx xxxx 00-0 0000 1111 1111 --11 1111 --11 1111 0000 0000 --01 --0x MCLR Reset WDT Reset Brown-out Reset(1) uuuu uuuu uuuu uuuu uuuu uuuu 0000 0000 000q quuu(4) uuuu uuuu --00 0000 --00 0000 ---0 0000 0000 000x 0000 0000 uuuu uuuu uuuu uuuu uuuu uuuu 01-0 0-00 -000 0000 0000 0000 0000 0000 0000 0000 0000 0010 000x 000x ---0 1000 0000 0000 ---- --10 uuuu uuuu 00-0 0000 1111 1111 --11 1111 --11 1111 0000 0000 --0u --uu(1,5) Wake-up from Sleep through Interrupt Wake-up from Sleep through WDT Time-out uuuu uuuu uuuu uuuu uuuu uuuu PC + 1(3) uuuq quuu(4) uuuu uuuu --uu uuuu --uu uuuu ---u uuuu uuuu uuuu(2) uuuu uuuu(2) uuuu uuuu uuuu uuuu -uuu uuuu uu-u u-uu -uuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu ---u uuuu uuuu uuuu ---- --uu uuuu uuuu uu-u uuuu uuuu uuuu --uu uuuu --uu uuuu uuuu uuuu --uu --uu
W INDF TMR0 PCL STATUS FSR PORTA PORTC PCLATH INTCON PIR1 TMR1L TMR1H T1CON BAUDCTL SPBRGH SPBRG RCREG TXREG TXSTA RCSTA WDTCON CMCON0 CMCON1 ADRESH ADCON0 OPTION_REG TRISA TRISC PIE1 PCON Legend: Note 1: 2: 3: 4: 5:
-- 00h/80h/100h/180h 01h/101h 02h/82h/102h/182h 03h/83h/103h/183h 04h/84h/104h/184h 05h/105h 07h/107h 0Ah/8Ah/10Ah/18Ah 0Bh/8Bh/10Bh/18Bh 0Ch 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Eh 1Fh 81h/181h 85h/185h 87h/187h 8Ch 8Eh
u = unchanged, x = unknown, - = unimplemented bit, reads as `0', q = value depends on condition. If VDD goes too low, Power-on Reset will be activated and registers will be affected differently. One or more bits in INTCON and/or PIR1 will be affected (to cause wake-up). When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h). See Table 11-5 for Reset value for specific condition. If Reset was due to brown-out, then bit 0 = 0. All other Resets will cause bit 0 = u.
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TABLE 11-4:
Register
INITIALIZATION CONDITION FOR REGISTERS (CONTINUED)
Address Power-on Reset -110 q000 ---0 0000 1111 1111 --11 -111 --00 0000 --00 0000 ---- 0000 0-0- 0000 0000 0000 0000 0000 x--- x000 ---- ---xxxx xxxx -000 ---* MCLR Reset * WDT Reset * Brown-out Reset(1) -110 q000 ---u uuuu 1111 1111 --11 -111 --00 0000 --00 0000 ---- 0000 0-0- 0000 0000 0000 0000 0000 u--- q000 ---- ---uuuu uuuu -000 ---* Wake-up from Sleep through interrupt * Wake-up from Sleep through WDT time-out -uuu uuuu ---u uuuu uuuu uuuu uuuu uuuu --uu uuuu --uu uuuu ---- uuuu u-u- uuuu uuuu uuuu uuuu uuuu u--- uuuu ---- ---uuuu uuuu -uuu ----
OSCCON OSCTUNE ANSEL WPUA IOCA EEDATH EEADRH VRCON EEDAT EEADR EECON1 EECON2 ADRESL ADCON1 Legend: Note 1: 2: 3: 4: 5:
8Fh 90h 91h 95h 96h 97h 98h 99h 9Ah 9Bh 9Ch 9Dh 9Eh 9Fh
u = unchanged, x = unknown, - = unimplemented bit, reads as `0', q = value depends on condition. If VDD goes too low, Power-on Reset will be activated and registers will be affected differently. One or more bits in INTCON and/or PIR1 will be affected (to cause wake-up). When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h). See Table 11-5 for Reset value for specific condition. If Reset was due to brown-out, then bit 0 = 0. All other Resets will cause bit 0 = u.
TABLE 11-5:
INITIALIZATION CONDITION FOR SPECIAL REGISTERS
Condition Program Counter 000h 000h 000h 000h PC + 1 000h PC + 1
(1)
Status Register 0001 1xxx 000u uuuu 0001 0uuu 0000 uuuu uuu0 0uuu 0001 1uuu uuu1 0uuu
PCON Register --01 --0x --0u --uu --0u --uu --0u --uu --uu --uu --01 --10 --uu --uu
Power-on Reset MCLR Reset during normal operation MCLR Reset during Sleep WDT Reset WDT Wake-up Brown-out Reset Interrupt Wake-up from Sleep
Legend: u = unchanged, x = unknown, - = unimplemented bit, reads as `0'. Note 1: When the wake-up is due to an interrupt and Global Interrupt Enable bit, GIE, is set, the PC is loaded with the interrupt vector (0004h) after execution of PC + 1.
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11.3
* * * * * * * * *
Interrupts
The PIC16F688 has multiple sources of interrupt: External Interrupt RA2/INT TMR0 Overflow Interrupt PORTA Change Interrupts 2 Comparator Interrupts A/D Interrupt Timer1 Overflow Interrupt EEPROM Data Write Interrupt Fail-Safe Clock Monitor Interrupt EUSART Receive and Transmit interrupts
For external interrupt events, such as the INT pin or PORTA change interrupt, the interrupt latency will be three or four instruction cycles. The exact latency depends upon when the interrupt event occurs (see Figure 11-8). The latency is the same for one or two-cycle instructions. Once in the Interrupt Service Routine, the source(s) of the interrupt can be determined by polling the interrupt flag bits. The interrupt flag bit(s) must be cleared in software before re-enabling interrupts to avoid multiple interrupt requests. Note 1: Individual interrupt flag bits are set, regardless of the status of their corresponding mask bit or the GIE bit. 2: When an instruction that clears the GIE bit is executed, any interrupts that were pending for execution in the next cycle are ignored. The interrupts, which were ignored, are still pending to be serviced when the GIE bit is set again. For additional information on Timer1, A/D or data EEPROM modules, refer to the respective peripheral section.
The Interrupt Control (INTCON) register and Peripheral Interrupt Request 1 (PIR1) register record individual interrupt requests in flag bits. The INTCON register also has individual and global interrupt enable bits. A Global Interrupt Enable bit, GIE bit of the INTCON register, enables (if set) all unmasked interrupts, or disables (if cleared) all interrupts. Individual interrupts can be disabled through their corresponding enable bits in the INTCON register and PIE1 register. GIE is cleared on Reset. The Return from Interrupt instruction, RETFIE, exits the interrupt routine, as well as sets the GIE bit, which re-enables unmasked interrupts. The following interrupt flags are contained in the INTCON register: * INT Pin Interrupt * PORTA Change Interrupt * TMR0 Overflow Interrupt The peripheral interrupt flags are contained in the special register, PIR1. The corresponding interrupt enable bit is contained in special register, PIE1. The following interrupt flags are contained in the PIR1 register: * * * * * * EEPROM Data Write Interrupt A/D Interrupt EUSART Receive and Transmit Interrupts 2 Comparator Interrupts Timer1 Overflow Interrupt Fail-Safe Clock Monitor Interrupt
When an interrupt is serviced: * The GIE is cleared to disable any further interrupt. * The return address is pushed onto the stack. * The PC is loaded with 0004h.
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11.3.1 RA2/INT INTERRUPT 11.3.2 TIMER0 INTERRUPT
External interrupt on RA2/INT pin is edge-triggered; either rising if the INTEDG bit of the OPTION register is set, or falling if the INTEDG bit is clear. When a valid edge appears on the RA2/INT pin, the INTF bit of the INTCON register is set. This interrupt can be disabled by clearing the INTE control bit of the INTCON register. The INTF bit must be cleared in software in the Interrupt Service Routine before re-enabling this interrupt. The RA2/INT interrupt can wake-up the processor from Sleep if the INTE bit was set prior to going into Sleep. The status of the GIE bit decides whether or not the processor branches to the interrupt vector following wake-up (0004h). See Section 11.6 "Power-Down Mode (Sleep)" for details on Sleep and Figure 11-10 for timing of wake-up from Sleep through RA2/INT interrupt. Note: The ANSEL (91h) and CMCON0 (19h) registers must be initialized to configure an analog channel as a digital input. Pins configured as analog inputs will read `0'. An overflow (FFh 00h) in the TMR0 register will set the T0IF of the INTCON register bit. The interrupt can be enabled/disabled by setting/clearing T0IE bit of the INTCON register. See Section 5.0 "Timer0 Module" for operation of the Timer0 module.
11.3.3
PORTA INTERRUPT
An input change on PORTA change sets the RAIF bit of the INTCON register. The interrupt can be enabled/disabled by setting/clearing the RAIE bit of the INTCON register. Plus, individual pins can be configured through the IOCA register. Note: If a change on the I/O pin should occur when the read operation is being executed (start of the Q2 cycle), then the RAIF interrupt flag may not get set.
FIGURE 11-7:
INTERRUPT LOGIC
IOC-RA0 IOCA0 IOC-RA1 IOCA1 IOC-RA2 IOCA2 IOC-RA3 IOCA3 IOC-RA4 IOCA4 IOC-RA5 IOCA5 TXIF TXIE TMR1IF TMR1IE C1IF C1IE C2IF C2IE ADIF ADIE EEIF EEIE OSFIF OSFIE RCIF RCIE T0IF T0IE INTF INTE RAIF RAIE PEIE GIE Wake-up (If in Sleep mode)
Interrupt to CPU
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FIGURE 11-8:
Q1 OSC1 CLKOUT (3)
(4)
INT PIN INTERRUPT TIMING
Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
INT pin INTF Flag (INTCON<1>) GIE bit (INTCON<7>) Instruction Flow PC Instruction Fetched Instruction Executed Note 1: 2: 3: 4: 5:
(1) (5)
(1)
Interrupt Latency (2)
PC Inst (PC) Inst (PC - 1)
PC + 1 Inst (PC + 1) Inst (PC)
PC + 1 -- Dummy Cycle
0004h Inst (0004h) Dummy Cycle
0005h Inst (0005h) Inst (0004h)
INTF flag is sampled here (every Q1). Asynchronous interrupt latency = 3-4 TCY. Synchronous latency = 3 TCY, where TCY = instruction cycle time. Latency is the same whether Inst (PC) is a single cycle or a two-cycle instruction. CLKOUT is available only in INTOSC and RC Oscillator modes. For minimum width of INT pulse, refer to AC specifications in Section 14.0 "Electrical Specifications". INTF is enabled to be set any time during the Q4-Q1 cycles.
TABLE 11-6:
Name INTCON PIE1 PIR1 Legend:
SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPTS
Bit 7 GIE EEIE EEIF Bit 6 PEIE ADIE ADIF Bit 5 T0IE RCIE RCIF Bit 4 INTE C2IE C2IF Bit 3 RAIE C1IE C1IF Bit 2 T0IF OSFIE OSFIF Bit 1 INTF TXIE TXIF Bit 0 RAIF TMR1IE TMR1IF Value on POR, BOR 0000 000x 0000 0000 0000 0000 Value on all other Resets 0000 000x 0000 0000 0000 0000
x = unknown, u = unchanged, -- = unimplemented read as `0', q = value depends upon condition. Shaded cells are not used by the Interrupt module.
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11.4 Context Saving During Interrupts
During an interrupt, only the return PC value is saved on the stack. Typically, users may wish to save key registers during an interrupt (e.g., W and Status registers). This must be implemented in software. Since the lower 16 bytes of all banks are common in the PIC16F688 (see Figure 2-2), temporary holding registers, W_TEMP and STATUS_TEMP, should be placed in here. These 16 locations do not require banking and therefore, make it easier to context save and restore. The same code shown in Example 11-1 can be used to: * * * * * Store the W register Store the Status register Execute the ISR code Restore the Status (and Bank Select Bit register) Restore the W register
Note:
The PIC16F688 normally does not require saving the PCLATH. However, if computed GOTO's are used in the ISR and the main code, the PCLATH must be saved and restored in the ISR.
EXAMPLE 11-1:
MOVWF SWAPF
SAVING STATUS AND W REGISTERS IN RAM
;Copy W to TEMP ;Swap status to ;Swaps are used ;Save status to register be saved into W because they do not affect the status bits bank zero STATUS_TEMP register
W_TEMP STATUS,W
MOVWF STATUS_TEMP : :(ISR) : SWAPF STATUS_TEMP,W MOVWF SWAPF SWAPF STATUS W_TEMP,F W_TEMP,W
;Insert user code here ;Swap STATUS_TEMP register into W ;(sets bank to original state) ;Move W into STATUS register ;Swap W_TEMP ;Swap W_TEMP into W
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11.5
* * * * *
Watchdog Timer (WDT)
The WDT has the following features: Operates from the LFINTOSC (31 kHz) Contains a 16-bit prescaler Shares an 8-bit prescaler with Timer0 Time-out period is from 1 ms to 268 seconds Configuration bit and software controlled
A new prescaler has been added to the path between the INTRC and the multiplexers used to select the path for the WDT. This prescaler is 16 bits and can be programmed to divide the INTRC by 32 to 65536, giving the WDT a nominal range of 1 ms to 268s.
11.5.2
WDT CONTROL
The WDTE bit is located in the Configuration Word register. When set, the WDT runs continuously. When the WDTE bit in the Configuration Word register is set, the SWDTEN bit of the WDTCON register has no effect. If WDTE is clear, then the SWDTEN bit can be used to enable and disable the WDT. Setting the bit will enable it and clearing the bit will disable it. The PSA and PS<2:0> bits of the OPTION register have the same function as in previous versions of the PIC16F688 family of microcontrollers. See Section 5.0 "Timer0 Module" for more information.
WDT is cleared under certain conditions described in Table 11-7.
11.5.1
WDT OSCILLATOR
The WDT derives its time base from the 31 kHz LFINTOSC. The LTS bit does not reflect that the LFINTOSC is enabled. The value of WDTCON is `---0 1000' on all Resets. This gives a nominal time base of 16 ms, which is compatible with the time base generated with previous PIC16F688 microcontroller versions. Note: When the Oscillator Start-up Timer (OST) is invoked, the WDT is held in Reset, because the WDT Ripple Counter is used by the OST to perform the oscillator delay count. When the OST count has expired, the WDT will begin counting (if enabled).
FIGURE 11-9:
WATCHDOG TIMER BLOCK DIAGRAM
From TMR0 Clock Source 0 Prescaler(1) 16-bit WDT Prescaler 1 8 PSA
PS<2:0> To TMR0 0 1 PSA
31 kHz LFINTOSC Clock
WDTPS<3:0>
WDTE from Configuration Word Register SWDTEN from WDTCON WDT Time-out Note 1: This is the shared Timer0/WDT prescaler. See Section 5.1.3 "Software Programmable Prescaler" for more information.
TABLE 11-7:
WDT STATUS
Conditions WDT
WDTE = 0 CLRWDT Command Oscillator Fail Detected Exit Sleep + System Clock = T1OSC, EXTRC, INTRC, EXTCLK Exit Sleep + System Clock = XT, HS, LP
Cleared
Cleared until the end of OST
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REGISTER 11-2:
U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7-5 bit 4-1 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
WDTCON: WATCHDOG TIMER CONTROL REGISTER
U-0 -- U-0 -- R/W-0 WDTPS3 R/W-1 WDTPS2 R/W-0 WDTPS1 R/W-0 WDTPS0 R/W-0 SWDTEN bit 0
Unimplemented: Read as `0' WDTPS<3:0>: Watchdog Timer Period Select bits Bit Value = Prescale Rate 0000 = 1:32 0001 = 1:64 0010 = 1:128 0011 = 1:256 0100 = 1:512 (Reset value) 0101 = 1:1024 0110 = 1:2048 0111 = 1:4096 1000 = 1:8192 1001 = 1:16384 1010 = 1:32768 1011 = 1:65536 1100 = Reserved 1101 = Reserved 1110 = Reserved 1111 = Reserved SWDTEN: Software Enable or Disable the Watchdog Timer(1) 1 = WDT is turned on 0 = WDT is turned off (Reset value) If WDTE Configuration bit = 1, then WDT is always enabled, irrespective of this control bit. If WDTE Configuration bit = 0, then it is possible to turn WDT on/off with this control bit.
bit 0
Note 1:
TABLE 11-8:
Name WDTCON OPTION_REG CONFIG Legend: Note 1:
SUMMARY OF REGISTERS ASSOCIATED WITH WATCHDOG TIMER
Bit 7 -- RAPU CPD Bit 6 -- INTEDG CP Bit 5 -- T0CS MCLRE Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR ---0 1000 1111 1111 -- Value on all other Resets ---0 1000 1111 1111 --
WDTPS3 WDTPS2 WSTPS1 WDTPS0 SWDTEN T0SE PWRTE PSA WDTE PS2 FOSC2 PS1 FOSC1 PS0 FOSC0
Shaded cells are not used by the Watchdog Timer. See Register 11.0 for operation of all Configuration Word register bits.
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11.6 Power-Down Mode (Sleep)
The Power-down mode is entered by executing a SLEEP instruction. If the Watchdog Timer is enabled: * * * * * WDT will be cleared but keeps running. PD bit in the Status register is cleared. TO bit is set. Oscillator driver is turned off. I/O ports maintain the status they had before SLEEP was executed (driving high, low or high-impedance). Other peripherals cannot generate interrupts since during Sleep, no on-chip clocks are present. When the SLEEP instruction is being executed, the next instruction (PC + 1) is prefetched. For the device to wake-up through an interrupt event, the corresponding interrupt enable bit must be set (enabled). Wake-up is regardless of the state of the GIE bit. If the GIE bit is clear (disabled), the device continues execution at the instruction after the SLEEP instruction. If the GIE bit is set (enabled), the device executes the instruction after the SLEEP instruction, then branches to the interrupt address (0004h). In cases where the execution of the instruction following SLEEP is not desirable, the user should have a NOP after the SLEEP instruction. Note: If the global interrupts are disabled (GIE is cleared), but any interrupt source has both its interrupt enable bit and the corresponding interrupt flag bits set, the device will immediately wake-up from Sleep. The SLEEP instruction is completely executed.
For lowest current consumption in this mode, all I/O pins should be either at VDD or VSS, with no external circuitry drawing current from the I/O pin, and the comparators and CVREF should be disabled. I/O pins that are high-impedance inputs should be pulled high or low externally to avoid switching currents caused by floating inputs. The T0CKI input should also be at VDD or VSS for lowest current consumption. The contribution from on-chip pull-ups on PORTA should be considered. The MCLR pin must be at a logic high level. Note: It should be noted that a Reset generated by a WDT time-out does not drive MCLR pin low.
The WDT is cleared when the device wakes up from Sleep, regardless of the source of wake-up.
11.6.2
WAKE-UP USING INTERRUPTS
11.6.1
WAKE-UP FROM SLEEP
When global interrupts are disabled (GIE cleared) and any interrupt source has both its interrupt enable bit and interrupt flag bit set, one of the following will occur: * If the interrupt occurs before the execution of a SLEEP instruction, the SLEEP instruction will complete as a NOP. Therefore, the WDT and WDT prescaler and postscaler (if enabled) will not be cleared, the TO bit will not be set and the PD bit will not be cleared. * If the interrupt occurs during or after the execution of a SLEEP instruction, the device will immediately wake-up from Sleep. The SLEEP instruction will be completely executed before the wake-up. Therefore, the WDT and WDT prescaler and postscaler (if enabled) will be cleared, the TO bit will be set and the PD bit will be cleared. Even if the flag bits were checked before executing a SLEEP instruction, it may be possible for flag bits to become set before the SLEEP instruction completes. To determine whether a SLEEP instruction executed, test the PD bit. If the PD bit is set, the SLEEP instruction was executed as a NOP. To ensure that the WDT is cleared, a CLRWDT instruction should be executed before a SLEEP instruction.
The device can wake-up from Sleep through one of the following events: 1. 2. 3. External Reset input on MCLR pin. Watchdog Timer wake-up (if WDT was enabled). Interrupt from RA2/INT pin, PORTA change or a peripheral interrupt.
The first event will cause a device Reset. The two latter events are considered a continuation of program execution. The TO and PD bits in the Status register can be used to determine the cause of device Reset. The PD bit, which is set on power-up, is cleared when Sleep is invoked. TO bit is cleared if WDT wake-up occurred. The following peripheral interrupts can wake the device from Sleep: 1. 2. 3. 4. 5. 6. 7. 8. Timer1 interrupt. Timer1 must be operating as an asynchronous counter. A/D conversion (when A/D clock source is FRC). EEPROM write operation completion. Comparator output changes state. Interrupt-on-change. External Interrupt from INT pin. EUSART Receive Interrupt. ULPWU Interrupt.
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FIGURE 11-10: WAKE-UP FROM SLEEP THROUGH INTERRUPT
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 TOST(2) Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 OSC1 CLKOUT(4) INT pin INTF flag (INTCON<1>) GIE bit (INTCON<7>) Instruction Flow PC Instruction Fetched Instruction Executed Note 1: 2: 3: 4: Processor in Sleep Interrupt Latency (3)
PC Inst(PC) = Sleep Inst(PC - 1)
PC + 1 Inst(PC + 1) Sleep
PC + 2
PC + 2 Inst(PC + 2) Inst(PC + 1)
PC + 2
0004h Inst(0004h)
0005h Inst(0005h) Inst(0004h)
Dummy Cycle
Dummy Cycle
XT, HS or LP Oscillator mode assumed. TOST = 1024 TOSC (drawing not to scale). This delay does not apply to EC and RC Oscillator modes. GIE = 1 assumed. In this case after wake-up, the processor jumps to 0004h. If GIE = 0, execution will continue in-line. CLKOUT is not available in XT, HS, LP or EC Oscillator modes, but shown here for timing reference.
11.7
Code Protection
If the code protection bit(s) have not been programmed, the on-chip program memory can be read out using ICSP for verification purposes. Note: The entire data EEPROM and Flash program memory will be erased when the code protection is turned off. See the "PIC12F6XX/16F6XX Memory Programming Specification" (DS41204) for more information.
11.8
ID Locations
Four memory locations (2000h-2003h) are designated as ID locations where the user can store checksum or other code identification numbers. These locations are not accessible during normal execution but are readable and writable during Program/Verify mode. Only the Least Significant 7 bits of the ID locations are used.
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11.9 In-Circuit Serial Programming 11.10 In-Circuit Debugger
Since in-circuit debugging requires access to the data and MCLR pins, MPLAB(R) ICD 2 development with an 14-pin device is not practical. A special 20-pin PIC16F688 ICD device is used with MPLAB ICD 2 to provide separate clock, data and MCLR pins and frees all normally available pins to the user. A special debugging adapter allows the ICD device to be used in place of a PIC16F688 device. The debugging adapter is the only source of the ICD device. When the ICD pin on the PIC16F688 ICD device is held low, the In-Circuit Debugger functionality is enabled. This function allows simple debugging functions when used with MPLAB ICD 2. When the microcontroller has this feature enabled, some of the resources are not available for general use. Table 11-9 shows which features are consumed by the background debugger: This allows customers to manufacture boards with unprogrammed devices and then program the microcontroller just before shipping the product. This also allows the most recent firmware or a custom firmware to be programmed. The device is placed into a Program/Verify mode by holding the RA0 and RA1 pins low, while raising the MCLR (VPP) pin from VIL to VIHH. See the "PIC12F6XX/16F6XX Memory Programming Specification" (DS41204) for more information. RA0 becomes the programming data and RA1 becomes the programming clock. Both RA0 and RA1 are Schmitt Trigger inputs in Program/Verify mode. A typical In-Circuit Serial Programming connection is shown in Figure 11-11.
FIGURE 11-11:
TYPICAL IN-CIRCUIT SERIAL PROGRAMMING CONNECTION
To Normal Connections
TABLE 11-9:
Resource I/O pins Stack
DEBUGGER RESOURCES
Description ICDCLK, ICDDATA 1 level Address 0h must be NOP 700h-7FFh
External Connector Signals +5V 0V VPP CLK Data I/O
*
Program Memory
PIC16F688 VDD VSS MCLR/VPP/RA3 RA1 RA0
For more information, see "MPLAB(R) ICD 2 In-Circuit Debugger User's Guide" (DS51331), available on Microchip's web site (www.microchip.com).
FIGURE 11-12:
20-Pin PDIP
20-PIN ICD PINOUT
In-Circuit Debug Device
NC
1 2 3 4 5 6 7 8 9 10 20
PIC16F688 -ICD
*
*
*
To Normal Connections * Isolation devices (as required)
ICDMCLR/VPP VDD RA5 RA4 RA3 RC5 RC4 RC3 ICD
19 18 17 16 15 14 13 12 11
ICDCLK ICDDATA Vss RA0 RA1 RA2 RC0 RC1 RC2 NC
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NOTES:
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12.0 INSTRUCTION SET SUMMARY
TABLE 12-1:
Field
f W b k x
The PIC16F688 instruction set is highly orthogonal and is comprised of three basic categories: * Byte-oriented operations * Bit-oriented operations * Literal and control operations Each PIC16 instruction is a 14-bit word divided into an opcode, which specifies the instruction type and one or more operands, which further specify the operation of the instruction. The formats for each of the categories is presented in Figure 12-1, while the various opcode fields are summarized in Table 12-1. Table 12-2 lists the instructions recognized by the MPASMTM assembler. For byte-oriented instructions, `f' represents a file register designator and `d' represents a destination designator. The file register designator specifies which file register is to be used by the instruction. The destination designator specifies where the result of the operation is to be placed. If `d' is zero, the result is placed in the W register. If `d' is one, the result is placed in the file register specified in the instruction. For bit-oriented instructions, `b' represents a bit field designator, which selects the bit affected by the operation, while `f' represents the address of the file in which the bit is located. For literal and control operations, `k' represents an 8-bit or 11-bit constant, or literal value. One instruction cycle consists of four oscillator periods; for an oscillator frequency of 4 MHz, this gives a nominal instruction execution time of 1 s. All instructions are executed within a single instruction cycle, unless a conditional test is true, or the program counter is changed as a result of an instruction. When this occurs, the execution takes two instruction cycles, with the second cycle executed as a NOP. All instruction examples use the format `0xhh' to represent a hexadecimal number, where `h' signifies a hexadecimal digit.
OPCODE FIELD DESCRIPTIONS
Description
Register file address (0x00 to 0x7F) Working register (accumulator) Bit address within an 8-bit file register Literal field, constant data or label Don't care location (= 0 or 1). The assembler will generate code with x = 0. It is the recommended form of use for compatibility with all Microchip software tools. Destination select; d = 0: store result in W, d = 1: store result in file register f. Default is d = 1. Program Counter Time-out bit Carry bit Digit carry bit Zero bit Power-down bit
d
PC TO C DC Z PD
FIGURE 12-1:
GENERAL FORMAT FOR INSTRUCTIONS
0
Byte-oriented file register operations 13 876 OPCODE d f (FILE #) d = 0 for destination W d = 1 for destination f f = 7-bit file register address Bit-oriented file register operations 13 10 9 76 OPCODE b (BIT #) f (FILE #) b = 3-bit bit address f = 7-bit file register address Literal and control operations General 13 OPCODE 8 7 k (literal)
0
12.1
Read-Modify-Write Operations
0
Any instruction that specifies a file register as part of the instruction performs a Read-Modify-Write (R-M-W) operation. The register is read, the data is modified, and the result is stored according to either the instruction, or the destination designator `d'. A read operation is performed on a register even if the instruction writes to that register. For example, a CLRF PORTA instruction will read PORTA, clear all the data bits, then write the result back to PORTA. This example would have the unintended consequence of clearing the condition that set the RAIF flag.
k = 8-bit immediate value CALL and GOTO instructions only 13 11 OPCODE 10 k (literal) 0
k = 11-bit immediate value
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TABLE 12-2:
Mnemonic, Operands
PIC16F684 INSTRUCTION SET
14-Bit Opcode Description Cycles MSb BYTE-ORIENTED FILE REGISTER OPERATIONS LSb Status Affected Notes
ADDWF ANDWF CLRF CLRW COMF DECF DECFSZ INCF INCFSZ IORWF MOVF MOVWF NOP RLF RRF SUBWF SWAPF XORWF
f, d f, d f - f, d f, d f, d f, d f, d f, d f, d f - f, d f, d f, d f, d f, d
Add W and f AND W with f Clear f Clear W Complement f Decrement f Decrement f, Skip if 0 Increment f Increment f, Skip if 0 Inclusive OR W with f Move f Move W to f No Operation Rotate Left f through Carry Rotate Right f through Carry Subtract W from f Swap nibbles in f Exclusive OR W with f
1 1 1 1 1 1 1(2) 1 1(2) 1 1 1 1 1 1 1 1 1
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0111 0101 0001 0001 1001 0011 1011 1010 1111 0100 1000 0000 0000 1101 1100 0010 1110 0110
dfff dfff lfff 0xxx dfff dfff dfff dfff dfff dfff dfff lfff 0xx0 dfff dfff dfff dfff dfff
ffff ffff ffff xxxx ffff ffff ffff ffff ffff ffff ffff ffff 0000 ffff ffff ffff ffff ffff
C, DC, Z Z Z Z Z Z Z Z Z
1, 2 1, 2 2 1, 2 1, 2 1, 2, 3 1, 2 1, 2, 3 1, 2 1, 2
C C C, DC, Z Z
1, 2 1, 2 1, 2 1, 2 1, 2
BIT-ORIENTED FILE REGISTER OPERATIONS BCF BSF BTFSC BTFSS ADDLW ANDLW CALL CLRWDT GOTO IORLW MOVLW RETFIE RETLW RETURN SLEEP SUBLW XORLW Note 1: f, b f, b f, b f, b k k k - k k k - k - - k k Bit Clear f Bit Set f Bit Test f, Skip if Clear Bit Test f, Skip if Set Add literal and W AND literal with W Call Subroutine Clear Watchdog Timer Go to address Inclusive OR literal with W Move literal to W Return from interrupt Return with literal in W Return from Subroutine Go into Standby mode Subtract W from literal Exclusive OR literal with W 1 1 1 (2) 1 (2) 1 1 2 1 2 1 1 2 2 2 1 1 1 01 01 01 01 00bb 01bb 10bb 11bb bfff bfff bfff bfff ffff ffff ffff ffff C, DC, Z Z TO, PD Z 1, 2 1, 2 3 3
LITERAL AND CONTROL OPERATIONS 11 11 10 00 10 11 11 00 11 00 00 11 11 111x 1001 0kkk 0000 1kkk 1000 00xx 0000 01xx 0000 0000 110x 1010 kkkk kkkk kkkk 0110 kkkk kkkk kkkk 0000 kkkk 0000 0110 kkkk kkkk kkkk kkkk kkkk 0100 kkkk kkkk kkkk 1001 kkkk 1000 0011 kkkk kkkk
TO, PD C, DC, Z Z
2: 3:
When an I/O register is modified as a function of itself (e.g., MOVF GPIO, 1), the value used will be that value present on the pins themselves. For example, if the data latch is `1' for a pin configured as input and is driven low by an external device, the data will be written back with a `0'. If this instruction is executed on the TMR0 register (and where applicable, d = 1), the prescaler will be cleared if assigned to the Timer0 module. If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP.
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12.2
ADDLW Syntax: Operands: Operation: Status Affected: Description:
Instruction Descriptions
Add literal and W [ label ] ADDLW 0 k 255 (W) + k (W) C, DC, Z The contents of the W register are added to the eight-bit literal `k' and the result is placed in the W register. Operation: Status Affected: Description: k BCF Syntax: Operands: Bit Clear f [ label ] BCF 0 f 127 0b7 0 (f) None Bit `b' in register `f' is cleared. f,b
ADDWF Syntax: Operands: Operation: Status Affected: Description:
Add W and f [ label ] ADDWF 0 f 127 d [0,1] (W) + (f) (destination) C, DC, Z Add the contents of the W register with register `f'. If `d' is `0', the result is stored in the W register. If `d' is `1', the result is stored back in register `f'. f,d
BSF Syntax: Operands: Operation: Status Affected: Description:
Bit Set f [ label ] BSF 0 f 127 0b7 1 (f) None Bit `b' in register `f' is set. f,b
ANDLW Syntax: Operands: Operation: Status Affected: Description:
AND literal with W [ label ] ANDLW 0 k 255 (W) .AND. (k) (W) Z The contents of W register are AND'ed with the eight-bit literal `k'. The result is placed in the W register. k
BTFSC Syntax: Operands: Operation: Status Affected: Description:
Bit Test f, Skip if Clear [ label ] BTFSC f,b 0 f 127 0b7 skip if (f) = 0 None If bit `b' in register `f' is `1', the next instruction is executed. If bit `b', in register `f', is `0', the next instruction is discarded, and a NOP is executed instead, making this a two-cycle instruction.
ANDWF Syntax: Operands: Operation: Status Affected: Description:
AND W with f [ label ] ANDWF 0 f 127 d [0,1] (W) .AND. (f) (destination) Z AND the W register with register `f'. If `d' is `0', the result is stored in the W register. If `d' is `1', the result is stored back in register `f'. f,d
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BTFSS Syntax: Operands: Operation: Status Affected: Description: Bit Test f, Skip if Set [ label ] BTFSS f,b 0 f 127 0b<7 skip if (f) = 1 None If bit `b' in register `f' is `0', the next instruction is executed. If bit `b' is `1', then the next instruction is discarded and a NOP is executed instead, making this a two-cycle instruction. Status Affected: Description: CLRWDT Syntax: Operands: Operation: Clear Watchdog Timer [ label ] CLRWDT None 00h WDT 0 WDT prescaler, 1 TO 1 PD TO, PD CLRWDT instruction resets the Watchdog Timer. It also resets the prescaler of the WDT. Status bits TO and PD are set.
CALL Syntax: Operands: Operation:
Call Subroutine [ label ] CALL k 0 k 2047 (PC)+ 1 TOS, k PC<10:0>, (PCLATH<4:3>) PC<12:11> None Call Subroutine. First, return address (PC + 1) is pushed onto the stack. The eleven-bit immediate address is loaded into PC bits <10:0>. The upper bits of the PC are loaded from PCLATH. CALL is a two-cycle instruction.
COMF Syntax: Operands: Operation: Status Affected: Description:
Complement f [ label ] COMF 0 f 127 d [0,1] (f) (destination) Z The contents of register `f' are complemented. If `d' is `0', the result is stored in W. If `d' is `1', the result is stored back in register `f'. f,d
Status Affected: Description:
CLRF Syntax: Operands: Operation: Status Affected: Description:
Clear f [ label ] CLRF 0 f 127 00h (f) 1Z Z The contents of register `f' are cleared and the Z bit is set. f
DECF Syntax: Operands: Operation: Status Affected: Description:
Decrement f [ label ] DECF f,d 0 f 127 d [0,1] (f) - 1 (destination) Z Decrement register `f'. If `d' is `0', the result is stored in the W register. If `d' is `1', the result is stored back in register `f'.
CLRW Syntax: Operands: Operation: Status Affected: Description:
Clear W [ label ] CLRW None 00h (W) 1Z Z W register is cleared. Zero bit (Z) is set.
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DECFSZ Syntax: Operands: Operation: Status Affected: Description: Decrement f, Skip if 0 [ label ] DECFSZ f,d 0 f 127 d [0,1] (f) - 1 (destination); skip if result = 0 None The contents of register `f' are decremented. If `d' is `0', the result is placed in the W register. If `d' is `1', the result is placed back in register `f'. If the result is `1', the next instruction is executed. If the result is `0', then a NOP is executed instead, making it a two-cycle instruction. INCFSZ Syntax: Operands: Operation: Status Affected: Description: Increment f, Skip if 0 [ label ] INCFSZ f,d 0 f 127 d [0,1] (f) + 1 (destination), skip if result = 0 None The contents of register `f' are incremented. If `d' is `0', the result is placed in the W register. If `d' is `1', the result is placed back in register `f'. If the result is `1', the next instruction is executed. If the result is `0', a NOP is executed instead, making it a two-cycle instruction.
GOTO Syntax: Operands: Operation: Status Affected: Description:
Unconditional Branch [ label ] GOTO k 0 k 2047 k PC<10:0> PCLATH<4:3> PC<12:11> None GOTO is an unconditional branch. The eleven-bit immediate value is loaded into PC bits <10:0>. The upper bits of PC are loaded from PCLATH<4:3>. GOTO is a two-cycle instruction.
IORLW Syntax: Operands: Operation: Status Affected: Description:
Inclusive OR literal with W [ label ] IORLW k 0 k 255 (W) .OR. k (W) Z The contents of the W register are OR'ed with the eight-bit literal `k'. The result is placed in the W register.
INCF Syntax: Operands: Operation: Status Affected: Description:
Increment f [ label ] INCF f,d 0 f 127 d [0,1] (f) + 1 (destination) Z The contents of register `f' are incremented. If `d' is `0', the result is placed in the W register. If `d' is `1', the result is placed back in register `f'.
IORWF Syntax: Operands: Operation: Status Affected: Description:
Inclusive OR W with f [ label ] IORWF f,d 0 f 127 d [0,1] (W) .OR. (f) (destination) Z Inclusive OR the W register with register `f'. If `d' is `0', the result is placed in the W register. If `d' is `1', the result is placed back in register `f'.
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MOVF Syntax: Operands: Operation: Status Affected: Description: Move f [ label ] MOVF f,d 0 f 127 d [0,1] (f) (dest) Z The contents of register f is moved to a destination dependent upon the status of d. If d = 0, destination is W register. If d = 1, the destination is file register f itself. d = 1 is useful to test a file register since status flag Z is affected. 1 1
MOVF FSR, 0
MOVWF Syntax: Operands: Operation: Status Affected: Description: Words: Cycles: Example:
Move W to f [ label ] (W) (f) None Move data from W register to register `f'. 1 1 MOVW F OPTION MOVWF f 0 f 127
Words: Cycles: Example:
Before Instruction OPTION = W = After Instruction OPTION = W =
0xFF 0x4F 0x4F 0x4F
After Instruction W= value in FSR register Z=1
MOVLW Syntax: Operands: Operation: Status Affected: Description:
Move literal to W [ label ] k (W) None The eight-bit literal `k' is loaded into W register. The "don't cares" will assemble as `0's. 1 1
MOVLW 0x5A
NOP Syntax: Operands: Operation: Status Affected: Description: Words: Cycles: Example:
No Operation [ label ] None No operation None No operation. 1 1
NOP
MOVLW k
NOP
0 k 255
Words: Cycles: Example:
After Instruction W=
0x5A
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RETFIE Syntax: Operands: Operation: Status Affected: Description: Return from Interrupt [ label ] None TOS PC, 1 GIE None Return from Interrupt. Stack is POPed and Top-of-Stack (TOS) is loaded in the PC. Interrupts are enabled by setting Global Interrupt Enable bit, GIE (INTCON<7>). This is a two-cycle instruction. 1 2
RETFIE
RETLW Syntax: Operands: Operation: Status Affected: Description:
Return with literal in W [ label ] RETLW k 0 k 255 k (W); TOS PC None The W register is loaded with the eight bit literal `k'. The program counter is loaded from the top of the stack (the return address). This is a two-cycle instruction. 1 2 CALL TABLE;W contains table
;offset value * ;W now has table value * * ADDWF PC ;W = offset RETLW k1 ;Begin table RETLW k2 ; * * * RETLW kn ; End of table
RETFIE
Words: Cycles: Example:
Words: Cycles: Example:
After Interrupt PC = GIE =
TABLE TOS 1
Before Instruction W = 0x07 After Instruction W = value of k8
RETURN Syntax: Operands: Operation: Status Affected: Description:
Return from Subroutine [ label ] None TOS PC None Return from subroutine. The stack is POPed and the top of the stack (TOS) is loaded into the program counter. This is a two-cycle instruction. RETURN
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RLF Syntax: Operands: Operation: Status Affected: Description: Rotate Left f through Carry [ label ] 0 f 127 d [0,1] See description below C The contents of register `f' are rotated one bit to the left through the Carry flag. If `d' is `0', the result is placed in the W register. If `d' is `1', the result is stored back in register `f'.
C Register f
SLEEP Syntax: Operands: Operation:
Enter Sleep mode [ label ] SLEEP None 00h WDT, 0 WDT prescaler, 1 TO, 0 PD TO, PD The power-down Status bit, PD is cleared. Time-out Status bit, TO is set. Watchdog Timer and its prescaler are cleared. The processor is put into Sleep mode with the oscillator stopped.
RLF
f,d
Status Affected: Description:
Words: Cycles: Example:
1 1
RLF REG1,0 REG1 C = = = = = 1110 0110 0 1110 0110 1100 1100 1
Before Instruction
After Instruction
REG1 W C
RRF Syntax: Operands: Operation: Status Affected: Description:
Rotate Right f through Carry [ label ] RRF f,d 0 f 127 d [0,1] See description below C The contents of register `f' are rotated one bit to the right through the Carry flag. If `d' is `0', the result is placed in the W register. If `d' is `1', the result is placed back in register `f'.
C Register f
SUBLW Syntax: Operands: Operation: Description:
Subtract W from literal [ label ] SUBLW k 0 k 255 k - (W) (W) The W register is subtracted (2's complement method) from the eight-bit literal `k'. The result is placed in the W register. C=0 C=1 DC = 0 DC = 1 W>k Wk W<3:0> > k<3:0> W<3:0> k<3:0>
Status Affected: C, DC, Z
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SUBWF Syntax: Operands: Operation: Description: Subtract W from f [ label ] SUBWF f,d 0 f 127 d [0,1] (f) - (W) (destination) Subtract (2's complement method) W register from register `f'. If `d' is `0', the result is stored in the W register. If `d' is `1', the result is stored back in register `f. C=0 C=1 DC = 0 DC = 1 W>f Wf W<3:0> > f<3:0> W<3:0> f<3:0> XORLW Syntax: Operands: Operation: Status Affected: Description: Exclusive OR literal with W [ label ] XORLW k 0 k 255 (W) .XOR. k (W) Z The contents of the W register are XOR'ed with the eight-bit literal `k'. The result is placed in the W register.
Status Affected: C, DC, Z
SWAPF Syntax: Operands: Operation: Status Affected: Description:
Swap Nibbles in f [ label ] SWAPF f,d 0 f 127 d [0,1] (f<3:0>) (destination<7:4>), (f<7:4>) (destination<3:0>) None The upper and lower nibbles of register `f' are exchanged. If `d' is `0', the result is placed in the W register. If `d' is `1', the result is placed in register `f'.
XORWF Syntax: Operands: Operation: Status Affected: Description:
Exclusive OR W with f [ label ] XORWF 0 f 127 d [0,1] (W) .XOR. (f) (destination) Z Exclusive OR the contents of the W register with register `f'. If `d' is `0', the result is stored in the W register. If `d' is `1', the result is stored back in register `f'. f,d
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NOTES:
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13.0 DEVELOPMENT SUPPORT
13.1
The PIC(R) microcontrollers are supported with a full range of hardware and software development tools: * Integrated Development Environment - MPLAB(R) IDE Software * Assemblers/Compilers/Linkers - MPASMTM Assembler - MPLAB C18 and MPLAB C30 C Compilers - MPLINKTM Object Linker/ MPLIBTM Object Librarian - MPLAB ASM30 Assembler/Linker/Library * Simulators - MPLAB SIM Software Simulator * Emulators - MPLAB ICE 2000 In-Circuit Emulator - MPLAB REAL ICETM In-Circuit Emulator * In-Circuit Debugger - MPLAB ICD 2 * Device Programmers - PICSTART(R) Plus Development Programmer - MPLAB PM3 Device Programmer - PICkitTM 2 Development Programmer * Low-Cost Demonstration and Development Boards and Evaluation Kits
MPLAB Integrated Development Environment Software
The MPLAB IDE software brings an ease of software development previously unseen in the 8/16-bit microcontroller market. The MPLAB IDE is a Windows(R) operating system-based application that contains: * A single graphical interface to all debugging tools - Simulator - Programmer (sold separately) - Emulator (sold separately) - In-Circuit Debugger (sold separately) * A full-featured editor with color-coded context * A multiple project manager * Customizable data windows with direct edit of contents * High-level source code debugging * Visual device initializer for easy register initialization * Mouse over variable inspection * Drag and drop variables from source to watch windows * Extensive on-line help * Integration of select third party tools, such as HI-TECH Software C Compilers and IAR C Compilers The MPLAB IDE allows you to: * Edit your source files (either assembly or C) * One touch assemble (or compile) and download to PIC MCU emulator and simulator tools (automatically updates all project information) * Debug using: - Source files (assembly or C) - Mixed assembly and C - Machine code MPLAB IDE supports multiple debugging tools in a single development paradigm, from the cost-effective simulators, through low-cost in-circuit debuggers, to full-featured emulators. This eliminates the learning curve when upgrading to tools with increased flexibility and power.
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13.2 MPASM Assembler 13.5
The MPASM Assembler is a full-featured, universal macro assembler for all PIC MCUs. The MPASM Assembler generates relocatable object files for the MPLINK Object Linker, Intel(R) standard HEX files, MAP files to detail memory usage and symbol reference, absolute LST files that contain source lines and generated machine code and COFF files for debugging. The MPASM Assembler features include: * Integration into MPLAB IDE projects * User-defined macros to streamline assembly code * Conditional assembly for multi-purpose source files * Directives that allow complete control over the assembly process
MPLAB ASM30 Assembler, Linker and Librarian
MPLAB ASM30 Assembler produces relocatable machine code from symbolic assembly language for dsPIC30F devices. MPLAB C30 C Compiler uses the assembler to produce its object file. The assembler generates relocatable object files that can then be archived or linked with other relocatable object files and archives to create an executable file. Notable features of the assembler include: * * * * * * Support for the entire dsPIC30F instruction set Support for fixed-point and floating-point data Command line interface Rich directive set Flexible macro language MPLAB IDE compatibility
13.6 13.3 MPLAB C18 and MPLAB C30 C Compilers
MPLAB SIM Software Simulator
The MPLAB C18 and MPLAB C30 Code Development Systems are complete ANSI C compilers for Microchip's PIC18 and PIC24 families of microcontrollers and the dsPIC30 and dsPIC33 family of digital signal controllers. These compilers provide powerful integration capabilities, superior code optimization and ease of use not found with other compilers. For easy source level debugging, the compilers provide symbol information that is optimized to the MPLAB IDE debugger.
The MPLAB SIM Software Simulator allows code development in a PC-hosted environment by simulating the PIC MCUs and dsPIC(R) DSCs on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. Registers can be logged to files for further run-time analysis. The trace buffer and logic analyzer display extend the power of the simulator to record and track program execution, actions on I/O, most peripherals and internal registers. The MPLAB SIM Software Simulator fully supports symbolic debugging using the MPLAB C18 and MPLAB C30 C Compilers, and the MPASM and MPLAB ASM30 Assemblers. The software simulator offers the flexibility to develop and debug code outside of the hardware laboratory environment, making it an excellent, economical software development tool.
13.4
MPLINK Object Linker/ MPLIB Object Librarian
The MPLINK Object Linker combines relocatable objects created by the MPASM Assembler and the MPLAB C18 C Compiler. It can link relocatable objects from precompiled libraries, using directives from a linker script. The MPLIB Object Librarian manages the creation and modification of library files of precompiled code. When a routine from a library is called from a source file, only the modules that contain that routine will be linked in with the application. This allows large libraries to be used efficiently in many different applications. The object linker/library features include: * Efficient linking of single libraries instead of many smaller files * Enhanced code maintainability by grouping related modules together * Flexible creation of libraries with easy module listing, replacement, deletion and extraction
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13.7 MPLAB ICE 2000 High-Performance In-Circuit Emulator 13.9 MPLAB ICD 2 In-Circuit Debugger
Microchip's In-Circuit Debugger, MPLAB ICD 2, is a powerful, low-cost, run-time development tool, connecting to the host PC via an RS-232 or high-speed USB interface. This tool is based on the Flash PIC MCUs and can be used to develop for these and other PIC MCUs and dsPIC DSCs. The MPLAB ICD 2 utilizes the in-circuit debugging capability built into the Flash devices. This feature, along with Microchip's In-Circuit Serial ProgrammingTM (ICSPTM) protocol, offers costeffective, in-circuit Flash debugging from the graphical user interface of the MPLAB Integrated Development Environment. This enables a designer to develop and debug source code by setting breakpoints, single stepping and watching variables, and CPU status and peripheral registers. Running at full speed enables testing hardware and applications in real time. MPLAB ICD 2 also serves as a development programmer for selected PIC devices.
The MPLAB ICE 2000 In-Circuit Emulator is intended to provide the product development engineer with a complete microcontroller design tool set for PIC microcontrollers. Software control of the MPLAB ICE 2000 In-Circuit Emulator is advanced by the MPLAB Integrated Development Environment, which allows editing, building, downloading and source debugging from a single environment. The MPLAB ICE 2000 is a full-featured emulator system with enhanced trace, trigger and data monitoring features. Interchangeable processor modules allow the system to be easily reconfigured for emulation of different processors. The architecture of the MPLAB ICE 2000 In-Circuit Emulator allows expansion to support new PIC microcontrollers. The MPLAB ICE 2000 In-Circuit Emulator system has been designed as a real-time emulation system with advanced features that are typically found on more expensive development tools. The PC platform and Microsoft(R) Windows(R) 32-bit operating system were chosen to best make these features available in a simple, unified application.
13.10 MPLAB PM3 Device Programmer
The MPLAB PM3 Device Programmer is a universal, CE compliant device programmer with programmable voltage verification at VDDMIN and VDDMAX for maximum reliability. It features a large LCD display (128 x 64) for menus and error messages and a modular, detachable socket assembly to support various package types. The ICSPTM cable assembly is included as a standard item. In Stand-Alone mode, the MPLAB PM3 Device Programmer can read, verify and program PIC devices without a PC connection. It can also set code protection in this mode. The MPLAB PM3 connects to the host PC via an RS-232 or USB cable. The MPLAB PM3 has high-speed communications and optimized algorithms for quick programming of large memory devices and incorporates an SD/MMC card for file storage and secure data applications.
13.8
MPLAB REAL ICE In-Circuit Emulator System
MPLAB REAL ICE In-Circuit Emulator System is Microchip's next generation high-speed emulator for Microchip Flash DSC and MCU devices. It debugs and programs PIC(R) Flash MCUs and dsPIC(R) Flash DSCs with the easy-to-use, powerful graphical user interface of the MPLAB Integrated Development Environment (IDE), included with each kit. The MPLAB REAL ICE probe is connected to the design engineer's PC using a high-speed USB 2.0 interface and is connected to the target with either a connector compatible with the popular MPLAB ICD 2 system (RJ11) or with the new high-speed, noise tolerant, LowVoltage Differential Signal (LVDS) interconnection (CAT5). MPLAB REAL ICE is field upgradeable through future firmware downloads in MPLAB IDE. In upcoming releases of MPLAB IDE, new devices will be supported, and new features will be added, such as software breakpoints and assembly code trace. MPLAB REAL ICE offers significant advantages over competitive emulators including low-cost, full-speed emulation, real-time variable watches, trace analysis, complex breakpoints, a ruggedized probe interface and long (up to three meters) interconnection cables.
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13.11 PICSTART Plus Development Programmer
The PICSTART Plus Development Programmer is an easy-to-use, low-cost, prototype programmer. It connects to the PC via a COM (RS-232) port. MPLAB Integrated Development Environment software makes using the programmer simple and efficient. The PICSTART Plus Development Programmer supports most PIC devices in DIP packages up to 40 pins. Larger pin count devices, such as the PIC16C92X and PIC17C76X, may be supported with an adapter socket. The PICSTART Plus Development Programmer is CE compliant.
13.13 Demonstration, Development and Evaluation Boards
A wide variety of demonstration, development and evaluation boards for various PIC MCUs and dsPIC DSCs allows quick application development on fully functional systems. Most boards include prototyping areas for adding custom circuitry and provide application firmware and source code for examination and modification. The boards support a variety of features, including LEDs, temperature sensors, switches, speakers, RS-232 interfaces, LCD displays, potentiometers and additional EEPROM memory. The demonstration and development boards can be used in teaching environments, for prototyping custom circuits and for learning about various microcontroller applications. In addition to the PICDEMTM and dsPICDEMTM demonstration/development board series of circuits, Microchip has a line of evaluation kits and demonstration software for analog filter design, KEELOQ(R) security ICs, CAN, IrDA(R), PowerSmart battery management, SEEVAL(R) evaluation system, Sigma-Delta ADC, flow rate sensing, plus many more. Check the Microchip web page (www.microchip.com) for the complete list of demonstration, development and evaluation kits.
13.12 PICkit 2 Development Programmer
The PICkitTM 2 Development Programmer is a low-cost programmer and selected Flash device debugger with an easy-to-use interface for programming many of Microchip's baseline, mid-range and PIC18F families of Flash memory microcontrollers. The PICkit 2 Starter Kit includes a prototyping development board, twelve sequential lessons, software and HI-TECH's PICCTM Lite C compiler, and is designed to help get up to speed quickly using PIC(R) microcontrollers. The kit provides everything needed to program, evaluate and develop applications using Microchip's powerful, mid-range Flash memory family of microcontrollers.
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14.0 ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings()
Ambient temperature under bias..........................................................................................................-40 to +125C Storage temperature ........................................................................................................................ -65C to +150C Voltage on VDD with respect to VSS ................................................................................................... -0.3V to +6.5V Voltage on MCLR with respect to Vss ............................................................................................... -0.3V to +13.5V Voltage on all other pins with respect to VSS ........................................................................... -0.3V to (VDD + 0.3V) Total power dissipation(1) ............................................................................................................................... 800 mW Maximum current out of VSS pin ...................................................................................................................... 95 mA Maximum current into VDD pin ......................................................................................................................... 95 mA Input clamp current, IIK (VI < 0 or VI > VDD)............................................................................................................... 20 mA Output clamp current, IOK (Vo < 0 or Vo >VDD)......................................................................................................... 20 mA Maximum output current sunk by any I/O pin.................................................................................................... 25 mA Maximum output current sourced by any I/O pin .............................................................................................. 25 mA Maximum current sunk by PORTA and PORTC (combined) ........................................................................... 90 mA Maximum current sourced PORTA and PORTC (combined) ........................................................................... 90 mA Note 1: Power dissipation is calculated as follows: PDIS = VDD x {IDD - IOH} + {(VDD - VOH) x IOH} + (VOl x IOL).
NOTICE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure above maximum rating conditions for extended periods may affect device reliability.
(c) 2009 Microchip Technology Inc.
DS41203E-page 143
PIC16F688
FIGURE 14-1: PIC16F688 VOLTAGE-FREQUENCY GRAPH, -40C TA +125C
5.5 5.0 4.5 VDD (V) 4.0 3.5 3.0 2.5 2.0 0 8 10 Frequency (MHz) Note 1: The shaded region indicates the permissible combinations of voltage and frequency. 20
FIGURE 14-2:
HFINTOSC FREQUENCY ACCURACY OVER DEVICE VDD AND TEMPERATURE
125 5% 85 Temperature (C)
60
2%
25
1%
0
2.0
2.5
3.0
3.5
4.0 VDD (V)
4.5
5.0
5.5
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PIC16F688
14.1 DC Characteristics: PIC16F688 -I (Industrial) PIC16F688 -E (Extended)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Min Typ Max Units 2.0 2.0 3.0 4.5 1.5 -- -- -- -- -- -- VSS 5.5 5.5 5.5 5.5 -- -- V V V V V V Conditions FOSC < = 8 MHz: HFINTOSC, EC FOSC < = 4 MHz FOSC < = 10 MHz FOSC < = 20 MHz Device in Sleep mode See Section 11.2.1 "Power-On Reset" for details.
DC CHARACTERISTICS Param No. D001 D001C D001D D002* D003 VDR VPOR RAM Data Retention Voltage(1) VDD Start Voltage to ensure internal Power-on Reset signal VDD Rise Rate to ensure internal Power-on Reset signal
Sym VDD
Characteristic Supply Voltage
D004*
SVDD
0.05
--
--
V/ms See Section 11.2.1 "Power-On Reset" for details.
* These parameters are characterized but not tested. Data in "Typ" column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: This is the limit to which VDD can be lowered in Sleep mode without losing RAM data.
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PIC16F688
14.2 DC Characteristics: PIC16F688 -I (Industrial) PIC16F688 -E (Extended)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Conditions Device Characteristics Supply Current (IDD)(1, 2) Min -- -- -- D011* -- -- -- D012 -- -- -- D013* -- -- -- D014 -- -- -- D015 -- -- -- D016* -- -- -- D017 -- -- -- D018 -- -- -- D019 -- -- Typ 16 27 47 180 290 490 280 480 0.9 130 215 360 220 375 0.65 8 16 31 320 490 0.87 0.5 0.78 1.43 340 550 0.92 2.9 3.1 Max 23 38 75 250 400 650 380 670 1.4 220 360 520 340 550 1.0 20 40 65 400 640 1.2 0.7 1 1.8 580 950 1.6 3.7 3.8 Units VDD A A A A A A A A mA A A A A A mA A A A A A mA mA mA mA A A mA mA mA 2.0 3.0 5.0 2.0 3.0 5.0 2.0 3.0 5.0 2.0 3.0 5.0 2.0 3.0 5.0 2.0 3.0 5.0 2.0 3.0 5.0 2.0 3.0 5.0 2.0 3.0 5.0 4.5 5.0 FOSC = 20 MHz HS Oscillator mode FOSC = 4 MHz EXTRC mode(3) FOSC = 8 MHz HFINTOSC mode FOSC = 4 MHz HFINTOSC mode FOSC = 31 kHz LFINTOSC mode FOSC = 4 MHz EC Oscillator mode FOSC = 1 MHz EC Oscillator mode FOSC = 4 MHz XT Oscillator mode FOSC = 1 MHz XT Oscillator mode Note FOSC = 32 kHz LP Oscillator mode
DC CHARACTERISTICS
Param No. D010
* These parameters are characterized but not tested. Data in "Typ" column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. 3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be extended by the formula IR = VDD/2REXT (mA) with REXT in k.
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(c) 2009 Microchip Technology Inc.
PIC16F688
14.3 DC Characteristics: PIC16F688-I (Industrial)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Conditions Device Characteristics Power-down Base Current(IPD)(2) Min -- -- -- -- D021 -- -- -- D022 D023 -- -- -- -- -- D024 -- -- -- D025* -- -- -- D026 -- -- -- D027 -- -- Typ 0.05 0.15 0.35 150 1.0 2.0 3.0 42 85 32 60 120 30 45 75 39 59 98 4.5 5.0 6.0 0.30 0.36 Max 1.2 1.5 1.8 500 2.2 4.0 7.0 60 122 45 78 160 36 55 95 47 72 124 7.0 8.0 12 1.6 1.9 Units VDD A A A nA A A A A A A A A A A A A A A A A A A A 2.0 3.0 5.0 3.0 2.0 3.0 5.0 3.0 5.0 2.0 3.0 5.0 2.0 3.0 5.0 2.0 3.0 5.0 2.0 3.0 5.0 3.0 5.0 A/D Current(1), no conversion in progress T1OSC Current(1), 32.768 kHz CVREF Current(1) (low range) CVREF Current(1) (high range) Comparator Current(1), both comparators enabled BOR Current(1) -40C TA +25C WDT Current(1) Note WDT, BOR, Comparators, VREF and T1OSC disabled
DC CHARACTERISTICS Param No. D020
* These parameters are characterized but not tested. Data in "Typ" column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral is enabled. The peripheral current can be determined by subtracting the base IDD or IPD current from this limit. Max values should be used when calculating total current consumption. 2: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD.
(c) 2009 Microchip Technology Inc.
DS41203E-page 147
PIC16F688
14.4
DC Characteristics: PIC16F688-E (Extended)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +125C for extended Conditions Device Characteristics Power-down Base Current (IPD)(2) Min -- -- -- D021E -- -- -- D022E D023E -- -- -- -- -- D024E -- -- -- D025E* -- -- -- D026E -- -- -- D027E -- -- Typ 0.05 0.15 0.35 1 2 3 42 85 32 60 120 30 45 75 39 59 98 4.5 5 6 0.30 0.36 Max 9 11 15 28 30 35 65 127 45 78 160 70 90 120 91 117 156 25 30 40 12 16 Units VDD A A A A A A A A A A A A A A A A A A A A A A 2.0 3.0 5.0 2.0 3.0 5.0 3.0 5.0 2.0 3.0 5.0 2.0 3.0 5.0 2.0 3.0 5.0 2.0 3.0 5.0 3.0 5.0 A/D Current(1), no conversion in progress T1OSC Current(1), 32.768 kHz CVREF Current(1) (low range) CVREF Current(1) (high range) Comparator Current(1), both comparators enabled BOR Current(1) WDT Current(1) Note WDT, BOR, Comparators, VREF and T1OSC disabled
DC CHARACTERISTICS Param No. D020E
* These parameters are characterized but not tested. Data in "Typ" column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral is enabled. The peripheral current can be determined by subtracting the base IDD or IPD current from this limit. Max values should be used when calculating total current consumption. 2: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD.
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PIC16F688
14.5 DC Characteristics: PIC16F688 -I (Industrial) PIC16F688 -E (Extended)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Min Typ Max Units Conditions
DC CHARACTERISTICS Param No.
Sym
VIL
Characteristic
Input Low Voltage I/O Port: with TTL buffer with Schmitt Trigger buffer MCLR, OSC1 (RC mode) OSC1 (HS mode)
(1)
D030 D030A D031 D032 D033 D033A VIH D040 D040A D041 D042 D043 D043A D043B IIL D060 D061 D063 D070* D080 VOH D090 * Note 1: 2: 3: 4: 5: IPUR VOL
Vss Vss Vss VSS VSS VSS
-- -- -- -- -- -- --
0.8 0.15 VDD 0.2 VDD 0.2 VDD 0.3 0.3 VDD
V V V V V V
4.5V VDD 5.5V 2.0V VDD 4.5V 2.0V VDD 5.5V
OSC1 (XT and LP modes) Input High Voltage I/O ports: with TTL buffer with Schmitt Trigger buffer MCLR OSC1 (XT and LP modes) OSC1 (HS mode) OSC1 (RC mode) Input Leakage Current I/O ports MCLR(3) OSC1 PORTA Weak Pull-up Current Output Low Voltage(5) I/O ports Output High Voltage(5) I/O ports
(2)
2.0 0.25 VDD + 0.8 0.8 VDD 0.8 VDD 1.6 0.7 VDD 0.9 VDD -- -- -- 50 -- VDD - 0.7
-- -- -- -- -- -- -- 0.1 0.1 0.1 250 -- --
VDD VDD VDD VDD VDD VDD VDD 1 5 5 400 0.6 --
V V V V V V V A A A A V V
4.5V VDD 5.5V 2.0V VDD 4.5V 2.0V VDD 5.5V
(Note 1) VSS VPIN VDD, Pin at high-impedance VSS VPIN VDD VSS VPIN VDD, XT, HS and LP oscillator configuration VDD = 5.0V, VPIN = VSS IOL = 8.5 mA, VDD = 4.5V (Ind.) IOH = -3.0 mA, VDD = 4.5V (Ind.)
These parameters are characterized but not tested. Data in "Typ" column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended to use an external clock in RC mode. Negative current is defined as current sourced by the pin. The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. See Section 9.0 "Data EEPROM and Flash Program Memory Control" for additional information. Including OSC2 in CLKOUT mode.
(c) 2009 Microchip Technology Inc.
DS41203E-page 149
PIC16F688
14.5 DC Characteristics: PIC16F688 -I (Industrial) PIC16F688 -E (Extended) (Continued)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Min
--
DC CHARACTERISTICS Param No.
D100
Sym
IULP
Characteristic
Ultra Low-Power Wake-Up Current
Typ
200
Max
--
Units
nA
Conditions
See Application Note AN879, "Using the Microchip Ultra Low-Power Wake-up Module" (DS00879)
Capacitive Loading Specs on Output Pins D101* COSC2 OSC2 pin -- -- 15 pF In XT, HS and LP modes when external clock is used to drive OSC1
D101A* CIO D120 D120A D121 ED ED VDRW
All I/O pins Data EEPROM Memory Byte Endurance Byte Endurance VDD for Read/Write
-- 100K 10K VMIN
-- 1M 100K --
50 -- -- 5.5
pF E/W E/W V -40C TA +85C +85C TA +125C Using EECON1 to read/write VMIN = Minimum operating voltage
D122 D123 D124
TDEW TRETD TREF
Erase/Write Cycle Time Characteristic Retention Number of Total Erase/Write Cycles before Refresh(4) Program Flash Memory Cell Endurance Cell Endurance VDD for Read VDD for Erase/Write Erase/Write cycle time Characteristic Retention
-- 40 1M
5 -- 10M
6 -- --
ms Year Provided no other specifications are violated E/W -40C TA +85C
D130 D130A D131 D132 D133 D134
EP ED VPR VPEW TPEW TRETD *
10K 1K VMIN 4.5 -- 40
100K 10K -- -- 2 --
-- -- 5.5 5.5 2.5 --
E/W E/W V V ms
-40C TA +85C +85C TA +125C VMIN = Minimum operating voltage
Year Provided no other specifications are violated
Note 1: 2: 3: 4: 5:
These parameters are characterized but not tested. Data in "Typ" column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended to use an external clock in RC mode. Negative current is defined as current sourced by the pin. The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. See Section 9.0 "Data EEPROM and Flash Program Memory Control" for additional information. Including OSC2 in CLKOUT mode.
DS41203E-page 150
(c) 2009 Microchip Technology Inc.
PIC16F688
14.6 Thermal Considerations
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +125C Param No. TH01 JA Sym Characteristic Thermal Resistance Junction to Ambient Typ 69.8 85.0 100.4 46.3 32.5 31.0 31.7 2.6 150 -- -- Units C/W C/W C/W C/W C/W C/W C/W C/W C W W Conditions
TH02
TH03 TH04 TH05 TH06 TH07 Note 1: 2: 3:
14-pin PDIP package 14-pin SOIC package 14-pin TSSOP package 16-pin QFN 4x0.9mm package JC Thermal Resistance 14-pin PDIP package Junction to Case 14-pin SOIC package 14-pin TSSOP package 16-pin QFN 4x0.9mm package TJ Junction Temperature For derated power calculations PD Power Dissipation PD = PINTERNAL + PI/O PINTERNAL Internal Power Dissipation PINTERNAL = IDD x VDD (NOTE 1) PI/O I/O Power Dissipation -- W PI/O = (IOL * VOL) + (IOH * (VDD - VOH)) PDER Derated Power -- W PDER = (TJ - TA)/JA (NOTE 2, 3) IDD is current to run the chip alone without driving any load on the output pins. TA = Ambient Temperature. Maximum allowable power dissipation is the lower value of either the absolute maximum total power dissipation or derated power (PDER).
(c) 2009 Microchip Technology Inc.
DS41203E-page 151
PIC16F688
14.7 Timing Parameter Symbology
The timing parameter symbols have been created with one of the following formats: 1. TppS2ppS 2. TppS T F Frequency Lowercase letters (pp) and their meanings: pp cc CCP1 ck CLKOUT cs CS di SDI do SDO dt Data in io I/O PORT mc MCLR Uppercase letters and their meanings: S F Fall H High I Invalid (High-impedance) L Low
T
Time
osc rd rw sc ss t0 t1 wr
OSC1 RD RD or WR SCK SS T0CKI T1CKI WR
P R V Z
Period Rise Valid High-impedance
FIGURE 14-3:
LOAD CONDITIONS
Load Condition
Pin
CL
VSS
Legend: CL = 50 pF for all pins 15 pF for OSC2 output
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(c) 2009 Microchip Technology Inc.
PIC16F688
14.8 AC Characteristics: PIC16F688 (Industrial, Extended)
CLOCK TIMING
Q4 Q1 Q2 Q3 Q4 Q1
FIGURE 14-4:
OSC1/CLKIN OS02 OS04 OS03 OSC2/CLKOUT (LP, XT, HS Modes) OS04
OSC2/CLKOUT (CLKOUT Mode)
TABLE 14-1:
CLOCK OSCILLATOR TIMING REQUIREMENTS
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +125C Param No. OS01 Sym FOSC Characteristic External CLKIN Frequency(1) Min DC DC DC DC -- 0.1 1 DC 27 250 50 50 -- 250 50 250 Typ -- -- -- -- 32.768 -- -- -- -- -- -- -- 30.5 -- -- -- Max 37 4 20 20 -- 4 20 4 * * * * -- 10,000 1,000 -- Units kHz MHz MHz MHz kHz MHz MHz MHz s ns ns ns s ns ns ns Conditions LP Oscillator mode XT Oscillator mode HS Oscillator mode EC Oscillator mode LP Oscillator mode XT Oscillator mode HS Oscillator mode RC Oscillator mode LP Oscillator mode XT Oscillator mode HS Oscillator mode EC Oscillator mode LP Oscillator mode XT Oscillator mode HS Oscillator mode RC Oscillator mode
Oscillator Frequency(1)
OS02
TOSC
External CLKIN Period(1)
Oscillator Period(1)
200 TCY DC ns TCY = 4/FOSC 2 -- -- s LP oscillator 100 -- -- ns XT oscillator 20 -- -- ns HS oscillator OS05* TosR, External CLKIN Rise, 0 -- * ns LP oscillator TosF External CLKIN Fall 0 -- * ns XT oscillator 0 -- * ns HS oscillator * These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at "min" values with an external clock applied to OSC1 pin. When an external clock input is used, the "max" cycle time limit is "DC" (no clock) for all devices.
OS03 OS04*
TCY TosH, TosL
Instruction Cycle Time(1) External CLKIN High, External CLKIN Low
(c) 2009 Microchip Technology Inc.
DS41203E-page 153
PIC16F688
TABLE 14-2: OSCILLATOR PARAMETERS
Standard Operating Conditions (unless otherwise stated) Operating Temperature -40C TA +125C Param No. OS06 OS07 OS08 Sym TWARM TSC HFOSC Characteristic Internal Oscillator Switch when running(3) Fail-Safe Sample Clock Period(1) Internal Calibrated HFINTOSC Frequency(2) Freq Tolerance -- -- 1% 2% 5% Min -- -- 7.92 7.84 7.60 Typ -- 21 8.0 8.0 8.0 Max 2 -- 8.08 8.16 8.40 Units TOSC ms MHz MHz MHz Conditions Slowest clock LFINTOSC/64 VDD = 3.5V, 25C 2.5V VDD 5.5V, 0C TA +85C 2.0V VDD 5.5V, -40C TA +85C (Ind.), -40C TA +125C (Ext.)
OS09* OS10*
LFOSC TIOSC
ST
Internal Uncalibrated LFINTOSC Frequency HFINTOSC Oscillator Wake-up from Sleep Start-up Time
-- -- -- --
15 5.5 3.5 3
31 12 7 6
45 24 14 11
kHz s s s VDD = 2.0V, -40C to +85C VDD = 3.0V, -40C to +85C VDD = 5.0V, -40C to +85C
* These parameters are characterized but not tested. Data in "Typ" column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at "min" values with an external clock applied to the OSC1 pin. When an external clock input is used, the "max" cycle time limit is "DC" (no clock) for all devices. 2: To ensure these oscillator frequency tolerances, VDD and VSS must be capacitively decoupled as close to the device as possible. 0.1 F and 0.01 F values in parallel are recommended. 3: By design.
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PIC16F688
FIGURE 14-5:
Cycle
CLKOUT AND I/O TIMING
Write Q4 Fetch Q1 Read Q2 Execute Q3
FOSC OS11 CLKOUT OS19 OS13 I/O pin (Input) OS15 I/O pin (Output) Old Value OS18, OS19 OS14 New Value OS17 OS20 OS21 OS16 OS18 OS12
TABLE 14-3:
CLKOUT AND I/O TIMING PARAMETERS
Standard Operating Conditions (unless otherwise stated) Operating Temperature -40C TA +125C Param No. OS11 OS12 OS13 OS14 OS15* OS16 OS17 OS18 OS19 OS20* OS21* * Note 1: 2: Sym TOSH2CKL TOSH2CKH TCKL2IOV TIOV2CKH TOSH2IOV TOSH2IOI TIOV2OSH TIOR TIOF TINP TRAP Characteristic FOSC to CLKOUT (1) FOSC to CLKOUT
(1)
Min -- -- -- TOSC + 200 ns -- 50 20 -- -- -- -- 25 TCY
Typ -- -- -- -- 50 -- -- 15 10 28 15 -- --
Max 70 72 20 -- 70 -- -- 72 32 55 30 -- --
Units ns ns ns ns ns ns ns ns ns ns ns
Conditions VDD = 5.0V VDD = 5.0V
CLKOUT to Port out valid(1) Port input valid before CLKOUT(1) FOSC (Q1 cycle) to Port out valid FOSC (Q2 cycle) to Port input invalid (I/O in hold time) Port input valid to FOSC (Q2 cycle) (I/O in setup time) Port output rise time(2) Port output fall time(2) INT pin input high or low time PORTA interrupt-on-change new input level time
VDD = 5.0V VDD = 5.0V
VDD = 2.0V VDD = 5.0V VDD = 2.0V VDD = 5.0V
These parameters are characterized but not tested. Data in "Typ" column is at 5.0V, 25C unless otherwise stated. Measurements are taken in RC mode where CLKOUT output is 4 x TOSC. Includes OSC2 in CLKOUT mode.
(c) 2009 Microchip Technology Inc.
DS41203E-page 155
PIC16F688
FIGURE 14-6: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING
VDD MCLR Internal POR 33 PWRT Time-out OSC Start-Up Time 32 30
Internal Reset(1) Watchdog Timer Reset(1) 34 I/O pins Note 1: Asserted low. 31 34
FIGURE 14-7:
VDD
BROWN-OUT RESET TIMING AND CHARACTERISTICS
VBOR
VBOR + VHYST
(Device in Brown-out Reset)
(Device not in Brown-out Reset)
37
Reset (due to BOR) *
33*
64 ms delay only if PWRTE bit in the Configuration Word register is programmed to `0'.
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PIC16F688
TABLE 14-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER AND BROWN-OUT RESET PARAMETERS
Standard Operating Conditions (unless otherwise stated) Operating Temperature -40C TA +125C Param No. 30 31 32 33* 34* Sym TMCL TWDT TOST TPWRT TIOZ Characteristic MCLR Pulse Width (low) Watchdog Timer Time-out Period (No Prescaler) Oscillation Start-up Timer Period(1, 2) Power-up Timer Period I/O High-impedance from MCLR Low or Watchdog Timer Reset Brown-out Reset Voltage Brown-out Reset Hysteresis Brown-out Reset Minimum Detection Period Min 2 5 10 10 -- 40 -- Typ -- -- 16 16 1024 65 -- Max -- -- 29 31 -- 140 2.0 Units s s ms ms Conditions VDD = 5V, -40C to +85C VDD = 5V VDD = 5V, -40C to +85C VDD = 5V
TOSC (NOTE 3) ms s
35 36* 37*
VBOR VHYST TBOR
2.0 -- 100
-- 50 --
2.2 -- --
V mV s
(NOTE 4) VDD VBOR
* These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at "min" values with an external clock applied to the OSC1 pin. When an external clock input is used, the "max" cycle time limit is "DC" (no clock) for all devices. 2: By design. 3: Period of the slower clock. 4: To ensure these voltage tolerances, VDD and VSS must be capacitively decoupled as close to the device as possible. 0.1 F and 0.01 F values in parallel are recommended.
(c) 2009 Microchip Technology Inc.
DS41203E-page 157
PIC16F688
FIGURE 14-8: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS
T0CKI 40 41
42
T1CKI 45 47 46 49
TMR0 or TMR1
TABLE 14-5:
TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS
Standard Operating Conditions (unless otherwise stated) Operating Temperature -40C TA +125C Param No. 40* 41* 42* Sym TT0H TT0L TT0P Characteristic T0CKI High Pulse Width T0CKI Low Pulse Width T0CKI Period No Prescaler With Prescaler No Prescaler With Prescaler Min 0.5 TCY + 20 10 0.5 TCY + 20 10 Greater of: 20 or TCY + 40 N 0.5 TCY + 20 15 30 0.5 TCY + 20 15 30 Greater of: 30 or TCY + 40 N 60 -- 2 TOSC Typ -- -- -- -- -- Max -- -- -- -- -- Units ns ns ns ns ns N = prescale value (2, 4, ..., 256) Conditions
45*
TT1H
T1CKI High Synchronous, No Prescaler Time Synchronous, with Prescaler Asynchronous T1CKI Low Time Synchronous, No Prescaler Synchronous, with Prescaler Asynchronous
-- -- -- -- -- -- --
-- -- -- -- -- -- --
ns ns ns ns ns ns ns N = prescale value (1, 2, 4, 8)
46*
TT1L
47*
TT1P
T1CKI Input Synchronous Period Asynchronous
-- 32.768 --
-- -- 7 TOSC
ns kHz -- Timers in Sync mode
48 49*
FT1
Timer1 Oscillator Input Frequency Range (oscillator enabled by setting bit T1OSCEN)
TCKEZTMR1 Delay from External Clock Edge to Timer Increment *
These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
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PIC16F688
TABLE 14-6: COMPARATOR SPECIFICATIONS
Standard Operating Conditions (unless otherwise stated) Operating Temperature -40C TA +125C Param No. CM01 CM02 Sym VOS VCM Characteristics Input Offset Voltage Input Common Mode Voltage Common Mode Rejection Ratio Response Time Falling Rising CM05* TMC2COV Comparator Mode Change to Output Valid Min -- 0 +55 -- -- -- Typ 5.0 -- -- 150 200 -- Max 10 VDD - 1.5 -- 600 1000 10 Units mV V dB ns ns s (NOTE 1) Comments (VDD - 1.5)/2
CM03* CMRR CM04* TRT
* These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Response time is measured with one comparator input at (VDD - 1.5)/2 - 100 mV to (VDD - 1.5)/2 + 20 mV.
TABLE 14-7:
COMPARATOR VOLTAGE REFERENCE (CVREF) SPECIFICATIONS
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +125C Param No. CV01* CV02* CV03* CV04* Sym CLSB CACC CR CST Characteristics Step Size(2) Absolute Accuracy Unit Resistor Value (R) Settling Time(1) Min -- -- -- -- -- -- Typ VDD/24 VDD/32 -- -- 2k -- Max -- -- 1/2 1/2 -- 10 Units V V LSb LSb s Comments Low Range (VRR = 1) High Range (VRR = 0) Low Range (VRR = 1) High Range (VRR = 0)
* These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Settling time measured while VRR = 1 and VR<3:0> transitions from `0000' to `1111'. 2: See Section 7.10 "Comparator Voltage Reference" for more information.
(c) 2009 Microchip Technology Inc.
DS41203E-page 159
PIC16F688
TABLE 14-8: PIC16F688 A/D CONVERTER (ADC) CHARACTERISTICS
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +125C Param Sym No. AD01 AD02 AD03 AD04 AD07 NR EIL EDL EOFF EGN Characteristic Resolution Integral Error Differential Error Offset Error Gain Error Reference Voltage(1) Min -- -- -- -- -- 2.2 2.7 VSS -- Typ -- -- -- -- -- -- Max 10 bits 1 1 1 1 -- VDD VREF 10 Units bit LSb VREF = 5.12V LSb No missing codes to 10 bits VREF = 5.12V LSb VREF = 5.12V LSb VREF = 5.12V V Absolute minimum to ensure 1 LSb accuracy V k Conditions
AD06 VREF AD06A AD07 AD08 VAIN ZAIN
Full-Scale Range Recommended Impedance of Analog Voltage Source VREF Input Current(1)
-- --
AD09* IREF
10 --
-- --
1000 50
A A
During VAIN acquisition. Based on differential of VHOLD to VAIN. During A/D conversion cycle.
* These parameters are characterized but not tested. Data in "Typ" column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: ADC VREF is from external VREF or VDD pin, whichever is selected as reference input.
DS41203E-page 160
(c) 2009 Microchip Technology Inc.
PIC16F688
TABLE 14-9: PIC16F688 A/D CONVERSION REQUIREMENTS
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +125C Param No. Sym Characteristic A/D Clock Period A/D Internal RC Oscillator Period AD131 TCNV Conversion Time (not including Acquisition Time)(1) Min 1.6 3.0 3.0 1.6 -- Typ -- -- 6.0 4.0 11 Max Units 9.0 9.0 9.0 6.0 -- s s s s TAD Conditions TOSC-based, VREF 3.0V TOSC-based, VREF full range ADCS<1:0> = 11 (ADRC mode) At VDD = 2.5V At VDD = 5.0V Set GO/DONE bit to new data in A/D Result register
AD130* TAD
AD132* TACQ Acquisition Time AD133* TAMP Amplifier Settling Time AD134 TGO Q4 to A/D Clock Start -- -- --
11.5 -- TOSC/2 TOSC/2 + TCY
-- 5 -- --
s s -- -- If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed.
* These parameters are characterized but not tested. Data in "Typ" column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: ADRESH and ADRESL registers may be read on the following TCY cycle. 2: See Section 8.3 "A/D Acquisition Requirements" for minimum conditions.
(c) 2009 Microchip Technology Inc.
DS41203E-page 161
PIC16F688
FIGURE 14-9: PIC16F688 A/D CONVERSION TIMING (NORMAL MODE)
1 TCY AD131 AD130 A/D CLK A/D Data ADRES ADIF GO Sample Note 1: AD132 Sampling Stopped 9 8 OLD_DATA 7 6 3 2 1 0 NEW_DATA 1 TCY DONE BSF ADCON0, GO AD134 Q4
(TOSC/2(1))
If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed.
FIGURE 14-10:
PIC16F688 A/D CONVERSION TIMING (SLEEP MODE)
BSF ADCON0, GO AD134 Q4 A/D CLK A/D Data ADRES ADIF GO Sample AD132 Sampling Stopped 9 8 7 6 3 2 1 0 NEW_DATA 1 TCY DONE (TOSC/2 + TCY(1)) AD131 AD130 1 TCY
OLD_DATA
Note 1:
If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed.
DS41203E-page 162
(c) 2009 Microchip Technology Inc.
PIC16F688
15.0 DC AND AC CHARACTERISTICS GRAPHS AND TABLES
The graphs and tables provided in this section are for design guidance and are not tested. In some graphs or tables, the data presented are outside specified operating range (i.e., outside specified VDD range). This is for information only and devices are ensured to operate properly only within the specified range. Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore, outside the warranted range.
"Typical" represents the mean of the distribution at 25C. "Maximum" or "minimum" represents (mean + 3) or (mean - 3) respectively, where is a standard deviation, over each temperature range. FIGURE 15-1:
3.5 Typical: Statistical Mean @25C Maximum: Mean (Worst-case Temp) + 3 (-40C to 125C)
TYPICAL IDD vs. FOSC OVER VDD (EC MODE)
3.0
5.5V 5.0V
2.5
IDD (mA)
2.0
4.0V
1.5
3.0V
1.0
2.0V
0.5
0.0 1 MHz 2 MHz 4 MHz 6 MHz 8 MHz 10 MHz FOSC 12 MHz 14 MHz 16 MHz 18 MHz 20 MHz
(c) 2009 Microchip Technology Inc.
DS41203E-page 163
PIC16F688
FIGURE 15-2:
4.0 3.5 3.0 2.5 IDD (mA) 4.0V 2.0 1.5 1.0 0.5 0.0 1 MHz 2 MHz 4 MHz 6 MHz 8 MHz 10 MHz FOSC 12 MHz 14 MHz 16 MHz 18 MHz 20 MHz 3.0V Typical: Statistical Mean @25C Maximum: Mean (Worst-case Temp) + 3 (-40C to 125C) 5.5V 5.0V
MAXIMUM IDD vs. FOSC OVER VDD (EC MODE) EC Mode
2.0V
FIGURE 15-3:
4.0 3.5 3.0 2.5 IDD (mA) 2.0 1.5 1.0 0.5 0.0
TYPICAL IDD vs. FOSC OVER VDD (HS MODE)
Typical: Statistical Mean @25C Maximum: Mean (Worst-case Temp) + 3 (-40C + 125C) to Temp)
5.5V 5,0V 4.5V
4.0V 3.5V 3.0V
4 MHz
10 MHz FOSC
16 MHz
20 MHz
(c) 2009 Microchip Technology Inc.
DS41203E-page 164
PIC16F688
FIGURE 15-4:
5.0 4.5 4.0 3.5 IDD (mA) 3.0 2.5 2.0 1.5 1.0 0.5 0.0 4 MHz 10 MHz FOSC 16 MHz 20 MHz 4.0V 3.5V 3.0V Typical: Statistical Mean @25C Typical: Statistical Mean @25xC Maximum: Mean (Worst-case Temp) + 3 Maximum: Mean (Worst Case (-40C+to 125C) Temp) 3 5.5V 5.0V 4.5V
MAXIMUM IDD vs. FOSC OVER VDD (HS MODE)
FIGURE 15-5:
1200
TYPICAL IDD vs. VDD OVER FOSC (XT MODE)
@25C Typical: Statistical Mean @25xC Maximum: Mean (Worst Case Temp) + 3 (Worst-case Temp) + 1000
800 IDD (uA)
600
4 MHz
400 1 MHz 200
0 2 2.5 3 3.5 VDD (V) 4 4.5 5 5.5
(c) 2009 Microchip Technology Inc.
DS41203E-page 165
PIC16F688
FIGURE 15-6:
1,800 1,600 1,400 1,200 IDD (uA) 1,000 800 600 400 200 0 2 2.5 3 3.5 VDD (V) 4 4.5 5 5.5 1 MHz 4 MHz Typical: Statistical Mean @25C Maximum: Mean (Worst-case Temp) + 3 (-40C to 125C)
MAXIMUM IDD vs. VDD OVER FOSC (XT MODE)
FIGURE 15-7:
1,200
TYPICAL IDD vs. VDD OVER FOSC (EXTRC MODE)
1,000
Typical: Statistical Mean @25xC Typical: Statistical Mean @25C Maximum: Mean (Worst Case Temp) + Maximum: Mean (Worst-case Temp) + 3 3 ((-40C to 125C) 40xC 125xC) t 4 MHz
800
IDD (uA)
600 1 MHz 400
200
0 2 2.5 3 3.5 VDD (V) 4 4.5 5 5.5
(c) 2009 Microchip Technology Inc.
DS41203E-page 166
PIC16F688
FIGURE 15-8:
2,000 1,800 1,600 1,400 4 MHz 1,200 IDD (uA) 1,000 800 1 MHz 600 400 200 0 2 2.5 3 3.5 VDD (V) 4 4.5 5 5.5 Typical: Statistical Mean @25C Maximum: Mean (Worst-case Temp) + + 3 Maximum: Mean (Worst Case Temp) 3s (-40xC to 125xC) (-40C to 125C)
MAXIMUM IDD vs. VDD (EXTRC MODE)
FIGURE 15-9:
80 70 60 50 IDD (A) 40 30
IDD vs. VDD OVER FOSC (LFINTOSC MODE, 31 kHz)
LFINTOSC Mode, 31KHZ
Typical: Statistical Mean @25C Maximum: Mean (Worst-case Temp) + 3 (-40C to 125C)
Maximum
Typical 20 10 0 2.0 2.5 3.0 3.5 VDD (V) 4.0 4.5 5.0 5.5
(c) 2009 Microchip Technology Inc.
DS41203E-page 167
PIC16F688
FIGURE 15-10:
90 80 70 60 IDD (uA) 50 40 30 32 kHz Typical 20 10 0 2 2.5 3 3.5 VDD (V) 4 4.5 5 5.5 32 kHz Maximum Typical: Statistical Mean @25C Maximum: Mean (Worst-case Temp) + 3 (-40C to 125C)
IDD vs. VDD (LP MODE)
FIGURE 15-11:
1,800 1,600 1,400 1,200
TYPICAL IDD vs. FOSC OVER VDD (HFINTOSC MODE) HFINTOSC
Typical: Statistical Mean @25C Maximum: Mean (Worst-case Temp) + 3 (-40C to 125C)
5.5V 5.0V
4.0V IDD (uA) 1,000 800 600 2.0V 400 200 0 125 kHz 250 kHz 500 kHz 1 MHz VDD (V) 2 MHz 4 MHz 8 MHz 3.0V
(c) 2009 Microchip Technology Inc.
DS41203E-page 168
PIC16F688
FIGURE 15-12:
2,500 Typical: Statistical Mean @ 25C Maximum: Mean (Worst-case Temp) +3 (-40C to 125C)
MAXIMUM IDD vs. FOSC OVER VDD (HFINTOSC MODE)
2,000
5.5V 5.0V
1,500 IDD (uA) 4.0V 3.0V
1,000
2.0V 500
0 125 kHz 250 kHz 500 kHz 1 MHz VDD (V) 2 MHz 4 MHz 8 MHz
FIGURE 15-13:
0.45 0.40 0.35 0.30 IPD (A) 0.25 0.20 0.15 0.10 0.05 0.0 2.0
TYPICAL IPD vs. VDD (SLEEP MODE, ALL PERIPHERALS DISABLED)
Typical (Sleep Mode all Peripherals Disabled)
Typical: Statistical Mean @25C Maximum: Mean (Worst-case Temp) + 3 (-40C to 125C)
2.5
3.0
3.5 VDD (V)
4.0
4.5
5.0
5.5
(c) 2009 Microchip Technology Inc.
DS41203E-page 169
PIC16F688
FIGURE 15-14:
18.0 16.0 14.0 Max. 125C 12.0 IPD (A) 10.0 8.0 6.0 4.0 2.0 0.0 2.0 2.5 3.0 3.5 VDD (V) 4.0 4.5 5.0 5.5 Max. 85C Typical: Statistical Mean @25C Maximum: Mean + 3 Maximum: Mean (Worst-case Temp) + 3 (-40C to 125C)
MAXIMUM IPD vs. VDD (SLEEP MODE, ALL PERIPHERALS DISABLED)
Maximum (Sleep Mode all Peripherals Disabled)
FIGURE 15-15:
180 160 140 120 IPD (A) 100
COMPARATOR IPD vs. VDD (BOTH COMPARATORS ENABLED)
Typical: Statistical Mean @25C Maximum: Mean (Worst-case Temp) + 3 (-40C to 125C)
Maximum
Typical 80 60 40 20 0 2.0 2.5 3.0 3.5 VDD (V) 4.0 4.5 5.0 5.5
(c) 2009 Microchip Technology Inc.
DS41203E-page 170
PIC16F688
FIGURE 15-16:
160 Typical: Statistical Mean @25C Maximum: Mean (Worst-case Temp) + 3 (-40C to 125C)
BOR IPD vs. VDD OVER TEMPERATURE
140
120
100 IPD (A) Maximum 80 Typical 60
40
20
0 2.5 3.0 3.5 4.0 VDD (V) 4.5 5.0 5.5
FIGURE 15-17:
3.0
TYPICAL WDT IPD vs. VDD (25C)
2.5
2.0 IPD (uA)
1.5
1.0
0.5
0.0 2.0V 2.5V 3.0V 3.5V VDD (V) 4.0V 4.5V 5.0V 5.5V
(c) 2009 Microchip Technology Inc.
DS41203E-page 171
PIC16F688
FIGURE 15-18:
40.0 35.0 Max. 125C 30.0 25.0 IPD (uA) 20.0 15.0 10.0 Max. 85C 5.0 0.0 2.0V 2.5V 3.0V 3.5V VDD (V) 4.0V 4.5V 5.0V 5.5V
MAXIMUM WDT IPD vs. VDD OVER TEMPERATURE
FIGURE 15-19:
30 28 26 24 22 Time (ms) 20
WDT PERIOD vs. VDD OVER TEMPERATURE
Typical: Statistical Mean @25C Maximum: Mean + 3 (-40C to 125C) Maximum: Mean + 3 Max. (125C) Max. (85C)
Typical 18 16 14 Minimum 12 10 2.0 2.5 3.0 3.5 VDD (V) 4.0 4.5 5.0 5.5
(c) 2009 Microchip Technology Inc.
DS41203E-page 172
PIC16F688
FIGURE 15-20:
30 28 26 Maximum 24 22 Time (ms) 20 Typical 18 16 Minimum 14 12 10 -40C 25C Temperature (C) 85C 125C Typical: Statistical Mean @25C Maximum: Mean + 3
WDT PERIOD vs. TEMPERATURE
Vdd = 5V
FIGURE 15-21:
140
CVREF IPD vs. VDD OVER TEMPERATURE (HIGH RANGE)
High Range
120
Typical: Statistical Mean @25C Maximum: Mean + 3 (-40C to 125C)
100 Max. 125C IPD (A) 80 Max. 85C 60 Typical 40
20
0 2.0 2.5 3.0 3.5 VDD (V) 4.0 4.5 5.0 5.5
(c) 2009 Microchip Technology Inc.
DS41203E-page 173
PIC16F688
FIGURE 15-22:
180 160 140 120 Max. 125C IPD (A) 100 Max. 85C 80 Typical 60 40 20 0 2.0 2.5 3.0 3.5 VDD (V) 4.0 4.5 5.0 5.5 Typical: Statistical Mean @25C Maximum: Mean (Worst-case Temp) + 3 (-40C to 125C)
CVREF IPD vs. VDD OVER TEMPERATURE (LOW RANGE)
FIGURE 15-23:
VOL vs. IOL OVER TEMPERATURE (VDD = 3.0V)
(VDD = 3V, -40xC TO 125xC)
0.8 Typical: Statistical Mean @25C Maximum: Mean + 3 Max. 125C 0.6
0.7
0.5 VOL (V)
Max. 85C
0.4
0.3
Typical 25C
0.2 Min. -40C 0.1
0.0 5.0 5.5 6.0 6.5 7.0 7.5 IOL (mA) 8.0 8.5 9.0 9.5 10.0
(c) 2009 Microchip Technology Inc.
DS41203E-page 174
PIC16F688
FIGURE 15-24:
0.45 Typical: Statistical Mean @25C Typical: Statistical Maximum: Mean + 3 Mean Maximum: Means + 3 Max. 125C 0.35 Max. 85C 0.30
VOL vs. IOL OVER TEMPERATURE (VDD = 5.0V)
0.40
VOL (V)
0.25 Typ. 25C 0.20
0.15
Min. -40C
0.10
0.05
0.00 5.0 5.5 6.0 6.5 7.0 7.5 IOL (mA) 8.0 8.5 9.0 9.5 10.0
FIGURE 15-25:
3.5
VOH vs. IOH OVER TEMPERATURE (VDD = 3.0V)
3.0 Max. -40C Typ. 25C
2.5
Min. 125C 2.0 VOH (V) 1.5 Typical: Statistical Mean @25C Maximum: Mean (Worst-case Temp) + 3 (-40C to 125C) 1.0 0.5 0.0 0.0 -0.5 -1.0 -1.5 -2.0 IOH (mA) -2.5 -3.0 -3.5 -4.0 (c) 2009 Microchip Technology Inc.
DS41203E-page 175
PIC16F688
FIGURE 15-26:
5.5
VOH vs. IOH OVER TEMPERATURE (VDD = 5.0V) ( , )
5.0 Max. -40C
Typ. 25C 4.5 VOH (V) Min. 125C
4.0
3.5
Typical: Statistical Mean @25C Maximum: Mean (Worst-case Temp) + 3 (-40C to 125C)
3.0 0.0 -0.5 -1.0 -1.5 -2.0 -2.5 IOH (mA) -3.0 -3.5 -4.0 -4.5 -5.0
FIGURE 15-27:
1.7
TTL INPUT THRESHOLD VIN vs. VDD OVER TEMPERATURE
(TTL Input, -40xC TO 125xC)
1.5
Typical: Statistical Mean @25C Maximum: Mean (Worst-case Temp) + 3 (-40C to 125C) Max. -40C
1.3 VIN (V) Typ. 25C 1.1 Min. 125C 0.9
0.7
0.5 2.0 2.5 3.0 3.5 VDD (V) 4.0 4.5 5.0 5.5
(c) 2009 Microchip Technology Inc.
DS41203E-page 176
PIC16F688
FIGURE 15-28: SCHMITT TRIGGER INPUT THRESHOLD VIN vs. VDD OVER TEMPERATURE
(ST Input, -40xC TO 125xC) 4.0 VIH Max. 125C 3.5 Typical: Statistical Mean @25C Maximum: Mean (Worst-case Temp) + 3 (-40C to 125C)
VIH Min. -40C
3.0
VIN (V)
2.5
2.0 VIL Max. -40C 1.5 VIL Min. 125C
1.0
0.5 2.0 2.5 3.0 3.5 VDD (V) 4.0 4.5 5.0 5.5
FIGURE 15-29:
45.0 40.0 35.0 30.0 IPD (mA) 25.0 20.0 15.0 10.0 5.0 0.0 2.0
T1OSC IPD vs. VDD OVER TEMPERATURE (32 kHz)
Typical: Statistical Mean @25C Maximum: Mean (Worst-case Temp) + 3 Maximum: Mean + 3 to 125xC) (-40xC (-40C to 125C) Max. 125C
Max. 85C
Typ. 25C
2.5
3.0
3.5 VDD (V)
4.0
4.5
5.0
5.5
(c) 2009 Microchip Technology Inc.
DS41203E-page 177
PIC16F688
FIGURE 15-30:
1000 900 800 Response Time (nS) 700 600 500 400 300 200 100 0 2.0 2.5 VDD (V) 4.0 5.5 Typ. 25C Min. -40C Note: VCM = VDD - 1.5V)/2 V+ input = VCM V- input = Transition from VCM + 100MV to VCM - 20MV Max. 125C
COMPARATOR RESPONSE TIME (RISING EDGE)
531 806
Max. 85C
FIGURE 15-31:
1000 900 800 700 Response Time (nS) 600 500 400 300 200 100 0 Note:
COMPARATOR RESPONSE TIME (FALLING EDGE)
Max. 125C
VCM = VDD - 1.5V)/2 V+ input = VCM V- input = Transition from VCM - 100MV to VCM + 20MV
Max. 85C
Typ. 25C Min. -40C
2.0
2.5 VDD (V)
4.0
5.5
(c) 2009 Microchip Technology Inc.
DS41203E-page 178
PIC16F688
FIGURE 15-32:
45,000 40,000 35,000 30,000 Frequency (Hz) 25,000 20,000 15,000 10,000 5,000 0 2.0 2.5 3.0 3.5 VDD (V) 4.0 4.5 5.0 5.5 Min. 85C Min. 125C Typ. 25C
LFINTOSC FREQUENCY vs. VDD OVER TEMPERATURE (31 kHz)
LFINTOSC 31Khz
Max. -40C
Typical: Statistical Mean @25C Maximum: Mean (Worst-case Temp) + 3 (-40C to 125C)
FIGURE 15-33:
8
ADC CLOCK PERIOD vs. VDD OVER TEMPERATURE
125C 6 85C
Typical: Statistical Mean @25C Maximum: Mean (Worst-case Temp) + 3 (-40C to 125C)
Time (s)
4
25C
-40C 2
0 2.0 2.5 3.0 3.5 VDD (V) 4.0 4.5 5.0 5.5
(c) 2009 Microchip Technology Inc.
DS41203E-page 179
PIC16F688
FIGURE 15-34:
16 Typical: Statistical Mean @25C Maximum: Mean (Worst-case Temp) + 3 (-40C to 125C)
TYPICAL HFINTOSC START-UP TIMES vs. VDD OVER TEMPERATURE
14 85C 12 25C 10 Time (s) -40C 8
6
4
2
0 2.0
2.5
3.0
3.5 VDD (V)
4.0
4.5
5.0
5.5
FIGURE 15-35:
25
MAXIMUM HFINTOSC START-UP TIMES vs. VDD OVER TEMPERATURE
-40C to +85C
20
Typical: Statistical Mean @25C Maximum: Mean (Worst-case Temp) + 3 (-40C to 125C)
Time (s)
15 85C 25C 10 -40C
5
0 2.0
2.5
3.0
3.5 VDD (V)
4.0
4.5
5.0
5.5
(c) 2009 Microchip Technology Inc.
DS41203E-page 180
PIC16F688
FIGURE 15-36:
10 9 8 7 85C Time (s) 6 25C 5 -40C 4 3 2 1 0 2.0 Typical: Statistical Mean @25C Maximum: Mean (Worst-case Temp) + 3 (-40C to 125C)
MINIMUM HFINTOSC START-UP TIMES vs. VDD OVER TEMPERATURE
-40C to +85C
2.5
3.0
3.5 VDD (V)
4.0
4.5
5.0
5.5
FIGURE 15-37:
5 4 3 Change from Calibration (%) 2 1 0 -1 -2 -3 -4 -5 2.0
TYPICAL HFINTOSC FREQUENCY CHANGE vs. VDD (25C)
2.5
3.0
3.5 VDD (V)
4.0
4.5
5.0
5.5
(c) 2009 Microchip Technology Inc.
DS41203E-page 181
PIC16F688
FIGURE 15-38:
5 4 3 Change from Calibration (%) 2 1 0 -1 -2 -3 -4 -5 2.0 2.5 3.0 3.5 VDD (V) 4.0 4.5 5.0 5.5
TYPICAL HFINTOSC FREQUENCY CHANGE OVER DEVICE VDD (85C)
FIGURE 15-39:
5 4 3 Change from Calibration (%) 2 1 0 -1 -2 -3 -4 -5 2.0
TYPICAL HFINTOSC FREQUENCY CHANGE vs. VDD (125C)
2.5
3.0
3.5 VDD (V)
4.0
4.5
5.0
5.5
(c) 2009 Microchip Technology Inc.
DS41203E-page 182
PIC16F688
FIGURE 15-40:
5 4 3 Change from Calibration (%) 2 1 0 -1 -2 -3 -4 -5 2.0 2.5 3.0 3.5 VDD (V) 4.0 4.5 5.0 5.5
TYPICAL HFINTOSC FREQUENCY CHANGE vs. VDD (-40C)
(c) 2009 Microchip Technology Inc.
DS41203E-page 183
PIC16F688
NOTES:
(c) 2009 Microchip Technology Inc.
DS41203E-page 184
PIC16F688
16.0
16.1
PACKAGING INFORMATION
Package Marking Information
14-Lead PDIP (Skinny DIP) XXXXXXXXXXXXXX XXXXXXXXXXXXXX YYWWNNN 14-Lead SOIC (3.90 mm) XXXXXXXXXXX XXXXXXXXXXX YYWWNNN Example PIC16F688 -I/P e3 0610017 Example PIC16C688 -I/SL e3 0610017
14-Lead TSSOP
Example
XXXXXXXX YYWW NNN
688/ST e3 0610 017
16-Lead QFN
Example
XXXXXX XXXXXX YWWNNN
16F688 -I/ML e3 610017
Legend: XX...X Y YY WW NNN
e3
*
Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week `01') Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package.
Note:
In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.
*
Standard PIC(R) device marking consists of Microchip part number, year code, week code, and traceability code. For PIC device marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price.
(c) 2009 Microchip Technology Inc.
DS41203E-page 185
PIC16F688
16.2 Package Details
The following sections give the technical details of the packages.
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A1 b
b1 e
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DS41203E-page 186
(c) 2009 Microchip Technology Inc.
PIC16F688
14-Lead Plastic Small Outline (SL) - Narrow, 3.90 mm Body [SOIC]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging
D N
E E1 NOTE 1 1 2 b h 3
e h c
A
A2
A1
L L1
Units Dimension Limits Number of Pins Pitch Overall Height Molded Package Thickness Standoff Overall Width Molded Package Width Overall Length Chamfer (optional) Foot Length Footprint Foot Angle Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom N e A A2 A1 E E1 D h L L1 c b 0 0.17 0.31 5 5 0.25 0.40 - 1.25 0.10 MIN
MILLMETERS NOM 14 1.27 BSC - - - 6.00 BSC 3.90 BSC 8.65 BSC - - 1.04 REF - - - - - 8 0.25 0.51 15 0.50 1.27 1.75 - 0.25 MAX
15 Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Significant Characteristic. 3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side. 4. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-065B
(c) 2009 Microchip Technology Inc.
DS41203E-page 187
PIC16F688
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DS41203E-page 188
(c) 2009 Microchip Technology Inc.
PIC16F688
14-Lead Plastic Thin Shrink Small Outline (ST) - 4.4 mm Body [TSSOP]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging
D N
E E1
NOTE 1 12 e b c A A2
A1
Units Dimension Limits Number of Pins Pitch Overall Height Molded Package Thickness Standoff Overall Width Molded Package Width Molded Package Length Foot Length Footprint Foot Angle Lead Thickness N e A A2 A1 E E1 D L L1 c
L1
MILLIMETERS MIN NOM 14 0.65 BSC - 0.80 0.05 4.30 4.90 0.45 0 0.09 - 1.00 - 6.40 BSC 4.40 5.00 0.60 1.00 REF - - 8 0.20 4.50 5.10 0.75 1.20 1.05 0.15 MAX
L
Lead Width b 0.19 - 0.30 Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side. 3. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-087B
(c) 2009 Microchip Technology Inc.
DS41203E-page 189
PIC16F688
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging
DS41203E-page 190
(c) 2009 Microchip Technology Inc.
PIC16F688
16-Lead Plastic Quad Flat, No Lead Package (ML) - 4x4x0.9 mm Body [QFN]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging
D EXPOSED PAD
D2
e E 2 1 E2 2 1 b
N TOP VIEW NOTE 1
N BOTTOM VIEW L
K
A A1
A3
Units Dimension Limits Number of Pins Pitch Overall Height Standoff Contact Thickness Overall Width Exposed Pad Width Overall Length Exposed Pad Length Contact Width Contact Length Contact-to-Exposed Pad N e A A1 A3 E E2 D D2 b L K 2.50 0.25 0.30 0.20 2.50 0.80 0.00 MIN
MILLIMETERS NOM 16 0.65 BSC 0.90 0.02 0.20 REF 4.00 BSC 2.65 4.00 BSC 2.65 0.30 0.40 - 2.80 0.35 0.50 - 2.80 1.00 0.05 MAX
Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Package is saw singulated. 3. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-127B
(c) 2009 Microchip Technology Inc.
DS41203E-page 191
PIC16F688
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DS41203E-page 192
(c) 2009 Microchip Technology Inc.
PIC16F688
APPENDIX A:
Revision A
This is a new data sheet.
DATA SHEET REVISION HISTORY
APPENDIX B:
MIGRATING FROM OTHER PIC(R) DEVICES
This discusses some of the issues in migrating from other PIC devices to the PIC16F6XX family of devices.
Revision B
Rewrites of the Oscillator and Special Features of the CPU Sections. General corrections to Figures and formatting.
B.1
PIC16F676 to PIC16F688
FEATURE COMPARISON
PIC16F676 20 MHz 1024 64 10-bit 128 1/1 8 Y RA0/1/2/4/5 RA0/1/2/3 /4/5 1 N N N N 4 MHz N PIC16F688 20 MHz 4K 256 10-bit 256 1/1 8 Y RA0/1/2/4/5, MCLR RA0/1/2/3/4/5 2 Y Y Y Y 32 kHz 8 MHz Y Feature
TABLE B-1:
Max Operating Speed
Revision C
Revised Electrical Section and added Char Data. Added Golden Chapters.
Max Program Memory (Words) SRAM (Bytes) A/D Resolution Data EEPROM (bytes) Timers (8/16-bit) Oscillator Modes Brown-out Reset Internal Pull-ups Interrupt-on-change Comparator EUSART Ultra Low-Power Wake-up Extended WDT Software Control Option of WDT/BOR INTOSC Frequencies Clock Switching Note:
Revision D
Replaced Package Drawings; Revised Product ID (SL Package to 3.90 mm); Replaced PICmicro with PIC; Replaced Dev. Tool Section.
Revision E
Updated Peripheral Features, page 1; Deleted Note 1, page 13; Updated the Typical Info. in Param. OS18, Table 14-3; Added sub-section 10.3.2 (Auto-Baud Overflow, page 100) to Chapter 10; Added SOIC, TSSOP, QFN Package Land Patterns.
This device has been designed to perform to the parameters of its data sheet. It has been tested to an electrical specification designed to determine its conformance with these parameters. Due to process differences in the manufacture of this device, this device may have different performance characteristics than its earlier version. These differences may cause this device to perform differently in your application than the earlier version of this device.
(c) 2009 Microchip Technology Inc.
DS41203E-page 193
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NOTES:
DS41203E-page 194
(c) 2009 Microchip Technology Inc.
PIC16F688
INDEX
A
A/D Specifications.................................................... 160, 161 Absolute Maximum Ratings .............................................. 143 AC Characteristics Industrial and Extended ............................................ 153 Load Conditions ........................................................ 152 ADC .................................................................................... 65 Acquisition Requirements ........................................... 73 Associated registers.................................................... 75 Block Diagram............................................................. 65 Calculating Acquisition Time....................................... 73 Channel Selection....................................................... 66 Configuration............................................................... 66 Configuring Interrupt ................................................... 69 Conversion Clock........................................................ 66 Conversion Procedure ................................................ 69 Internal Sampling Switch (RSS) Impedance................ 73 Interrupts..................................................................... 68 Operation .................................................................... 69 Operation During Sleep .............................................. 69 Port Configuration ....................................................... 66 Reference Voltage (VREF)........................................... 66 Result Formatting........................................................ 68 Source Impedance...................................................... 73 Starting an A/D Conversion ........................................ 68 ADCON0 Register............................................................... 71 ADCON1 Register............................................................... 71 ADRESH Register (ADFM = 0) ........................................... 72 ADRESH Register (ADFM = 1) ........................................... 72 ADRESL Register (ADFM = 0)............................................ 72 ADRESL Register (ADFM = 1)............................................ 72 Analog Front-end (AFE) Power-On Reset ....................................................... 113 Analog Input Connection Considerations............................ 55 Analog-to-Digital Converter. See ADC ANSEL Register .................................................................. 34 Assembler MPASM Assembler................................................... 140 RA5 Pin ...................................................................... 40 RC0 and RC1 Pins ..................................................... 43 RC2 and RC3 Pins ..................................................... 43 RC4 Pin ...................................................................... 44 RC5 Pin ...................................................................... 44 Resonator Operation .................................................. 24 Timer1 ........................................................................ 48 TMR0/WDT Prescaler ................................................ 45 Watchdog Timer (WDT)............................................ 123 Break Character (12-bit) Transmit and Receive ............... 101 Brown-out Reset (BOR).................................................... 114 Associated ................................................................ 115 Specifications ........................................................... 157 Timing and Characteristics ....................................... 156
C
C Compilers MPLAB C18.............................................................. 140 MPLAB C30.............................................................. 140 Clock Accuracy with Asynchronous Operation ................... 92 Clock Sources External Modes........................................................... 23 EC ...................................................................... 23 HS ...................................................................... 24 LP ....................................................................... 24 OST .................................................................... 23 RC ...................................................................... 25 XT ....................................................................... 24 Internal Modes............................................................ 25 Frequency Selection........................................... 27 HFINTOSC ......................................................... 25 INTOSC .............................................................. 25 INTOSCIO .......................................................... 25 LFINTOSC.......................................................... 27 Clock Switching .................................................................. 29 CMCON0 Register.............................................................. 61 CMCON1 Register.............................................................. 62 Code Examples A/D Conversion .......................................................... 70 Assigning Prescaler to Timer0.................................... 46 Assigning Prescaler to WDT....................................... 46 Indirect Addressing..................................................... 20 Initializing PORTA ...................................................... 33 Initializing PORTC ...................................................... 42 Saving Status and W Registers in RAM ................... 122 Ultra Low-Power Wake-up Initialization...................... 36 Code Protection ................................................................ 126 Comparator......................................................................... 53 C2OUT as T1 Gate..................................................... 62 Configurations ............................................................ 56 Interrupts .................................................................... 59 Operation.............................................................. 53, 58 Operation During Sleep .............................................. 60 Response Time .......................................................... 59 Synchronizing COUT w/Timer1 .................................. 62 Comparator Module Associated registers ................................................... 64 Comparator Voltage Reference (CVREF)............................ 63 Effects of a Reset ....................................................... 60 Response Time .......................................................... 59 Specifications ........................................................... 159 Comparators C2OUT as T1 Gate..................................................... 49 Effects of a Reset ....................................................... 60
B
BAUDCTL Register ............................................................. 94 Block Diagrams ADC ............................................................................ 65 ADC Transfer Function ............................................... 74 Analog Input Model ............................................... 55, 74 Clock Source............................................................... 21 Comparator 1 .............................................................. 54 Comparator 2 .............................................................. 54 Comparator Modes ..................................................... 57 Crystal Operation ........................................................ 24 EUSART Receive ....................................................... 84 EUSART Transmit ...................................................... 83 External RC Mode....................................................... 25 Fail-Safe Clock Monitor (FSCM) ................................. 31 In-Circuit Serial Programming Connections.............. 127 Interrupt Logic ........................................................... 120 MCLR Circuit............................................................. 113 On-Chip Reset Circuit ............................................... 112 PIC16F688.................................................................... 5 RA1 Pins ..................................................................... 38 RA2 Pin....................................................................... 38 RA3 Pin....................................................................... 39 RA4 Pin....................................................................... 39
(c) 2009 Microchip Technology Inc.
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Specifications ............................................................ 159 CONFIG Register.............................................................. 111 Configuration Bits.............................................................. 110 CPU Features ................................................................... 109 Customer Change Notification Service ............................. 199 Customer Notification Service........................................... 199 Customer Support ............................................................. 199 Transmission .................................................... 107
F
Fail-Safe Clock Monitor ...................................................... 31 Fail-Safe Condition Clearing....................................... 31 Fail-Safe Detection ..................................................... 31 Fail-Safe Operation..................................................... 31 Reset or Wake-up from Sleep .................................... 31 Firmware Instructions ....................................................... 129 Flash Program Memory ...................................................... 77 Fuses. See Configuration Bits
D
Data EEPROM Memory ...................................................... 77 Associated Registers .................................................. 82 Reading....................................................................... 80 Writing ......................................................................... 80 Data Memory......................................................................... 7 DC and AC Characteristics Graphs and Tables ................................................... 163 DC Characteristics Extended and Industrial ............................................ 149 Industrial and Extended ............................................ 145 Development Support ....................................................... 139 Device Overview ................................................................... 5
G
General Purpose Register File ............................................. 7
I
I/O Ports.............................................................................. 33 ID Locations...................................................................... 126 In-Circuit Debugger........................................................... 127 In-Circuit Serial Programming (ICSP)............................... 127 Indirect Addressing, INDF and FSR Registers ................... 20 Instruction Format............................................................. 129 Instruction Set................................................................... 129 ADDLW..................................................................... 131 ADDWF..................................................................... 131 ANDLW..................................................................... 131 ANDWF..................................................................... 131 MOVF ....................................................................... 134 BCF .......................................................................... 131 BSF........................................................................... 131 BTFSC ...................................................................... 131 BTFSS ...................................................................... 132 CALL......................................................................... 132 CLRF ........................................................................ 132 CLRW ....................................................................... 132 CLRWDT .................................................................. 132 COMF ....................................................................... 132 DECF ........................................................................ 132 DECFSZ ................................................................... 133 GOTO ....................................................................... 133 INCF ......................................................................... 133 INCFSZ..................................................................... 133 IORLW ...................................................................... 133 IORWF...................................................................... 133 MOVLW .................................................................... 134 MOVWF .................................................................... 134 NOP .......................................................................... 134 RETFIE ..................................................................... 135 RETLW ..................................................................... 135 RETURN................................................................... 135 RLF ........................................................................... 136 RRF .......................................................................... 136 SLEEP ...................................................................... 136 SUBLW ..................................................................... 136 SUBWF..................................................................... 137 SWAPF ..................................................................... 137 XORLW .................................................................... 137 XORWF .................................................................... 137 Summary Table ........................................................ 130 INTCON Register................................................................ 15 Internal Oscillator Block INTOSC Specifications ........................................... 154, 155 Internal Sampling Switch (RSS) Impedance........................ 73 Internet Address ............................................................... 199 Interrupts........................................................................... 119
E
EEADR Register ................................................................. 78 EEADR Registers................................................................ 77 EEADRH Registers ............................................................. 77 EECON1 Register ......................................................... 77, 79 EECON2 Register ............................................................... 77 EEDAT Register.................................................................. 78 EEDATH Register ............................................................... 78 Electrical Specifications .................................................... 143 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART)................................. 83 Errata .................................................................................... 4 EUSART.............................................................................. 83 Associated Registers Baud Rate Generator.......................................... 95 Asynchronous Mode ................................................... 85 12-bit Break Transmit and Receive................... 101 Associated Registers Receive ....................................................... 91 Transmit ...................................................... 87 Auto-Baud Overflow.......................................... 100 Auto-Wake-up on Break.................................... 100 Baud Rate Generator (BRG)............................... 95 Clock Accuracy ................................................... 92 Receiver.............................................................. 88 Setting up 9-bit Mode with Address Detect......... 90 Transmitter.......................................................... 85 Baud Rate Generator (BRG) Auto Baud Rate Detect ....................................... 99 Baud Rate Error, Calculating .............................. 95 Baud Rates, Asynchronous Modes..................... 96 Formulas ............................................................. 95 High Baud Rate Select (BRGH Bit)..................... 95 Synchronous Master Mode ............................... 103, 107 Associated Registers Receive ..................................................... 106 Transmit .................................................... 104 Reception.......................................................... 105 Transmission..................................................... 103 Synchronous Slave Mode Associated Registers Receive ..................................................... 108 Transmit .................................................... 107 Reception.......................................................... 108
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PIC16F688
ADC ............................................................................ 69 Associated Registers ................................................ 121 Comparator ................................................................. 59 Context Saving.......................................................... 122 Interrupt-on-Change.................................................... 34 PORTA Interrupt-on-Change .................................... 120 RA2/INT .................................................................... 120 Timer0....................................................................... 120 TMR1 .......................................................................... 50 INTOSC Specifications ............................................. 154, 155 IOCA Register ..................................................................... 35 ANSEL Register ................................................. 34 Interrupt-on-Change ........................................... 34 Ultra Low-Power Wake-up............................ 34, 36 Weak Pull-up ...................................................... 34 Associated registers ................................................... 41 Pin Descriptions and Diagrams .................................. 37 RA0............................................................................. 37 RA1............................................................................. 38 RA2............................................................................. 38 RA4............................................................................. 39 RA5............................................................................. 40 Specifications ........................................................... 155 PORTA Register ................................................................. 33 PORTC ............................................................................... 42 Associated registers ................................................... 44 PA/PB/PC/PD.See Enhanced Universal Asynchronous Receiver Transmitter (EUSART) ........................ 42 Specifications ........................................................... 155 PORTC Register................................................................. 42 Power-Down Mode (Sleep)............................................... 125 Power-up Timer (PWRT) .................................................. 113 Specifications ........................................................... 157 Precision Internal Oscillator Parameters .......................... 155 Prescaler Shared WDT/Timer0................................................... 46 Switching Prescaler Assignment ................................ 46 Program Memory .................................................................. 7 Map and Stack.............................................................. 7 Programming, Device Instructions.................................... 129
L
Load Conditions ................................................................ 152
M
MCLR ................................................................................ 113 Internal ...................................................................... 113 .............................................................................................. 7 Data .............................................................................. 7 Program ........................................................................ 7 .......................................... 199, 193, 140, 141, 139, 141, 140
O
OPCODE Field Descriptions ............................................. 129 OPTION Register ................................................................ 14 OPTION_REG Register ...................................................... 47 OSCCON Register ........................................................ 10, 22 Oscillator Associated registers.............................................. 32, 52 Oscillator Module ................................................................ 21 EC ............................................................................... 21 HFINTOSC.................................................................. 21 HS ............................................................................... 21 INTOSC ...................................................................... 21 INTOSCIO................................................................... 21 LFINTOSC .................................................................. 21 LP................................................................................ 21 RC............................................................................... 21 RCIO ........................................................................... 21 XT ............................................................................... 21 Oscillator Parameters ....................................................... 154 Oscillator Specifications .................................................... 153 Oscillator Start-up Timer (OST) Specifications............................................................ 157 Oscillator Switching Fail-Safe Clock Monitor............................................... 31 Two-Speed Clock Start-up.......................................... 29 OSCTUNE Register ............................................................ 26
R
RA3/MCLR/VPP .................................................................. 39 RCREG............................................................................... 90 RCSTA Register ................................................................. 93 Reader Response............................................................. 200 Read-Modify-Write Operations ......................................... 129 Register RCREG Register ........................................................ 99 Registers ADCON0 (ADC Control 0) .......................................... 71 ADCON1 (ADC Control 1) .......................................... 71 ADRESH (ADC Result High) with ADFM = 0) ............ 72 ADRESH (ADC Result High) with ADFM = 1) ............ 72 ADRESL (ADC Result Low) with ADFM = 0).............. 72 ADRESL (ADC Result Low) with ADFM = 1).............. 72 ANSEL (Analog Select) .............................................. 34 BAUDCTL (Baud Rate Control).................................. 94 CMCON0 (Comparator Control 0) .............................. 61 CMCON1 (Comparator Control 1) .............................. 62 CONFIG (Configuration Word) ................................. 111 EEADR (EEPROM Address) ...................................... 78 EECON1 (EEPROM Control 1) .................................. 79 EEDAT (EEPROM Data) ............................................ 78 EEDATH (EEPROM Data High Byte) ......................... 78 INTCON (Interrupt Control) ........................................ 15 IOCA (Interrupt-on-Change PORTA).......................... 35 OPTION_REG (OPTION)........................................... 14 OPTION_REG (Option) .............................................. 47 OSCCON (Oscillator Control)..................................... 22 OSCTUNE (Oscillator Tuning).................................... 26 PCON (Power Control Register)................................. 18 PCON (Power Control) ............................................. 115 PIE1 (Peripheral Interrupt Enable 1) .......................... 16 PIR1 (Peripheral Interrupt Register 1) ........................ 17 PORTA ....................................................................... 33 PORTC ....................................................................... 42
P
Packaging ......................................................................... 185 Marking ..................................................................... 185 PDIP Details.............................................................. 186 PCL and PCLATH ............................................................... 19 Computed GOTO........................................................ 19 Stack ........................................................................... 19 PCON Register ........................................................... 18, 115 PICSTART Plus Development Programmer ..................... 142 PIE1 Register ...................................................................... 16 Pin Diagram ...................................................................... 2, 3 Pinout Description PIC16F688.................................................................... 6 PIR1 Register...................................................................... 17 PORTA................................................................................ 33 Additional Pin Functions ............................................. 34
(c) 2009 Microchip Technology Inc.
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PIC16F688
RCSTA (Receive Status and Control)......................... 93 Reset Values............................................................. 117 Reset Values (Special Registers) ............................. 118 Special Function Register Map ..................................... 8 Special Register Summary ........................................... 9 STATUS ...................................................................... 13 T1CON ........................................................................ 51 TRISA (Tri-State PORTA) ........................................... 33 TRISC (Tri-State PORTC) .......................................... 42 TXSTA (Transmit Status and Control) ........................ 92 VRCON (Voltage Reference Control) ......................... 63 WDTCON (Watchdog Timer Control)........................ 124 WPUA (Weak Pull-Up PORTA) .................................. 35 Reset................................................................................. 112 Revision History ................................................................ 193 Comparator Output ..................................................... 53 Fail-Safe Clock Monitor (FSCM)................................. 32 INT Pin Interrupt ....................................................... 121 Internal Oscillator Switch Timing ................................ 28 Reset, WDT, OST and Power-up Timer ................... 156 Send Break Character Sequence ............................. 102 Synchronous Reception (Master Mode, SREN) ....... 106 Synchronous Transmission ...................................... 104 Synchronous Transmission (Through TXEN) ........... 104 Time-out Sequence .................................................. 116 Case 3 .............................................................. 116 Timer0 and Timer1 External Clock ........................... 158 Timer1 Incrementing Edge ......................................... 50 Two Speed Start-up.................................................... 30 Wake-up from Interrupt............................................. 126 Timing Parameter Symbology .......................................... 152 TRISA ................................................................................. 33 TRISA Register................................................................... 33 TRISC Register................................................................... 42 Two-Speed Clock Start-up Mode........................................ 29 TXREG ............................................................................... 85 TXSTA Register.................................................................. 92 BRGH Bit .................................................................... 95
S
Software Simulator (MPLAB SIM)..................................... 140 SPBRG................................................................................ 95 SPBRGH ............................................................................. 95 Special Function Registers ................................................... 7 STATUS Register................................................................ 13
T
T1CON Register.................................................................. 51 Thermal Considerations .................................................... 151 Time-out Sequence........................................................... 115 Timer0 ................................................................................. 45 Associated Registers .................................................. 47 External Clock ............................................................. 46 Interrupt....................................................................... 47 Operation .............................................................. 45, 48 Specifications ............................................................ 158 T0CKI .......................................................................... 46 Timer1 ................................................................................. 48 Associated registers.................................................... 52 Asynchronous Counter Mode ..................................... 49 Reading and Writing ........................................... 49 Interrupt....................................................................... 50 Modes of Operation .................................................... 48 Operation During Sleep .............................................. 50 Oscillator ..................................................................... 49 Prescaler ..................................................................... 49 Specifications ............................................................ 158 Timer1 Gate Inverting Gate ..................................................... 49 Selecting Source........................................... 49, 62 Synchronizing COUT w/Timer1 .......................... 62 TMR1H Register ......................................................... 48 TMR1L Register .......................................................... 48 Timers Timer1 T1CON................................................................ 51 Timing Diagrams A/D Conversion ......................................................... 162 A/D Conversion (Sleep Mode) .................................. 162 Asynchronous Reception ............................................ 90 Asynchronous Transmission ....................................... 86 Asynchronous Transmission (Back to Back) .............. 86 Auto Wake-up Bit (WUE) During Normal Operation . 100 Auto Wake-up Bit (WUE) During Sleep .................... 101 Automatic Baud Rate Calculator ................................. 99 Brown-out Reset (BOR) ............................................ 156 Brown-out Reset Situations ...................................... 114 CLKOUT and I/O....................................................... 155 Clock Timing ............................................................. 153
U
Ultra Low-Power Wake-up........................................ 6, 34, 36
V
Voltage Reference. See Comparator Voltage Reference (CVREF) Voltage References Associated registers ................................................... 64 VREF. SEE ADC Reference Voltage
W
Wake-up on Break ............................................................ 100 Wake-up Using Interrupts ................................................. 125 Watchdog Timer (WDT).................................................... 123 Associated Registers ................................................ 124 Clock Source ............................................................ 123 Modes ....................................................................... 123 Period ....................................................................... 123 Specifications ........................................................... 157 WDTCON Register ....................................................... 9, 124 WPUA Register................................................................... 35 WWW Address ................................................................. 199 WWW, On-Line Support ....................................................... 4
DS41203E-page 198
(c) 2009 Microchip Technology Inc.
PIC16F688
THE MICROCHIP WEB SITE
Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers. Accessible by using your favorite Internet browser, the web site contains the following information: * Product Support - Data sheets and errata, application notes and sample programs, design resources, user's guides and hardware support documents, latest software releases and archived software * General Technical Support - Frequently Asked Questions (FAQ), technical support requests, online discussion groups, Microchip consultant program member listing * Business of Microchip - Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives
CUSTOMER SUPPORT
Users of Microchip products can receive assistance through several channels: * * * * * Distributor or Representative Local Sales Office Field Application Engineer (FAE) Technical Support Development Systems Information Line
Customers should contact their distributor, representative or field application engineer (FAE) for support. Local sales offices are also available to help customers. A listing of sales offices and locations is included in the back of this document. Technical support is available through the web site at: http://support.microchip.com
CUSTOMER CHANGE NOTIFICATION SERVICE
Microchip's customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com, click on Customer Change Notification and follow the registration instructions.
(c) 2009 Microchip Technology Inc.
DS41203E-page 199
PIC16F688
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document. To: RE: Technical Publications Manager Reader Response Total Pages Sent ________
From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ Application (optional): Would you like a reply? Device: PIC16F688 Questions: 1. What are the best features of this document? Y N Literature Number: DS41203E FAX: (______) _________ - _________
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this document easy to follow? If not, why?
4. What additions to the document do you think would enhance the structure and subject?
5. What deletions from the document could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
DS41203E-page 200
(c) 2009 Microchip Technology Inc.
PIC16F688
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. Device X Temperature Range /XX Package XXX Pattern Examples:
a) b) Device PIC16F688, PIC16F688T(1) VDD range 2.0V to 5.5V PIC16F688-E/P 301 = Extended Temp., PDIP package, 20 MHz, QTP pattern #301 PIC16F688-I/SO = Industrial Temp., SOIC package, 20 MHz.
Temperature Range
I E
= -40C to +85C = -40C to +125C
(Industrial) (Extended)
Package
ML P SL ST
= Quad Flat No Leads (QFN) = Plastic DIP = 16-lead Small Outline (3.90 mm) = Thin Shrink Small Outline (4.4 mm) Note 1: T=In tape and reel TSSOP, SOIC and QFN packages only.
Pattern
QTP, SQTPSM or ROM Code; Special Requirements (blank otherwise)
(c) 2009 Microchip Technology Inc.
DS41203E-page 201
WORLDWIDE SALES AND SERVICE
AMERICAS
Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://support.microchip.com Web Address: www.microchip.com Atlanta Duluth, GA Tel: 678-957-9614 Fax: 678-957-1455 Boston Westborough, MA Tel: 774-760-0087 Fax: 774-760-0088 Chicago Itasca, IL Tel: 630-285-0071 Fax: 630-285-0075 Cleveland Independence, OH Tel: 216-447-0464 Fax: 216-447-0643 Dallas Addison, TX Tel: 972-818-7423 Fax: 972-818-2924 Detroit Farmington Hills, MI Tel: 248-538-2250 Fax: 248-538-2260 Kokomo Kokomo, IN Tel: 765-864-8360 Fax: 765-864-8387 Los Angeles Mission Viejo, CA Tel: 949-462-9523 Fax: 949-462-9608 Santa Clara Santa Clara, CA Tel: 408-961-6444 Fax: 408-961-6445 Toronto Mississauga, Ontario, Canada Tel: 905-673-0699 Fax: 905-673-6509
ASIA/PACIFIC
Asia Pacific Office Suites 3707-14, 37th Floor Tower 6, The Gateway Harbour City, Kowloon Hong Kong Tel: 852-2401-1200 Fax: 852-2401-3431 Australia - Sydney Tel: 61-2-9868-6733 Fax: 61-2-9868-6755 China - Beijing Tel: 86-10-8528-2100 Fax: 86-10-8528-2104 China - Chengdu Tel: 86-28-8665-5511 Fax: 86-28-8665-7889 China - Hong Kong SAR Tel: 852-2401-1200 Fax: 852-2401-3431 China - Nanjing Tel: 86-25-8473-2460 Fax: 86-25-8473-2470 China - Qingdao Tel: 86-532-8502-7355 Fax: 86-532-8502-7205 China - Shanghai Tel: 86-21-5407-5533 Fax: 86-21-5407-5066 China - Shenyang Tel: 86-24-2334-2829 Fax: 86-24-2334-2393 China - Shenzhen Tel: 86-755-8203-2660 Fax: 86-755-8203-1760 China - Wuhan Tel: 86-27-5980-5300 Fax: 86-27-5980-5118 China - Xiamen Tel: 86-592-2388138 Fax: 86-592-2388130 China - Xian Tel: 86-29-8833-7252 Fax: 86-29-8833-7256 China - Zhuhai Tel: 86-756-3210040 Fax: 86-756-3210049
ASIA/PACIFIC
India - Bangalore Tel: 91-80-3090-4444 Fax: 91-80-3090-4080 India - New Delhi Tel: 91-11-4160-8631 Fax: 91-11-4160-8632 India - Pune Tel: 91-20-2566-1512 Fax: 91-20-2566-1513 Japan - Yokohama Tel: 81-45-471- 6166 Fax: 81-45-471-6122 Korea - Daegu Tel: 82-53-744-4301 Fax: 82-53-744-4302 Korea - Seoul Tel: 82-2-554-7200 Fax: 82-2-558-5932 or 82-2-558-5934 Malaysia - Kuala Lumpur Tel: 60-3-6201-9857 Fax: 60-3-6201-9859 Malaysia - Penang Tel: 60-4-227-8870 Fax: 60-4-227-4068 Philippines - Manila Tel: 63-2-634-9065 Fax: 63-2-634-9069 Singapore Tel: 65-6334-8870 Fax: 65-6334-8850 Taiwan - Hsin Chu Tel: 886-3-6578-300 Fax: 886-3-6578-370 Taiwan - Kaohsiung Tel: 886-7-536-4818 Fax: 886-7-536-4803 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350
EUROPE
Austria - Wels Tel: 43-7242-2244-39 Fax: 43-7242-2244-393 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 France - Paris Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 Germany - Munich Tel: 49-89-627-144-0 Fax: 49-89-627-144-44 Italy - Milan Tel: 39-0331-742611 Fax: 39-0331-466781 Netherlands - Drunen Tel: 31-416-690399 Fax: 31-416-690340 Spain - Madrid Tel: 34-91-708-08-90 Fax: 34-91-708-08-91 UK - Wokingham Tel: 44-118-921-5869 Fax: 44-118-921-5820
03/26/09
DS41203E-page 202
(c) 2009 Microchip Technology Inc.

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