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ST
Sitronix
INTRODUCTION
ST7528
16 Gray Scale Dot Matrix LCD Controller/Driver
The ST7528 is a driver & controller LSI for 16-level gray scale graphic dot-matrix liquid crystal display systems. It contains 2 Mode (160X100,132X128) for Segment and Common driver circuits. This chip is connected directly to a microprocessor, accepts Serial Peripheral Interface (SPI), IIC or 8-bit parallel display data and stores in an on-chip display data RAM of 160 x 129 x 4 bits. It performs display data RAM read/write operation with no external operating clock to minimize power consumption. In addition, because it contains power supply circuits necessary to drive liquid crystal, it is possible to make a display system with the fewest components.
FEATURES
16-level (White Mode ~ Dark Mode) Gray Scale Display with PWM and FRC Methods
DDRAM data [ 4n : 4n+3 ] 4n 0 0 0 : : 1 1 1 4n + 1 0 0 0 : : 1 1 1 4n + 2 0 0 1 : : 0 1 1 4n+ 3 0 1 0 : : 1 0 1 Gray Scale White Mode Gray Level 1 Gray Level 2 : : Gray Level 13 Gray Level 14 Dark
(Mode0: Accessible column address, n = 0, 1, 2, ......, 129, 130, 131) (Mode1: Accessible column address, n = 0, 1, 2, ......, 157, 158, 159)
Driver Output Circuits
-Mode 0 : 132 segment outputs / 128+1 common outputs (16-level gray scale) -Mode 1: 160 segment outputs / 100+1 common outputs (16-level gray scale)
Applicable Display Ratios
- Various partial display - Partial window moving & data scrolling
On-chip Display Data RAM
- Capacity: 129 x 160 x 4 = 82,560 bits -16-Gray Level display dot is illuminated by 4 bit data control
Ver2.3
1/97
2007/1/3
ST7528
Microprocessor Interface
- 8-bit parallel bi-directional interface with 6800-series or 8080-series - 4-line serial interface (4-line-SIF) - 3-line serial interface (3-line-SIF) - IIC serial interface
On-chip Low Power Analog Circuit
- On-chip oscillator circuit - Voltage converter (x3, x4, x5 or x6) - Voltage regulator (temperature coefficient: -0.125%/C, or external input) - On-chip electronic contrast control function (64 steps X 8 ) - Voltage follower (LCD bias: 1/5 to 1/12)
Operating Voltage Range
- Supply voltage (VDD): 1.8 to 3.3V (VDD2): 2.4 to 3.3V - LCD driving voltage (VLCD = V0 - VSS): 3.5 to 15.0 V
Package Type
- Application for COG
ST7528
6800 , 8080 , 4-Line , 3-Line interface (without IIC interface) IIC interface
ST7528i
Note1: we would like to recommend to use the external VOUT when the panel is large than 1.8 inch Note2: we would like to recommend to set lower VOP than 12 voltage, when the panel size is large like 1.6 inch
Ver2.3
2/97
2007/1/3
ST7528
ST7528 Pad Arrangement (COG)
Chip Size: 12,575 um x 1,220 um Bump Pitch: PAD NO 1 ~ 229, 353 ~ 385: 55 um (COM/SEG), PAD NO 230 ~ 338: 75 um (I/O) ,PAD NO 339 ~ 352: 75 um (I/O) , PAD 338~339: 81um. Bump Size: PAD NO 1 ~ 196, 218 ~ 229, 353 ~ 364 : 35(x) um x96(y) um PAD NO 230 ~ 352 : 55(x)um x60(y) um Bump Height: 17 um (Typical) Chip Thickness: 635 um PAD NO 197 ~ 217, 365 ~ 385 : 96(x) um x35(y) um
Ver2.3
3/97
2007/1/3
ST7528
Pad Center Coordinates
Pad No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 Name for Mode0 Name for Mode1 (132seg x 128com) (160seg x 100com) COM30 COM29 COM28 COM27 COM26 COM25 COM24 COM23 COM22 COM21 COM20 COM19 COM18 COM17 COM16 COM15 COM14 COM13 COM12 COM11 COM10 COM9 COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1 COM0 COMS1 SEG0 COM16 COM15 COM14 COM13 COM12 COM11 COM10 COM9 COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1 COM0 COMS1 SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 X(um) 5095 5040 4985 4930 4875 4820 4765 4710 4655 4600 4545 4490 4435 4380 4325 4270 4215 4160 4105 4050 3995 3940 3885 3830 3775 3720 3665 3610 3555 3500 3445 3390 3335 Y(um) 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556
Ver2.3
4/97
2007/1/3
ST7528
Pad No. 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 Ver2.3 Name for Mode0 Name for Mode1 (132seg x 128com) (160seg x 100com) SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 X(um) 3280 3225 3170 3115 3060 3005 2950 2895 2840 2785 2730 2675 2620 2565 2510 2455 2400 2345 2290 2235 2180 2125 2070 2015 1960 1905 1850 1795 1740 1685 1630 1575 1520 1465 1410 5/97 Y(um) 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 2007/1/3
ST7528
Pad No. 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 Ver2.3 Name for Mode0 Name for Mode1 (132seg x 128com) (160seg x 100com) SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 SEG51 SEG52 SEG53 SEG54 SEG55 SEG56 SEG57 SEG58 SEG59 SEG60 SEG61 SEG62 SEG63 SEG64 SEG65 SEG66 SEG67 SEG68 SEG69 SEG70 SEG50 SEG51 SEG52 SEG53 SEG54 SEG55 SEG56 SEG57 SEG58 SEG59 SEG60 SEG61 SEG62 SEG63 SEG64 SEG65 SEG66 SEG67 SEG68 SEG69 SEG70 SEG71 SEG72 SEG73 SEG74 SEG75 SEG76 SEG77 SEG78 SEG79 SEG80 SEG81 SEG82 SEG83 SEG84 6/97 X(um) 1355 1300 1245 1190 1135 1080 1025 970 915 860 805 750 695 640 585 530 475 420 365 310 255 200 145 90 35 -19 -74 -129 -184 -239 -294 -349 -404 -459 -514 Y(um) 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 2007/1/3
ST7528
Pad No. 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 Ver2.3 Name for Mode0 Name for Mode1 (132seg x 128com) (160seg x 100com) SEG71 SEG72 SEG73 SEG74 SEG75 SEG76 SEG77 SEG78 SEG79 SEG80 SEG81 SEG82 SEG83 SEG84 SEG85 SEG86 SEG87 SEG88 SEG89 SEG90 SEG91 SEG92 SEG93 SEG94 SEG95 SEG96 SEG97 SEG98 SEG99 SEG100 SEG101 SEG102 SEG103 SEG104 SEG105 SEG85 SEG86 SEG87 SEG88 SEG89 SEG90 SEG91 SEG92 SEG93 SEG94 SEG95 SEG96 SEG97 SEG98 SEG99 SEG100 SEG101 SEG102 SEG103 SEG104 SEG105 SEG106 SEG107 SEG108 SEG109 SEG110 SEG111 SEG112 SEG113 SEG114 SEG115 SEG116 SEG117 SEG118 SEG119 X(um) -569 -624 -679 -734 -789 -844 -899 -954 -1009 -1064 -1119 -1174 -1229 -1284 -1339 -1394 -1449 -1504 -1559 -1614 -1669 -1724 -1779 -1834 -1889 -1944 -1999 -2054 -2109 -2164 -2219 -2274 -2329 -2384 -2439 7/97 Y(um) 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 2007/1/3
ST7528
Pad No. 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 Ver2.3 Name for Mode0 Name for Mode1 (132seg x 128com) (160seg x 100com) SEG106 SEG107 SEG108 SEG109 SEG110 SEG111 SEG112 SEG113 SEG114 SEG115 SEG116 SEG117 SEG118 SEG119 SEG120 SEG121 SEG122 SEG123 SEG124 SEG125 SEG126 SEG127 SEG128 SEG129 SEG130 SEG131 COM64 COM65 COM66 COM67 COM68 COM69 COM70 COM71 COM72 SEG120 SEG121 SEG122 SEG123 SEG124 SEG125 SEG126 SEG127 SEG128 SEG129 SEG130 SEG131 SEG132 SEG133 SEG134 SEG135 SEG136 SEG137 SEG138 SEG139 SEG140 SEG141 SEG142 SEG143 SEG144 SEG145 SEG146 SEG147 SEG148 SEG149 SEG150 SEG151 SEG152 SEG153 SEG154 X(um) -2494 -2549 -2604 -2659 -2714 -2769 -2824 -2879 -2934 -2989 -3044 -3099 -3154 -3209 -3264 -3319 -3374 -3429 -3484 -3539 -3594 -3649 -3704 -3759 -3814 -3869 -3924 -3979 -4034 -4089 -4144 -4199 -4254 -4309 -4364 8/97 Y(um) 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 2007/1/3
ST7528
Pad No. 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 Ver2.3 Name for Mode0 Name for Mode1 (132seg x 128com) (160seg x 100com) COM73 COM74 COM75 COM76 COM77 COM78 COM79 COM80 COM81 COM82 COM83 COM84 COM85 COM86 COM87 COM88 COM89 COM90 COM91 COM92 COM93 COM94 COM95 COM96 COM97 COM98 COM99 COM100 COM101 COM102 COM103 COM104 COM105 COM106 COM107 SEG155 SEG156 SEG157 SEG158 SEG159 COM50 COM51 COM52 COM53 COM54 COM55 COM56 COM57 COM58 COM59 COM60 COM61 COM62 COM63 COM64 COM65 COM66 COM67 COM68 COM69 COM70 COM71 COM72 COM73 COM74 COM75 COM76 COM77 COM78 COM79 X(um) -4419 -4474 -4529 -4584 -4639 -4694 -4749 -4804 -4859 -4914 -4969 -5024 -5079 -5134 -5189 -5244 -5299 -5354 -5409 -5464 -5519 -5574 -5629 -6233 -6233 -6233 -6233 -6233 -6233 -6233 -6233 -6233 -6233 -6233 -6233 9/97 Y(um) 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 550 495 440 385 330 275 220 165 110 55 0 -55 2007/1/3
ST7528
Pad No. 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 Ver2.3 Name for Mode0 Name for Mode1 (132seg x 128com) (160seg x 100com) COM108 COM109 COM110 COM111 COM112 COM113 COM114 COM115 COM116 COM117 COM118 COM119 COM120 COM121 COM122 COM123 COM124 COM125 COM126 COM127 COMS2 T9 VDD PS0 PS1 PS2 VSS CSB CSB RST RST A0 A0 RW_WR RW_WR COM80 COM81 COM82 COM83 COM84 COM85 COM86 COM87 COM88 COM89 COM90 COM91 COM92 COM93 COM94 COM95 COM96 COM97 COM98 COM99 COMS2 T9 VDD PS0 PS1 PS2 VSS CSB CSB RST RST A0 A0 RW_WR RW_WR X(um) -6233 -6233 -6233 -6233 -6233 -6233 -6233 -6233 -6233 -5417 -5362 -5307 -5252 -5197 -5142 -5087 -5032 -4977 -4922 -4867 -4812 -4728 -4653 -4578 -4503 -4428 -4353 -4278 -4203 -4128 -4053 -3978 -3903 -3828 -3753 10/97 Y(um) -110 -165 -220 -275 -330 -385 -440 -495 -550 -556 -556 -556 -556 -556 -556 -556 -556 -556 -556 -556 -556 -574 -574 -574 -574 -574 -574 -574 -574 -574 -574 -574 -574 -574 -574 2007/1/3
ST7528
Pad No. 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 Ver2.3 Name for Mode0 Name for Mode1 (132seg x 128com) (160seg x 100com) E_RD E_RD D0 D0 D1 D1 D2 D2 D3 D3 D4 D4 D5 D5 D6 D6 D7 D7 VDD VDD VDD VDD VDD VDD VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 E_RD E_RD D0 D0 D1 D1 D2 D2 D3 D3 D4 D4 D5 D5 D6 D6 D7 D7 VDD VDD VDD VDD VDD VDD VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 X(um) -3678 -3603 -3528 -3453 -3378 -3303 -3228 -3153 -3078 -3003 -2928 -2853 -2778 -2703 -2628 -2553 -2478 -2403 -2328 -2253 -2178 -2103 -2028 -1953 -1878 -1803 -1728 -1653 -1578 -1503 -1428 -1353 -1278 -1203 -1128 11/97 Y(um) -574 -574 -574 -574 -574 -574 -574 -574 -574 -574 -574 -574 -574 -574 -574 -574 -574 -574 -574 -574 -574 -574 -574 -574 -574 -574 -574 -574 -574 -574 -574 -574 -574 -574 -574 2007/1/3
ST7528
Pad No. 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 Ver2.3 Name for Mode0 Name for Mode1 (132seg x 128com) (160seg x 100com) VDD2 VDD2 VDD2 VDD2 VDD2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS VSS VSS VSS VSS VSS MODE TA MF2 MF1 MF0 DS0 DS1 VDD VDD2 VDD2 VDD2 VDD2 VDD2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS VSS VSS VSS VSS VSS MODE TA MF2 MF1 MF0 DS0 DS1 VDD X(um) -1053 -978 -903 -828 -753 -678 -603 -528 -453 -378 -303 -228 -153 -78 -3 71 146 221 296 371 446 521 596 671 746 821 896 971 1046 1121 1196 1271 1346 1421 1496 12/97 Y(um) -574 -574 -574 -574 -574 -574 -574 -574 -574 -574 -574 -574 -574 -574 -574 -574 -574 -574 -574 -574 -574 -574 -574 -574 -574 -574 -574 -574 -574 -574 -574 -574 -574 -574 -574 2007/1/3
ST7528
Pad No. 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 Ver2.3 Name for Mode0 Name for Mode1 (132seg x 128com) (160seg x 100com) VOUT_OUT VOUT_OUT VOUT_OUT VOUT_OUT VOUT_OUT VOUT_OUT VOUT_IN VOUT_IN VOUT_IN VOUT_IN VOUT_IN VOUT_IN T[8] T[7] T[6] T[5] T[4] T[3] T[2] T[1] T[0] VDD REF VSS VEXT VDD INTRS VSS OSC1 OSC1 VDD VR VR V4 V3 VOUT_OUT VOUT_OUT VOUT_OUT VOUT_OUT VOUT_OUT VOUT_OUT VOUT_IN VOUT_IN VOUT_IN VOUT_IN VOUT_IN VOUT_IN T[8] T[7] T[6] T[5] T[4] T[3] T[2] T[1] T[0] VDD REF VSS VEXT VDD INTRS VSS OSC1 OSC1 VDD VR VR V4 V3 X(um) 1571 1646 1721 1796 1871 1946 2021 2096 2171 2246 2321 2396 2471 2546 2621 2696 2771 2846 2921 2996 3071 3146 3221 3296 3371 3452 3527 3602 3677 3752 3827 3902 3977 4052 4127 13/97 Y(um) -574 -574 -574 -574 -574 -574 -574 -574 -574 -574 -574 -574 -574 -574 -574 -574 -574 -574 -574 -574 -574 -574 -574 -574 -574 -574 -574 -574 -574 -574 -574 -574 -574 -574 -574 2007/1/3
ST7528
Pad No. 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 Name for Mode0 V2 V1 V0 V0 COM63 COM62 COM61 COM60 COM59 COM58 COM57 COM56 COM55 COM54 COM53 COM52 COM51 COM50 COM49 COM48 COM47 COM46 COM45 COM44 COM43 COM42 COM41 COM40 COM39 COM38 COM37 COM36 COM35 COM34 COM33 COM32 COM31 Name for Mode1 V2 V1 V0 V0 COM49 COM48 COM47 COM46 COM45 COM44 COM43 COM42 COM41 COM40 COM39 COM38 COM37 COM36 COM35 COM34 COM33 COM32 COM31 COM30 COM29 COM28 COM27 COM26 COM25 COM24 COM23 COM22 COM21 COM20 COM19 COM18 COM17 (132seg x 128com) (160seg x 100com) X(um) 4202 4277 4352 4427 5339 5394 5449 5504 5559 5614 5669 5724 5779 5834 5889 5944 6233 6233 6233 6233 6233 6233 6233 6233 6233 6233 6233 6233 6233 6233 6233 6233 6233 6233 6233 6233 6233 Y(um) -574 -574 -574 -574 -556 -556 -556 -556 -556 -556 -556 -556 -556 -556 -556 -556 -550 -495 -440 -385 -330 -275 -220 -165 -110 -55 0 55 110 165 220 275 330 385 440 495 550
The tolerance is around +/- 1um. The number under floating point is truncated.
Ver2.3
14/97
2007/1/3
ST7528
BLOCK DIAGRAM
SEG0 TO SEG159
COM0 TO COM128
VDD
V0 V1 V2 V3 V4 SEGMENT DRIVERS COMMON DRIVERS
VSS
DATA LATCHES V/F Circuit
COMMON OUTPUT CONTROLLER CIRCUIT
V0 VR INTRS VEXT REF
FRC/PWM FUNCTION CIRCUIT RESET V/R Circuit
DISPLAY DATA RAM (DDRAM) [160X129X4]
OSCILLATOR TIMING GENERATOR DISPLAY ADDRESS COUNTER
OSC1
V/C Circuit ADDRESS COUNTER
VOUT_IN VOUT_OUT VDD2 VSS2
DATA REGISTER BUS HOLDER INSTRUCTION REGISTER INSTRUCTION DECODER
MPU INTERFACE(PARALLEL & SERIAL)
RW_WR
MF0 MF1 MF2
E_RD
MODE
A0 CSB /RST PS0 PS1 PS2
DS0 DS1
DB7(SCL)
DB6(SI)
DB0 DB1 DB2 DB3 DB4 DB5
Ver2.3
15/97
2007/1/3
ST7528
PIN DESCRIPTION
POWER SUPPLY
Power Supply Pin Description
Name VDD VSS VSS2 VDD2 VOUT_OUT VOUT_IN V0 V1 V2 V3 V4 I/O Supply Supply Supply Supply Supply Supply Description Power supply Ground Ground Power supply If the internal Vout voltage generator is used, the VOUT_IN & VOUT_OUT must be connected together. If an external supply is used, this pin must be left open. An external Vout supply voltage can be supplied using the VOUT_IN pad. In this case, VOUT_OUT has to be left open, and the internal voltage generator has to be programmed to zero. (SET register VC=0) LCD driver supply voltages The voltage determined by LCD pixel is impedance-converted by an operational amplifier for application. V1,V2,V3,V4 need the capacitor between with VSS Voltages should have the following relationship; V0 V1 V2 V3 V4 VSS When the internal power circuit is active, these voltages are generated as following table according to the state of LCD bias. LCD bias 1/N bias NOTE: N = 5 to 12 V1 (N-1) / N x V0 V2 (N-2) / N x V0 V3 (2/N) x V0 V4 (1/N) x V0
I/O
LCD DRIVER SUPPLY
LCD Driver Supply Pin Description
Name VR I/O I Description V0 voltage adjustment pin It is valid only when on-chip resistors are not used (INTRS = "L") When using internal resistors (INTRS = "H"), open this pin REF I Selects the external VREF voltage via the VEXT pin - REF = "H": using the internal VREF - REF = "L": using the external VREF VEXT I Externally input reference voltage (VREF) for the internal voltage regulator It is valid only when REF is "L" When using internal voltage regulator, this pin must be open OSC1 I External OSC input pin, when using internal clock oscillator, connect OSC1 to VDD.
Ver2.3
16/97
2007/1/3
ST7528
SYSTEM CONTROL
System Control Pin Description
Name INTRS I/O I Description Internal resistor select pin This pin selects the resistors for adjusting V0 voltage level - INTRS = "H": use the internal resistors. - INTRS = "L": use the external resistors VR pin and external resistive divider control V0 voltage T[0] ~ T[9] O Test pins Don' t use these pins. Please Open these pins. TA I Test pin TA must connect to VDD. Reserve MODE X I This pin must be OPEN MODE = 0 MODE = 1 MF[2:0] DS[1:0] I I : 129 com X 132 SEG : 101 com X 160 SEG
Manufacturer ID code for reference, suggestion setting [ MF2.MF1.MF0 = 0.0.0 ] Display size ID code for reference, suggestion setting [ DS1.DS0 = 1.0 or DS1.DS0 = 0.0]
Ver2.3
17/97
2007/1/3
ST7528
MICROPROCESSOR INTERFACE
Microprocessor Interface Pin Description
Name RST I/O I Description Reset input pin When RESETB is "L", initialization is executed. PS[2:0] I Parallel / Serial data input select input PS2 PS1 PS0 Interface mode L L L L H L H L H L H H L L L Parallel 80 Parallel 68 3Line Serial 4Line Serial IIC Serial Data / Command A0 A0 A0 DB0 to DB7 DB0 to DB7 SID (DB7) SID (DB7) SDA RD / WR E / RW Write only Write only Read/Write SCLK (DB6) SCLK (DB6) SCL Data Read/Write Serial clock
*NOTE: In 4-Line, 3-Line and IIC serial mode, it is impossible to read data from the on-chip RAM. In 3-Line or 4-Line interface: DB0 to DB5, E_RD and RW_WR must be fixed to "H" or "L". In IIC and 3-Line interface: A0 must be fixed to "H" or "L" Microprocessor interface select input pin - PS[2:0]=001: 8080-series parallel MPU interface - PS[2:0]=011: 68000-series parallel MPU interface - PS[2:0]=000: 3-Line-SPI MPU interface - PS[2:0]=010: 4-Line-SPI MPU interface - PS[2:0]=100: IIC-SPI MPU interface CSB I Chip select input pins Data/instruction I/O is enabled only when CSB is "L". When chip select is non-active, DB0 to DB7 may be high impedance. A0 I Register select input pin - A0 = "H": DB0 to DB7 are display data - A0 = "L": DB0 to DB7 are control data RW_WR I Read / Write execution control pin PS1 H MPU type 6800-series RW_WR RW Description Read / Write control input pin RW = "H" : read RW = "L" : write L 8080-series /WR Write enable clock input pin The data on DB0 to DB7 are latched at the rising edge of the /WR signal.
Ver2.3
18/97
2007/1/3
ST7528
Microprocessor Interface Pin Description (Continued)
Name I/O Description
E_RD
I
Read / Write execution control pin PS1 H MPU Type 6800-series E_RD E Description
Read / Write control input pin When RW = "H": E is "H", DB0 to DB7 are in an output status. When RW = "L": The data on DB0 to DB7 are latched at the falling edge of the E signal.
L
8080-series
/RD
Read enable clock input pin When /RD is "L", DB0 to DB7 are in an output status.
DB0 to DB7
I/O
8-bit bi-directional data bus that is connected to the standard 8-bit microprocessor data bus. When chip select is not active (CSB=H), DB0 to DB7 may be high impedance. When the 3-Line/4-Line serial interface selected (PS[2:0] = "000" or "010"); - DB0 to DB5: high impedance - DB6: serial input clock (SCLK) - DB7: serial input data (SID) When chip select is not active, D0 to D7 is high impedance. When the IIC serial interface selected (PS[2:0] = "100"); D7: serial clock input (SCL) D6 , D5 , D4: serial input data (SDA_IN) D3, D2: (SDA_OUT) serial data acknowledge for the IIC interface. By connecting SDA_OUT to SDA_IN externally, the SDA line becomes fully IIC interface compatible. Having the acknowledge output separated from the serial data line is advantageous in chip on glass (COG) applications. In COG application where the track resistance from the SDA_OUT pad to the system SDA line can be significant, a potential divider is generated by the bus pull-up resistor and the ITO track resistance. It is possible during the acknowledge cycle the ST7528 will not be able to create a valid logic 0 level. By splitting the SDA_IN input from the SDA_OUT output the device could be used in a mode that ignores the acknowledge bit. In COG applications where the acknowledge cycle is required, it is necessary to minimize the track resistance from the SDA_OUT pad to the system SDA line to guarantee a valid low level. D6, D5, ....D2 must be connected together (SDA) D1, D0: Is slave address (SA) bit1, 0, must connect to Vdd or Vss. When chip select is not active, D0 to D7 is high impedance.
Ver2.3
19/97
2007/1/3
ST7528
LCD DRIVER OUTPUTS
LCD Driver Output Pin Description
Name I/O Description
SEG0 to SEG159
O
LCD segment driver outputs The display data and the M signal control the output voltage of segment driver. Display data H H L L Power save mode M (Internal) H L H L Segment driver output voltage Normal display V0 VSS V2 V3 VSS Reverse display V2 V3 V0 VSS VSS
COM0 to COM127
O
LCD common driver outputs The internal scanning data and M signal control the output voltage of common driver. Scan data H H L L Power save mode M (Internal) H L H L Common driver output voltage VSS V0 V1 V4 VSS
COMS (COMS1)
O
Common output for the icons The output signals of two pins are same. When not used, these pins should be left open.
ST7528 I/O PIN ITO Resister Limitation PIN Name PS2,PS1,PS0,REF,OCS1,INTRS,Mode, TA T0...9 , VR(No used) , VEXT(No used) Vdd, Vdd2, Vss, Vss2, VOUT_IN , VOUT_OUT, VR(used) , VEXT(used) CSB , E , R/W , A0 , D0 ...D7 V1 , V2 , V3 , V4 RST ITO Resister No Limitation Floating <100 <500 <1K <500 <10K
In IIC interface: SDA , SCL ITO resister recommend to less than 100 ohm
Ver2.3
20/97
2007/1/3
ST7528
FUNCTIONAL DESCRIPTION
MICROPROCESSOR INTERFACE
Chip Select Input
There is CSB pin for chip selection. The ST7528 can interface with an MPU when CSB is "L". When these pins are set to any other combination, A0, E_RD, and RW_WR inputs are disabled and DB0 to DB7 are to be high impedance. And, in case of serial interface, the internal shift register and the counter are reset.
Parallel / Serial Interface
ST7528 has five types of interface with an MPU, which are three serial and two parallel interfaces. This parallel or serial interface is determined by PS pin as shown in Table 1.
Table 1 Parallel / Serial Interface Mode
Type Parallel PS2 L L L Serial L H PS1 H L L H L PS0 H L L L CSB CSB CSB CSB CSB Interface mode 6800-series MPU mode 8080-series MPU mode 3-Line SPI mode 4-Line SPI mode IIC SPI mode
Parallel Interface (PS0 = "H")
The 8-bit bi-directional data bus is used in parallel interface and the type of MPU is selected by PS1 as shown in Table 2. The type of data transfer is determined by signals at A0, E_RD and RW_WR as shown in Table 3.
Table 2 Microprocessor Selection for Parallel Interface
PS1 H L CSB CSB CSB A0 A0 A0 E_RD E /RD RW_WR RW /WR DB0 to DB7 DB0 to DB7 DB0 to DB7 MPU bus 6800-series 8080-series
Table 3 Parallel Data Transfer
Common 6800-series 8080-series Description E_RD (E) H H H H RW_WR (RW) H L H L E_RD (/RD) L H L H RW_WR (/WR) H L H L Display data read out Display data write Register status read Writes to internal register (instruction)
A0 H H L L
NOTE: When E_RD pin is always pulled high for 6800-series interface, it can be used CSB for enable signal. In this case, interface data is latched at the rising edge of CSB and the type of data transfer is determined by signals at A0, RW_WR as in case of 6800-series mode.
Ver2.3
21/97
2007/1/3
ST7528
Serial Interface 3-Line / 4-Line (PS[2:0] = "000" or "010")
When the ST7528 is active (CSB="L"), serial data (DB7) and serial clock (DB6) inputs are enabled. And not active, the internal 8-bit shift register and the 3-bit counter are reset. The display data/command indication may be controlled either via software or the Register Select (A0) Pin, based on the setting of PS1. When the A0 pin is used (PS1 = "H"), data is display data when A0 is high, and command data when A0 is low. When A0 is not used (PS1 ="L"), the LCD Driver will receive command from MCU by default. If messages on the data pin are data rather than command, MCU should send Data Direction command (11101000) to control the data direction and then one more command to define the number of data bytes will be write. After these two continuous commands are sent, the following messages will be data rather than command. Serial data can be read on the rising edge of serial clock going into DB6 and processed as 8-bit parallel data on the eighth serial clock. And the DDRAM column address pointer will be increased by one automatically. The next bytes after the display data string is handled as command data. In 3-Line mode, default message from MCU is command, the 2 bytes command of Set Data Direction & Display Data Length must be set before display data send from MCU, after the display data is sent over, the next message is turned to be command. Serial mode 3-Line SPI mode 4-Line SPI mode IIC SPI mode PS0 L L L PS1 L H L PS2 L L H CSB CSB CSB CSB A0 No used Used No Used
If A0 is not used it must be fixed either "H" or "L"
4-Line SPI Mode (PS0 = "L", PS1 = "H" , PS2 = "L")
/CB SI SCL A0
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB7 DB6
Figure 1 4-line SPI Timing
Ver2.3
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2007/1/3
ST7528
3-Line SPI Mode (PS0 = "L", PS1 = "L",PS2= "L")
To write data to the DDRAM, send Data Direction Command in 3-Line SPI mode. Data is latched at the rising edge of SCLK. And the DDRAM column address pointer will be increased by one automatically.
(1) Set Page and Column Address. Set Page Address Set Column Address MSB Set Column Address LSB :1 :0 :0 0 0 0 1 0 0 1 1 0 P3 P2 P1 P0 0 Y7 Y6 Y5 Y4 Y3 Y2 Y1
(2) Set DDC (Data Direction Command) and No. of Data Bytes. Set Data Direction Command (For SPI mode Only): 11 Set No. of Data Bytes 1 0 1 0 0 0 : D7 D6 D5 D4 D3 D2 D1 D0
(3) This figure is example for 104 Data bytes to be transferred. Figure 2 3-pin SPI Timing (RS is not used)
This command is used in 3-Line SPI mode only. It will be two continuous commands, the first byte controls the data direction and informs the LCD driver the second byte will be number of data bytes will be write. After these two commands sending out, the following messages will be data. If data is stopped in transmitting, it is not valid data. New data will be transferred serially with most significant bit first. NOTE: In spite of transmission of data, if CSB is disabling, state terminates abnormally. Next state is initialized.
Ver2.3
23/97
2007/1/3
ST7528
IIC Interface (PS0 = "L", PS1 = "L", PS2= "H")
The IIC interface receives and executes the commands sent via the IIC Interface. It also receives RAM data and sends it to the RAM. The IIC Interface is for bi-directional, two-line communication between different ICs or modules. The two lines are a Serial Data line (SDA) and a Serial Clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor. Data transfer may be initiated only when the bus is not busy. BIT TRANSFER One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock pulse because changes in the data line at this time will be interpreted as a control signal. Bit transfer is illustrated in Figure 3. START AND STOP CONDITIONS Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line, while the clock is HIGH is defined as the START condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP condition (P). The START and STOP conditions are illustrated in Figure 4. SYSTEM CONFIGURATION The system configuration is illustrated in Figure 5. * Transmitter: the device, which sends the data to the bus. * Receiver: the device, which receives the data from the bus. * Master: the device, which initiates a transfer, generates clock signals and terminates a transfer. * Slave: the device addressed by a master. * Multi-Master: more than one master can attempt to control the bus at the same time without corrupting the message. * Arbitration: procedure to ensure that, if more than one master simultaneously tries to control the bus, only one is allowed to do so and the message is not corrupted. * Synchronization: procedure to synchronize the clock signals of two or more devices. ACKNOWLEDGE Each byte of eight bits is followed by an acknowledge bit. The acknowledge bit is a HIGH signal put on the bus by the transmitter during which time the master generates an extra acknowledge related clock pulse. A slave receiver which is addressed must generate an acknowledge after the reception of each byte. A master receiver must also generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges must pull-down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse (set-up and hold times must be taken into consideration). A master receiver must signal an end-of-data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event the transmitter must leave the data line HIGH to enable the master to generate a STOP condition. Acknowledgement on the IIC Interface is illustrated in Figure 5.
Ver2.3
24/97
2007/1/3
ST7528
SDA SCL
data line stable; data valid change of data allowed
Figure 3 Bit transfer
SDA SCL S
START condition
Figure 4 Definition of START and STOP conditions
P
STOP condition
DATA OUTPUT BY TRANSMITTER DATA OUTPUT BY RECEIVER SCL FROM MASTER 1 2
not acknowledge acknowledge 8 9 clock pulse for acknowledge ment
S
START condition
Figure 5 Acknowledgement on the 2-line Interface
Ver2.3
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2007/1/3
ST7528
IIC Interface protocol The ST7528 supports command, data write addressed slaves on the bus. Before any data is transmitted on the IIC Interface, the device, which should respond, is addressed first. Four 7-bit slave addresses (0111100, 0111101, 0111110 and 0111111) are reserved for the ST7528. The least significant bit of the slave address is set by connecting the input SA0 and SA1 to either logic 0 (VSS) or logic 1 (VDD). The IIC Interface protocol is illustrated in Figure 6.
Note: ST7528 IIC interface can not use with other slaver IIC device
The sequence is initiated with a START condition (S) from the IIC Interface master, which is followed by the slave address. All slaves with the corresponding address acknowledge in parallel, all the others will ignore the IIC Interface transfer. After acknowledgement, one or more command words follow which define the status of the addressed slaves. A command word consists of a control byte, which defines Co and A0, plus a data byte. The last control byte is tagged with a cleared most significant bit (i.e. the continuation bit Co). After a control byte with a cleared Co bit, only data bytes will follow. The state of the A0 bit defines whether the data byte is interpreted as a command or as RAM data. All addressed slaves on the bus also acknowledge the control and data bytes. After the last control byte, depending on the A0 bit setting; either a series of display data bytes or command data bytes may follow. If the A0 bit is set to logic 1, these display bytes are stored in the display RAM at the address specified by the data pointer. The data pointer is automatically updated and the data is directed to the intended ST7528 device. If the A0 bit of the last control byte is set to logic 0, these command bytes will be decoded and the setting of the device will be changed according to the received commands. Only the addressed slave makes the acknowledgement after each byte. At the end of the transmission the IIC INTERFACE-bus master issues a STOP condition (P).If the R/W bit is set to logic 1 the chip will output data immediately after the slave address if the A0 bit, which was sent during the last write access, is set to logic 0. If no acknowledge is generated by the master after a byte, the driver stops transferring data to the master.
Write mode
acknowledgement from ST7528
S A 1 S A 0
acknowledgement from ST7528
acknowledgement from ST7528
acknowledgement from ST7528
acknowledgement from ST7528
S01111 slave address
0A1
R/W
A 0
control byte
A 2n>=0bytes command word
data byte
A0
A 0
control byte
A
data byte
AP
1 byte Co
n>=0bytes MSB.......................LSB
Co
01111
S A 1
S A 0
R / W
Co
A 0
000000A control byte
slave address
Figure 6 2-line Interface protocol 0 1 Last control byte to be sent. Only a stream of data bytes is allowed to follow. This stream may only be terminated by s STOP or RE-START condition. Another control byte will follow the data byte unless a STOP or RE-START condition is received.
Co
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ST7528
Busy Flag
The Busy Flag indicates whether the ST7528 is operating or not. When DB7 is "H" in read status operation, this device is in busy status and will accept only read status instruction. If the cycle time is correct, the microprocessor needs not to check this flag before each instruction, which improves the MPU performance.
Data Transfer
The ST7528 uses bus holder and internal data bus for data transfer with the MPU. When writing data from the MPU to on-chip RAM, data is automatically transferred from the bus holder to the RAM as shown in Figure 7. And when reading data from on-chip RAM to the MPU, the data for the initial read cycle is stored in the bus holder (dummy read) and the MPU reads this stored data from bus holder for the next data read cycle as shown in Figure 8. This means that a dummy read cycle must be inserted between each pair of address sets when a sequence of address sets is executed. Therefore, the data of the specified address cannot be output with the read display data instruction right after the address sets, but can be output at the second read of data.
M P U s ig n a l A0 /W R D 0 to D 7 In t e r n a l s ig n a ls /W R B U S H O LD E R C O LU M N AD D R E S S N D (N ) N D (N + 1 ) N+1 D (N + 2 ) N+2 D (N + 3 ) N+3 N D (N ) D (N + 1 ) D (N + 2 ) D (N + 3 )
Figure 7 Write Timing
M P U s ig n a l A0 /W R /R D D 0 to D 7 I n t e r n a l s ig n a ls /W R /R D BUS H O LD E R N N+1 D (N ) D (N ) D (N + 1 ) D (N + 1 ) D (N + 2 ) D (N + 2 ) N Dum m y D (N ) D (N + 1 )
C O LU M N AD D R E S S
Figure 8 Read Timing
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2007/1/3
ST7528
DISPLAY DATA RAM (DDRAM)
When Mode 0 is selected The Display Data RAM stores pixel data for the LCD. It is 129-row (17 pages by 8 bits) by 132-column addressable array. Each pixel can be selected when the page and column addresses are specified. The 129 rows are divided into 16 pages of 8 lines and the 17th page with a single line (DB0 only). Data is read from or written to the 8 lines of each page directly through DB0 to DB7. The display data of DB0 to DB7 from the microprocessor correspond to the LCD common lines. The microprocessor can read from and write to RAM through the I/O buffer. Since the LCD controller operates independently, data can be written into RAM at the same time as data is being displayed without causing the LCD flicker.
When Mode 1 is selected The Display Data RAM stores pixel data for the LCD. It is 101-row (13 pages by 8 bits) by 160-column addressable array. Each pixel can be selected when the page and column addresses are specified. The 101 rows are divided into 12 pages of 8 lines and the 13th page with 4 lines; the Page Address 16 (17th page) is for Icon page with a single line (DB0 only). Data is read from or written to the 8 lines of each page directly through DB0 to DB7. The display data of DB0 to DB7 from the microprocessor correspond to the LCD common lines. The microprocessor can read from and write to RAM through the I/O buffer. Since the LCD controller operates independently, data can be written into RAM at the same time as data is being displayed without causing the LCD flicker.
Page Address Circuit
In mode 0 It incorporates 4-bit Page Address register changed by only the "Set Page" instruction. Page Address 16 is a special RAM area for the icons and display data DB0 is only valid. The page address is set from 0 to 15, and Page 16 is for Icon page. In mode 1 It incorporates 4-bit Page Address register changed by only the "Set Page" instruction. Page Address 16 is a special RAM area for the icons and display data DB0 is only valid. The page address is set from 0 to 12, and Page 16 is for Icon page.
Line Address Circuit
In mode 0 This circuit assigns DDRAM a Line Address corresponding to the first line (COM0) of the display. Therefore, by setting Line Address repeatedly, it is possible to realize the screen scrolling and page switching without changing the contents of on-chip RAM. It incorporates 7-bit Line Address register changed by only the initial display line instruction and 7-bit counter circuit. At the beginning of each LCD frame, the contents of register are copied to the line counter which is increased by CL signal and generates the line address for transferring the 128-bit RAM data to the display data latch circuit. When icon is enabled by setting icon control register, display data of icons are not scrolled because the MPU can not access Line Address of icons. In mode 1 The 7-bit Line Address register is set from 0 ~ 99, If the register is set from 100 ~ 127, It will be no operation. The register value will be kept in last value.
Ver2.3
28/97
2007/1/3
ST7528
Column Address Circuit
In Mode 0, 1 Column Address Circuit has a 10-bit preset counter that provides Column Address to the Display Data RAM. When set Column Address MSB / LSB instruction is issued, 8-bit [Y9:Y2] are set and lowest 2 bit, Y[1:0] is set to "00". Since this address is increased by 1 each a read or write data instruction, microprocessor can access the display data continuously. However, the counter is not increased and locked if a non-existing address above 9FH. It is unlocked if a column address is set again by set Column Address MSB / LSB instruction. And the column address counter is independent of page address register. ADC select instruction makes it possible to invert the relationship between the Column Address and the segment outputs. It is necessary to rewrite the display data on built-in RAM after issuing ADC select instruction. Refer to the following Figure 9 and Figure 10. (Note: in mode read or write in fourth, the column address will turn to next column address)
MODE 0
SEG output Column address [Y9:Y2] Internal column address [Y9:Y0] Display data (ADC=0) LCD panel display SEG 0 00H SEG 1 01H SEG 2 02H SEG 3 03H ... ... SEG 128 80H SEG 129 81H SEG 130 82H SEG 131 83H
00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F
...
200 201 202 203 204 205 206 207 208 209 20A 20B 20C 20D 20E 20F
1
1
1
1
1
1
1
0
1
1
0
1
1
1
0
0
... ...
0
0
1
1
0
0
1
0
0
0
0
1
0
0
0
0
Display data (ADC=1) LCD panel display
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
... ...
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
Figure 9. The Relationship between the Column Address and the Segment Outputs
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ST7528
MODE 1
SEG output Column address [Y9:Y2] Internal column address [Y9:Y0] Display data (ADC=0) LCD panel display SEG 0 00H SEG 1 01H SEG 2 02H SEG 3 03H ... ... SEG 156 9CH SEG 157 9DH SEG 158 9EH SEG 159 9FH
00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F
...
270 271 272 273 274 275 276 277 278 279 27A 27B 27C 27D 27E 27F
1
1
1
1
1
1
1
0
1
1
0
1
1
1
0
0
... ...
0
0
1
1
0
0
1
0
0
0
0
1
0
0
0
0
Display data (ADC=1) LCD panel display
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
... ...
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
Figure 10. The Relationship between the Column Address and the Segment Outputs
Segment Control Circuit
This circuit controls the display data by the display ON / OFF, reverse display ON / OFF and entire display ON / OFF instructions without changing the data in the display data RAM.
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ST7528
ST7528 Mode-0 Display RAM Mapping diagram
Page Address Data D3 D2 D1 D0 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 Line Address 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H COM COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 COM17 COM18 COM19 COM20 COM21 COM22 COM23
0
0
0
0
Page 0
0
0
0
1
Page 1
0
0
1
0
Page 2
1
1
0
1
1
1
1
0
1
1
1
1
D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0
Page 13
Page 14
Page 15
68H 69H 6AH 6BH 6CH 6DH 6EH 6FH 70H 71H 72H 73H 74H 75H 76H 77H 78H 79H 7AH 7BH 7CH 7DH 7EH 7FH 80H
COM104 COM105 COM106 COM107 COM108 COM109 COM110 COM111 COM112 COM113 COM114 COM115 COM116 COM117 COM118 COM119 COM120 COM121 COM122 COM123 COM124 COM125 COM126 COM127 COMS
ICON ICON address just can set by ICON ON instruction
Page 16
ADC SEG 01 83 00 SEG131 82 01 SEG130 81 02 SEG129 80 03 SEG128 7F 04 SEG127 7E 05 SEG126 7D 06 SEG125 7C 07 SEG124
07 7C 06 7D 05 7E 04 7F 03 80 02 81 01 82 00 83 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0
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ST7528
ST7528 Mode-1 Display RAM Mapping diagram
Page Address Data D3 D2 D1 D0 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 Line Address 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H COM COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 COM17 COM18 COM19 COM20 COM21 COM22 COM23
0
0
0
0
Page 0
0
0
0
1
Page 1
0
0
1
0
Page 2
1
0
1
0
1
0
1
1
1
1
0
0
D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0
07 06 05 04 03 02 01 00 98 99 9A 9B 9C 9D 9E 9F
Page 10
Page 11
Page 12
50H 51H 52H 53H 54H 55H 56H 57H 58H 59H 5AH 5BH 5CH 5DH 5EH 5FH 60H 61H 62H 63H
COM80 COM81 COM82 COM83 COM84 COM85 COM86 COM87 COM88 COM89 COM90 COM91 COM92 COM93 COM94 COM95 COM96 COM97 COM98 COM99
ICON ICON address just can set by ICON ON instruction
Page 16
9F 9E 9D 9C 9B 9A 99 98 00 01 02 03 04 05 06 07
80H
ADC 01
COMS
SEG159 SEG158 SEG157 SEG156 SEG155 SEG154 SEG153 SEG152
SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0
SEG
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ST7528
LCD DISPLAY CIRCUITS
FRC (Frame Rate Control) and PWM (Pulse Width Modulation) Function Circuit
The ST7528 incorporates an FRC function and a PWM function circuit to display a 16-level gray scale. The FRC function and PWM utilize liquid crystal characteristics whose transmittance is changed by an effective value of applied voltage. The ST7528 provides palette-registers to assign the desired gray level. These registers are set by the instructions and the RESETB.
ST7528-- 4FRC & 3FRC / 45PWM, 60PWM
- Gray Scale Table of 4 FRC (Frame Rate Control)
4 FRC setting 1st FR (FR1) 1st FR (FR1) 2nd FR (FR2) 2nd FR (FR2) 3rd FR (FR3) 3rd FR (FR3) 4th FR (FR4) 4th FR (FR4) (DB7 to DB0) Set 1 Frame Pulse Width Modulation Instruction Set 1 Frame Pulse Width Modulation Data Set 2 Set 2
nd nd rd rd th th st st
Frame Pulse Width Modulation Instruction Frame Pulse Width Modulation Data
Set 3 Frame Pulse Width Modulation Instruction Set 3 Frame Pulse Width Modulation Data Set 4 Frame Pulse Width Modulation Instruction Set 4 Frame Pulse Width Modulation Data
- Gray Scale Table of 3 FRC (Frame Rate Control)
3 FRC setting 1st FR (FR1) 1st FR (FR1) 2nd FR (FR2) 2nd FR (FR2) 3rd FR (FR3) 3rd FR (FR3) 4th FR (FR4) 4th FR (FR4) (DB7 to DB0) Set 1 Frame Pulse Width Modulation Instruction Set 1 Frame Pulse Width Modulation Data Set 2 Set 2
nd nd rd rd st st
Frame Pulse Width Modulation Instruction Frame Pulse Width Modulation Data
Set 3 Frame Pulse Width Modulation Instruction Set 3 Frame Pulse Width Modulation Data No used No used
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ST7528
-Gray Scale Table of 45 PWM (Pulse Width Modulation)
Dec 0 1 2 3 4 ... ... ... ... 42 43 44 45 ... ... 61 62 63 Hex 00 01 02 03 04 ... ... ... ... 2A 2B 2C 2D ... ... 3D 3E 3F 6-bits 000000 000001 000010 000011 000100 ... ... ... ... 101010 101011 101100 101101 ... ... 111101 111110 111111 PWM (on width) 0(0/45) 1/45 2/45 3/45 4/45 ... ... ... ... 42/45 43/45 44/45 1(45/45) ... ... 0/45 0/45 0/45 Note Brighter
Darker This area is selected to OFF level (0/45 level)
-Gray Scale Table of 60 PWM (Pulse Width Modulation)
Dec 0 1 2 3 4 ... ... ... ... ... ... 56 57 58 59 60 61 62 63 Hex 00 01 02 03 04 ... ... ... ... ... ... 39 3A 3B 3C 39 3D 3E 3F 6-bits 000000 000001 000010 000011 000100 ... ... ... ... ... ... 111001 111010 111011 111100 111001 111101 111110 111111 PWM (on width) 0(0/60) 1/60 2/60 3/60 4/60 ... ... ... ... ... ... 56/60 57/60 58/60 59/60 1 (60/60) 0/60 0/60 0/60 Note Brighter
Darker This area is selected to OFF level (0/60 level)
Oscillator
This is on-chip Oscillator without external resistor. When the internal oscillator is used, this pin must connect to VDD; when the external oscillator is used, this pin could be input pin. This oscillator signal is used in the voltage converter and display timing generation circuit.
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ST7528
Display Timing Generator Circuit
This circuit generates some signals to be used for displaying LCD. The display clock, CL (internal), generated by oscillation clock, generates the clock for the line counter and the signal for the display data latch. The line address of on-chip RAM is generated in synchronization with the display clock and the display data latch circuit latches the128-bit display data in synchronization with the display clock. The display data, which is read to the LCD driver, is completely independent of the access to the display data RAM from the microprocessor. The display clock generates an LCD AC signal (M) which enables the LCD driver to make an AC drive waveform, and also generates an internal common timing signal and start signal to the common driver. The frame signal or the line signal changes the M by setting internal instruction. Driving waveform and internal timing signal are shown in Figure 11.
128 129 1 2 3 4 5 6 7 8 9 10 11 12 121 122 123 124 125 126 127 128 129 1 2 3 4 5
CL(Internal) FR(Internal) M(Internal)
V0 V1 V2 V3 V4 VSS V0 V1 V2 V3 V4 VSS V0 V1 V2 V3 V4 VSS
COM0
COM1
SEGn
Figure 11 2-frame AC Driving Waveform (Duty Ratio: 1/129 in mode-0)
128 129 1 2 3 4 5 6 7 8 9 10 11 12 120 121 122 123 124 125 126 127 128 129 1 2 3 4
CL(Internal)
FR(Internal) M(Internal)
V0
COM0
V1 V2 V3 V4 Vss V0 V1 V2 V3 V4 Vss V0 V1 V2 V3 V4 Vss
COM1
SEGn
Figure 12 N-Line Inversion Driving Waveform (N=5, Duty Ratio=1/129 in mode-0)
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ST7528
LCD DRIVER CIRCUIT
This driver circuit is configured by 129-channel common drivers and 160-channel segment drivers. This LCD panel driver voltage depends on the combination of display data and M signal.
M
COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7
VDD VSS
V0 V1 V2 V3 V4 VSS V0 V1 V2 V3 V4 VSS V0 V1 V2 V3 V4 VSS V0 V1 V2 V3 V4 VSS V0 V1 V2 V3 V4 VSS V0 V1 V2 V3 V4 VSS -V4 -V3 -V2 -V1 -V0 V0 V1 V2 V3 V4 VSS -V4 -V3 -V2 -V1 -V0
COM0
COM1
COM8 COM9 COM10 COM11 COM12 COM13 COM14
COM2
SEG0
SEG 0 1 2 3 4
SEG1
COM0 to SEG0
COM0 to SEG1
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ST7528
Partial Display on LCD
The ST7528 realizes the Partial Display function on LCD with low-ratio driving for saving power consumption and showing the various display ratio. To show the various display ratio on LCD, LCD driving ratio and bias are programmable via the instruction. And, built-in power supply circuits are controlled by the instruction for adjusting the LCD driving voltages. In mode 0 the partial display ratio could be set from 16 ~ 128. In mode 1 could be set from 16 ~ 100. If the partial display region is out of the Max. Display range, it would be no operation.
-COM0 -COM1 -COM2 -COM3 -COM4 -COM5 -COM6 -COM7 -COM8 -COM9 -COM10 -COM11 -COM12 -COM13 -COM14 -COM15 -COM16 -COM17 -COM18 -COM19 -COM20 -COM21 -COM22 -COM23
Figure 13 Reference Example for Partial Display
-COM0 -COM1 -COM2 -COM3 -COM4 -COM5 -COM6 -COM7 -COM8 -COM9 -COM10 -COM11 -COM12 -COM13 -COM14 -COM15 -COM16 -COM17 -COM18 -COM19 -COM20 -COM21 -COM22 -COM23
Figure 14 Partial Display (Partial Display ratio=16,initial COM0=0)
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-COM0 -COM1 -COM2 -COM3 -COM4 -COM5 -COM6 -COM7 -COM8 -COM9 -COM10 -COM11 -COM12 -COM13 -COM14 -COM15 -COM16 -COM17 -COM18 -COM19 -COM20 -COM21 -COM22 -COM23
Figure 15 Moving Display (Partial Display ratio=16,Initial COM0=8)
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POWER SUPPLY CIRCUITS
The Power Supply circuits generate the voltage levels necessary to drive liquid crystal driver circuits with low power consumption and the fewest components. There are voltage converter circuits, voltage regulator circuits, and voltage follower circuits. They are controlled by power control instruction. For details, refers to "Instruction Description". Table 4 shows the referenced combinations in using Power Supply circuits. Table 4 Recommended Power Supply Combinations Power User setup control (VC VR VF) Only the internal power supply circuits are used Only the voltage regulator circuits and voltage follower circuits are used Only the voltage follower circuits are used Only the external power supply circuits are used 000 OFF OFF OFF OPEN 001 OFF OFF ON OPEN External input External input With capacitor External input 011 OFF ON ON External input Without capacitor With capacitor 111 V/C circuits V/R circuits V/F circuits
VOUT_IN
V0
V1 to V4
ON
ON
ON
Internal
Without capacitor
With capacitor
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Voltage Converter Circuits
These circuits boost up the electric potential between VDD2 and Vss to 3, 4, 5 or 6 times toward positive side and boosted voltage is outputted from VOUT pin. It is possible to select the lower boosting level in any boosting circuit by "Set DC-DC Step-up" instruction. When the higher level is selected by instruction, VOUT voltage is not valid. Note: we would like to recommend to use the external VOUT when the panel is large than 1.8 inch
Voltage Regulator Circuits
The function of the internal Voltage Regulator circuits is to determine liquid crystal operating voltage, V0, by adjusting resistors, Ra and Rb, within the range of |V0| < |VOUT|. Because VOUT is the operating voltage of operational-amplifier circuits shown in Figure 16, it is necessary to be applied internally or externally. For the Eq. 1, we determine V0 by Ra, Rb and VEV. The Ra and Rb are connected internally or externally by INTRS pin. And VEV called the voltage of electronic volume is determined by Eq. 2, where the parameter is the value selected by instruction, "Set Reference Voltage Register", within the range 0 to 63. VREF voltage at Ta= 25C is shown in Table 5. Rb V0 = (1 + ) x VEV [V] ------ (Eq. 1) Ra (63 - ) VEV = (1 - ) x VREF [V] ------ (Eq. 2) 210 Table 5 VREF Voltage at Ta = 25C REF 1 0 Temp. coefficient -0.125% / C External input VREF [ V ] 2.1 VEXT
VOUT + _
V0 Rb
VEV VR Ra VSS GND
Figure 16 Internal Voltage Regulator Circuit
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In Case of Using Internal Resistors, Ra and Rb (INTRS = "H")
When INTRS pin is "H", resistor Ra is connected internally between VR pin and VSS, and Rb is connected between V0 and VR. We determine V0 by two instructions, "Regulator Resistor Select" and "Set Reference Voltage". Table 6 Internal Rb / Ra Ratio depending on 3-bit Data (R2 R1 R0) 3-bit data settings (R2 R1 R0) 000 1 + (Rb / Ra) 2.3 001 3.0 010 3.7 011 4.4 100 5.1 101 5.8 110 6.5 111 7.2
Figure 17 shows V0 voltage measured by adjusting internal regulator register ratio (Rb / Ra) and 6-bit electronic volume registers for each temperature coefficient at Ta = 25 C.
16.000
14.000
12.000 000 001 010 011 100 101 110 111
10.000
8.000
6.000
4.000
2.000
0.000
0 3 6 9 12 15 18 21 24 27 30 33 36 39 42 45 48 51 54 57 60 63
Figure 17 Electronic volume register (0 to 63)
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In Case of Using External Resistors, Ra and Rb (INTRS = "L")
When INTRS pin is "L", it is necessary to connect external regulator resistor Ra between VR and VSS, and Rb between V0 and VR. Example: For the following requirements 1. LCD driver voltage, V0 = 10V 2. 6-bit reference voltage register = (1, 0, 0, 0, 0, 0) 3. Maximum current flowing Ra, Rb = 1 uA From Eq. 1 Rb 10 = (1 + ) x VEV [V] ------ (Eq. 3) Ra From Eq. 1 (63 - 32) VEV = (1 - ) x 2.1 = 1.79 [V] ------ (Eq. 4) 210 From requirement 3. 10 = 1 [uA] ------ (Eq. 5) Ra + Rb From equations Eq. 3, 4 and 5 Ra = 1.79 [M] Rb = 8.21 [M] Table 7 Shows the Range of V0 depending on the above Requirements. Table 7 The Range of V0 Electronic volume level 0 V0 8.21 ....... ....... 32 10.00 ....... ....... 63 11.73
Voltage Follower Circuits
VLCD voltage (V0) is resistively divided into four voltage levels (V1, V2, V3 and V4), and those output impedance are converted by the Voltage Follower for increasing drive capability. Table 8 shows the relationship between V1 to V4 level and each duty ratio. Table 8 The Relationship between V1 to V4 Level and Each Duty Ratio LCD bias 1/N V1 (N-1)/N x V0 V2 (N-2)/N x V0 V3 2/N x V0 V4 1/N x V0 Remarks N = 5 to 12
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Bias Power Save circuit:
When we set the Instruction of Bias Power Save, the bias also could be working, and the IC current consumption will be lower about 100uA to 200uA (according to the panel loading) Follower voltage reference circuit (Internal Booster & Regulator)
VSS2 VSS C1 VOUT VSS C1
VSS2 VOUT
VDD
INTR
VSS
INTR
Rb V0 VR VSS Ra VSS V0 C2 C2 C2 C2 V1 V2 V3 V4
ST7528
ST7528
VSS VSS V0 C2 C2 C2 C2 V1 V2 V3 V4
Left is using internal Resister Right is using External Resister C1= 1u F ~ 4.7u F, C2 = 0.1u F ~ 1u F (suggestion value: C1=1uF, C2=0.1uF)
Follower voltage reference circuit (External Vout & Internal Regulator)
External
VOUT
External
VOUT
VDD
INTR
VSS
INTR
Rb V0 VR VSS Ra VSS V0 C2 C2 C2 C2 V1 V2 V3 V4
ST7528
ST7528
VSS VSS V0 C2 C2 C2 C2 V1 V2 V3 V4
Left is using internal Resister Right is using External Resister C1= 1u F ~ 4.7u F, C2 = 0.1u F ~ 1u F (suggestion value: C1=1uF , C2=0.1uF)
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Booster Efficiency By Booster Stages (3X, 4X, 5X, 6X) and Booster Efficiency (Level1~2) commands, we could easily set the best Booster performance with suitable current consumption. If the Booster Efficiency is set to higher level (level2 is higher than level1), The Boost Efficiency is better than lower level, and it just need few more power consumption current. It could be applied to each multiple voltage Condition. When the LCD Panel loading is heavier, then the Performance of Booster will be not in a good working condition. We could set the BE level to be higher. We do not need to change to higher Booster Stage, and just need few more current. The Booster Efficiency Command could be used together with Booster Stage Command to choose one best Boost output condition. We could see the Boost Stage Command as a large scale operation, and see the Booster Efficiency Command as a small scale operation. These commands are very convenient for using.
Level1
Vout Voltage
Level2
5X boost
Loading
VSS Current
Level1
Level2
5X Current
Loading
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RESET CIRCUIT
Setting RESETB to "L" or Reset instruction can initialize internal function. When RESETB becomes "L", following procedure is occurred. Page address: 0 Column address: 0 Read-modify-write: OFF Display ON / OFF: OFF Initial display line: 0 (first) Initial COM0 register: 0 (COM0) Partial display ratio: 1/128 Reverse display ON / OFF: OFF (normal) N-line inversion register: 0 (disable) Entire Display ON/OFF: OFF ICON Control register ON/OFF: OFF (ICON disable) Power control register (VC, VR, VF) = (0, 0, 0) DC-DC converter circuit = (0, 0) Booster Efficiency BE = (1) Regulator resistor select register: (R2, R1, R0) = (0, 0, 0) Contrast Level: 32 LCD bias ratio: 1/12 COM Scan Direction: 0 ADC Select: 0 Oscillator: OFF Power Save Mode: Release Display Data Length register: 0 (for SPI mode) All Gray Level Set : OFF In Level0, 2, 4, 6, 8, 10, 12, 14 , the Gray Level palette register (GA5, GA4, GA3, GA2, GA1, GA0) = (0,0,0,0,0) All Gray Level Set : OFF In Level1, 3, 5, 7, 9, 11, 13, 15, the Gray Level palette register (GA5, GA4, GA3, GA2, GA1, GA0) = (1,1,1,1,1) FRC, PWM mode: 4FRC, 45PWM When RESET instruction is issued, following procedure is occurred. Page address: 0 Column address: 0 Read-modify-write: OFF Initial display line: 0 (First) Regulator resistor select register: (R2, R1, R0) = (0, 0, 0) Contrast Level: 32 Display Data Length register: 0 (for SPI mode) All Gray Level Set : OFF In Level0, 2, 4, 6, 8, 10, 12, 14 , the Gray Level palette register (GA5, GA4, GA3, GA2, GA1, GA0) = (0,0,0,0,0) All Gray Level Set : OFF In Level1, 3, 5, 7, 9, 11, 13, 15, the Gray Level palette register (GA5, GA4, GA3, GA2, GA1, GA0) = (1,1,1,1,1) FRC, PWM mode: 4FRC, 45PWM While RESETB is "L" or reset instruction is executed, no instruction except read status can be accepted. Reset status appears at DB4. After DB4 becomes "L", any instruction can be accepted. RESETB must be connected to the reset pin of the MPU, and initialize the MPU and this LSI at the same time. The initialization by RESETB is essential before used.
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Instruction EXT=0 or 1 A0 RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Description
0
Mode Set
0 0
0 FR3
0
1
1 FR0
1 0
0 BE
0 x'
0
FR2 FR1
2-byte instruction to set Mode and EXT FR( Frame frequency control) BE( Booster efficiency control)
0
EXT=0 Read display data Write display data Read status 1 1 0 1 0 1 BUSY ON RES Read data Write data MF2 MF1 MF0 DS1 DS0 Read data into DDRAM Write data into DDRAM Read the internal status
ICON control register ON/OFF
0
0
1
0
1
0
0
0
1
ICON=0: ICON disable(default) ICON ICON=1: ICON enable & set the page address to 16 P0 Y6 Y2 0 0 D x' S0 x' C0 x' D0 x' N0 0 REV EON Set page address Set column address MSB Set column address LSB Set modify-read mode release modify-read mode D=0: Display OFF D=1: Display ON 2-byte instruction to specify the initial display line to realize vertical scrolling 2-byte instruction to specify the initial COM0 to realize window scrolling 2-byte instruction to set partial display ratio 2-byte instruction to set N-line inversion register Release N-line inversion mode REV=0: normal display REV=1: reverse display EON=0: normal display EON=1: entire display ON
Set page address Set column address MSB Set column address LSB Set modify-read Reset modify-read Display ON/OFF Set initial display line register
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
1 0 0 1 1 1 0 x' 0 x' 0 D7 0 x' 1 1 1
0 0 0 1 1 0 1 S6 1 C6 1 D6 1 x' 1 0 0
1 0 0 1 1 1 0 S5 0 C5 0 D5 0 x' 1 1 1
1 1 0 0 0 0 0 S4 0 C4 0 D4 0 N4 0 0 0
P3 Y9 Y5 0 1 1 0 S3 0 C3 1 D3 1 N3 0 0 0
P2 Y8 Y4 0 1 1 0 S2 1 C2 0 D2 1 N2 1 1 1
P1 Y7 Y3 0 1 1 x' S1 x' C1 x' D1 x' N1 0 1 0
Set initial COM0 register 0 0 Select partial display line 0 0 Set N-line inversion 0 Release N-line inversion Reverse display ON/OFF Entire display ON/OFF 0 0 0
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Instruction Ext=0 Power control Select DC-DC step-up Select regulator register Select electronic volumn register Select LCD bias Set Bias Power Save Mode 0 Release Bias Power Save Mode SHL select 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 0 0 1 0 0 0 0 0 SHL 0 0 1 x' 0 1 0 x' 0 1 0 x' 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 x' 0 1 0 1 0 0 x' 1 1 1 1 1 0 EV5 0 1 0 0 0 0 EV4 1 1 1 0 0 0 EV3 0 0 VC 1 R2 0 EV2 B2 0 VR DC1 R1 0 EV1 B1 1 VF DC0 R0 1 EV0 B0 1 Control power circuit operation Select the step-up of internal voltage converter Select the internal resistance ratio of the regulator resistor 2-byte instruction to specify the reference voltage Select LCD bias Bias Power save Save the Bias current consumption Bias Power save release set the Bias power to normal COM bi-directional selection SHL=0: normal direction SHL=1: reverse direction SEG bi-direction selection ADC=0: normal direction ADC=1: reverse direction Start the built-in oscillator P=0: normal mode P=1: sleep mode release power save mode initial the internal function 2-byte instruction to specify the number of data bytes. (SPI mode) A0 RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Description
ADC select Oscillator on start Set power save mode Release power save mode Reset Set data direction & display data length(DDL)
0 0 0 0 0 x' x'
0 0 0 0 0 x' x'
1 1 1 1 1 1 D7
0 0 0 1 1 1 D6
1 1 1 1 1 1 D5
0 0 0 0 0 0 D4
0 1 1 0 0 1 D3
0 0 0 0 0 0 D2
0 1 0 0 1 0 D1
ADC 1 P 1 0 0 D0
Select FRC and PWM mode 0 0 1 0 0 1 0 FRC PWM1
FRC(1:3FRC, 0:4FRC) PWM1 PWM0 0 0 45PWM PWM0 0 1 45 PWM 1 0 60PWM 1 1 --1 x' No operation Don't use this instruction
NOP Test Instruction
0 0
0 0
1 1
1 1
1 1
0 1
0 x'
0 x'
1 x'
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ST7528 Instruction EXT=1 Set white mode and 1st frame, 0 set pulse width 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 X' 1 X' 1 X' 1 X' 0 X' 0 X' 0 X' 0 X' 1 X' 1 X' 1 X' 1 X' 0 X' 0 X' 0 X' 0 X' 0 0 0 0 0 GA01 0 GA01 1 GA01 1 GA01 0 Set white mode and 1st frame GA05 GA04 GA03 GA02 0 0 0 0 GA00 Set white mode and 2nd GA00 frame Set white mode and 3rd GA00 frame Set white mode and 4th GA00 frame Set gray level1 Set gray level2 Set gray level3 Set gray level4 Set gray level5 Set gray level6 Set gray level7 Set gray level8 Set gray level9 Set gray level10 Set gray level11 Set gray level12 Set gray level13 Set gray level14 0 0 GAF0 1 GAF0 0 GAF0 1 GAF0 Set Dark mode and 1st frame, set pulse width Set Dark mode and 2nd frame, set pulse width Set Dark mode and 3rd frame, set pulse width Set Dark mode and 4th frame, set pulse width 1 0 1 Set white mode and 2nd frame, 0 set pulse width 0 A0 RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Description
GA05 GA04 GA03 GA02 0 0 0 0
Set white mode and 3rd frame, 0 set pulse width
th
0
GA05 GA04 GA03 GA02 0 0 0 0
Set white mode and 4 frame, 0 set pulse width Set gray level 1 mode Set gray level 2 mode Set gray level 3 mode Set gray level 4 mode Set gray level 5 mode Set gray level 6 mode Set gray level 7 mode Set gray level 8 mode Set gray level 9 mode Set gray level 10 mode Set gray level 11mode Set gray level 12 mode Set gray level 13 mode Set gray level 14 mode Set Dark mode and 1st frame, set pulse width Set Dark mode and 2nd frame, set pulse width Set Dark mode and 3rd frame, set pulse width Set Dark mode and 4th frame, set pulse width 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
GA05 GA04 GA03 GA02
84H~87H (4 bytes) 88H~8BH (4 bytes) 8CH~8FH (4bytes) 90H~93H (4bytes) 94H~97H (4bytes) 98H~9BH (4 bytes) 9CH~9FH (4 bytes) A0H~A3H (4 bytes) A4H~A7H (4 bytes) A8H~ABH (4 bytes) ACH~AFH (4 bytes) B0H~B3H (4 bytes) B4H~B7H (4 bytes) B8H~BBH (4 bytes)
1 1 1 1
GAF5 GAF4 GAF3 GAF2 GAF1 1 1 1 1 0
GAF5 GAF4 GAF3 GAF2 GAF1 1 1 1 1 1
GAF5 GAF4 GAF3 GAF2 GAF1 1 1 1 1 1
GAF5 GAF4 GAF3 GAF2 GAF1
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Set Mode Register 2-byte instruction to set Mode (EXT) and FR (Frame frequency control), BE (Booster efficiency control). The 1st Instruction
A0 0 RW 0 DB7 0 DB6 0 DB5 1 DB4 1 DB3 1 DB2 0 DB1 0 DB0 0
The 2nd Instruction
A0 0 RW 0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
FR3
FR2
FR1
FR0
0
BE
x'
EXT
Frame frequency This command is used to set the frame frequency. This table is suitable for no partial display FR3 FR2 FR1 FR0 FR frequency 0 0 0 0 77 Hz 5% 0 0 0 1 51 Hz 20% 0 0 1 0 55 Hz 20% 0 0 1 1 58 Hz 20% 0 1 0 0 63 Hz 20% 0 1 0 1 67 Hz 20% 0 1 1 0 68 Hz 20% 0 1 1 1 70 Hz 20% 1 0 0 0 73 Hz 20% 1 0 0 1 75 Hz 20% 1 0 1 0 80 Hz 20% 1 0 1 1 85 Hz 20% 1 1 0 0 91 Hz 20% 1 1 0 1 102 Hz 20% 1 1 1 0 113 Hz 20% 1 1 1 1 123 Hz 20% Booster Efficiency
The ST7528 incorporates software configurable Booster Efficiency Command. It could be used with Voltage multiplier to get the suitable Vout and Power consumption. Default setting is Level 2
Flag BE Mode Set Flag EXT Description Default EXT=0 EXT=1 EXT=0 The Instruction of EXT=0 Mode is available The Instruction of EXT=1 Mode is available Description 0 Booster Efficiency Level 1 1 Booster Efficiency Level 2
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Read Display Data
8-bit data from Display Data RAM specified by the column address and page address can be read by this instruction. As the column address is increased by 1 automatically after each this instruction, the microprocessor can continuously read data from the addressed page. A dummy read is required after loading an address into the column address register. Display Data cannot be read through the serial interface. A0 1 RW 1 DB7 DB6 DB5 DB4 DB3 Read data DB2 DB1 DB0
Write Display Data
8-bit data of Display Data from the microprocessor can be written to the RAM location specified by the column address and page address. The column address is increased by 1 automatically so that the microprocessor can continuously write data to the addressed page. During auto-increment, the column address wraps to 0 after the last column is written. A0 1 RW 1 DB7 DB6 DB5 DB4 DB3 Write data DB2 DB1 DB0
Set Page Address
Set Page Address
Set Column Address
Set Column Address
Data Write
Dummy Data Read
Column = Column + 1
Column = Column + 1
YES Data Write Continue ?
Data Read
NO Optional Status
Column = Column + 1
YES Data Read Continue ?
NO Optional Status
Figure 18 Sequence for Writing Display Data (Left) and Sequence for Reading Display Data (Right)
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Read Status
Indicates the internal status of the ST7528 A0 0 RW 1 DB7 BUSY DB6 ON DB5 RES DB4 MF2 DB3 MF1 DB2 MF0 DB1 DS1 DB0 DS0
Flag BUSY
Description The device is busy when internal operation or reset. Any instruction is rejected until BUSY goes Low. 0: chip is active, 1: chip is being busy
ON
Indicates display ON / OFF status 0: display OFF, 1: display ON
RESET
Indicates the initialization is in progress by RESET signal. 0: chip is active, 1: chip is being reset
MF
Manufacturer ID; suggest value: MF2 MF1 MF0 = [0 0 0] The value of MF2, MF1 and MF0 will follow the hardware selection.
DS
Display size ID; suggest value: DS1 DS0 = [1 0] The value of DS1 and DS2 will follow the hardware selection.
ICON Control Register ON/OFF
This instruction makes ICON enable or disable. By default, ICON display is disabled (ICON= 0). When ICON control register is set to "1", ICON display is enabled and page address is set to "16". Then user can write data for icons. It is impossible to set the page address to "16" by Set Page Address instruction. Therefore, when writing data for icons, ICON control register ON instruction would be used to set the page address to "16". When ICON control register is set to "0", ICON display is disabled. A0 0 RW 0 DB7 1 DB6 0 DB5 1 DB4 0 DB3 0 DB2 0 DB1 1 DB0 ICON
ICON=0: ICON disable (default) ICON=1: ICON enable & set the page address to 16
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Set Page Address
Sets the Page Address of display data RAM from the microprocessor into the page address register. Any RAM data bit can be accessed when its Page Address and column address are specified. Along with the column address, the Page Address defines the address of the display RAM to write or read display data. Changing the Page Address doesn't affect the display status. Set Page Address instruction can not be used to set the page address to "16". Use ICON control register ON/OFF instruction to set the page address to "16". A0 0 RW 0 DB7 1 DB6 0 DB5 1 DB4 1 DB3 P3 DB2 P2 DB1 P1 DB0 P0
P3 0 0 : 1 1
P2 0 0 : 1 1
P1 0 0 : 1 1
P0 0 1 : 0 1
Page 0 1 : 14 15
Set Column Address
Sets the Column Address of display RAM from the microprocessor into the column address register. Along with the Column Address, the Column Address defines the address of the display RAM to write or read display data. When the microprocessor reads or writes display data to or from display RAM, Column Addresses are automatically increased.
Set Column Address MSB
A0 0 RW 0 DB7 0 DB6 0 DB5 0 DB4 1 DB3 Y9 DB2 Y8 DB1 Y7 DB0 Y6
Set Column Address LSB
A0 0 RW 0 DB7 0 DB6 0 DB5 0 DB4 0 DB3 Y5 DB2 Y4 DB1 Y3 DB0 Y2
Y9
Y8
Y7
Y6
Y5
Y4
Y3
Y2
Column address [Y9:Y2]
0 0 : 0 0 : 1 1
0 0 : 1 1 : 0 0
0 0 : 1 1 : 0 0
0 0 : 1 1 : 1 1
0 0 : 1 1 : 1 1
0 0 : 1 1 : 1 1
0 0 : 1 1 : 1 1
0 1 : 0 1 : 0 1
0 1 : 126 127 : 158 159
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Set Modify-Read
This instruction stops the automatic increment of the column address by the read display data instruction, but the column address is still increased by the write display data instruction. And it reduces the load of microprocessor when the data of a specific area is repeatedly changed during cursor blinking or others. This mode is canceled by the reset Modify-Read instruction. A0 0 RW 0 DB7 1 DB6 1 DB5 1 DB4 0 DB3 0 DB2 0 DB1 0 DB0 0
Reset Modify-Read
This instruction cancels the Modify-Read mode, and makes the column address return to its initial value just before the set Modify-Read instruction is started. A0 0 RW 0 DB7 1 DB6 1 DB5 1 DB4 0 DB3 1 DB2 1 DB1 1 DB0 0
Set Page Address
Set Column Address (N)
Set Modify-Read
Dummy Read
Data Read
Data Process
Data Write
NO Change Completed? YES Read Modify-read
Return Column Address (N)
Figure 19 Sequence for Cursor Display
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Display ON / OFF
Turns the display ON or OFF. This command has priority over Entire Display On/Off and Reverse Display On/Off. Commands are accepted while the display is off, but the visual state of the display does not change. A0 0 RW 0 DB7 1 DB6 0 DB5 1 DB4 0 DB3 1 DB2 1 DB1 1 DB0 DON
DON = 1: display ON DON = 0: display OFF
Set Initial Display Line Register
Sets the line address of display RAM to determine the initial display line using 2-byte instruction. The RAM display data is displayed at the top of row (COM0) of LCD panel.
The 1st Instruction
A0 0 RW 0 DB7 0 DB6 1 DB5 0 DB4 0 DB3 0 DB2 0 DB1 x DB0 x
The 2nd Instruction
A0 0 RW 0 DB7 x DB6 S6 DB5 S5 DB4 S4 DB3 S3 DB2 S2 DB1 S1 DB0 S0
S6 0 0 0 0 : 1 1 1 1
S5 0 0 0 0 : 1 1 1 1
S4 0 0 0 0 : 1 1 1 1
S3 0 0 0 0 : 1 1 1 1
S2 0 0 0 0 : 1 1 1 1
S1 0 0 1 1 : 0 0 1 1
S0 0 1 0 1 : 0 1 0 1
Line address 0 1 2 3 : 124 125 126 127
S e ttin g In itia l D is p la y L in e S ta rt 1 st I n s tr u c tio n f o r M o d e s e ttin g 2 nd In s tru c tio n fo r In itia l D is p la y L in e s e ttin g S e ttin g In itia l D is p la y L in e E n d
Figure 20 Sequence For Setting Initial Display Line
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Set Initial COM0 Register
Sets the initial row (COM) of the LCD panel using the 2-byte instruction. By using this instruction, it is possible to realize the window moving without the change of display data.
The 1st Instruction
A0 0 RW 0 DB7 0 DB6 1 DB5 0 DB4 0 DB3 0 DB2 1 DB1 x DB0 x
The 2nd Instruction
A0 0 RW 0 DB7 x DB6 C6 DB5 C5 DB4 C4 DB3 C3 DB2 C2 DB1 C1 DB0 C0
C6 0 0 0 0 : 1 1 1 1
C5 0 0 0 0 : 1 1 1 1
C4 0 0 0 0 : 1 1 1 1
C3 0 0 0 0 : 1 1 1 1
C2 0 0 0 0 : 1 1 1 1
C1 0 0 1 1 : 0 0 1 1
C0 0 1 0 1 : 0 1 0 1
Initial COM0 COM0 COM1 COM2 COM3 : COM124 COM125 COM126 COM127
S e tt in g I n itia l C O M 0 S ta r t 1 s t I n s tr u c ti o n f o r M o d e s e tt in g 2 n d I n s t r u c ti o n f o r I n i ti a l C O M 0 s e ttin g S e ttin g I n it ia l C O M 0 E n d
Figure 21 Sequence For Setting Initial COM0
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Select partial display line
Sets the ratio within range of 16 to 128 (ICON disabled) or 17 to 129 (ICON enabled) to realize partial display by using the 2-byte instruction.
The 1st Instruction
A0 0 RW 0 DB7 0 DB6 1 DB5 0 DB4 0 DB3 1 DB2 0 DB1 x DB0 x
The 2nd Instruction
A0 0 RW 0 DB7 D7 DB6 D6 DB5 D5 DB4 D4 DB3 D3 DB2 D2 DB1 D1 DB0 D0
D7 0 : 0 0 0 : 0 : 0 1 1 : 1
D6 0 : 0 0 0 : 1 : 1 0 0 : 1
D5 0 : 0 0 0 : 1 : 1 0 0 : 1
D4 0 : 0 1 1 : 0 : 1 0 0 : 1
D3 0 : 1 0 0 : 0 : 1 0 0 : 1
D2 0 : 1 0 0 : 1 : 1 0 0 : 1
D1 0 : 1 0 0 : 0 : 1 0 0 : 1
D0 0 : 1 0 1 : 0 : 1 0 1 : 1
Selected partial Display line mode 0 No operation 1/16 1/17 : 1/100 : 1/127 1/128 No Operation
Selected partial Display line mode 1 No operation 1/16 1/17 : 1/100 1/100 1/100 1/100 No Operation
S e ttin g P a rtia l D is p la y S ta rt 1 s t I n s tr u c tio n fo r M o d e s e ttin g 2 n d I n s tr u c tio n f o r P a rtia l D is p la y D u ty s e ttin g S e ttin g P a rtia l D is p la y E n d
Figure 22 Sequence For Setting Partial Display
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ST7528
Set N-line Inversion Register
Sets the inverted line number within range of 3 to 33 to improve the display quality by controlling the phase of the internal LCD AC signal (M) by using the 2-byte instruction. The DC-bias problem could be occurred if K is even number. So, we recommend customers to set K to be odd number. K : D/N D : The number of display ratio (D is selectable by customers) N : N for N-line inversion (N is selectable by customers).
The 1st Instruction
A0 0 RW 0 DB7 0 DB6 1 DB5 0 DB4 0 DB3 1 DB2 1 DB1 x DB0 x
The 2nd Instruction
A0 0 RW 0 DB7 x DB6 x DB5 x DB4 N4 DB3 N3 DB2 N2 DB1 N1 DB0 N0
N4 0 0 0 0 : 1 1 1
N3 0 0 0 0 : 1 1 1
N2 0 0 0 0 : 1 1 1
N1 0 0 1 1 : 0 1 1
N0 0 1 0 1 : 1 0 1
Selected n-line inversion 0-line inversion (frame inversion) 3-line inversion 4-line inversion 5-line inversion : 31-line inversion 32-line inversion 33-line inversion
Setting N-line Inversion Start 1 st Instruction for M ode setting 2 nd Instruction for N -line Inversion setting Setting N -line Inversion End
Figure 23 Sequence For N-line Inversion
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Release N-line Inversion
Returns to the frame inversion condition from the n-line inversion condition. A0 0 RW 0 DB7 1 DB6 1 DB5 1 DB4 0 DB3 0 DB2 1 DB1 0 DB0 0
Reverse Display ON / OFF
Reverses the display status on LCD panel without rewriting the contents of the display data RAM. A0 0 RW 0 DB7 1 DB6 0 DB5 1 DB4 0 DB3 0 DB2 1 DB1 1 DB0 REV
REV 0 (normal) 1 (reverse)
White White ("0000") Dark ("1111")
Gray level 1 Gray 1 ("0001") Gray 14 ("1110")
..... ..... .....
Gray level 14 Gray 14 ("1110") Gray 1 ("0001")
- Dark Dark ("1111") White ("0000")
Entire Display ON / OFF
Forces the whole LCD points to be turned on regardless of the contents of the display data RAM. At this time, the contents of the display data RAM are held. This instruction has priority over the Reverse Display ON / OFF instruction. A0 0 RW 0 DB7 1 DB6 0 DB5 1 DB4 0 DB3 0 DB2 1 DB1 0 DB0 EON
Entire 0 (normal) 1 (Entire)
White White ("0000") Dark ("1111")
Gray level 1 Gray 1 ("0001") Dark ("1111")
..... ..... Dark ("1111")
Gray level 14 Gray 14 ("1110") Dark ("1111")
- Dark Dark ("1111") Dark ("1111")
Power Control
Selects one of eight power circuit functions by using 3-bit register. An external power supply and part of internal power supply functions can be used simultaneously. A0 0 RW 0 DB7 0 DB6 0 DB5 1 DB4 0 DB3 1 DB2 VC DB1 VR DB0 VF
VC 0 1
VR
VF
Status of internal power supply circuits Internal voltage converter circuit is OFF Internal voltage converter circuit is ON
0 1 0 1
Internal voltage regulator circuit is OFF Internal voltage regulator circuit is ON Internal voltage follower circuit is OFF Internal voltage follower circuit is ON
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Set Bias Power Save Mode
Consist of 2-byte Instructions
The 1st Instruction
A0 0 RW 0 DB7 1 DB6 1 DB5 1 DB4 1 DB3 0 DB2 0 DB1 1 DB0 1
The 2nd Instruction
A0 0 RW 0 DB7 0 DB6 0 DB5 0 DB4 0 DB3 0 DB2 0 DB1 0 DB0 0
This command is for saving the IC current consumption by Bias Power Saving After this Instruction is set, Bias function is also working Release Bias Power Save Mode
Consist of 2-byte Instructions
The 1st Instruction
A0 0 RW 0 DB7 1 DB6 1 DB5 1 DB4 1 DB3 0 DB2 0 DB1 1 DB0 1
The 2nd Instruction
A0 0 RW 0 DB7 0 DB6 0 DB5 0 DB4 0 DB3 0 DB2 1 DB1 0 DB0 0
This command is for release Bias Power Save
Select DC-DC Step-up
Selects one of 4 DC-DC step-up to reduce the power consumption by this instruction. It is very useful to realize the partial display function. A0 0 RW 0 DB7 0 DB6 1 DB5 1 DB4 0 DB3 0 DB2 1 DB1 DC1 DB0 DC0
DC1 0 0 1 1
DC0 0 1 0 1
Selected DC-DC converter circuit 3 times boosting circuit 4 times boosting circuit 5 times boosting circuit 6 times boosting circuit
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Select Regulator Resistor
Selects resistance ratio of the internal resistor used in the internal voltage regulator. See voltage regulator section in power supply circuit. Refer to the Table 6. A0 0 RW 0 DB7 0 DB6 0 DB5 1 DB4 0 DB3 0 DB2 R2 DB1 R1 DB0 R0
R2 0 0 0 0 1 1 1 1
R1 0 0 1 1 0 0 1 1
R0 0 1 0 1 0 1 0 1
1+ (Rb / Ra) 2.3 3.0 3.7 4.4 5.1 5.8 6.5 7.2
Set Electronic Volume Register
Consist of 2-byte Instructions The 1st instruction set Reference Voltage mode, the 2nd one updates the contents of reference voltage register. After second instruction, Reference Voltage mode is released.
The 1st Instruction: Set Reference Voltage Select Mode
A0 0 RW 0 DB7 1 DB6 0 DB5 0 DB4 0 DB3 0 DB2 0 DB1 0 DB0 1
The 2nd Instruction: Set Reference Voltage Register
A0 0 RW 0 DB7 x DB6 x DB5 EV5 DB4 EV4 DB3 EV3 DB2 EV2 DB1 EV1 DB0 EV0
EV5 0 0 : : 1 1
EV4 0 0 : : 1 1
EV3 0 0 : : 1 1
EV2 0 0 : : 1 1
EV1 0 0 : : 1 1
EV0 0 1 : : 0 1
Reference voltage parameter (a) 0 1 : : 62 63
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S e ttin g R e f e r e n c e V o lta g e S ta r t 1 s t I n s tr u c tio n fo r M o d e s e ttin g 2 n d I n s tr u c tio n f o r R e g is te r s e ttin g S e ttin g R e f e re n c e V o lta g e E n d
Figure 24 Sequence For Setting the Electronic Volume
Select LCD Bias
Selects LCD bias ratio of the voltage required for driving the LCD. A0 0 RW 0 DB7 0 DB6 1 DB5 0 DB4 1 DB3 0 DB2 B2 DB1 B1 DB0 B0
B2 0 0 0 0 1 1 1 1
B1 0 0 1 1 0 0 1 1
B0 0 1 0 1 0 1 0 1
LCD bias 1/5 1/6 1/7 1/8 1/9 1/10 1/11 1/12
SHL Select
COM output scanning direction is selected by this instruction which determines the LCD driver output status. A0 0 In Mode 0 SHL = 0: normal direction (COM0 COM127) SHL = 1: reverse direction (COM127 COM0) In Mode 1 RW 0 DB7 1 DB6 1 DB5 0 DB4 0 DB3 SHL DB2 x DB1 x DB0 x
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SHL = 0: normal direction (COM0 COM99) SHL = 1: reverse direction (COM99 COM0)
ADC Select
Changes the relationship between RAM column address and segment driver. The direction of segment driver output pins could be reversed by software. This makes IC layout flexible in LCD module assembly. A0 0 In Mode 0 ADC = 0: normal direction (SEG0 SEG127) ADC = 1: reverse direction (SEG127 SEG0) In Mode 1 ADC = 0: normal direction (SEG0 SEG159) ADC = 1: reverse direction (SEG159 SEG) RW 0 DB7 1 DB6 0 DB5 1 DB4 0 DB3 0 DB2 0 DB1 0 DB0 ADC
Oscillator ON Start
This instruction enables the built-in oscillator circuit. A0 0 RW 0 DB7 1 DB6 0 DB5 1 DB4 0 DB3 1 DB2 0 DB1 1 DB0 1
Power Save
The ST7528 enters the Power Save status to reduce the power consumption to the static power consumption value and returns to the normal operation status by the following instructions.
Set Power Save Mode
A0 0 RW 0 DB7 1 DB6 0 DB5 1 DB4 0 DB3 1 DB2 0 DB1 0 DB0 P
P = 0: normal mode P = 1: sleep mode
Release Power Save Mode
A0 0 RW 0 DB7 1 DB6 1 DB5 1 DB4 0 DB3 0 DB2 0 DB1 0 DB0 1
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Set Power Save Mode (Sleep Mode)
Sleep Mode Oscillator Circuit: OFF LCD Power Supply Circuit: OFF All COM / SEG Output Level: VSS Consumption Current < 2uA
Release Power Save Mode (Sleep Mode)
Figure 25 Power Save Routine
Reset
This instruction Resets initial display line, column address, page address, and common output status select to their initial status, but dose not affect the contents of display data RAM. This instruction cannot initialize the LCD power supply, which is initialized by the RESETB pin. A0 0 RW 0 DB7 1 DB6 1 DB5 1 DB4 0 DB3 0 DB2 0 DB1 1 DB0 0
Set Data Direction & Display Data Length (3-Line SPI Mode)
Consists of 2 bytes instruction. This command is used in 3-Line SPI mode only (PS0 = "L" and PS1 = "L" ). It will be two continuous commands, the first byte control the data direction(write mode only) and inform the LCD driver the second byte will be number of data bytes will be write. When A0 is not used, the Display Data Length instruction is used to indicate that a specified number of display data bytes are to be transmitted. The next byte after the display data string is handled as command data.
The 1st Instruction: Set Data Direction (Only Write Mode)
A0 x RW x DB7 1 DB6 1 DB5 1 DB4 0 DB3 1 DB2 0 DB1 0 DB0 0
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The 2nd Instruction: Set Display Data Length (DDL) Register
A0 x RW x DB7 D7 DB6 D6 DB5 D5 DB4 D4 DB3 D3 DB2 D2 DB1 D1 DB0 D0
D7 0 0 0 : 1 1 1
D6 0 0 0 : 1 1 1
D5 0 0 0 : 1 1 1
D4 0 0 0 : 1 1 1
D3 0 0 0 : 1 1 1
D2 0 0 0 : 1 1 1
D1 0 0 1 : 0 1 1
D0 0 1 0 : 1 0 1
Display Data Length 1 2 3 : 254 255 256
NOP
No operation A0 0 RW 0 DB7 1 DB6 1 DB5 1 DB4 0 DB3 0 DB2 0 DB1 1 DB0 1
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Test Instruction
This instruction is for testing IC. Please do not use it. A0 0 RW 0 DB7 1 DB6 1 DB5 1 DB4 1 DB3 x DB2 x DB1 x DB0 x
Set FRC & PWM mode
Selects 3/4 FRC and 45 / 60 PWM FRC 0 1 0 0 1 1 0 1 0 1 PWM1 PWM0 Status of PWM & FRC 4FRC 3FRC 45PWM 45PWM 60PWM ---
NOTE: the value of register could not set [PWM1:PWM0]=[1:1] Set Gray Scale Mode & Register
Consists of 2 bytes instruction. The first byte sets grayscale mode and the second byte updates the contents of gray scale register without issuing any other instruction.
- Set Gray Scale Mode
A0 0 RW 0 DB7 1 DB6 0 DB5 GRAY3 DB4 GRAY2 DB3 GRAY1 DB2 GRAY0 Description In case of setting whit mode and 1 frame nd In case of setting whit mode and 2 frame rd In case of setting whit mode and 3 frame th In case of setting whit mode and 4 frame st In case of setting GRAY LEVEL 1 mode and 1 frame rd In case of setting GRAY LEVEL 1 mode and 2 frame rd In case of setting GRAY LEVEL 1 mode and 3 frame : In case of setting GRAY LEVEL 14 mode and 2 frame rd In case of setting GRAY LEVEL 14 mode and 3 frame th In case of setting GRAY LEVEL 14 mode and 4 frame st In case of setting dark mode and 1 frame nd In case of setting dark mode and 2 frame rd In case of setting dark mode and 3 frame th In case of setting dark mode and 4 frame
nd st
DB1 FRAMX1
DB0 FRAMX0
GRAY3 GRAY2 GRAY1 GRAY0 FRAMX1 FRAMX0 0 0 0 0 0 0 0 : 1 1 1 1 1 1 1 0 0 0 0 0 0 0 : 1 1 1 1 1 1 1 0 0 0 0 0 0 0 : 1 1 1 1 1 1 1 0 0 0 0 1 1 1 : 0 0 0 1 1 1 1 0 0 1 1 0 0 1 : 0 1 1 0 0 1 1 0 1 0 1 0 1 0 : 1 0 1 0 1 0 1
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--Set Gray Scale Register
A0 0 RW 0 DB7 X DB6 X DB5 GAX5 DB4 GAX4 DB3 GAX3 DB2 GAX2 DB1 GAX1 DB0 GAX0
GAX5 0 0 0 0 0 : 1 1 1 1 1 : 1 1 1 : 1
GAX4 0 0 0 0 0 : 0 0 0 0 0 : 1 1 1 : 1
GAX3 0 0 0 0 0 : 1 1 1 1 1 : 1 1 1 : 1
GAX2 0 0 0 0 1 : 0 1 1 1 1 : 0 1 1 : 1
GAX1 0 0 1 1 0 : 1 0 0 1 1 : 1 0 0 : 1
GAX0 0 1 0 1 0 : 1 0 1 0 1 : 1 0 1 : 1
Pulse width (45 PWM) 0/45 1/45 2/45 3/45 4/45 : 43/45 44/45 45/45 0/45 0/45 : 0/45 0/45 0/45 : 0/45
Pulse width (60 PWM) 0/60 1/60 2/60 3/60 4/60 : 43/60 44/60 45/60 46/60 47/60 : 59/60 60/60 0/60 : 0/60
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COMMAND DESCRIPTION
Referential Instruction Setup Flow: Initializing with the built-in Power Supply Circuits User System Setup by External Pins Start of Initialization
Power ON(VDD-VSS) Keeping the /RES Pin="L"
Waiting for Stabilizing the Power
/RES Pin="H"
User Application Setup by Internal Instructions [Display Duty Select] [ADC Select] [SHL Select] [COM0 Register Select] User LCD Power Setup by Internal Instructions [Oscillator ON] [Regulator Resistor] [Electronic Volume Register Select] [LCD Bias Register Select]
[ DC-DC Step-up Register Select] [ (DC[1:0]=00) booster 3 X ] Delay - 200m SEC [Power Control VC,VR,VF=1,0,0] [ DC-DC Step-up Register Select] [ (DC[1:0]=11) booster 6 X ] Delay - 200m SEC [Power Control VC,VR,VF=1,1,0] Delay - 10m SEC [Power Control VC,VR,VF=1,1,1]
End of Initialization
Figure 26 Initializing with the Built-in Power Supply Circuits
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Referential Instruction Setup Flow: Initializing without the built-in Power Supply Circuits User System Setup by External Pins Start of Initialization
Power ON(VDD-VSS) Keeping the /RES Pin="L"
Waiting for Stabilizing the Power
/RES Pin="H"
Set Power Save
User Application Setup by Internal Instructions [Display Duty Select] [ADC Select] [SHL Select] [COM0 Register Select] User LCD Power Setup by Internal Instructions [Oscillator ON] [Regulator Resistor] [Electronic Volume Register Select] [LCD Bias Register Select]
[ DC-DC Step-up Register Select] [ (DC[1:0]=00) booster 3 X ] Delay - 200m SEC [Power Control VC,VR,VF=1,0,0] [ DC-DC Step-up Register Select] [ (DC[1:0]=11) booster 6 X ] Delay - 200m SEC [Power Control VC,VR,VF=1,1,0] Delay - 10m SEC [Power Control VC,VR,VF=1,1,1] Release Power Save Waiting for Stabilizing the LCD Power Levels
End of Initialization
Figure 27 Initializing without Built-in Power Supply Circuits
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Referential Instruction Setup Flow: Data Displaying
End of Initialization
Display Data RAM Addressing by Instruction [Initial Display Line] [Set Page Address] [Set Column Address]
Write Display Data by Instruction [Display Data Write]
Turn Display ON/OFF Instruction [Display ON/OFF]
End of Data Display
Figure 28 Data Displaying
Referential Instruction Setup Flow: Power OFF
Optional Status
Set Power Save by Instruction
Power OFF(VDD-VSS)
End of Power OFF
Figure 29 Power OFF
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LIMITING VALUES
In accordance with the Absolute Maximum Rating System; see notes 1 and 2. Parameter Power Supply Voltage Power Supply Voltage External Reference Voltage Power supply voltage Power supply voltage Power supply voltage Input voltage Output voltage Operating temperature Storage temperature VDD VDD2 VEXT V0 VOUT_IN V1, V2, V3, V4 VIN VO TOPR TSTR Symbol Conditions -0.5 ~ +3.6 -0.5 ~ +3.6 2.0 ~ 3.3 3.5~15 -0.5 ~ +20 0.3 to VOUT_IN -0.5 to VDD+0.5 -0.5 to VDD+0.5 -30 to +85 -65 to +150 V V V V V V V V C C Unit
VLCD
V1 to V4
VDD
VDD
VSS System (MPU) side
VSS ST7528 chip side
VSS
Notes 1. Stresses above those listed under Limiting Values may cause permanent damage to the device. 2. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless otherwise noted. 3. Insure that the voltage levels of V1, V2, V3, and V4 are always such that VOUT_IN V0 V1 V2 V3 V4 Vss
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DC CHARACTERISTICS
VDD = 1.8 V to 3.3V; VSS = 0 V; VLCD = 3.0 to 13.0V; Tamb = -30 to +85; unless otherwise specified. Item Symbol Condition Rating Min. 1.8 Typ. -- Max. 3.3 Units Applicable Pin Vss*1
Operating Voltage (1)
VDD
V
Operating Voltage (2) High-level Input Voltage Low-level Input Voltage High-level Output Voltage Low-level Output Voltage Input leakage current Output leakage current
VDD2 VIHC VILC VOHC VOLC ILI ILO
(Relative to VSS)
2.4
--
3.3 VDD
V V
VSS2 *2 *2 *3 *3 *4 *5
0.7 x VDD -- VSS IOH=1mA IOL=-1mA VIN = VDD or VSS VIN = VDD or VSS Ta = VOUT_IN = 15.0 V --
0.3 x VDD V VDD V
0.7 x VDD -- VSS -1.0 -3.0 -- -- -- -- 2.0
0.3 x VDD V 1.0 3.0 3.5 K A A
Liquid Crystal Driver ON Resistance
RON
25C
SEGn COMn *6
(Relative VOUT_IN = To VSS) 8.0 V
-- 570.57
3.2
5.4 kHz kHz kHz Hz *7 OSC
Default Oscillator Frequency
Internal Oscillator fOSC External Input Mode0 fCL fOSC fFRAME 128 line Ta = 25C 60 PWM
600.6 630.63 600.6 630.63 959.4 1151.28 77 80.85
570.57 767.52 73.15
Max OSC under FR=1,1,1,1 Mode 10 Default Frame frequency
Item Input voltage Internal Power Supply Step-up output voltage Circuit Voltage regulator Circuit Operating Voltage
Symbol VDD VOUT_OUT
Condition (Relative To VSS) (Relative To VSS)
Rating Min. 1.8 -- Typ. -- -- Max. 3.3 18
Units V V
Applicable Pin
VOUT_OUT
VOUT_IN
(Relative To VSS)
--
--
18
V
VOUT_IN
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Bare Dice Consumption Current : During Display, with the Internal Power Supply, Current consumed by total ICs when an external power supply(VDD,VDD2) is used . Test pattern Symbol Condition VDD = 3.3 V, Display Pattern SNOW ISS V0 - VSS = 10.7 V 5X booster 1/11 bias Power Down ISS Ta = 25C -- 0.01 2 A *9 -- 550 650 A *8 Rating Min. Typ. Max. Units Notes
Notes to the DC characteristics 1. The maximum possible VOUT voltage that may be generated is dependent on voltage, temperature and (display) load. 2. Internal clock 3. Power-down mode. During power down all static currents are switched off. 4. If external VLCD, the display load current is not transmitted to I DD. 5. VOUT external voltage applied to VOUT_IN pin; VOUT_IN disconnected from VOUT_OUT
References for items market with *
*1 While a broad range of operating voltages is guaranteed, performance cannot be guaranteed if there are sudden fluctuations to the voltage while the MPU is being accessed. *2 The A0, D0 to D5, D6 (SI), D7 (SCL), /RD (E), /WR ,/(R/W), CSB, IMS, OSC, P/S, /DOF, RESB ,and MODE terminals. *3 The D0 to D7, and OSC terminals. *4 The A0,/RD (E), /WR ,/(R/W), CSB, IMS, OSC, P/S, /DOF, RESB ,and MODE terminals. *5 Applies when the D0 to D5, D6 (SI), D7 (SCL) terminals are in a high impedance state. *6 These are the resistance values for when a 0.1 V voltage is applied between the output terminal SEGn or COMn and the various power supply terminals (V1, V2, V3, and V4). These are specified for the operating voltage range. RON = 0.1 V /I (Where I is the current that flows when 0.1 V is applied while the power supply is ON.) *7 The relationship between the oscillator frequency and the frame rate frequency. *8,9 It indicates the current consumed on bare dice when the internal oscillator circuit and display are turned on.
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TIMING CHARACTERISTICS
System Bus Read/Write Characteristics 1 (For the 8080 Series MPU)
A0 tAW8 tAH8
/CS tCYC8
tF
WR,RD
tCCLR,tCCLW
tR
tCCHR,tCCHW
tDS8 D0 to D7 (Write)
tDH8
tACC8 D0 to D7 (Read)
tOH8
Figure 26.
(VDD = 3.3V , Ta =-30~85C) Item Address hold time Address setup time System cycle time Enable L pulse width (WRITE) Enable H pulse width (WRITE) Enable L pulse width (READ) Enable H pulse width (READ) WRITE Data setup time WRITE Data hold time READ access time READ Output disable time tF tR D0 to D7 WR A0 Signal Symbol tAH8 tAW8 tCYC8 tCCLW tCCHW tCCLR tCCHR tDS8 tDH8 tACC8 tOH8 CL = 100 pF CL = 100 pF Condition Rating Min. 0 0 240 80 80 140 80 40 10 -- 5 -- -- -- -- 70 50 10 10 Max. -- -- -- -- -- -- ns Units
RD
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(VDD = 2.7 V , Ta = -30~85C ) Item Address hold time Address setup time System cycle time Enable L pulse width (WRITE) Enable H pulse width (WRITE) Enable L pulse width (READ) Enable H pulse width (READ) WRITE Data setup time WRITE Data hold time READ access time READ Output disable time tF tR D0 to D7 WR A0 Signal Symbol tAH8 tAW8 tCYC8 tCCLW tCCHW tCCLR tCCHR tDS8 tDH8 tACC8 tOH8 CL = 100 pF CL = 100 pF Condition Rating Min. 0 0 400 220 180 220 180 40 15 -- 10 -- -- Max. -- -- -- -- -- -- -- -- -- 140 100 10 10 ns Units
RD
(VDD = 1.8V , Ta = -30~85C ) Item Address hold time Address setup time System cycle time Enable L pulse width (WRITE) Enable H pulse width (WRITE) Enable L pulse width (READ) Enable H pulse width (READ) WRITE Data setup time WRITE Data hold time READ access time READ Output disable time tF tR D0 to D7 WR A0 Signal Symbol tAH8 tAW8 tCYC8 tCCLW tCCHW tCCLR tCCHR tDS8 tDH8 tACC8 tOH8 CL = 100 pF CL = 100 pF Condition Rating Min. 0 0 640 360 280 360 280 80 30 -- 10 -- -- -- -- 240 200 10 10 Max. -- -- -- -- -- -- ns Units
RD
*1 The input signal rise time and fall time (tr, tf) is specified at 15 ns or less. When the system cycle time is extremely fast, (tr +tf) (tCYC8 - tCCLW - tCCHW) for (tr + tf) (tCYC8 - tCCLR - tCCHR) are specified. *2 All timing is specified using 20% and 80% of VDD as the reference. *3 tCCLW and tCCLR are specified as the overlap between CSB being "L" and WR and RD being at the "L" level.
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System Bus Read/Write Characteristics 1 (For the 6800 Series MPU)
A0 R/W tAW6 CS1 (CS2="1") tCYC6 tAH6
tR
E
tewLR ,tewLW
tF
tewHR,tewHW
tDS6 D0 to D7 (Write)
tDH6
tACC6 D0 to D7 (Read)
tOH6
Figure 30
(VDD = 3.3 V,Ta = -30~85C ) Item Address hold time Address setup time System cycle time Enable L pulse width (WRITE) Enable H pulse width (WRITE) Enable L pulse width (READ) Enable H pulse width (READ) WRITE Data setup time WRITE Data hold time READ access time READ Output disable time tF tR D0 to D7 E_WR A0 Signal Symbol tAH6 tAW6 tCYC6 tEWLW tEWHW tEWLR tEWHR tDS6 tDH6 tACC6 tOH6 CL = 100 pF CL = 100 pF Condition Rating Min. 0 0 240 80 80 80 140 40 10 -- 5 -- -- -- -- 70 50 10 10 Max. -- -- -- -- -- -- ns Units
E_RD
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(VDD = 2.7V,Ta =-30~85C ) Item Address hold time Address setup time System cycle time Enable L pulse width (WRITE) Enable H pulse width (WRITE) Enable L pulse width (READ) Enable H pulse width (READ) WRITE Data setup time WRITE Data hold time READ access time READ Output disable time tF tR D0 to D7 WR A0 Signal Symbol tAH6 tAW6 tCYC6 tEWLW tEWHW tEWLR tEWHR tDS6 tDH6 tACC6 tOH6 CL = 100 pF CL = 100 pF Condition Rating Min. 0 0 400 220 180 220 180 40 15 -- 10 -- -- Max. -- -- -- -- -- -- -- -- -- 140 100 10 10
Units
RD
ns
(VDD =1.8V,Ta =-30~85C ) Item Address hold time Address setup time System cycle time Enable L pulse width (WRITE) Enable H pulse width (WRITE) Enable L pulse width (READ) Enable H pulse width (READ) WRITE Data setup time WRITE Data hold time READ access time READ Output disable time tF tR D0 to D7 WR A0 Signal Symbol tAH6 tAW6 tCYC6 tEWLW tEWHW tEWLR tEWHR tDS6 tDH6 tACC6 tOH6 CL = 100 pF CL = 100 pF Condition Rating Min. 0 0 640 360 280 360 280 80 30 -- 10 -- -- Max. -- -- -- -- -- -- -- -- -- 240 200 10 10 ns Units
RD
*1 The input signal rise time and fall time (tr, tf) is specified at 15 ns or less. When the system cycle time is extremely fast, (tr +tf) (tCYC6 - tEWLW - tEWHW) for (tr + tf) (tCYC6 - tEWLR - tEWHR) are specified. *2 All timing is specified using 20% and 80% of VDD as the reference. *3 tEWLW and tEWLR are specified as the overlap between CSB being "L" and E.
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SERIAL INTERFACE (4-Line Interface)
tCCSS /CS1 (CS2="1") tSAS A0 tSCYC tSLW SCL tSHW tf tSDS SI tr tSDH tSAH tCSH
Figure 31 (VDD=3.3V,Ta=-30~85) Item Serial Clock Period SCL "H" pulse width SCL "L" pulse width Address setup time Address hold time Data setup time Data hold time CS-SCL time CS-SCL time A0 SCL Signal Symbol tSCYC tSHW tSLW tSAS tSAH tSDS tSDH tCSS tCSH Condition Rating Min. 50 25 25 20 10 20 10 20 40 Max. -- -- -- -- -- -- -- -- -- ns Units
SI
CSB
(VDD=2.7V,Ta=-30~85) Item Serial Clock Period SCL "H" pulse width SCL "L" pulse width Address setup time Address hold time Data setup time Data hold time CS-SCL time CS-SCL time A0 SCL Signal Symbol tSCYC tSHW tSLW tSAS tSAH tSDS tSDH tCSS tCSH Condition Rating Min. 100 50 50 30 20 30 20 30 60 Max. -- -- -- -- -- -- -- -- -- ns Units
SI
CSB
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(VDD=1.8V,Ta=-30~85) Item Serial Clock Period SCL "H" pulse width SCL "L" pulse width Address setup time Address hold time Data setup time Data hold time CS-SCL time CS-SCL time A0 SCL Signal Symbol tSCYC tSHW tSLW tSAS tSAH tSDS tSDH tCSS tCSH Condition Rating Min. 200 80 80 60 30 60 30 40 100 Max. -- -- -- -- -- -- -- -- -- ns Units
SI
CSB
*1 The input signal rise and fall time (tr, tf) are specified at 15 ns or less. *2 All timing is specified using 20% and 80% of VDD as the standard. SERIAL INTERFACE(3-Line Interface)
tCCSS /CS1 (CS2="1") tCSH
tSCYC tSLW SCL tSHW tf tSDS SI tr tSDH
Figure 32 (VDD=3.3V,Ta=-30~85) Item Serial Clock Period SCL "H" pulse width SCL "L" pulse width Data setup time Data hold time CS-SCL time CS-SCL time SI CSB SCL Signal Symbol tSCYC tSHW tSLW tSDS tSDH tCSS tCSH Condition Rating Min. 50 25 25 20 10 20 40 Max. -- -- -- -- -- -- -- ns Units
(VDD=2.7V,Ta=-30~85)
Ver2.3
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2007/1/3
ST7528
Item Serial Clock Period SCL "H" pulse width SCL "L" pulse width Data setup time Data hold time CS-SCL time CS-SCL time SI SCL Signal Symbol tSCYC tSHW tSLW tSDS tSDH tCSS tCSH Condition Rating Min. 100 50 50 30 20 30 60 Max. -- -- -- -- -- -- -- ns Units
CSB
(VDD=1.8V,Ta=-30~85) Item Serial Clock Period SCL "H" pulse width SCL "L" pulse width Data setup time Data hold time CS-SCL time CS-SCL time SI SCL Signal Symbol tSCYC tSHW tSLW tSDS tSDH tCSS tCSH Condition Rating Min. 200 80 80 60 30 40 100 Max. -- -- -- -- -- -- -- ns Units
CSB
*1 The input signal rise and fall time (tr, tf) are specified at 15 ns or less. *2 All timing is specified using 20% and 80% of VDD as the standard.
Ver2.3
79/97
2007/1/3
ST7528
SERIAL INTERFACE(IIC Interface)
SDA
tBUF tLOW tHIGH tSU;DAT
SCL tDH;STA SDA tr tHD;DAT tf
tSU;STA
Figure 33
tSU;STO
(VDD=3.3V,Ta=-30~85) Item SCL clock frequency SCL clock low period SCL clock high period Data set-up time Data hold time SCL,SDA rise time SCL,SDA fall time Capacitive load represented by each bus line Setup time for a repeated START condition Start condition hold time Setup time for STOP ondition Tolerable spike width on bus BUS free time between a STOP and StART condition SCL SI SI Signal Symbol SCL SCL SCL SI SI SCL SCL FSCLK TLOW THIGH TSU;Data THD;Data TR TF Cb TSU;SUA THD;STA TSU;STO TSW TBUF Condition 1.3 0.6 100 0 Rating Min. Max. 400 0.9 Units kHZ us us ns us ns ns pF us us us ns us
20+0.1Cb 300 20+0.1Cb 300 0.6 0.6 0.6 1.3 400 50
Ver2.3
80/97
2007/1/3
ST7528
RESET TIMING
tRW /RES
tR Internal status During reset Reset complete
Figure 34 (VDD = 3.3V , Ta = -30 to 85C ) Item Reset time Reset "L" pulse width RESB Signal Symbol tR tRW Condition Rating Min. -- 1 Typ. -- -- Max. 1 -- Units us us
(VDD = 2.7V , Ta = -30 to 85C ) Item Reset time Reset "L" pulse width RESB Signal Symbol tR tRW Condition Rating Min. -- 1.5 Typ. -- -- Max. 1.5 -- Units us us
(VDD = 1.8V , Ta = -30 to 85C ) Item Reset time Reset "L" pulse width RESB Signal Symbol tR tRW Condition Rating Min. -- 2.0 Typ. -- -- Max. 2.0 -- Units us us
Ver2.3
81/97
2007/1/3
ST7528
POWER PAD CONNECT
The pinning of the ST7528 is optimized for single plane wiring e.g. for chip-on-glass display modules. Display size: 160 X 100 pixels or 132 X 128 pixels.
Display 160 X 100 pixels Display 132 X 128 pixels
COM
SEG
COM
ST7528 VDD2 VDD VSS1 VSS2
*6 if external oscillator
Cvout I/O VDD CVDD VSS
Figure 35 Application diagram: internal charge pump is used and s single V DD
Display 160 X 100 pixels Display 132 X 128 pixels
COM
SEG
VOUT_OUT VOUT_IN
COM
ST7528 VDD2 VDD VSS1 VSS2
*6 if external oscillator
VDD CVDD1 Cvout I/O VDD2 CVDD2 VSS
Figure 36 Application diagram: Internal charge pump is used and two separate VDD(VDD2)
Ver2.3
82/97
VOUT_OUY VOUT_IN
2007/1/3
ST7528
Display 160 X 100 pixels Display 132 X 128 pixels
COM
SEG
COM
ST7528 VDD2 VDD VSS1 VSS2
*6 if external oscillator
I/O VDD2 CVDD VSS
Figure 37 application diagram : External high voltage generation is used
The required minimum value for the external capacitors in an application with the ST7528 are: CVLCD = min. 100nF CVDD,2= min. 1.0 F
Higher capacitor values are recommended for ripple reduction.
Ver2.3
83/97
VOUT_OUT VOUT_IN
VL2
2007/1/3
ST7528
THE MPU INTERFACE (REFERENCE EXAMPLES)
The ST7528 Series can be connected to either60X86 Series MPUs or to 6800Series MPUs. Moreover, using the serial interface it is possible to operate the ST7528 series chips with fewer signal lines. The display area can be enlarged by using multiple ST7528 Series chips. When this is done, the chip select signal can be used to select the individual ICs to access. (1) 8080 Series MPUs
VDD VCC A0 CS1
MPU
VDD A0 CS1 D0 to D7 E (/RD) R/W (/WR) /RES RESET VSS VSS
ST7528
DO to D7 RD WR RES
GND
(2) 6800 Series MPUs
VDD VCC A0 CS1 MPU DO to D7 E R/W RES RESET A0 CS1 D0 to D7 /RD (E) /W R (R/W ) /RES VSS VSS ST7541 PS
VDD VCC A0 CS1
MPU
VDD IM S
GND
(3) Using the Serial Interface (4-line interface)
V DD A0
ST7528
CS1
Port 1 Port 2 RES GND RESET
SI SCL /RES VSS V SS
Ver2.3
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2007/1/3
ST7528
(4) Using the Serial Interface (3-line interface)
VDD VCC VDD
Port 1 Port 2 RES GND RESET
SI SCL /RES VSS VSS
(5) Using the Serial Interface (IIC interface)
VDD VCC R MPU R ST7528 VSS VSS VDD
Port 1 Port 2 RES RESET
SDA SCL /RES
GND
Ver2.3
85/97
ST7528
CS1 MPU
CS1
2007/1/3
ST7528
APPLICATION Program Example
16-Gray programming example for ST7528 SETP 0 1 Start A0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 1 0 1 0 1 0 0 1 0 x' 0 0 SERIAL BUS BYTE DISPLAY OPERATION CSB IS going low. Mode Set. FR[3:0] = 0000 BE = 1 EXT= 0 (Normal INST. Mode) 2 A0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 3.a 1 0 1 0 1 0 1 1 Set DC-DC Step up Set Vout Set Ra/Rb Set R[2:0] Set EV Set Ev[5:0] Ev0 Set Bias Set B[2:0] Mode Set. EXT= 1 (Extension INST. Mode) Gray-Scale Setting Mode Set. EXT= 0 (Normal INST. Mode) SET Power Control Booster ON Regulator ON Follower ON 5.b A0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 6 1 0 1 0 1 1 1 1 Display control. Display on Data Write. Y,X are initialized to 0 by default, so they aren't set here... OSC ON
A0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 1 1 0 0 1 DC1 DC0
3.b
A0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 1 0 R2 R1 R0
3.c A0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 3.d 1 x' 0 x' 0 Ev5 0 Ev4 0 0 Ev3 0 Ev2 1 Ev1
A0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 1 0 1 0 B2 B1 B0
4.a
A0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 1 0 1 0 1 0 0 1 0 x' 0 1
4.b 4.c
SET pulse width of Gray scale A0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 1 0 1 0 1 0 0 1 0 x' 0 0
5.a
A0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 1 0 1 1 1 1
A0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0
Ver2.3
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ST7528
7 A0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 1 1 1 1 8 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 Data Write. Data Write.
A0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1
9
A0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1
Data Write.
10
A0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0
Data Write.
11
A0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Data Write.
12
A0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1
Data Write.
13
A0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Data Write.
Ver2.3
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2007/1/3
ST7528
14 A0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 1 1 1 1 15 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 Display Control. Set Reverse display mode REV=1 Data Write.
A0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 1 0 1 0 0 1 1 1
16
A0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0
Set column address of RAM. Set address to "00000000". Y[9:2]=00000000 (Y[1:0] default is 00)
17
A0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Data Write.
programming example for ST7528(Use IIC Interface)
SETP 1 2
SERIAL BUS BYTE IIC INTERFACE Start DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
DISPLAY
OPERATION
Slave address for write
3 4
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 0 0
Control byte with cleared Co bit and A0 set to logic 0 Mode Set. FR[3:0] = 0000 BE= 1 EXT= 0 (Normal INST. Mode)
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 1 0 1 0 1 0 0 1 0 x' 0 0
5
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 1 0 1 0 1 0 1 1
OSC ON
6.a
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 1 1 0 0 1 DC1 DC0
Set DC-DC Step up Set Vout Set Ra/Rb Set R[2:0] Set EV
6.b
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 1 0 R2 R1 R0
6.c
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Ver2.3
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2007/1/3
ST7528
1 x' 6.d 0 x' 0 Ev5 0 Ev4 0 0 Ev3 0 Ev2 1 Ev1 Ev0 Set Bias Set B[2:0] Mode Set. EXT= 1 (Extension INST. Mode) Gray-Scale Setting Mode Set. EXT= 0 (Normal INST. Mode) SET Power Control Booster ON Regulator ON Follower ON 8.b DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 1 9 10 0 1 0 1 1 1 1 Display control. Display on restart Slave address for write Set Ev[5:0]
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 1 0 1 0 B2 B1 B0
7.a
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 1 0 1 0 1 0 0 1 0 x' 0 1
7.b 7.c
SET pulse width of Gray scale DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 1 0 1 0 1 0 0 1 0 x' 0 0
8.a
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 1 0 1 1 1 1
IIC INTERFACE Start DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
11
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 1 0 0 0 0 0 0
Control byte with clear Co bit and A0 set to logic 1 Data Write. Y,X are initialized to 0 by default, so they aren't set here...
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 12 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 13 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1
Data Write.
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 14 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1
Data Write.
Ver2.3
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2007/1/3
ST7528
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 15 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 Data Write. Data Write.
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 16 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 17 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Data Write.
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 18 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1
Data Write.
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 19 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Data Write.
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 20 0 0 0 21 22 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1
Data Write.
IIC INTERFACE start DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
restart Slave address for write
23
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 1 0 0 0 0 0 0 0
Control byte with set Co bit and A0 set to logic 0
Ver2.3
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2007/1/3
ST7528
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 24 1 0 1 0 0 1 1 1 Display Control. Set Reverse display mode REV=1
25
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 1 0 0 0 0 0 0 0
Control byte with set Co bit and A0 set to logic 0 Set column address of RAM. Set address to "00000000". Y[9:2]=00000000 (Y[1:0] default is 00)
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 26 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0
27
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 1 1 0 0 0 0 0 0
Control byte with set Co bit and A0 set to logic 1 Data Write.
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 28 0 0 0 29 30 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
IIC INTERFACE start DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
restart Slave address for write
31
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 1 0 0 0 0 0 0 0
Control byte with set Co bit and A0 set to logic 0 Set X address of RAM. Set address to "0000000".
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 32 1 0 0 0 0 0 0 0
33
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 1 0 0 0 0 0 0 0
Control byte with cleared Co bit and A0 set to logic 0
Ver2.3
91/97
2007/1/3
ST7528
ST7528 APPICATION NOTE
ST7528
Internal analog circuit Mode 0, Resolution : 129(128COM+ICON)*132(SEG) Interface:8080 series OSC1:External for input (the same pin shoud be connected together, for example,pin246(D0) connect to pin247(D0) exclude power pin) PS0:VDD PS1:VSS PS2:VSS Mode:VSS TA:VDD REF:VDD INTRS:VDD VR:OPEN VEXT:OPEN T0~T9:OPEN MF[2:0]:VDD OR VSS=(0,0,0) DS[1:0]:VDD OR VSS=(1,0) (MF[2:0]&DS[1:0] is ID of this IC, these pins cannot be left open) C=1uF
................
385
COM31
1
COM30
COM51
................
365
364 ............
COM52 ............ COM63 V0 V1 V2 V3 V4 VR VDD OSC1 VSS INTRS VDD VEXT VSS REF VDD T8~T0
VOUT_IN
VOUT_OUT
353 .......................................... ..........................................
351~352
350 349 348 347
345~346
344
342~343
341 340 31 32 33 COM0 COMS1 SEG0 339 338 337 336 335
326~334 320~325 314~319
313 ....................................................... ....................................................... 312 311 310 309 308 307 306
300~305 284~299 268~283 262~267 260~261 258~259 256~257 254~255 252~253
VDD DS1 DS0 MF0 MF1 MF2 TA Mode VSS VSS2 VDD2 VDD D7 D6 D5 D4 D3 D2 D1 D0 E_RD RW_WR A0 RST CSB VSS PS2 PS1 PS0 VDD T9 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 V0 V2 V3 V4 VOUT D7 D6 D5 D4 D3 D2 D1 D0 E_RD RW_WR A0 RST CSB VSS VDD C CCCC V1
163 164 165
SEG130 SEG131 COM64
ST7528
250~251 248~249 246~247 244~245 242~243 240~241 238~239 236~237
235 ........................................................ ........................................................ 234 233 232 231 230
229 228
COMS2 COM127
................
197
196
COM95 COM96
................ COM116
217
218
COM117
................
Ver2.3
................
92/97
2007/1/3
ST7528
ST7528
Internal analog circuit Mode1: Resolution : 101(100COM+ICON)*160(SEG) Interface : 4 SPI OSC1:External for input (the same pin shoud be connected together, for example,pin246(D0) connect to pin247(D0) exclude power pin)
................
PS0:VSS PS1:VDD PS2:VSS Mode:VDD TA:VDD REF:VDD INTRS:VDD
VR:OPEN VEXT:OPEN T0~T9:OPEN MF[2:0]:VDD OR VSS=(0,0,0) DS[1:0]:VDD OR VSS=(1,0) (MF[2:0]&DS[1:0] is ID of this IC, these pins cannot be left open) C=1uF
385
................ COM17 1 COM16 COM37 364 ............ COM38 ............ COM49 V0 V1 V2 V3 V4 VR VDD OSC1 VSS INTRS VDD VEXT VSS REF VDD T8~T0
VOUT_IN
VOUT_OUT
365
353 .......................................... ..........................................
351~352
350 349 348 347
345~346
344
342~343
341 340 17 18 19 COM0 COMS1 SEG0 339 338 337 336 335
326~334 320~325 314~319
313 ....................................................... ....................................................... 312 311
VDD DS1 DS0 MF0 MF1 MF2 TA Mode VSS VSS2 VDD2 VDD D7 D6 D5 D4 D3 D2 D1 D0 E_RD RW_WR A0 RST CSB VSS PS2 PS1 PS0 VDD T9 13 12 11 10 9 8 7 6 5 4 3 2 1 V0 V1 V2 V3 V4 VOUT SID SCLK A0 RST CSB VSS VDD C CC C C
ST7528
SEG158 SEG159 COM50
310 309 308 307 306
300~305 284~299 268~283 262~267 260~261 258~259 256~257 254~255 252~253
177 178 179
250~251 248~249 246~247 244~245 242~243 240~241 238~239 236~237
235 ........................................................ ........................................................ 234 233 232 231 230
229 228
COMS2 COM99
................
197
196
COM67 COM68
................ COM88
217
218
COM89
................
Ver2.3
................
93/97
2007/1/3
ST7528
ST7528
Internal analog circuit Mode1: Resolution : 101(100COM+ICON)*160(SEG) Interface : 3 SPI OSC1:External for input (the same pin shoud be connected together, for example,pin246(D0) connect to pin247(D0) exclude power pin)
................
PS0:VSS PS1:VSS PS2:VSS Mode:VDD TA:VDD REF:VDD INTRS:VDD
VR:OPEN VEXT:OPEN T0~T9:OPEN MF[2:0]:VDD OR VSS=(0,0,0) DS[1:0]:VDD OR VSS=(1,0) (MF[2:0]&DS[1:0] is ID of this IC, these pins cannot be left open) C=1uF
385
................ COM17 1 COM16 COM37 364 ............ COM38 ............ COM49 V0 V1 V2 V3 V4 VR VDD OSC1 VSS INTRS VDD VEXT VSS REF VDD T8~T0
VOUT_IN
VOUT_OUT
365
353 .......................................... ..........................................
351~352
350 349 348 347
345~346
344
342~343
341 340 17 18 19 COM0 COMS1 SEG0 339 338 337 336 335
326~334 320~325 314~319
313 ....................................................... ....................................................... 312 311
VDD DS1 DS0 MF0 MF1 MF2 TA Mode VSS VSS2 VDD2 VDD D7 D6 D5 D4 D3 D2 D1 D0 E_RD RW_WR A0 RST CSB VSS PS2 PS1 PS0 VDD T9 4 3 2 1 RST CSB VSS VDD 12 11 10 9 8 7 6 5 V0 V1 V2 V3 V4 VOUT SID SCLK C CC C ................ C
ST7528
SEG158 SEG159 COM50
310 309 308 307 306
300~305 284~299 268~283 262~267 260~261 258~259 256~257 254~255 252~253
177 178 179
250~251 248~249 246~247 244~245 242~243 240~241 238~239 236~237
235 ........................................................ ........................................................ 234 233 232 231 230
229 228
COMS2 COM99
197
196
COM67 COM68
................ COM88
217
218
................ COM89 ................
Ver2.3
94/97
2007/1/3
ST7528
ST7528
Internal analog circuit Mode0, Resolution : 129(128COM+ICON)*132(SEG) Interface : I2C OSC1:External for input (the same pin shoud be connected together, for example,pin246(D0) connect to pin247(D0) exclude power pin) SA[1:0]:VDD OR VSS=(0,0) (SA[1:0] are Slave address of I2C)
................
PS0:VSS PS1:VSS PS2:VDD Mode:VSS TA:VDD REF:VDD INTRS:VDD
VR:OPEN VEXT:OPEN T0~T9:OPEN MF[2:0]:VDD OR VSS=(0,0,0) DS[1:0]:VDD OR VSS=(1,0) (MF[2:0]&DS[1:0] is ID of this IC, these pins cannot be left open) C=1uF ; R=10K
385
................ COM31 1 COM30 COM51 364 ............ COM52 ............ COM63 V0 V1 V2 V3 V4 VR VDD OSC1 VSS INTRS VDD VEXT VSS REF VDD T8~T0
VOUT_IN
VOUT_OUT
365
353 .......................................... ..........................................
351~352
350 349 348 347
345~346
344
342~343
341 340 31 32 33 COM0 COMS1 SEG0 339 338 337 336 335
326~334 320~325 314~319
313 ....................................................... ....................................................... 312 311 310 309 308 307 306
300~305 284~299 268~283 262~267 260~261 258~259 256~257 254~255 252~253
VDD DS1 DS0 MF0 MF1 MF2 TA Mode VSS VSS2 VDD2 VDD D7(SCL) D6(SDA_IN) D5(SDA_IN) D4(SDA_IN)
D3(SDA_OUT) D2(SDA_OUT)
ST7528
11 10 9 8 7 6 5 4 3 2 1
V0 V2 V3 V4 VOUT SCL SDA RST VSS VDD R R CCC C C V1
163 164 165
SEG130 SEG131 COM64
250~251 248~249 246~247 244~245 242~243 240~241 238~239 236~237
D1(SA1) D0(SA0) E_RD RW_WR A0 RST CSB VSS PS2 PS1 PS0 VDD T9
235 ........................................................ ........................................................ 234 233 232 231 230
229 228
COMS2 COM127
................
196
COM95 COM96
................ COM116
217
197
218
COM117
................
Ver2.3
................
95/97
2007/1/3
ST7528
ST7528
Internal analog circuit Mode1: Resolution : 101(100COM+ICON)*160(SEG) Interface : 8080 interface OSC1:External for input External VOUT from VOUT_IN (the same pin shoud be connected together, for example,pin246(D0) connect to pin247(D0) exclude power pin)
................
PS0:VDD PS1:VSS PS2:VSS Mode:VDD TA:VDD REF:VDD INTRS:VDD
VR:OPEN VEXT:OPEN T0~T9:OPEN MF[2:0]:VDD OR VSS=(0,0,0) DS[1:0]:VDD OR VSS=(1,0) (MF[2:0]&DS[1:0] is ID of this IC, these pins cannot be left open) C=1uF
385
................ COM17 1 COM16 COM37 364 ............ COM38 ............ COM49 V0 V1 V2 V3 V4 VR VDD OSC1 VSS INTRS VDD VEXT VSS REF VDD T8~T0
VOUT_IN
VOUT_OUT
365
353 .......................................... ..........................................
351~352
350 349 348 347
345~346
344
342~343
341 340 17 18 19 COM0 COMS1 SEG0 339 338 337 336 335
326~334 320~325 314~319
313 ....................................................... ....................................................... 312 311
VDD DS1 DS0 MF0 MF1 MF2 TA Mode VSS VSS2 VDD2 VDD D7 D6 D5 D4 D3 D2 D1 D0 E_RD RW_WR A0 RST CSB VSS PS2 PS1 PS0 VDD T9 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 D7 D6 D5 D4 D3 D2 D1 D0 RD WR A0 RST CSB VSS VDD 21 20 19 18 17 16 V0 V1 V2 V3 V4 VOUT_IN C ................ CC C C
ST7528
SEG158 SEG159 COM50
310 309 308 307 306
300~305 284~299 268~283 262~267 260~261 258~259 256~257 254~255 252~253
177 178 179
250~251 248~249 246~247 244~245 242~243 240~241 238~239 236~237
235 ........................................................ ........................................................ 234 233 232 231 230
229 228
COMS2 COM99
197
196
COM67 COM68
................ COM88
217
218
................ COM89 ................
Ver2.3
96/97
2007/1/3
ST7528
Reversion History
1.5V 1.6V 1.7V 1.8V 2004/6/29 2004/7/21 2004/10/12 2004/11/26 80,68,IIC Timing character definition Modify Application Note VDD, VSS routing Add Timing parameter , tF and tR
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Modify Vout Max limitation from 15V to 18V Add VEXT using range (2.0V~3.3V) Modify Frame rate frequency typical and Max/Min value. Modify 3FRC/4FRC setting description (page 33). Add description about the Panel Size large than 1.6", the VOP can not set over 12 voltage. Add description about IIC interface can not use with other IIC slaver device. Modify page 29, 30 key error. Change "partial display duty ratio" to "select partial display line". Add description on instruction of Frame Frequency to suitable for no partial display. Add release bias power save instruction. Remove page-3 "PAD NO 352 ~ 353: 913 um Change VDD1 to VDD. PAD NO 229 ~ 230: 84 um".
1.9V
2005/01/18
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2.0V 2.1V 2.2V 2.3V
2005/10/05 2005/10/20 2005/12/22 2005/12/27
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Modify E_RD , RW_WR , Pin description, and add VR,VEXT ITO resister limitation. Modify PAD Coordinates.
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Add DS1.DS0 recommended setting. Modify ADC description mistake.
Ver2.3
97/97
2007/1/3

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