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APL3201 Li+ Battery Charger with Thermal Regulation Features * * * * * * * * * * * Programmable Charge Current Up to 1A Charge Status Output Pins Soft-Start Limits Inrush Current 4.2V Charge Voltage with 1% Accuracy Fixed 55mA Prequal Charge Current Thermal Limiting Simplifies Board Design External Thermistor Monitor Enable/Disable Control 3mm x 3mm DFN-10 Package (DFN3x3-10) Disable Charging When VIN > 6.4V Lead Free and Green Devices Available (RoHS Compliant) General Description The APL3201 is a constant-current/constant-voltage linear charger for single cell Li+ batteries. The APL3201 needs no external MOSFET or diodes, and accepts input voltage up to 6.0V. The small packages and low external component count make the APL3201 ideally suited for portable applications. On-chip thermal limiting simplifies PC board layout and allows optimum charging rate without the thermal limits imposed by worst-case battery and input voltage. When the APL3201 thermal limit is reached, the charger does not shut down but simply reduces charging current. Ambient or battery temperature can be monitored with an external thermistor. When the temperature is out of range, charging pauses. Other features include the STAT1 and 2 outputs to indicate four charge states, and the EN input, switches the APL3201 on or off. The APL3201 is available in 3mmx3mm DFN-10 package, and operates over the -40C to +85C temperature range. Applications * * * * PDAs MP3 Players Cell Phones Wireless Appliances Simplified Application Circuit LI+ CELL Pin Configuration VIN STAT1 ISET GND EN 1 2 3 4 5 10 BATT 9 BYP 8 STAT2 7 REF 6 THRM INPUT Voltage VIN BATT STAT1 STAT2 BYP REF EN ISET GND THRM NTC THERMISTOR EP (Bottom) DFN3x3-10 (Top View) Note : EP should be connected to GND plane for better heat dissipation ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. Copyright (c) ANPEC Electronics Corp. Rev. A.4 - Mar., 2009 1 www.anpec.com.tw APL3201 Ordering and Marking Information APL3201 Assembly Material Handling Code Temperature Range Package Code APL 3201 XXXXX Package Code QA : DFN3x3-10 Operating Ambient Temperature Range I : -40 to 85 oC Handling Code TR : Tape & Reel Assembly Material G : Halogen and Lead Free Device XXXXX - Date Code APL3201 QA: Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020C for MSL classification at lead-free peak reflow temperature. ANPEC defines "Green" to mean lead-free (RoHS compliant) and halogen free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by weight). Absolute Maximum Ratings Symbol VIN VEN, VBATT, VTHRM ICHG TJ TSTG TL VIN to GND (Note 1) Rating -0.3 to 7 -0.3 to 7 1.2 150 -65 to 150 260 Unit V V A C C C Parameter EN, STAT1, STAT2, BATT, THRM to GND Charging Current Maximum Junction Temperature Storage Temperature Range Maximum Lead Soldering Temperature, 10 Seconds Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Thermal Characteristics Symbol JA Parameter Junction To Air Thermal Resistance (Note 2) DFN3x3-10 Typical Value 50 Unit C/W Note 2 : JA is measured with the component mounted on a high effective thermal conductivity test board in free air. The exposed pad of DFN-10 is soldered directly on the PCB. Recommended Operating Conditions Symbol VIN ICHG TJ TA VIN To GND Charging Current Junction Temperature Ambient Temperature Parameter Range 4.35 to 6.0 0.1 to 1 -40 to 125 -40 to 85 Unit V A C C Copyright (c) ANPEC Electronics Corp. Rev. A.4 - Mar., 2009 2 www.anpec.com.tw APL3201 Electrical Characteristics Refer to the typical application circuit. These specifications apply over VIN=5V, VBATT=4.2V, VTHRM=VREF/2, TJ= -40~125C, TA= -40~85C, unless otherwise specified. Typical values are at TA=25C. Symbol SUPPLY CURRENT IIN VIN Supply Current VEN = 0V VEN = 5V, ICHG=0A VIN Rising 3.90 0.15 TA=25C, VIN=4.35~6.0V TA =-40~85C (TJ=-40~125C) BATT Prequel Voltage Threshold Prequel Threshold Hysteresis VREF REF Regulation Voltage REF Voltage Accuracy REF Maximum Output Current IREF=0~500A, TJ=-40~125C, VIN=4.35V~6.0V REF=GND ICHG=KSET x VSET / RSET, Without thermal regulation Without thermal regulation TJ=-40~125C, VIN=4.35~6.0V ISET=GND 0.1AICHG1A VBATT<2.8V % of charger current set at ISET Hysteresis ICHG=1A, VIN=5V IBYP=5mA, VIN=5V VTHRM Rising VTHRM Falling -0.5 -1 2.8 -2 0.6 2 4.05 0.25 4.20 3 70 3 1.5 1.2 4 4.2 0.35 0.5 1 3.2 2 mA mA V V V % % V mV V % mA Parameter Test Conditions APL3201 Min. Typ. Max. Unit UNDER-VOLTAGE-LOCKOUT VIN UVLO Threshold VIN UVLO Hysteresis BATTERY VOLTAGE AND REFERENCE VOLTAGE VBATT BATT Regulation Voltage BATT Regulation Voltage Accuracy BATTERY CHARGING AND PRECHARGING CURRENT ICHG VSET Charging Current Range ISET Regulation Voltage ISET Regulation Voltage Accuracy Maximum ISET Output Current KSET Charging Current Set Factor Prequel Charging Current Charge-Done Current Threshold DROPOUT VOLTAGES VIN to BATT Dropout Voltage VIN to BYP Dropout Voltage THRM Cold Trip Level THRM Cold Trip Level Hysteresis THRM Hot Trip Level THRM Hot Trip Level Hysteresis Die Thermal Regulation Limit THRM Disable Voltage Threshold 0.79 0.28 50 250 300 0.81 0.03 0.29 0.03 120 100 450 0.82 0.30 150 mV mV VREF VREF VREF VREF C mV 100 -1 940 35 8 1 1.8 1000 55 12.5 12.5 1000 1 1060 70 19 mA V % mA mA % % THERMISTER MONITOR AND DIE TEMPERATURE REGULATION Copyright (c) ANPEC Electronics Corp. Rev. A.4 - Mar., 2009 3 www.anpec.com.tw APL3201 Electrical Characteristics (Cont.) Refer to the typical application circuit. These specifications apply over VIN=5V, VBATT=4.2V, VTHRM=VREF/2, TJ= -40~125 C, TA= -40~85C, unless otherwise specified. Typical values are at TA=25C. Symbol Parameter Test Conditions APL3201 Min. Typ. Max. Unit SOFT-START AND REVSRSE CURRENT TSS Soft-Start Interval BATT Input Current BATT Shutdown Input Current LOGIC INPUT/OUTPUTS STAT1, STAT2 Logic-Low Output STAT1, STAT2 Off-Leakage Current EN Logic Input-High Level EN Logic Input-Low Level EN Input Bias Current Sinking 10mA VSTAT1, 2=5V, VIN=0V 1.6 0.4 1 0.4 1 V A V V A ICHG=0A to Fast-Charging Current VIN=0V, VBATT=4.2V VEN=0V, VIN=5V, VBATT=4.2V 4 7 12 8 4 ms A A Pin Description PIN NO. 1 2 3 4 5 NAME VIN STAT1 ISET GND EN Input Supply Pin. Provides power to the charger, VIN can range from 4.35V to 6.0V and should be bypassed with at least a 4.7F capacitor. Charge Status Output Pin 1. This pin is an active-high, open-drain output pin. Charging Current Setting Pin. Connecting a resistor from this pin to GND set the fast-charge current when the VIN is powering the charger. Ground. Charging Enable/Disable Control Pin. Drive EN high to begin charging, and EN low to stop charging. External Thermistor Connection Pin. THRM pauses charging when an externally connected thermistor (10k at +25C) is at less than 0C or greater than +50C. Connecting this pin to GND disables this function. 3V Reference Voltage Output Pin. Sources up to 500A to bias the external thermistor. Bypass with 0.1F to GND. REF loading does not affect BATT regulation accuracy. Charge Status Output Pin 2. This pin is an active-high, open-drain output pin. Bias Supply Pin for Internal Circuitry. Bypass with a 2.2F capacitor to GND. Charger Output Pin. Connect this pin to the positive terminal of a Li+ battery. Exposed Pad. Connect a large ground plane for maximum package heat dissipation. Connect directly to GND under the IC. FUNCTION 6 THRM 7 8 9 10 - REF STAT2 BYP BATT EP Copyright (c) ANPEC Electronics Corp. Rev. A.4 - Mar., 2009 4 www.anpec.com.tw APL3201 Typical Operating Characteristics VIN Supply Current vs. VIN Input Voltage 4 VEN = 5V VIN Supply Current vs. VIN Input Voltage 4 VEN = 0V VIN Supply Current (mA) VIN Supply Current (mA) 3 3 2 2 1 1 0 0 1 2 3 4 5 6 7 0 0 1 2 3 4 5 6 7 VIN Input Voltage (V) VIN Input Voltage (V) Off-Battery Leakage Current vs. VIN Input Voltage 10 Off-Battery Leakage Current vs. BATT Voltage 8 Off-Battery Leakage Current (uA) 8 VEN = 0V VBATT =4.2V Off-Battery Leakage Current (uA) VEN = 0V VIN = 0V 6 6 4 4 2 2 0 0 1 2 3 4 5 6 7 0 0 1 2 3 4 5 VIN Input Voltage (V) BATT Voltage (V) Charge Current vs. Ambient Temperature 1200 1000 BATT Voltage vs. Junction Temperature 4.25 4.24 4.23 VIN = 5V Charge Current (mA) 800 600 400 200 0 -40 ICHG = set to 1A VBATT = 3.9V VIN =5V BATT Voltage (V) 60 80 100 120 4.22 4.21 4.2 4.19 4.18 4.17 4.16 -20 0 20 40 4.15 -40 -20 0 20 40 60 80 100 120 140 Ambient Temperature (C) Copyright (c) ANPEC Electronics Corp. Rev. A.4 - Mar., 2009 5 Junction Temperature (C) www.anpec.com.tw APL3201 Typical Operating Characteristics (Cont.) Charge Current vs. BATT Voltage 1200 1000 VIN = 5V, VEN = 5V ICHG = set to 1A Charge Current vs. (VIN-VBATT) 1200 ICHG = set to 1 A 1000 Charge Current (mA) 800 600 400 200 0 0 1 2 3 4 5 Charge Current (mA) 800 600 400 200 0 0 0.2 0.4 0.6 0.8 1 ICHG = set to 750mA BATT Voltage (V) V IN-V BATT (V) Copyright (c) ANPEC Electronics Corp. Rev. A.4 - Mar., 2009 6 www.anpec.com.tw APL3201 Operating Waveforms VIN Hot-Plug Power-Up Enable in Fast Charge VBATT=3.9V, VIN=5V CH1: VIN (5V/div) CH2: VBATT (2V/div) CH3: VSTAT1 (5V/div) CH4: ICHG (0.5A/div) Time: 5ms/div VBATT=3.9V, VIN=5V CH1: VEN (5V/div) CH2: VSTAT1 (5V/div) CH3: VSTAT2 (5V/div) CH4: ICHG (1A/div) Time: 20ms/div Enable in Precharge Enable in Charge Done VBATT=2.7V, VIN=5V CH1: VEN (5V/div) CH2: VSTAT1 (5V/div) CH3: VSTAT2 (5V/div) CH4: ICHG (50mA/div) Time: 20ms/div VBATT=4.2V, VIN=5V CH1: VEN (5V/div) CH2: VSTAT1 (5V/div) CH3: VSTAT2 (5V/div) CH4: ICHG (50mA/div) Time: 20ms/div Copyright (c) ANPEC Electronics Corp. Rev. A.4 - Mar., 2009 7 www.anpec.com.tw APL3201 Block Diagram VIN Current sense 0.25 BATT BYP REF 3.0V VREF Charge Controller STAT1 STAT2 EN ISET Thermal Regulation Thermistor Comparator THRM GND Typical Application Circuit BATT C2 2.2F Li+ Cell 5V C1 4.7F R2 R3 1.5K 1.5K VIN ISET STAT1 R1 2K STAT2 BYP C3 2.2F ON THRM EN OFF R5 NTC Thermistor 10K at 25 GND REF C4 0.1F R4 10K Designation C1 C2 C3 Description 4.7F, 10V, X5R, 0805 Murata GRM188R61A475K 2.2F, 6.3V, X5R, 0603 Murata GRM188R60J225K 2.2F, 10V, X5R, 0603 Murata GRM188R61A225K www.anpec.com.tw Murata website: www.murata.com Copyright (c) ANPEC Electronics Corp. Rev. A.4 - Mar., 2009 8 APL3201 Function Description Precharge Current When the APL3201 is powered with a battery connected, the IC first detects if the cell voltage is ready for full charge current. If the cell voltage is less than the prequal level (3V typ), the battery is precharged with a 55mA current until the cell reaches the proper level. The full charging current, as set by ISET pin, is then applied. Charging Current Setting The charge current is programmed by using a resistor from the ISET pin to the ground. The battery charge current is 1000 times the current out of the ISET pin. The battery charge current is calculated by the following equation: ICHG =KSET x VSET / RSET Where VSET is ISET regulation voltage (nominal=1V). KSET is the charging current set factor (nominal=1000). The charging current set factor and the ISET regulation voltage are shown in the Electrical Characteristics. The ISET regulation voltage is reduced by thermal regulation function. Enable (EN) The enable input, EN, switches the charging of APL3201 on or off. With EN high, the APL3201 can begin charging. When EN is low, charging stops, REF is shutdown, and STAT1 and STAT2 outputs are off (high). Battery Full Indication Charge-done occurs when ICHG falls to 12.5% of the current set by RSET and the charger is in voltage mode (VBATT near 4.2V). After the APL3201 enunciates the charge-done signal, it keeps operating in voltage mode without turning off the charger. The STAT1 is turned off (high) and STAT2 is turned on (low) when the charger is into charge-done state. Thermal Regulation On-chip thermal limiting in the APL3201 simplifies PC board layout and allows charging rates to be automatically optimized without constraints imposed by worst-case FFigure 1. Thermistor Sensing Block Diagram 10k THRM TCOLD Thermistor 10k at +25C 100mV To Regulator minimum battery voltage, maximum input voltage, and maximum ambient temperature. When the APL3201 thermal limit is reached, the charger does not shut down but simply reduces charging current. This allows the board design to be optimized for compact size and typical thermal conditions. The APL3201 reduces charging current to keep its die temperature below +120C. The APL3201' DFN3x3-10 package includes a bottom metal s plate that reduces thermal resistance between the die and the PC board. The external pad should be soldered to a large ground plane. This helps dissipate power and keeps the die temperature below the thermal limit. The APL3201' thermal regulator is set for a +120C die s temperature. External Thermistor Monitor (THRM) The APL3201 features an internal window comparator to monitor battery pack temperature or ambient temperature with an external negative temperature coefficient thermistor. In typical systems, temperature is monitored to prevent charging at ambient temperature extremes (below 0C or above +50C). When the temperature moves outside these limits, charging is stopped. If the V THRM returns to within its normal window, charging resumes. Connect THRM to GND when not using this feature. Note that the temperature monitor at THRM entirely separates from the on-chip temperature limiting discussed in the Thermal Regulation section. The input thresholds for the THRM input are 0.74 x VREF for the COLD trip point and 0.29 x VREF for the HOT trip point. REF THOT Copyright (c) ANPEC Electronics Corp. Rev. A.4 - Mar., 2009 9 www.anpec.com.tw APL3201 Function Description (Cont.) Charge Status Outputs The open-drain STAT1 and STAT2 outputs indicate four charger operations are shown in Table 1. The two outputs can be used to drive LEDs or communicate to the host processor. Note that OFF indicates the open-drain transistor is turned off. CHARGE STATE Precharge in progress Fast charge in progress Charge done Charge suspended Table 1. Status Pin Summary STAT1 ON ON OFF OFF STAT2 ON OFF ON OFF Disable Charging for VIN>6.4V When input voltage is over 6.4V overvoltage threshold, the charging of APL3201 will be turned off. The charging will be turned on until the input voltage is below the OVP threshold. The absolute maximum rating of input voltage is 7V. If the input voltage is over 7V the IC may be damaged. Soft-Start The APL3201 includes a soft-start function to control the rise rate of the charging current rising from zero to the fast-charging current level in constant current mode. During charger soft-start, the APL3201 ramps up the voltage on ISET pin with constant well-controlled slew rate. The charging current is proportional to the ISET voltage. The soft-start interval is 7ms (typical), which is independent of the fast-charging current level. ICHG 4.2V VBATT 3.0V Charge Done Full Charge Precharge Constant Current Mode Voltage Mode Figure 2. Typical Charging Profile Copyright (c) ANPEC Electronics Corp. Rev. A.4 - Mar., 2009 10 www.anpec.com.tw APL3201 Applicaiton Information STAT Pins The STAT1 and STAT2 outputs indicate four charger operations. These two pins can be used to drive LEDs or communicate to the host processor. When status pins are monitored by a processor, there should be a 10k pull-up resistor to connect each status pin and the VCC of the processor; furthermore, when the status is viewed by the LED, the LED with a current rating is less than 10mA and a resistor should be selected to connect the LED in series, so the current will be limited to the desired current value. The resistor is calculated by the following equation: R2,3 = ( VIN - VLED _ ON) PD where: TJ=device junction temperature TA= ambient temperature PD=device power dissipation The device power dissipation, PD, is the function of the charge rate and the voltage drop across the internal FET. It can be calculated by the following equation: PD = (VIN - VBATT ) x ICHG PCB Layout Consideration The APL3201 is packaged in a thermally enhanced QFN package. The package includes a thermal pad to provide an effective thermal contact between the device and the printed circuit board. Connecting the exposed pad to a large copper ground plane on the backside of the circuit board through several thermal vias for heatsinking is recommended. Connecting the battery to BATT as close to the device as possible provides accurate battery voltage sensing. All decoupling capacitors and filter capacitors should be placed as close as possible to the device. The high-current charge path into VIN and from the BATT pin must be short and wide to minimize voltage drops. In other words, the LED and resistor between the input and each status pin shoule be in series. Capacitor Selection Typically, a 4.7F ceramic capacitor is used to connect from VIN to GND. For high charging current, it is recommended to use a larger input bypass capacitance to reduce supply noise. There is a ceramic capacitor connecting from BATT to GND for proper stability. To work well with most application, at least a 2.2F X5R ceramic capacitor is required. Thermal Consideration The APL3201 is available in a thermally enhanced QFN package with an exposed pad. It is recommended to connect the exposed pad to a large copper ground plane on the backside of the circuit board through several thermal vias for heatsinking. The exposed pad transfers heat away from the device, allowing the APL3201 to charge the battery with maximum current while minimizing the increase in die temperature. The most common measure of package thermal performance is thermal resistance measured from the device junction to the air surrounding the package surface (JA). The JA can be calculated by the following equation: JA = TJ - TA PD Copyright (c) ANPEC Electronics Corp. Rev. A.4 - Mar., 2009 11 www.anpec.com.tw APL3201 Package Information DFN3x3-10 D A Pin 1 E D2 A3 Pin 1 Corner E2 e S Y M B O L A A1 A3 b D D2 E E2 e L K 0.30 0.20 0.18 2.90 2.20 2.90 1.40 0.50 BSC 0.50 0.012 0.008 DFN3x3-10 MILLIMETERS MIN. 0.80 0.00 0.20 REF 0.30 3.10 2.70 3.10 1.75 0.007 0.114 0.087 0.114 0.055 0.020 BSC 0.020 MAX. 1.00 0.05 MIN. 0.031 0.000 0.008 REF 0.012 0.122 0.106 0.122 0.069 INCHES MAX. 0.039 0.002 Note : 1. Followed from JEDEC MO-229 VEED-5. Copyright (c) ANPEC Electronics Corp. Rev. A.4 - Mar., 2009 12 L b A1 www.anpec.com.tw APL3201 Carrier Tape & Reel Dimensions OD0 P0 P2 P1 A E1 F K0 B SECTION A-A T B0 A0 OD1 B A SECTION B-B d Application A 178.0O .00 2 H 50 MIN. P1 8.0O .10 0 H A T1 T1 12.4+2.00 -0.00 P2 2.0O .05 0 C 13.0+0.50 -0.20 D0 1.5+0.10 -0.00 d 1.5 MIN. D1 1.5 MIN. D 20.2 MIN. T 0.6+0.00 -0.40 W 12.0O .30 0 A0 3.30O .20 0 E1 1.75O .10 0 B0 3.30O .20 0 W F 5.5O .05 0 K0 1.30O .20 0 (mm) DFN3x3-10 P0 4.0O .10 0 Devices Per Unit Package Type DFN3x3-10 Unit Tape & Reel Quantity 3000 Copyright (c) ANPEC Electronics Corp. Rev. A.4 - Mar., 2009 13 www.anpec.com.tw APL3201 Taping Direction Information DFN3x3-10 USER DIRECTION OF FEED Classification Profile Copyright (c) ANPEC Electronics Corp. Rev. A.4 - Mar., 2009 14 www.anpec.com.tw APL3201 Classification Reflow Profiles Profile Feature Preheat & Soak Temperature min (Tsmin) Temperature max (Tsmax) Time (Tsmin to Tsmax) (ts) Average ramp-up rate (Tsmax to TP) Liquidous temperature (TL) Time at liquidous (tL) Peak package body Temperature (Tp)* Time (tP)** within 5C of the specified classification temperature (Tc) Average ramp-down rate (Tp to Tsmax) Time 25C to peak temperature Sn-Pb Eutectic Assembly 100 C 150 C 60-120 seconds 3 C/second max. 183 C 60-150 seconds See Classification Temp in table 1 20** seconds 6 C/second max. 6 minutes max. Pb-Free Assembly 150 C 200 C 60-120 seconds 3C/second max. 217 C 60-150 seconds See Classification Temp in table 2 30** seconds 6 C/second max. 8 minutes max. * Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum. ** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum. Table 1. SnPb Eutectic Process - Classification Temperatures (Tc) Package Thickness <2.5 mm 2.5 mm 3 Volume mm <350 235 C 220 C 3 Volume mm 350 220 C 220 C 3 3 Table 2. Pb-free Process - Classification Temperatures (Tc) Package Thickness <1.6 mm 1.6 mm - 2.5 mm 2.5 mm Volume mm <350 260 C 260 C 250 C Volume mm 350-2000 260 C 250 C 245 C Volume mm >2000 260 C 245 C 245 C 3 Reliability Test Program Test item SOLDERABILITY HOLT PCT TCT ESD Latch-Up Method JESD-22, B102 JESD-22, A108 JESD-22, A102 JESD-22, A104 MIL-STD-883-3015.7 JESD 78 Description 5 Sec, 245C 1000 Hrs, Bias @ 125C 168 Hrs, 100%RH, 2atm, 121C 500 Cycles, -65C~150C VHBMU2KV, VMMU200V 10ms, 1trU 100mA Copyright (c) ANPEC Electronics Corp. Rev. A.4 - Mar., 2009 15 www.anpec.com.tw APL3201 Customer Service Anpec Electronics Corp. Head Office : No.6, Dusing 1st Road, SBIP, Hsin-Chu, Taiwan, R.O.C. Tel : 886-3-5642000 Fax : 886-3-5642050 Taipei Branch : 2F, No. 11, Lane 218, Sec 2 Jhongsing Rd., Sindian City, Taipei County 23146, Taiwan Tel : 886-2-2910-3838 Fax : 886-2-2917-3838 Copyright (c) ANPEC Electronics Corp. Rev. A.4 - Mar., 2009 16 www.anpec.com.tw |
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