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| PCA9558 8-bit I2C-bus and SMBus I/O port with 5-bit multiplexed/1-bit latched 6-bit I2C-bus EEPROM DIP switch and 2-kbit EEPROM Rev. 04 -- 14 April 2009 Product data sheet 1. General description The PCA9558 is a highly integrated, multi-function device that is composed of a 5-bit multiplexed/1-bit latched 6-bit I2C-bus/SMBus EEPROM DIP switch, an 8-bit I/O expander and a 2-kbit serial EEPROM with write protect. The PCA9558 integrates these commonly used components into a single chip to reduce component count and board space requirements and is useful in computer, server and telecom/networking applications. * Multiplexed/latched EEPROM DIP switch--used to select digital information between a set of 5 bits of default hardware inputs and an alternative set of inputs provided by the I2C-bus/SMBus interface and stored in the EEPROM. Examples of this type of selection include processor voltage configuration or processor vendor identification (VID). The multiplexed/latched EEPROM can also be used to replace DIP switches or jumpers, since the settings can be easily changed via I2C-bus/SMBus without having to power down the equipment to open the cabinet. The non-volatile memory retains the most current setting selected before the power is turned off. * 8-bit I/O expander--used to control, monitor or collect remote information or power LEDs. Monitored or collected information can be read through the I2C-bus/SMBus or can be stored in the internal EEPROM. * 2-kbit serial EEPROM--used to store information such as card identification or revision/maintenance history on every motherboard/line card and can be read or written via I2C-bus/SMBus when required. The PCA9558 has 1 address pin, allowing up to 2 devices to be placed on the same I2C-bus or SMBus. 2. Features I 5-bit 2-to-1 multiplexer, 1-bit latch DIP switch I 6-bit MUX_OUTx and NON_MUXED_OUT EEPROM programmable and readable via I2C-bus I 5 V tolerant open-drain MUX_OUTx and NON_MUXED_OUT outputs I Active LOW override input forces all MUX_OUTx outputs to logic 0 I I2C-bus readable MUX_INx inputs I 5 V tolerant open-drain IOx pins, power-up default as outputs I 1 address pin, allowing up to 2 devices on the I2C-bus I Active LOW reset input with internal pull-up for the 8 I/O pins I 2048-bit EEPROM programmable and readable via the I2C-bus or I/Os I Operating power supply voltage range of 3.0 V to 3.6 V I SMBus compliance with fixed 3.3 V levels NXP Semiconductors PCA9558 8-bit I2C-bus/SMBus I/O port I 2.5 V to 5 V tolerant inputs I ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per JESD22-A115 and 1000 V CDM per JESD22-C101 I Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA 3. Applications I I I I I Board version tracking and configuration Board health monitoring and status reporting Multi-card systems in telecom, networking and base station infrastructure equipment Field recall and troubleshooting functions for installed boards General-purpose integrated I/O with DIP switch and memory 4. Ordering information Table 1. Ordering information Topside mark PCA9558DH Temperature range 0 C to 70 C Package Name TSSOP28 Description plastic thin shrink small outline package; 28 leads; body width 4.4 mm Version SOT361-1 Type number PCA9558PW PCA9558_4 (c) NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 -- 14 April 2009 2 of 27 NXP Semiconductors PCA9558 8-bit I2C-bus/SMBus I/O port 5. Block diagram PCA9558 MUX_SELECT MUX_OUT_LOW 6-bit EEPROM LATCH NMO 5 NON_MUXED_OUT MUX_INA to MUX_INE 1 MUX_OUTA MUX_OUTB A0 I2C-BUS INTERFACE LOGIC INPUT FILTER 5 5-BIT 2 TO 1 MUX MUX_OUTC MUX_OUTD MUX_OUTE SCL SDA 0 VDD POWER-ON RESET I2C-BUS CONTROL LOGIC VSS 8 WP 256-BYTE EEPROM GPIO IO0 to IO7 IO_OUT_LOW 002aad366 Fig 1. Block diagram of PCA9558 PCA9558_4 (c) NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 -- 14 April 2009 3 of 27 NXP Semiconductors PCA9558 8-bit I2C-bus/SMBus I/O port 6. Pinning information 6.1 Pinning SCL SDA IO_OUT_LOW A0 MUX_INA MUX_INB MUX_INC MUX_IND MUX_INE 1 2 3 4 5 6 7 8 9 28 VDD 27 WP 26 MUX_OUT_LOW 25 NON_MUXED_OUT 24 MUX_OUTA 23 MUX_OUTB 22 MUX_OUTC 21 MUX_OUTD 20 MUX_OUTE 19 MUX_SELECT 18 IO7 17 IO6 16 IO5 15 IO4 002aad365 PCA9558PW VSS 10 IO0 11 IO1 12 IO2 13 IO3 14 Fig 2. Pin configuration for TSSOP28 6.2 Pin description Table 2. Symbol SCL SDA IO_OUT_LOW A0 MUX_INA MUX_INB MUX_INC MUX_IND MUX_INE VSS IO0 IO1 IO2 IO3 IO4 IO5 IO6 IO7 Pin description Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Description serial I2C-bus clock serial bidirectional I2C-bus data active LOW control forces all GPIO to logic 0 outputs A0 address external input A to multiplexer external input B to multiplexer external input C to multiplexer external input D to multiplexer external input E to multiplexer ground general purpose input/output 0 (open-drain output) general purpose input/output 1 (open-drain output) general purpose input/output 2 (open-drain output) general purpose input/output 3 (open-drain output) general purpose input/output 4 (open-drain output) general purpose input/output 5 (open-drain output) general purpose input/output 6 (open-drain output) general purpose input/output 7 (open-drain output) PCA9558_4 (c) NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 -- 14 April 2009 4 of 27 NXP Semiconductors PCA9558 8-bit I2C-bus/SMBus I/O port Pin description ...continued Pin 19 20 21 22 23 24 25 26 27 28 Description active LOW select of MUX_INx inputs or EEPROM contents for MUX_OUTx outputs open-drain multiplexed output E open-drain multiplexed output D open-drain multiplexed output C open-drain multiplexed output B open-drain multiplexed output A open-drain outputs from non-volatile memory active LOW control forces all MUX outputs to logic 0 active HIGH EEPROM write protect power supply (3.0 V to 3.6 V) Table 2. Symbol MUX_SELECT MUX_OUTE MUX_OUTD MUX_OUTC MUX_OUTB MUX_OUTA NON_MUXED_OUT MUX_OUT_LOW WP VDD 7. Functional description Refer to Figure 1 "Block diagram of PCA9558". 7.1 I2C-bus interface Communicating with this device is initiated by sending a valid address on the I2C-bus. The address format (see Figure 3) has 6 fixed bits and one user-programmable bit followed by a 1-bit read/write value which determines the direction of the data transfer. MSB 1 0 0 1 1 1 LSB A0 R/W hardware selectable 002aad367 fixed Fig 3. I2C-bus address byte Following the address and acknowledge bit are 8 data bits which, depending on the read/write bit in the address, will read data from or write data to the EEPROM. Data will be written to the register if the read/write bit is logic 0 and the WP input is logic 0. Data will be read from the register if the bit is logic 1. The four high-order bits are latched outputs, while the four low order bits are multiplexed outputs (Figure 5). Remark: To ensure data integrity, the EEPROM must be internally write protected when VDD to the I2C-bus is powered down or VDD to the component is dropped below normal operating levels. D7 D6 D5 D4 D3 D2 D1 D0 002aad368 Fig 4. Command byte PCA9558_4 (c) NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 -- 14 April 2009 5 of 27 NXP Semiconductors PCA9558 8-bit I2C-bus/SMBus I/O port Command byte D5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 : 1 D4 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 : 1 D3 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 : 1 D2 0 0 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 : 1 D1 0 1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 : 1 D0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 : 1 reserved Command write to 256-byte EEPROM via I2C-bus read from 256-byte EEPROM via I2C-bus write to 6-bit EEPROM via I2C-bus read from 6-bit EEPROM via I2C-bus read Input Port (IP) register via I2C-bus read/write Output Port (OP) register via I2C-bus read/write Polarity Inversion (PI) register via I2C-bus read/write Input/Output Configuration (IOC) register via I2C-bus read/write MUX Control (MUXCNTRL) register via I2C-bus read MUX_INx values via I2C-bus reserved reserved read 256-byte EEPROM and write OP register read 256-byte EEPROM and write PI register read 256-byte EEPROM and write IOC register read IP register and write to 256-byte EEPROM reserved Table 3. D7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 : 1 D6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 : 1 7.1.1 Multiplexer MSB 0 0 LSB NONMUX MUX MUX MUX MUX MUXED DATA E DATA D DATA C DATA B DATA A DATA 002aad369 Fig 5. I2C-bus MUX_OUTx data byte MSB 0 0 0 LSB MUX_IN MUX_IN MUX_IN MUX_IN MUX_IN D B A E C 002aad370 Fig 6. I2C-bus MUX_INx data byte PCA9558_4 (c) NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 -- 14 April 2009 6 of 27 NXP Semiconductors PCA9558 8-bit I2C-bus/SMBus I/O port The Multiplexer function controls the six open-drain outputs, MUX_OUTx and NON_MUXED_OUT. This control is affected by the input pins MUX_SELECT (pin 19), MUX_OUT_LOW (pin 26), and/or an internal register programmed via the I2C-bus. Upon power-up, the multiplex function is controlled by the MUX_SELECT and MUX_OUT_LOW pins. When the MUX_SELECT signal is a logic 0, the multiplexer will select the data from the 6-bit EEPROM to drive on the MUX_OUTx and NON_MUXED_OUT pins. When the MUX_SELECT signal is a logic 1, the multiplexer will select the MUX_INx pins to drive on the MUX_OUTx pins. The NON_MUXED_OUT output is latched from the 6-bit EEPROM on a rising edge of the MUX_SELECT signal. This latch is transparent while the MUX_SELECT signal is a logic 0. An internal control register, written via the I2C-bus, can also control the multiplexer function. When this register is written, the MUX_SELECT function can change from the external pin to an internal register. In this register a bit will act in a similar fashion to the MUX_SELECT input, i.e., a logic 1 will cause the multiplexer to select data from the 6-bit EEPROM to drive on the MUX_OUTx and NON_MUXED_OUT pins. In this configuration, the NON_MUXED_OUT will latch data when the PCA9558 acknowledges the I2C-bus. The MUX_SELECT pin will have no effect on the MUX_OUTx or NON_MUXED_OUT while in this mode. When the MUX_OUT_LOW signal is a logic 0 and the multiplexer is configured so that the MUX_OUTx pins are being driven by the 6-bit EEPROM, the MUX_OUTx pins will be driven to a logic 0. This information is summarized in Table 4. Table 4. Register B1[1] x x x x 0 1 0 1 [1] [2] [3] Multiplexer function table Input MUX_OUT_LOW MUX_SELECT 0 0 1 1 0 0 1 1 1 0 1 0 x x x x Output MUX_OUTx MUX_INx inputs 0 MUX_INx inputs from EEPROM MUX_INx inputs 0 MUX_INx inputs from EEPROM NON_MUXED_OUT latched from EEPROM[2] 0 latched from EEPROM[2] from EEPROM latched from EEPROM[3] 0 latched from EEPROM[3] from EEPROM B0[1] 0 0 0 0 1 1 1 1 These are the 2 LSBs of the MUX Control (MUXCNTRL) register. NON_MUXED_OUT value will be the value present in the 6-bit EEPROM at the time of the rising edge of the MUX_SELECT input. NON_MUXED_OUT value will be the value present in the 6-bit EEPROM at the time of the slave ACK when bit 1 has changed from logic 0 to logic 1. If the MUX_OUTx outputs are being driven by the 6-bit EEPROM and this EEPROM is programmed, the outputs will remain stable and change to the new values after the EEPROM program cycle completes. Examples of read/write for MUX control can be found in Figure 7. PCA9558_4 (c) NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 -- 14 April 2009 7 of 27 NXP Semiconductors PCA9558 8-bit I2C-bus/SMBus I/O port slave address S 1 0 0 1 1 1 A0 0 R/W A 0 0 command byte 0 0 1 0 1 1 A 0 0 0 data byte 0 0 0 B1 B0 A acknowledge from slave P STOP condition 002aad371 START condition acknowledge from slave acknowledge from slave Fig 7. I2C-bus write for MUXCNTRL register slave address S 1 0 0 1 1 1 A0 0 R/W A 0 0 command byte 0 0 1 0 1 1 A S 1 0 slave address 0 1 1 1 A0 1 R/W A (cont.) acknowledge from slave START condition acknowledge from slave acknowledge from slave (re)START condition data from slave (cont.) 0 0 0 0 0 0 B1 B0 NA P no acknowledge from master STOP condition 002aad372 Fig 8. I2C-bus read for MUXCNTRL register 7.1.2 Registers The GPIOs are controlled by a set of 4 internal registers: Input Port (IP) register; Output Port (OP) register; Polarity Inversion (PI) register; and the Input/Output Configuration (IOC) register. Each register is read/write via the I2C-bus or 256-byte EEPROM, with the exception of the Input Port register, which is read only, one at a time. The read/write takes place on the slave Acknowledge. The control of which register is currently available to the I2C-bus is set by bits in the control register. See Section 7.1.2.1 through Section 7.1.2.4 for details. 7.1.2.1 IP - Input Port register This register is an input-only port. It reflects the logic value present on the GPIO pins regardless of whether they are configured as inputs or outputs (IOC register). Writes to this register have no effect. Table 5. Bit Symbol Default IP - Input Port register description 7 I7 0 6 I6 0 5 I5 0 4 I4 0 3 I3 0 2 I2 0 1 I1 0 0 I0 0 PCA9558_4 (c) NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 -- 14 April 2009 8 of 27 NXP Semiconductors PCA9558 8-bit I2C-bus/SMBus I/O port 7.1.2.2 OP - Output Port register This register is an output-only port. It reflects the outgoing logic levels of the GPIO defined as outputs in the IOC register. Bit values in this register have no effect on GPIO defined as inputs. In turn, reads from this register reflect the value stored in the flip-flop controlling the output, not the actual output value. Table 6. Bit Symbol Default OP - Output Port register description 7 O7 0 6 O6 0 5 O5 0 4 O4 0 3 O3 0 2 O2 0 1 O1 0 0 O0 0 7.1.2.3 PI - Polarity Inversion register This register enables polarity inversion of GPIO defined as inputs by the IOC register. If a bit in this register is set to a logic 1, the corresponding GPIO input port is inverted. If a bit in this register is set to a logic 0, the corresponding GPIO input port is not inverted. Table 7. Bit Symbol Default PI - Polarity Inversion register description 7 P7 1 6 P6 1 5 P5 1 4 P4 1 3 P3 0 2 P2 0 1 P1 0 0 P0 0 7.1.2.4 IOC - Input/Output Configuration register This register configures the direction of the GPIO pins (IOx). If a bit is set to a logic 1, the corresponding port pin is enabled as an input with a high-impedance output driver. If a bit is set to a logic 0, the corresponding port pin is enabled as an output. Table 8. Bit Symbol Default IOC - Input/Output Configuration register description 7 C7 1 6 C6 1 5 C5 1 4 C4 1 3 C3 1 2 C2 1 1 C1 1 0 C0 1 Examples of read/write to these registers can be found in Figure 9, Figure 10, Figure 15, and Figure 16. The IO_OUT_LOW input, when held LOW longer than the time Tcy(W), will reset the GPIO registers to their default (power-up) values. A read of the present value of the inputs MUX_INx can be done via the I2C-bus. This is done by addressing the PCA9558 in a write mode and entering the correct command code. The preset value on the MUX_INx inputs is latched at the command code Acknowledge. A REPEATED START is then sent with the R/W bit set to a logic 1, read, and this latched data is read out on the I2C-bus. See Figure 11. PCA9558_4 (c) NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 -- 14 April 2009 9 of 27 NXP Semiconductors PCA9558 8-bit I2C-bus/SMBus I/O port slave address S 1 0 0 1 1 1 A0 0 R/W A 0 0 command byte 0 0 x x x x data byte A d7 d6 d5 d4 d3 d2 d1 d0 A acknowledge from slave P STOP condition 002aad373 START condition acknowledge from slave acknowledge from slave See Table 3 for the proper command byte. Fig 9. I2C-bus write for GPIO registers slave address S 1 0 0 1 1 1 A0 0 R/W A 0 0 command byte 0 0 x x x x A S 1 0 slave address 0 1 1 1 A0 1 R/W A (cont.) acknowledge from slave START condition acknowledge from slave acknowledge from slave (re)START condition data from slave (cont.) d7 d6 d5 d4 d3 d2 d1 d0 NA P no acknowledge from master STOP condition 002aad374 Fig 10. I2C-bus read for GPIO registers slave address S 1 0 0 1 1 1 A0 0 R/W A 0 0 command byte 0 0 1 1 0 0 A S 1 0 slave address 0 1 1 1 A0 1 R/W A (cont.) acknowledge from slave START condition acknowledge from slave acknowledge from slave (re)START condition data from slave (cont.) 0 0 0 d4 d3 d2 d1 d0 NA P no acknowledge from master STOP condition 002aad375 Fig 11. I2C-bus read of MUX_INx inputs PCA9558_4 (c) NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 -- 14 April 2009 10 of 27 NXP Semiconductors PCA9558 8-bit I2C-bus/SMBus I/O port 7.1.3 EEPROM write operation 7.1.3.1 6-bit write operation A write operation to the 6-bit EEPROM requires that an address byte be written after the command byte. This address points to the 6-bit address space in the EEPROM array. Upon receipt of this address, the PCA9558 waits for the next byte that will be written to the EEPROM. The master then ends the transaction with a STOP condition on the I2C-bus. See Figure 12. After the STOP condition, the E/W cycle starts, and the parts will not respond to any request to access the EEPROM array until the cycle finishes, approximately 4 ms. slave address S 1 0 0 1 1 1 A0 0 R/W A 0 0 command byte 0 0 0 1 0 0 A 1 1 EEPROM address 1 1 1 1 1 1 A (cont.) acknowledge from slave data for 6-bit EEPROM (cont.) X X d5 d4 d3 d2 d1 d0 A acknowledge from slave P programming begins after STOP START condition acknowledge from slave acknowledge from slave STOP condition 002aad376 Fig 12. I2C-bus write of 6-bit EEPROM 7.1.3.2 6-bit read operation A read operation is initiated in the same manner as a write operation, with the exception that after the word address has been written a REPEATED START condition is placed on the I2C-bus and the direction of communication is reversed (see Figure 13). slave address S 1 0 0 1 1 1 A0 0 R/W A 0 0 command byte 0 0 0 1 1 0 A 1 1 EEPROM address 1 1 1 1 1 1 A (cont.) START condition acknowledge from slave slave address acknowledge from slave acknowledge from slave data from 6-bit EEPROM (cont.) S 1 0 0 1 1 1 A0 1 R/W A 0 0 d5 d4 d3 d2 d1 d0 NA P no acknowledge from master STOP condition 002aad377 (re)START condition acknowledge from slave Fig 13. I2C-bus read of 6-bit EEPROM PCA9558_4 (c) NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 -- 14 April 2009 11 of 27 NXP Semiconductors PCA9558 8-bit I2C-bus/SMBus I/O port 7.1.3.3 256-byte write operation (I2C-bus) A write operation to the 256-byte EEPROM requires that an address byte be written after the command byte. This address points to the starting address in the EEPROM array. The four LSBs of this address select a position on a 16-byte page register, the 4 MSBs select which page register. The four LSBs will be auto-incremented after receipt of each byte of data; in this manner, the entire page register can be written starting at any point. Up to 16 bytes of data may be sent to the PCA9558, followed by a STOP condition on the I2C-bus. If the master sends more than 16 bytes of data prior to generating a STOP condition, data within the address page will be overwritten and unpredictable results may occur. See Figure 14. After the STOP condition, the E/W cycle starts, and the parts will not respond to any request to access the EEPROM array until the cycle finishes, approximately 4 ms. slave address S 1 0 0 1 1 1 A0 0 R/W A 0 0 command code 0 0 0 0 0 1 acknowledge from slave acknowledge from slave acknowledge from slave A (cont.) Auto-Increment word address A EEPROM address A DATA N START condition acknowledge from slave acknowledge from slave (cont.) acknowledge from slave DATA N + 1 A DATA N + M Auto-Increment word address A P STOP condition 002aad378 Auto-Increment word address M bytes where M 15. Fig 14. I2C-bus page write operation to 256-byte EEPROM 7.1.3.4 256-byte read operation (I2C-bus) A read operation is initiated in the same manner as a write operation, with the exception that after the word address has been written, a REPEATED START condition is placed on the I2C-bus, and the direction of communication is reversed. For a read operation, the entire address is incremented after the transmission of each byte, meaning that the entire 256-byte EEPROM array can be read at one time. See Figure 15. PCA9558_4 (c) NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 -- 14 April 2009 12 of 27 NXP Semiconductors PCA9558 8-bit I2C-bus/SMBus I/O port slave address S 1 0 0 1 1 1 A0 0 R/W acknowledge from slave command code A 0 0 0 0 0 0 1 1 acknowledge from slave acknowledge from slave A (cont.) A EEPROM address START condition slave address (cont.) S 1 0 0 1 1 acknowledge from slave acknowledge from master no acknowledge from master 1 A0 1 R/W A DATA N A Auto-Increment word address DATA N + M NA P STOP condition 002aad379 (re)START condition Auto-Increment word address M bytes where M 1. Fig 15. I2C-bus read operation from 256-byte EEPROM 7.1.3.5 256-byte EEPROM write to GPIO A mode is available whereby a byte of data in the 256-byte EEPROM array can be written to the GPIO (OP register). This is initiated by the I2C-bus. In this mode, a control word indicating a read from the 256-byte EEPROM and write to the GPIO is sent, followed by the word address of the data within the EEPROM array. Upon Acknowledge from the slave, the data is sent to the GPIO. See Figure 16. slave address S 1 0 0 1 1 1 A0 0 R/W A 0 0 command byte 0 x x x x x EEPROM address A a7 a6 a5 a4 a3 a2 a1 a0 A (cont.) acknowledge from slave data from 256-byte EEPROM START condition acknowledge from slave slave address acknowledge from slave (cont.) S 1 0 0 1 1 1 A0 1 R/W A d7 d6 d5 d4 d3 d2 d1 d0 NA P acknowledge from slave no acknowledge from master STOP condition; data latched into GPIO register 002aad380 (re)START condition See Table 3 for the needed command code. Fig 16. Read from 256-byte EEPROM and write to GPIO registers 7.1.3.6 256-byte EEPROM write from GPIO A mode is available whereby data in the GPIO (IP register) can be written to the 256-byte EEPROM. This is initiated by the I2C-bus. In this mode, a control word indicating a read from the GPIO and write to the 256-byte EEPROM is sent, followed by the word address for the data to be written. Once the slave has sent an Acknowledge, the master must send a STOP condition. See Figure 17. After the STOP condition, the E/W cycle starts, and the parts will not respond to any request to access the EEPROM array until the cycle finishes, approximately 4 ms. PCA9558_4 (c) NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 -- 14 April 2009 13 of 27 NXP Semiconductors PCA9558 8-bit I2C-bus/SMBus I/O port When the Write Protect (WP) input is a logic 0 it allows writes to both EEPROM arrays. When it is a logic 1, it prevents any writes to the EEPROM arrays. GPIO input port data latched slave address S 1 0 0 1 1 1 A0 0 R/W A 0 0 command byte 0 1 0 0 1 0 EEPROM address A a7 a6 a5 a4 a3 a2 a1 a0 A acknowledge from slave dummy byte xxxxxxxx A P START condition acknowledge from slave acknowledge from slave acknowledge from slave STOP condition; programming begins after STOP 002aad381 See Table 3 for the needed command code. Fig 17. Read from GPIO Input Port register and write to 256-byte EEPROM 7.1.4 Reset 7.1.4.1 Power-on reset When power is applied to VDD, an internal Power-On Reset (POR) holds the PCA9558 in a reset state until VDD has reached VPOR. At that point, the reset condition is released and the PCA9558 volatile registers and SMBus state machine will initialize to their default states. The GPIO outputs (IOx) will be selected as outputs. The DIP switch MUX_OUTx and NON_MUXED_OUT pin values depend on: * The MUX_OUT_LOW and MUX_SELECT logic levels * The previously stored values in the EEPROM register/current MUX_INx pin values as shown in Table 4 7.1.4.2 External reset A reset of the GPIO registers can be accomplished by holding the IO_OUT_LOW pin LOW for a minimum of Tcy(W). These GPIO registers return to their default states until the IO_OUT_LOW input is once again HIGH. 7.2 Using the PCA9558 on the SMBus It is possible to use Intel chip sets to communicate with the PCA9558. There are no limitations when the SMBus controller is communicating with the MUX or the GPIO; however, there are limitations with the 2-kbit serial EEPROM. Because of being able to address any location in the EEPROM block using the second command byte, the designer using the PCA9558 on the SMBus will have to program around it, an easy thing to do. The device designers had to deal with the specifics of addressing the EEPROM and chose the I2C-bus specification and use the second command byte to address any location in the EEPROM block. In order to write to the EEPROM, write the EEPROM address byte in the Data0 byte and the data to be sent should be placed in the Data1 byte. The Intel chip set's Word Data instruction would then send the address, followed by the command register then Data0 PCA9558_4 (c) NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 -- 14 April 2009 14 of 27 NXP Semiconductors PCA9558 8-bit I2C-bus/SMBus I/O port (EEPROM address), and then the Data1 (data byte). A read from the EEPROM would be a two-step process. The first step would be to do a `Write Byte' with the EEPROM address in the Data0 register. The second step would be to do a `Receive Byte' where the data is stored in the command register. Other differences from the SMBus specification: * Paragraph 5.5.5 - Read Byte/Word in figure 5-11: The PCA9558 follows this same command code with one exception, the PCA9558 requires 2 bytes of command before the repeated START. * Paragraph 5.5.6 - Process call in figure 5-15: The PCA9558 read operation is very similar to the SMBus process call. In the PCA9558 read operation you send a START condition - slave address with a write bit - 2 bytes of command code - repeated START - slave address with a read bit - then read data. 8. Application design-in information A central processor/controller typically located on the system main board can use the 400 kHz I2C-bus/SMBus to poll the PCA9558 devices located on the system cards for status or version control type of information. The PCA9558 may be programmed at manufacturing to store information regarding board build, firmware version, manufacturer identification, configuration option data, etc. Alternately, these devices can be used as convenient interface for board configuration, thereby utilizing the I2C-bus/SMBus as an intra-system communication bus. NXP 4-channel I2C-bus multiplexer I2C-bus I2C-bus CPU OR C I2C-bus PCA9544A BACKPLANE I2C-bus I2C-bus ASIC configuration settings DIP switch or jumper replacement PCA9558 MUXED EEPROM CONTROL GPIO EEPROM monitoring and control INPUTS ALARM LEDs card ID, subroutines, configuration data, or revision history 002aad392 Fig 18. Typical application PCA9558_4 (c) NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 -- 14 April 2009 15 of 27 NXP Semiconductors PCA9558 8-bit I2C-bus/SMBus I/O port 9. Limiting values Table 9. Limiting values[1] In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to VSS (0 V). Symbol VDD VI VO Tstg [1] Parameter supply voltage input voltage output voltage storage temperature Conditions [2] [2] Min 2.5 -0.5 -0.5 -60 Max 4.6 VDD + 0.5 VDD + 0.5 +150 Unit V V V C The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150 C. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] 10. Recommended operating conditions Table 10. Symbol VDD VIL VIH VOL IOL IOH t/V Tamb Operating conditions Parameter supply voltage LOW-level input voltage HIGH-level input voltage LOW-level output voltage LOW-level output current HIGH-level output current input transition rise and fall rate ambient temperature operating SCL, SDA; IOL = 3 mA MUX_OUT_LOW, MUX_INx, MUX_SELECT SCL, SDA; IOL = 3 mA MUX_OUT_LOW, MUX_INx, MUX_SELECT SCL, SDA; IOL = 3 mA SCL, SDA; IOL = 6 mA MUX_OUTx, NON_MUXED_OUT; VOL = 0.4 V MUX_OUTx, NON_MUXED_OUT Conditions Min 3 -0.5 -0.5 2.7 2.0 0 0 Typ Max 3.6 0.9 0.8 4.0 4.0 0.4 0.6 4 100 10 70 Unit V V V V V V V mA A ns/V C PCA9558_4 (c) NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 -- 14 April 2009 16 of 27 NXP Semiconductors PCA9558 8-bit I2C-bus/SMBus I/O port 11. Static characteristics Table 11. Symbol Supply VDD ICCL ICCH VPOR VIL VIH IOL ILH ILL Ci ILH ILL Ci MUX_INx ILH ILL Ci A0 input ILH ILL Ci MUX_OUTx VOL IOH VOL IOH GPIO (IOx) VOL IOH LOW-level output voltage HIGH-level output current IOL = 100 A IOL = 4 mA VOH = VDD 0.4 0.7 100 V V A LOW-level output voltage HIGH-level output current LOW-level output voltage HIGH-level output current IOL = 100 A IOL = 4 mA VOH = VDD IOL = 100 A IOL = 4 mA VOH = VDD NON_MUXED_OUT 0.4 0.7 100 V V A 0.4 0.7 100 V V A HIGH-level leakage current LOW-level leakage current input capacitance VI = VDD VI = VSS 1 -100 10 A A pF HIGH-level leakage current LOW-level leakage current input capacitance VI = VDD VI = VSS 1 -100 10 A A pF supply voltage LOW-level supply current HIGH-level supply current power-on reset voltage LOW-level input voltage HIGH-level input voltage LOW-level output current HIGH-level leakage current LOW-level leakage current input capacitance HIGH-level leakage current LOW-level leakage current input capacitance VI = VDD VI = VSS VOL = 0.4 V VOL = 0.6 V VI = VDD VI = VSS operating mode; all inputs = 0 V operating mode; all inputs = VDD no load; VI = VDD or VSS 3.0 -0.5 2 3 6 -1 -1 2.3 3.6 10 10 2.6 +0.8 VDD + 0.5 +1 +1 10 1 -100 10 V mA mA V V V mA mA A A pF A A pF Static characteristics Parameter Conditions Min Typ Max Unit Input SCL; input/output SDA MUX_OUT_LOW, WP, MUX_SELECT PCA9558_4 (c) NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 -- 14 April 2009 17 of 27 NXP Semiconductors PCA9558 8-bit I2C-bus/SMBus I/O port 12. Dynamic characteristics Table 12. Symbol tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tr tf CL I2C-bus fSCL tBUF tHD;STA tLOW tHIGH tSU;STA tHD;DAT tSU;DAT tSP tSU;STO tr tf Cb Tcy(W) [1] [2] Dynamic characteristics Parameter LOW to HIGH propagation delay HIGH to LOW propagation delay LOW to HIGH propagation delay HIGH to LOW propagation delay LOW to HIGH propagation delay HIGH to LOW propagation delay LOW to HIGH propagation delay HIGH to LOW propagation delay rise time fall time load capacitance SCL clock frequency bus free time between a STOP and START condition hold time (repeated) START condition LOW period of the SCL clock HIGH period of the SCL clock set-up time for a repeated START condition data hold time data set-up time pulse width of spikes that must be suppressed by the input filter set-up time for STOP condition rise time of both SDA and SCL signals fall time of both SDA and SCL signals capacitive load for each bus line write cycle time [2] [1] Conditions Min - Typ 21 7 20 8 20 8 20 7.0 15 Max 28 10 28 12 26 15 28 15 10 5 10 400 -12 -32 10 -100 50 10 300 300 400 - Unit ns ns ns ns ns ns ns ns ns/V ns/V pF kHz s ns s ns ns ns ns ns ns ns ns pF ms MUX_INx to MUX_OUTx MUX_SELECT to MUX_OUTx MUX_OUT_LOW to NON_MUXED_OUT MUX_OUT_LOW to MUX_OUTx output output test load on outputs 1.0 1.0 10 1.3 600 1.3 600 600 0 100 0 600 10 pF to 400 pF bus 10 pF to 400 pF bus 20 20 - After this period, the first clock pulse is generated. Write cycle time can only be measured indirectly during the write cycle. During this time, the device will not acknowledge its I2C-bus address. PCA9558_4 (c) NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 -- 14 April 2009 18 of 27 NXP Semiconductors PCA9558 8-bit I2C-bus/SMBus I/O port SDA tBUF tLOW SCL tr tf tHD;STA tSP tHD;STA P S tHD;DAT tHIGH tSU;DAT Sr tSU;STA tSU;STO P 002aaa986 Fig 19. Definition of timing VI MUX input VSS VM VM tPLZ VDD MUX output VOL VOL + 0.3 V tPZL VM 002aad416 Fig 20. Open-drain output enable and disable times 13. Non-volatile storage specifications Table 13. Parameter memory cell data retention number of memory cell write cycles Non-volatile storage specifications Specification 10 years (minimum) 100,000 cycles (minimum) PCA9558_4 (c) NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 -- 14 April 2009 19 of 27 NXP Semiconductors PCA9558 8-bit I2C-bus/SMBus I/O port 14. Test information VDD VDD RL PULSE GENERATOR VI DUT RT VO CL 002aac532 RL = load resistor (1 k) CL = load capacitance (includes jig and probe capacitance; 10 pF) RT = termination resistance; should be equal to Zo of pulse generators Fig 21. Test circuit for open-drain outputs PCA9558_4 (c) NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 -- 14 April 2009 20 of 27 NXP Semiconductors PCA9558 8-bit I2C-bus/SMBus I/O port 15. Package outline TSSOP28: plastic thin shrink small outline package; 28 leads; body width 4.4 mm SOT361-1 D E A X c y HE vMA Z 28 15 Q A2 pin 1 index A1 (A 3) A Lp L detail X 1 e bp 14 wM 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.1 A1 0.15 0.05 A2 0.95 0.80 A3 0.25 bp 0.30 0.19 c 0.2 0.1 D (1) 9.8 9.6 E (2) 4.5 4.3 e 0.65 HE 6.6 6.2 L 1 Lp 0.75 0.50 Q 0.4 0.3 v 0.2 w 0.13 y 0.1 Z (1) 0.8 0.5 8 o 0 o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT361-1 REFERENCES IEC JEDEC MO-153 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 22. Package outline SOT361-1 (TSSOP28) PCA9558_4 (c) NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 -- 14 April 2009 21 of 27 NXP Semiconductors PCA9558 8-bit I2C-bus/SMBus I/O port 16. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 "Surface mount reflow soldering description". 16.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 16.2 Wave and reflow soldering Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following: * Through-hole components * Leaded or leadless SMDs, which are glued to the surface of the printed circuit board Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are: * * * * * * Board specifications, including the board finish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus SnPb soldering 16.3 Wave soldering Key characteristics in wave soldering are: * Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave * Solder bath specifications, including temperature and impurities PCA9558_4 (c) NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 -- 14 April 2009 22 of 27 NXP Semiconductors PCA9558 8-bit I2C-bus/SMBus I/O port 16.4 Reflow soldering Key characteristics in reflow soldering are: * Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see Figure 23) than a SnPb process, thus reducing the process window * Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board * Reflow temperature profile; this profile includes preheat, reflow (in which the board is heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 14 and 15 Table 14. SnPb eutectic process (from J-STD-020C) Package reflow temperature (C) Volume (mm3) < 350 < 2.5 2.5 Table 15. 235 220 Lead-free process (from J-STD-020C) Package reflow temperature (C) Volume (mm3) < 350 < 1.6 1.6 to 2.5 > 2.5 260 260 250 350 to 2000 260 250 245 > 2000 260 245 245 350 220 220 Package thickness (mm) Package thickness (mm) Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 23. PCA9558_4 (c) NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 -- 14 April 2009 23 of 27 NXP Semiconductors PCA9558 8-bit I2C-bus/SMBus I/O port temperature maximum peak temperature = MSL limit, damage level minimum peak temperature = minimum soldering temperature peak temperature time 001aac844 MSL: Moisture Sensitivity Level Fig 23. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 "Surface mount reflow soldering description". 17. Abbreviations Table 16. Acronym ASIC CDM CPU DIP DUT EEPROM ESD GPIO HBM I/O I2C-bus LED LSB MM MSB POR SMBus C Abbreviations Description Application Specific Integrated Circuit Charged Device Model Central Processing Unit Dual In-line Package Device Under Test Electrically-Erasable Programmable Read-Only Memory ElectroStatic Discharge General Purpose Input/Output Human Body Model Input/Output Inter-Integrated Circuit bus Light Emitting Diode Least Significant Bit Machine Model Most Significant Bit Power-On Reset System Management Bus microcontroller PCA9558_4 (c) NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 -- 14 April 2009 24 of 27 NXP Semiconductors PCA9558 8-bit I2C-bus/SMBus I/O port 18. Revision history Table 17. Revision history Release date 20090414 Data sheet status Product data sheet Change notice Supersedes PCA9558_3 Document ID PCA9558_4 Modifications: * * * * * * * The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Legal texts have been adapted to the new company name where appropriate. Pin name "GND" changed to "VSS" Pin name "I/O_OUT_LOW" changed to "IO_OUT_LOW" Pin names "I/Ox" (I/O0 to I/O7) changed to "IOx" (IO0 to IO7) Symbol "VCC" changed to "VDD" Section 7.1.2.4 "IOC - Input/Output Configuration register": - Table 8: changed Default from "0000 0000" to "1111 1111" - 3rd paragraph: changed symbol from "tW" to "Tcy(W)" * * * * * Section 7.1.4.1 "Power-on reset", 2nd paragraph: changed from "... selected as inputs and in high impedance." to "... selected as outputs." Section 7.1.4.2 "External reset", 1st sentence: changed symbol from "tw" to "Tcy(W)" Table 9 "Limiting values[1]": deleted table note 1 (statement is now in Section 19.3 "Disclaimers") Table 10 "Operating conditions": changed symbol/parameter from "dt/dv, Input transition rise or fall time" to "t/V, input transition rise and fall rate" Table 11 "Static characteristics": - symbol/parameter "IIH, leakage current HIGH" changed to "ILH, HIGH-level leakage current" - symbol/parameter "IIL, leakage current LOW" changed to "ILL, LOW-level leakage current" - sub-sections MUX_OUTx, NON_MUXED_OUT, and GPIO: in parameter description for symbol "VOL" changed word "current" to "voltage" - deleted table note [1] * Table 12 "Dynamic characteristics": - for symbol "tPLH" changed parameter description from "LOW-to-HIGH transition time" to "LOW to HIGH propagation delay" - for symbol "tPHL" changed parameter description from "HIGH-to-LOW transition time" to "HIGH to LOW propagation delay" - sub-section "MUX_OUT_LOW to MUX_OUTx": changed CL max. value from "-" to "10 pF" - sub-section "I2C-bus": changed symbol "tSCL" to "fSCL" - sub-section "I2C-bus": parameter description for symbol "tSP" changed from "data spike time" to "pulse width of spikes that must be suppressed by the input filter" - sub-section "I2C-bus": symbol "CL" changed to "Cb" - sub-section "I2C-bus": symbol "TW" changed to "Tcy(W)" * * * * PCA9558_3 (9397 750 11674) PCA9558_2 (9397 750 09889) PCA9558_1 PCA9558_4 Figure 20 "Open-drain output enable and disable times": drawing replaced Section 13 "Non-volatile storage specifications": deleted sentence which followed Table 13 Added Section 16 "Soldering of SMD packages" Added Section 17 "Abbreviations" Product data Product data Product specification ECN 853-2235 29936 of 19 May 2003 ECN 853-2235 28310 of 24 May 2002 PCA9558_2 PCA9558_1 (c) NXP B.V. 2009. All rights reserved. 20030627 20020524 20001204 Product data sheet Rev. 04 -- 14 April 2009 25 of 27 NXP Semiconductors PCA9558 8-bit I2C-bus/SMBus I/O port 19. Legal information 19.1 Data sheet status Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet [1] [2] [3] Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification. Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 19.2 Definitions Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control -- This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 19.3 Disclaimers General -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental 19.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. I2C-bus -- logo is a trademark of NXP B.V. 20. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com PCA9558_4 (c) NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 -- 14 April 2009 26 of 27 NXP Semiconductors PCA9558 8-bit I2C-bus/SMBus I/O port 21. Contents 1 2 3 4 5 6 6.1 6.2 7 7.1 7.1.1 7.1.2 7.1.2.1 7.1.2.2 7.1.2.3 7.1.2.4 7.1.3 7.1.3.1 7.1.3.2 7.1.3.3 7.1.3.4 7.1.3.5 7.1.3.6 7.1.4 7.1.4.1 7.1.4.2 7.2 8 9 10 11 12 13 14 15 16 16.1 16.2 16.3 16.4 17 18 19 19.1 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 5 I2C-bus interface . . . . . . . . . . . . . . . . . . . . . . . . 5 Multiplexer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 IP - Input Port register. . . . . . . . . . . . . . . . . . . . 8 OP - Output Port register . . . . . . . . . . . . . . . . . 9 PI - Polarity Inversion register. . . . . . . . . . . . . . 9 IOC - Input/Output Configuration register . . . . . 9 EEPROM write operation . . . . . . . . . . . . . . . . 11 6-bit write operation . . . . . . . . . . . . . . . . . . . . 11 6-bit read operation. . . . . . . . . . . . . . . . . . . . . 11 256-byte write operation (I2C-bus) . . . . . . . . . 12 256-byte read operation (I2C-bus) . . . . . . . . . 12 256-byte EEPROM write to GPIO. . . . . . . . . . 13 256-byte EEPROM write from GPIO . . . . . . . 13 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . 14 External reset . . . . . . . . . . . . . . . . . . . . . . . . . 14 Using the PCA9558 on the SMBus. . . . . . . . . 14 Application design-in information . . . . . . . . . 15 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 16 Recommended operating conditions. . . . . . . 16 Static characteristics. . . . . . . . . . . . . . . . . . . . 17 Dynamic characteristics . . . . . . . . . . . . . . . . . 18 Non-volatile storage specifications . . . . . . . . 19 Test information . . . . . . . . . . . . . . . . . . . . . . . . 20 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 21 Soldering of SMD packages . . . . . . . . . . . . . . 22 Introduction to soldering . . . . . . . . . . . . . . . . . 22 Wave and reflow soldering . . . . . . . . . . . . . . . 22 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 22 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 23 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 25 Legal information. . . . . . . . . . . . . . . . . . . . . . . 26 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 26 19.2 19.3 19.4 20 21 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . Contact information . . . . . . . . . . . . . . . . . . . . Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 26 26 26 27 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'. (c) NXP B.V. 2009. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 14 April 2009 Document identifier: PCA9558_4 |
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