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| ST Sitronix INTRODUCTION ST7586S 4-Level Gray Scale Dot Matrix LCD Controller/Driver ST7586S is a driver & controller LSI for 4-level gray scale graphic dot-matrix liquid crystal display systems. It contains 384-segment and 160-common driver circuits. This chip can be connected directly to a microprocessor which accepts 8-bit parallel interface (8080-series or 6800-series type), 4-Line serial interface or 3-Line serial interface. Display data is stored into an on-chip Display Data RAM (DDRAM). It performs the Display Data RAM read/write operation without external operating clock, and the power consumption can be minimized. In addition, since all necessary power supply circuits for LCD system are built-in, ST7586S constructs a LCD display system with the fewest components. FEATURES Single-chip LCD controller/driver Driver Output Circuits 384 segment outputs / 160 common outputs On-chip oscillator circuit Voltage booster with built-in boost-capacitors Extremely few external components: 4 capacitors Built-in voltage regulator with programmable contrast Built-in voltage follower supports LCD bias voltage Available bias: 1/9 ~ 1/14 On-chip Display Data RAM Capacity: 384 x 160 x 2 = 122,880 bits Various Partial Display Features Applicable partial duty Partial window moving & data scrolling Operating Voltage Range Digital Power (VDD1): 1.8V ~ 3.3V (TYP.) Analog Power (VDD2~VDD5, VDDX): 2.8V ~ 3.3V (TYP.) LCD operation voltage (Vop = V0-XV0) : 18V Microprocessor Interface 8-bit parallel bi-directional interface supports 6800-series or 8080-series MPU 4-Line serial interface 3-Line (9-bit) serial interface Built-in OTP-ROM for LCD Vop Optimization Package Type: COG On-chip Low Power Analog Circuit ST7586S 6800, 8080, 4-Line & 3-Line Interface Sitronix Technology Corp. reserves the right to change the contents in this document without prior notice. Ver-1.1a 1/63 2009/11/30 ST7586S PAD ARRANGEMENT 154 Unit : um (5443.11 , -297.5) Unit: um Part Number ST7586S-G 300 Chip Size 11434 x 701 12 Chip Thickness Bump 10, 11, 31, 39 8, 29, 30, 37, 38 1~7, 9, 12~28, 32~36, 40~134 135~153, 660~678 154~659 Bump Height Bump Size 105 x 63 25 x 63 65 x 63 149.4 x 10.5 10.5 x 149.4 134 35 15 214 215 20 * Refer to "PAD CENTER COORDINATES" for ITO layout 20 598 599 15 1 35 659 (-5443.11 , -297.5) Unit : um Ver-1.1a 2/63 2009/11/30 ST7586S PAD CENTER COORDINATES PAD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 Ver-1.1a NAME VSS1 VPP VPP VPP VPP CL CLS VDD1 VD1S A0 RWR D0 DUMMY D1 D2 D3 D4 D5 D6 D7 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved VSS1 VDD1 ERD RSTB DUMMY IF1 IF2 IF3 VSS1 VDD1 CSB EXTB TE TCAP VDD1 VDD1 VDD1 VDD1 X -5300 -5220 -5140 -5060 -4980 -4900 -4820 -4760 -4700 -4600 -4480 -4380 -4300 -4220 -4140 -4060 -3980 -3900 -3820 -3740 -3660 -3580 -3500 -3420 -3340 -3260 -3180 -3100 -3040 -3000 -2920 -2820 -2740 -2660 -2580 -2500 -2440 -2400 -2320 -2220 -2140 -2060 -1980 -1900 -1820 -1740 Y -283 -283 -283 -283 -283 -283 -283 -283 -283 -283 -283 -283 -283 -283 -283 -283 -283 -283 -283 -283 -283 -283 -283 -283 -283 -283 -283 -283 -283 -283 -283 -283 -283 -283 -283 -283 -283 -283 -283 -283 -283 -283 -283 -283 -283 -283 3/63 PAD 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 NAME VDD1 VDD1 VD1I VD1I VD1I VD1I VD1O VD1O VSS1 VSS1 VSS1 VSS1 VSS1 VSS1 VSSX VSSX VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS4 VSS4 VSS4 VDDX VDDX VDD3 VDD3 VDD4 VDD4 VDD4 VDD5 VDD5 VDD5 VDD5 VDD5 VDD5 VDD5 VDD5 X -1660 -1580 -1500 -1420 -1340 -1260 -1180 -1100 -1020 -940 -860 -780 -700 -620 -540 -460 -380 -300 -220 -140 -60 20 100 180 260 340 420 500 580 660 740 820 900 980 1060 1140 1220 1300 1380 1460 1540 1620 1700 1780 1860 1940 Y -283 -283 -283 -283 -283 -283 -283 -283 -283 -283 -283 -283 -283 -283 -283 -283 -283 -283 -283 -283 -283 -283 -283 -283 -283 -283 -283 -283 -283 -283 -283 -283 -283 -283 -283 -283 -283 -283 -283 -283 -283 -283 -283 -283 -283 -283 2009/11/30 ST7586S PAD 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 Ver-1.1a NAME VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VM VM VM VM VM VM VM VREF V0I V0I V0I V0I V0S V0O V0O XV0O XV0O XV0S XV0I XV0I XV0I XV0I VGO VGO VGS VGI VGI VGI VGI VGI VGI VSS1 COM1 COM3 COM5 COM7 COM9 COM11 X 2020 2100 2180 2260 2340 2420 2500 2580 2660 2740 2820 2900 2980 3060 3140 3220 3300 3380 3460 3540 3620 3700 3780 3860 3940 4020 4100 4180 4260 4340 4420 4500 4580 4660 4740 4820 4900 4980 5060 5140 5220 5300 5606.5 5606.5 5606.5 5606.5 5606.5 5606.5 Y -283 -283 -283 -283 -283 -283 -283 -283 -283 -283 -283 -283 -283 -283 -283 -283 -283 -283 -283 -283 -283 -283 -283 -283 -283 -283 -283 -283 -283 -283 -283 -283 -283 -283 -283 -283 -283 -283 -283 -283 -283 -283 -284.5 -262.5 -240.5 -218.5 -196.5 -174.5 4/63 PAD 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 NAME COM13 COM15 COM17 COM19 COM21 COM23 COM25 COM27 COM29 COM31 COM33 COM35 COM37 COM39 COM41 COM43 COM45 COM47 COM49 COM51 COM53 COM55 COM57 COM59 COM61 COM63 COM65 COM67 COM69 COM71 COM73 COM75 COM77 COM79 COM81 COM83 COM85 COM87 COM89 COM91 COM93 COM95 COM97 COM99 COM101 COM103 COM105 COM107 X 5606.5 5606.5 5606.5 5606.5 5606.5 5606.5 5606.5 5606.5 5606.5 5606.5 5606.5 5606.5 5606.5 5649.33 5627.33 5605.33 5583.33 5561.33 5539.33 5517.33 5495.33 5473.33 5451.33 5429.33 5407.33 5385.33 5363.33 5341.33 5319.33 5297.33 5275.33 5253.33 5231.33 5209.33 5187.33 5165.33 5143.33 5121.33 5099.33 5077.33 5055.33 5033.33 5011.33 4989.33 4967.33 4945.33 4923.33 4901.33 Y -152.5 -130.5 -108.5 -86.5 -64.5 -42.5 -20.5 1.5 23.5 45.5 67.5 89.5 111.5 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 2009/11/30 ST7586S PAD 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 Ver-1.1a NAME COM109 COM111 COM113 COM115 COM117 COM119 COM121 COM123 COM125 COM127 COM129 COM131 COM133 COM135 COM137 COM139 COM141 COM143 COM145 COM147 COM149 COM151 COM153 COM155 COM157 COM159 SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 X 4879.33 4857.33 4835.33 4813.33 4791.33 4769.33 4747.33 4725.33 4703.33 4681.33 4659.33 4637.33 4615.33 4593.33 4571.33 4549.33 4527.33 4505.33 4483.33 4461.33 4439.33 4417.33 4395.33 4373.33 4351.33 4329.33 4213 4191 4169 4147 4125 4103 4081 4059 4037 4015 3993 3971 3949 3927 3905 3883 3861 3839 3817 3795 3773 3751 Y 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 5/63 PAD 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 NAME SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 SEG51 SEG52 SEG53 SEG54 SEG55 SEG56 SEG57 SEG58 SEG59 SEG60 SEG61 SEG62 SEG63 SEG64 SEG65 SEG66 SEG67 SEG68 SEG69 X 3729 3707 3685 3663 3641 3619 3597 3575 3553 3531 3509 3487 3465 3443 3421 3399 3377 3355 3333 3311 3289 3267 3245 3223 3201 3179 3157 3135 3113 3091 3069 3047 3025 3003 2981 2959 2937 2915 2893 2871 2849 2827 2805 2783 2761 2739 2717 2695 Y 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 2009/11/30 ST7586S PAD 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 Ver-1.1a NAME SEG70 SEG71 SEG72 SEG73 SEG74 SEG75 SEG76 SEG77 SEG78 SEG79 SEG80 SEG81 SEG82 SEG83 SEG84 SEG85 SEG86 SEG87 SEG88 SEG89 SEG90 SEG91 SEG92 SEG93 SEG94 SEG95 SEG96 SEG97 SEG98 SEG99 SEG100 SEG101 SEG102 SEG103 SEG104 SEG105 SEG106 SEG107 SEG108 SEG109 SEG110 SEG111 SEG112 SEG113 SEG114 SEG115 SEG116 SEG117 X 2673 2651 2629 2607 2585 2563 2541 2519 2497 2475 2453 2431 2409 2387 2365 2343 2321 2299 2277 2255 2233 2211 2189 2167 2145 2123 2101 2079 2057 2035 2013 1991 1969 1947 1925 1903 1881 1859 1837 1815 1793 1771 1749 1727 1705 1683 1661 1639 Y 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 6/63 PAD 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 NAME SEG118 SEG119 SEG120 SEG121 SEG122 SEG123 SEG124 SEG125 SEG126 SEG127 SEG128 SEG129 SEG130 SEG131 SEG132 SEG133 SEG134 SEG135 SEG136 SEG137 SEG138 SEG139 SEG140 SEG141 SEG142 SEG143 SEG144 SEG145 SEG146 SEG147 SEG148 SEG149 SEG150 SEG151 SEG152 SEG153 SEG154 SEG155 SEG156 SEG157 SEG158 SEG159 SEG160 SEG161 SEG162 SEG163 SEG164 SEG165 X 1617 1595 1573 1551 1529 1507 1485 1463 1441 1419 1397 1375 1353 1331 1309 1287 1265 1243 1221 1199 1177 1155 1133 1111 1089 1067 1045 1023 1001 979 957 935 913 891 869 847 825 803 781 759 737 715 693 671 649 627 605 583 Y 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 2009/11/30 ST7586S PAD 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 Ver-1.1a NAME SEG166 SEG167 SEG168 SEG169 SEG170 SEG171 SEG172 SEG173 SEG174 SEG175 SEG176 SEG177 SEG178 SEG179 SEG180 SEG181 SEG182 SEG183 SEG184 SEG185 SEG186 SEG187 SEG188 SEG189 SEG190 SEG191 SEG192 SEG193 SEG194 SEG195 SEG196 SEG197 SEG198 SEG199 SEG200 SEG201 SEG202 SEG203 SEG204 SEG205 SEG206 SEG207 SEG208 SEG209 SEG210 SEG211 SEG212 SEG213 X 561 539 517 495 473 451 429 407 385 363 341 319 297 275 253 231 209 187 165 143 121 99 77 55 33 11 -11 -33 -55 -77 -99 -121 -143 -165 -187 -209 -231 -253 -275 -297 -319 -341 -363 -385 -407 -429 -451 -473 Y 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 7/63 PAD 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 NAME SEG214 SEG215 SEG216 SEG217 SEG218 SEG219 SEG220 SEG221 SEG222 SEG223 SEG224 SEG225 SEG226 SEG227 SEG228 SEG229 SEG230 SEG231 SEG232 SEG233 SEG234 SEG235 SEG236 SEG237 SEG238 SEG239 SEG240 SEG241 SEG242 SEG243 SEG244 SEG245 SEG246 SEG247 SEG248 SEG249 SEG250 SEG251 SEG252 SEG253 SEG254 SEG255 SEG256 SEG257 SEG258 SEG259 SEG260 SEG261 X -495 -517 -539 -561 -583 -605 -627 -649 -671 -693 -715 -737 -759 -781 -803 -825 -847 -869 -891 -913 -935 -957 -979 -1001 -1023 -1045 -1067 -1089 -1111 -1133 -1155 -1177 -1199 -1221 -1243 -1265 -1287 -1309 -1331 -1353 -1375 -1397 -1419 -1441 -1463 -1485 -1507 -1529 Y 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 2009/11/30 ST7586S PAD 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 Ver-1.1a NAME SEG262 SEG263 SEG264 SEG265 SEG266 SEG267 SEG268 SEG269 SEG270 SEG271 SEG272 SEG273 SEG274 SEG275 SEG276 SEG277 SEG278 SEG279 SEG280 SEG281 SEG282 SEG283 SEG284 SEG285 SEG286 SEG287 SEG288 SEG289 SEG290 SEG291 SEG292 SEG293 SEG294 SEG295 SEG296 SEG297 SEG298 SEG299 SEG300 SEG301 SEG302 SEG303 SEG304 SEG305 SEG306 SEG307 SEG308 SEG309 X -1551 -1573 -1595 -1617 -1639 -1661 -1683 -1705 -1727 -1749 -1771 -1793 -1815 -1837 -1859 -1881 -1903 -1925 -1947 -1969 -1991 -2013 -2035 -2057 -2079 -2101 -2123 -2145 -2167 -2189 -2211 -2233 -2255 -2277 -2299 -2321 -2343 -2365 -2387 -2409 -2431 -2453 -2475 -2497 -2519 -2541 -2563 -2585 Y 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 8/63 PAD 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550 551 552 553 554 555 556 557 558 559 560 561 562 563 564 565 566 567 568 569 570 571 572 NAME SEG310 SEG311 SEG312 SEG313 SEG314 SEG315 SEG316 SEG317 SEG318 SEG319 SEG320 SEG321 SEG322 SEG323 SEG324 SEG325 SEG326 SEG327 SEG328 SEG329 SEG330 SEG331 SEG332 SEG333 SEG334 SEG335 SEG336 SEG337 SEG338 SEG339 SEG340 SEG341 SEG342 SEG343 SEG344 SEG345 SEG346 SEG347 SEG348 SEG349 SEG350 SEG351 SEG352 SEG353 SEG354 SEG355 SEG356 SEG357 X -2607 -2629 -2651 -2673 -2695 -2717 -2739 -2761 -2783 -2805 -2827 -2849 -2871 -2893 -2915 -2937 -2959 -2981 -3003 -3025 -3047 -3069 -3091 -3113 -3135 -3157 -3179 -3201 -3223 -3245 -3267 -3289 -3311 -3333 -3355 -3377 -3399 -3421 -3443 -3465 -3487 -3509 -3531 -3553 -3575 -3597 -3619 -3641 Y 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 2009/11/30 ST7586S PAD 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600 601 602 603 604 605 606 607 608 609 610 611 612 613 614 615 616 617 618 619 620 Ver-1.1a NAME SEG358 SEG359 SEG360 SEG361 SEG362 SEG363 SEG364 SEG365 SEG366 SEG367 SEG368 SEG369 SEG370 SEG371 SEG372 SEG373 SEG374 SEG375 SEG376 SEG377 SEG378 SEG379 SEG380 SEG381 SEG382 SEG383 COM158 COM156 COM154 COM152 COM150 COM148 COM146 COM144 COM142 COM140 COM138 COM136 COM134 COM132 COM130 COM128 COM126 COM124 COM122 COM120 COM118 COM116 X -3663 -3685 -3707 -3729 -3751 -3773 -3795 -3817 -3839 -3861 -3883 -3905 -3927 -3949 -3971 -3993 -4015 -4037 -4059 -4081 -4103 -4125 -4147 -4169 -4191 -4213 -4329.33 -4351.33 -4373.33 -4395.33 -4417.33 -4439.33 -4461.33 -4483.33 -4505.33 -4527.33 -4549.33 -4571.33 -4593.33 -4615.33 -4637.33 -4659.33 -4681.33 -4703.33 -4725.33 -4747.33 -4769.33 -4791.33 Y 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 9/63 PAD 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 645 646 647 648 649 650 651 652 653 654 655 656 657 658 659 660 661 662 663 664 665 666 667 668 NAME COM114 COM112 COM110 COM108 COM106 COM104 COM102 COM100 COM98 COM96 COM94 COM92 COM90 COM88 COM86 COM84 COM82 COM80 COM78 COM76 COM74 COM72 COM70 COM68 COM66 COM64 COM62 COM60 COM58 COM56 COM54 COM52 COM50 COM48 COM46 COM44 COM42 COM40 COM38 COM36 COM34 COM32 COM30 COM28 COM26 COM24 COM22 COM20 X -4813.33 -4835.33 -4857.33 -4879.33 -4901.33 -4923.33 -4945.33 -4967.33 -4989.33 -5011.33 -5033.33 -5055.33 -5077.33 -5099.33 -5121.33 -5143.33 -5165.33 -5187.33 -5209.33 -5231.33 -5253.33 -5275.33 -5297.33 -5319.33 -5341.33 -5363.33 -5385.33 -5407.33 -5429.33 -5451.33 -5473.33 -5495.33 -5517.33 -5539.33 -5561.33 -5583.33 -5605.33 -5627.33 -5649.33 -5606.5 -5606.5 -5606.5 -5606.5 -5606.5 -5606.5 -5606.5 -5606.5 -5606.5 Y 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 111.5 89.5 67.5 45.5 23.5 1.5 -20.5 -42.5 -64.5 2009/11/30 ST7586S PAD 669 670 671 672 673 674 675 676 677 678 NAME COM18 COM16 COM14 COM12 COM10 COM8 COM6 COM4 COM2 COM0 X -5606.5 -5606.5 -5606.5 -5606.5 -5606.5 -5606.5 -5606.5 -5606.5 -5606.5 -5606.5 Y -86.5 -108.5 -130.5 -152.5 -174.5 -196.5 -218.5 -240.5 -262.5 -284.5 Unit : um Ver-1.1a 10/63 2009/11/30 ST7586S BLOCK DIAGRAM RSTB TE TCAP VD1S ERD RWR A0 CSB D[7:0] IF[3:1] Ver-1.1a 11/63 2009/11/30 ST7586S PIN DESCRIPTION Power System Name VDD1 VDD2~5 VDDX VSS1 VSS2 VSS4 VSSX Type Power Power Power Power Power Power VDD1 is the power of interface I/O circuit. VDD2 is the analog power for internal booster. VDD3~5 are the analog power for LCD driver. VDD2~5 and VDDX are separated in ITO and connected together by FPC or PCB. Digital power for OSC circuit. VDD2~5 and VDDX are separated in ITO and connected together by FPC or PCB. Ground of interface, logic (VSS1) and OSC (VSSX) circuits. Ground system should be connected together by FPC or PCB. Ground of booster (VSS2) and LCD (VSS4) driver. Ground system should be connected together by FPC or PCB. Ground of OSC circuit. Ground system should be connected together by FPC or PCB. Digital power source selection. VD1S = "L": the power source of digital circuit is VDD1. VD1S = "H": the power source of digital circuit is internal regulator. VDD1 (TYP.) VD1S Input 1.8 2.8 3.0 3.3 VD1I VD1O V0O V0I V0S Power Cap. of VD1 and VSS Unnecessary Necessary Necessary Necessary Level of VD1S VSS1 VDD1 VDD1 VDD1 Description VD1I is the power source of digital circuits. VD1O is the VD1 output. VD1I and VD1O should be connected together by FPC or PCB. Positive operating voltage of COM-drivers. V0O is the output of the positive Vop generator. V0I is the positive Vop supply of LCD drivers. V0S is the sensor of the positive Vop generator. V0O, V0I & V0S should be separated on ITO and be connected together by FPC. Negative operating voltage of COM-drivers. Power Power Input XV0O XV0I XV0S Power Power Input XV0O is the output of the negative Vop generator. XV0I is the negative Vop supply of LCD drivers. XV0S is the sensor of the negative Vop generator. XV0O, XV0I & XV0S should be separated on ITO and be connected together by FPC. VG is the power of SEG-drivers. VM is the non-select voltage level of COM-drivers. VGO is the output of the VG regulator. VGI is the supply of SEG-drivers. VGO VGI VGS VM Power Power Input Power VGS is the sensor of the VG regulator. VGO, VGI & VGS should be separated on ITO and be connected together by FPC. Be sure the relationships (as shown below) among the LCD driving voltages: V0 VG VM VSS XV0; VDDA-0.7 VM 0.9V; and 2*VDDA-0.7 VG 1.8V When this IC is operating, VG and VM are generated according to the bias setting shown below: LCD Bias 1/N Bias VG (2/N) x V0 VM (1/N) x V0 Note: N = 9~14 Ver-1.1a 12/63 2009/11/30 ST7586S LCD Driver Outputs Name Type LCD SEG-driver outputs. The display data and the polar-signal (M) control the output voltage of SEG-driver. Display Data SEG0 to SEG383 Output H H L L H L H L M Segment Driver Output Voltage Normal Display VG VSS VSS VG VSS Reverse Display VSS VG VG VSS VSS Description Display OFF, Sleep-In mode LCD COM-driver outputs. The internal scanning data and the polar-signal (M) control the output voltage of COM-driver. Scan data COM0 to COM159 Output H H L L M H L H L Common Driver Output Voltage XV0 V0 VM VM VSS Display OFF, Sleep-In mode Microprocessor Interface Name RSTB Type Input Description Reset input pin. When RSTB is "L", internal initialization procedure is executed. These pins select interface operation mode. IF3 H IF[3:1] Input H L L IF2 H L H H IF1 L L H L MPU interface type 80 series 8-bit parallel 68 series 8-bit parallel 8-bit serial (4-Line) 9-bit serial (3-Line) Note: Refer to "Interface Selection" for detailed information. Chip select input pin. CSB Input CSB="L": This chip is selected and the MPU interface is active. CSB="H": This chip is not selected and the MPU interface is disabled (D[7:0] are high impedance). The function of this pin is different in parallel and serial interface. In parallel interface: A0 is register selection input. A0 Input A0 = "H": inputs on data bus are display data; A0 = "L": inputs on data bus are command. In serial interface: this pad will be used as SCL (serial-clock) input Read / Write execution control pin. (This pin is only used in parallel interface) MPU Type 6800-series RWR R/W R/W = "H" : read R/W = "L" : write 8080-series /WR Write enable clock input pin. The data are latched at the rising edge of the /WR signal. Description Read / Write control input pin RWR Input This pin is not used in serial interfaces and should be connected to VDD1. Ver-1.1a 13/63 2009/11/30 ST7586S Name Type MPU Type ERD Description Read / Write execution control pin. (This pin is only used in parallel interface) Description Read / Write control input pin. ERD Input 6800-series E R/W = "H": When E is "H", data bus is in output status. R/W = "L": The data are latched at the falling edge of the E signal. 8080-series /RD Read enable input pin. When /RD is "L", data bus is in output status. This pin is not used in serial interfaces and should be connected to VDD1. The bi-directional data bus of the MPU interface. When CSB is "H", they are high impedance. D[7:0] I/O If using serial interface: D0 is the SDA signal in 4-Line & 3-Line interface. D1 is the A0 signal in 4-Line interface. Note: 1. 2. After VDD1 is turned ON, all MPU interface pins should not be left OPEN. The un-used pins should be connected to VDD1. OTP Pins Name VPP Type Power Description The programming power supply of the built-in OTP. Apply external power (6.5~6.75V) here when programming (> 8mA for successful programming). EXTB="L": Enable the extension operation mode. EXTB Input When programming OTP, connect EXTB to VSS1 externally. This pin has an internal pull-high resistor. Please leave this pin OPEN after special operation. Test Pins Name CLS CL TCAP VREF TE Type Test Test Test Test Test Reserved for testing only. Please fix this pin to VDD1. Reserved for testing only. Leave this pin open. Reserved for testing only. Leave this pin open. Reserved for testing only. Leave this pin open. Reserved for testing only. Leave this pin open. Description Ver-1.1a 14/63 2009/11/30 ST7586S ITO Resistance Limitation Pin Name VDDX, VDD1~VDD5, VSSX, VSS1, VSS2, VSS4, V0I, V0O, V0S, XV0I, XV0O, XV0S, VM VPP, VGI, VGO, VGS A0, ERD, RWR, CSB, D[7:0], (SDA), (SCL), TE RSTB IF[3:1], CLS, EXTB TCAP, CL, VREF Note: 1. 2. 3. Make sure that the ITO resistance of COM0 ~ COM159 is equal, and so is it of SEG0 ~ SEG383. These Limitations include the bottleneck of ITO layout. Refer to the application note for ITO layout guideline. ITO Resister <100 <50 <700 <10K <1K Floating Ver-1.1a 15/63 2009/11/30 ST7586S FUNCTION DESCRIPTION Microprocessor Interface Chip Select Input CSB pin is used for chip selection. ST7586S can interface with an MPU when CSB is "L". If CSB is "H", the inputs of A0, ERD and RWR with any combination will be ignored and D[7:0] are high impedance. In 3-Line and 4-Line serial interfaces, the internal shift register and serial counter are reset when CSB is "H". Interface Selection The interface selection is controlled by IF[3..1] pins. Please refer to the table below: Table 1 Setting IF3 H H L L IF2 H L H H IF1 L L H L MPU Type Parallel 8080 series MPU Parallel 6800 series MPU Serial 4-Line series MPU Serial 3-Line series MPU CSB SCL Interface Pin Function CSB A0 A0 RWR /WR R/W --ERD /RD E --D[7:0] D[7:0] D1=A0; D0=SDA. D[7:2] are not used. D0=SDA. D[7:1] are not used. Note: The un-used pins are marked as "--" and should be fixed to "H" by "VDD1". Parallel Interface When parallel interface is selected, the interface transmission type will be determined by the combination of the control signals. Please refer to the table below: Table 2 8080 series MPU /WR H H /RD H H 6800 series MPU R/W L L H H E A0 L H H H L CSB Interface Transmission Type Write Command Write Display Data or Parameter Read Display Data or Parameter Start Read Display Data or Parameter Stop Note: Reading Display Data or Parameter is specified by the instruction before the read operation. Serial Interface In serial interface mode (4-Line or 3-Line), IC is active when CSB is "L". Control signals (SDA, SCL and A0 for 4-Line) are enabled when CSB is "L". When CSB is "H", the MPU interface is not active and the internal shift register and counter are reset. It is recommended to set CSB to "H" after each byte transmission. In 4-Line serial interface, A0 signal is latched at the 8 rising edge of the SCL signal (refer to Fig. 1). th Fig. 1 Write-Operation of 4-Line Serial Interface Ver-1.1a 16/63 2009/11/30 ST7586S In 3-Line interface, A0 signal is not available and the 1 output of SDA will be treated as A0 flag (refer to Fig. 2). st Fig. 2 Write-Operation of 4-Line Serial Interface Ver-1.1a 17/63 2009/11/30 ST7586S Display Data RAM (DDRAM) ST7586S containing a 384x160x2 bit static RAM stores the display data. The display data RAM (DDRAM) stores the pixel data of the LCD. The built-in DDRAM is an addressable memory array with 384 columns by 160 rows. ST7586S provides two kinds of display modes (monochrome mode and 4-level gray scale mode) and a fast-addressing mode for fast updating display data. Each column address represents 3 sub-columns. For example, setting the column address to "01h" means that upcoming 8 bits data is addressing to column 3; column 4 and column 5 respectively (refer to Fig. 3 and Fig. 4). The display data which is written by MCU will be stored in DDRAM with the format of D7 at the left and D0 at the right when MX=0 (refer to Fig. 3 and Fig. 4). The row address is directly related to the row output number. The LCD controller reads the pixel data in DDRAM, and then it outputs to COM/SEG pad. While the LCD controller operates independently, display data can be written into DDRAM at the same time and data is also being displayed on LCD panel without causing the abnormal display. SEG 3N (3 Bits) SEG 3N+1 (3 Bits) SEG 3N+2 (2 Bits) SEG 3N (3 Bits) SEG 3N+1 (3 Bits) SEG 3N+2 (2 Bits) D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 11110001 00010011 11100100111001 01001110000101 11110011000010 11001110000011 001011 111001 000101 100001 Display Data RAM Liquid Crystal Display 11110011111001 01110011000101 11100110100001 01001110000101 100111 100110 001101 011100 SEG 381 SEG 382 Column 381 Column 382 Column 383 SEG 383 SEG 0 SEG 1 SEG 2 SEG 3 SEG 4 SEG 5 Column 0 Column 1 Column 2 Column 3 Column 4 Column 5 Column 6 3 Bits Data D7 D6 D5 (D4) (D3) (D2) 1 0 1 0 1 0 0 1 1 0 0 0 DDRAM 1 0 1 0 1 0 0 1 LCD 2 Bits Data D1 1 0 1 0 D0 1 0 0 1 DDRAM 1 0 1 0 1 0 0 1 LCD Fix LSB to 0 if Gray Mode Fig. 3 DDRAM Mapping (4-Level Gray Scale Mode) Ver-1.1a 18/63 SEG 6 2009/11/30 ST7586S SEG 3N (3 Bits) SEG 3N+1 (3 Bits) SEG 3N+2 (2 Bits) SEG 3N (3 Bits) SEG 3N+1 (3 Bits) SEG 3N+2 (2 Bits) D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 11X00X00 00X11X11 11000000110011 00001100001100 11110011000011 11001111000011 001111 110000 001100 110000 Display Data RAM Liquid Crystal Display 11110011111100 00110011001111 11000011110000 00001100001100 110011 000011 001100 111100 SEG 381 SEG 382 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 96h 97h 98h 99h 9Ah 9Bh 9Ch 9Dh 9Eh 9Fh Row Address Column 381 Column 382 Column 383 SEG 383 160 Rows SEG 0 SEG 1 SEG 2 SEG 3 SEG 4 SEG 5 Column 0 Column 1 Column 2 Column 3 Column 4 Column 5 Column 6 3 Bits Data D7 D6 D5 (D4) (D3) (D2) 1 0 1 0 X X DDRAM 1 0 1 0 LCD 2 Bits Data D1 1 0 D0 1 0 DDRAM 1 0 1 0 LCD Fig. 4 DDRAM Mapping (Monochrome Mode) 384 Columns Column Address 00h 01h 02h 7Dh SEG 6 7Eh 7Fh D7 D0 Fig. 5 DDRAM Format Ver-1.1a 19/63 2009/11/30 ST7586S Addressing In order to allow MCU accessing display data continuously, the address counter is automatically increasing by one (+1) after accessing each byte of display data (i.e. "White Display Data" in all interface or "Read Display Data" in parallel interface). The locations of RAM are addressed by the address pointers (XS, XE, YS and YE). The address ranges are X=0~127 (column address) and Y=0~159 (row address). Addresses outside these range is not allowed. Before writing to DDRAM, a "window" must be defined for the incoming display data. By specifying the address pointers XS, XE, YS and YE, a "window" is established. The instruction registers XS and YS identify the start addresses while XE and YE identifying the end addresses. For example, the whole display range will be written via the following values to define 384x160: XS=0 (00h), YS=0 (00h) and XE=127 (7Fh), YE=159 (9Fh). Column Address Circuit The column address of DDRAM is specified by the "Set Column Address" instruction. Each column address includes three sub-columns Column N, Column N+1 and Column N+2 respectively ("N" is the column address value). The column address counter is increased by one (+1) after each byte of display data accessed (write/read). The starting column address is defined by XS and the ending column address is defined by XE. The column address counter will be returned to the starting column address (XS) immediately if the increment of the column address exceeds the boundary column address (XE). Row Address Circuit The circuit provides the row address of DDRAM. The row address is increased by one (+1) after the column address counter is over XE. The row address will be returned to starting row address (YS) immediately when the row address is increased by one over the ending row address (YE). Ver-1.1a 20/63 2009/11/30 ST7586S LCD Display Function DDRAM Map to LCD Driver Output The internal relation between DDRAM and LCD driver circuit (SEG/COM output path) with different MX or MY setting is illustrated below. Column Address MX=0 MX=1 Row Address 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h 21h 22h 23h 24h 25h 26h 27h 28h 29h 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh 30h 31h 32h 33h 34h 35h 36h 37h 38h 39h 3Ah 3Bh 3Ch 3Dh 3Eh 3Fh Start Line: S[7..0]=00h First Output COM: FC[7..0]=00h COM PAD COM0 COM159 COM1 COM158 COM2 COM157 COM3 COM156 COM4 COM155 COM5 COM154 COM6 COM153 COM7 COM152 COM8 COM151 COM9 COM150 COM10 COM149 COM11 COM148 COM12 COM147 COM13 COM146 COM14 COM145 COM15 COM144 COM16 COM143 COM17 COM142 COM18 COM141 COM19 COM140 COM20 COM139 COM21 COM138 COM22 COM137 COM23 COM136 COM24 COM135 COM25 COM134 COM26 COM133 COM27 COM132 COM28 COM131 COM29 COM130 COM30 COM129 COM31 COM128 COM32 COM127 COM33 COM126 COM34 COM125 COM35 COM124 COM36 COM123 COM37 COM122 COM38 COM121 COM39 COM120 COM40 COM119 COM41 COM118 COM42 COM117 COM43 COM116 COM44 COM115 COM45 COM114 COM46 COM113 COM47 COM112 COM48 COM111 COM49 COM110 COM50 COM109 COM51 COM108 COM52 COM107 COM53 COM106 COM54 COM105 COM55 COM104 COM56 COM103 COM57 COM102 COM58 COM101 COM59 COM100 COM60 COM99 COM61 COM98 COM62 COM97 COM63 COM96 MY=0 MY=1 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch 8Dh 8Eh 8Fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9Ah 9Bh 9Ch 9Dh 9Eh 9Fh COM128 COM129 COM130 COM131 COM132 COM133 COM134 COM135 COM136 COM137 COM138 COM139 COM140 COM141 COM142 COM143 COM144 COM145 COM146 COM147 COM148 COM149 COM150 COM151 COM152 COM153 COM154 COM155 COM156 COM157 COM158 COM159 COM31 COM30 COM29 COM28 COM27 COM26 COM25 COM24 COM23 COM22 COM21 COM20 COM19 COM18 COM17 COM16 COM15 COM14 COM13 COM12 COM11 COM10 COM9 COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1 COM0 MX=0 SEG PAD MX=1 Fig. 6 DDRAM Display Direction Ver-1.1a 21/63 2009/11/30 ST7586S Line Address Circuit This circuit assigns DDRAM a Line Address corresponding to the first line (setting by instruction of First Output COM) of display. Therefore, by setting Line Address repeatedly, ST7586S is possible to realize the screen scrolling without changing the content of DDRAM as shown in Fig. 7. Column Address MX=0 MX=1 Row Address 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h 21h 22h 23h 24h 25h 26h 27h 28h 29h 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh 30h 31h 32h 33h 34h 35h 36h 37h 38h 39h 3Ah 3Bh 3Ch 3Dh 3Eh 3Fh COM PAD COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 COM17 COM18 COM19 COM20 COM21 COM22 COM23 COM24 COM25 COM26 COM27 COM28 COM29 COM30 COM31 COM32 COM33 COM34 COM35 COM36 COM37 COM38 COM39 COM40 COM41 COM42 COM43 COM44 COM45 COM46 COM47 COM48 COM49 COM50 COM51 COM52 COM53 COM54 COM55 COM56 COM57 COM58 COM59 COM60 COM61 COM62 COM63 MY=0 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch 8Dh 8Eh 8Fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9Ah 9Bh 9Ch 9Dh 9Eh 9Fh COM128 COM129 COM130 COM131 COM132 COM133 COM134 COM135 COM136 COM137 COM138 COM139 COM140 COM141 COM142 COM143 COM144 COM145 COM146 COM147 COM148 COM149 COM150 COM151 COM152 COM153 COM154 COM155 COM156 COM157 COM158 COM159 MX=0 SEG PAD MX=1 Fig. 7 Display Data RAM Map (1/160 Duty) Ver-1.1a 22/63 2009/11/30 ST7586S Partial Display This function is defining the visible display area as illustrated in Fig. 8. The different partial display area setting will be changing frame rate or Vop to avoid abnormal display. The recommended range of partial display area setting is defined from 64 duty to 160 duty. The partial display setting is combining the instructions of Partial Display and Partial Display Area. Display Area Display Area Display Area Fig. 8 Partial Display Definition Rolling Scroll This function is determined by the instructions of Scroll Area and Start Line. TA, SA and BA meaning Top Area, Scrolling Area and Bottom Area respectively. The instruction of Scroll Area setting must correspond to TA+SA+BA=160. Depending on the Scroll Area setting, the setting range of Start Line must correspond to TAS[7..0]<(TA+SA). Start Line S[7..0] Fig. 9 Scroll Definition Ver-1.1a 23/63 2009/11/30 ST7586S Liquid Crystal Driver Power Circuit The built-in power circuits generate the voltage levels which are necessary to drive the liquid crystal. It consumes low power with the fewest external component. The built-in power system has voltage booster, voltage regulator and voltage follower circuits. Before power ST7586S is OFF, a Power OFF procedure is needed. Please refer to the OPERATION FLOW section. External Component of Power Circuit The recommended external power components need only three capacitors. The detailed values of these three capacitors are determined by panel size and loading. Fig. 10 Power Circuit Ver-1.1a 24/63 2009/11/30 ST7586S Temperature Gradient Selection Circuit SET V0 with temperature compensation (Temperature 24 C) There are 16-line slopes in each temperature step, and customer can select one line slope of temperature compensation coefficient for each temperature step. Each temperature step is 8 Please see Fig. 11 as below. C. Fig. 11 Temperature Compensation Coefficient Selection In instruction Temperature Gradient Compensation each parameter MTx, where x=0, 1, 2,..., E, F has a setting value between 0 and 15. MTx=0 results in Mx=0V increment on V0, MTx=1 results in Mx=5mV increment,..., MTx=15 results in Mx=15x5mV=75mV increment. Note that each MTx individually corresponds to a temperature interval; the Mx means temperature gradient slope coefficient. The relations between Mx and V0 quantity due to temperature V0(T) are described in the equation shown in Table 3. Temerature Range -40 T < -32 C C -32 T < -24 C C -24 T < -16 C C -16 T < -8 C C -8 T < 0 C C 0 T < 8 C C 8 T < 16 C C 16 T < 24 C C 24 T < 32 C C 32 T < 40 C C 40 T < 48 C C 48 T < 56 C C 56 T < 64 C C 64 T < 72 C C 72 T < 80 C C 80 T < 88 C C Equation V0(T) at temperature=T C V0(T) = V0(T24) + (-32 - T) x M0 + (M1 + M2 + M3 + M4 + M5 + M6 + M7) x 8 V0(T) = V0(T24) + (-24 - T) x M1 + (M2 + M3 + M4 + M5 + M6 + M7) x 8 V0(T) = V0(T24) + (-16 - T) x M2 + (M3 + M4 + M5 + M6 + M7) x 8 V0(T) = V0(T24) + (-8 - T) x M3 + (M4 + M5 + M6 + M7) x 8 V0(T) = V0(T24) + (0 - T) x M4 + (M5 + M6 + M7) x 8 V0(T) = V0(T24) + (8 - T) x M5 + (M6 + M7) x 8 V0(T) = V0(T24) + (16 - T) x M6 + M7 x 8 V0(T) = V0(T24) + (24 - T) x M7 V0(T) = V0(T24) - (T - 24) x M8 V0(T) = V0(T24) - (T - 32) x M9 - M8 x 8 V0(T) = V0(T24) - (T - 40) x M10 - (M9 + M8) x 8 V0(T) = V0(T24) - (T - 48) x M11 - (M10 + M9 + M 8) x 8 V0(T) = V0(T24) - (T - 56) x M12 - (M11 + M10 + M9 + M8) x 8 V0(T) = V0(T24) - (T - 64) x M13 - (M12 + M11 + M10 + M9 + M8) x 8 V0(T) = V0(T24) - (T - 72) x M14 - (M13 + M12 + M11 + M10 + M9 + M8) x 8 V0(T) = V0(T24) - (T - 80) x M15 - (M14 + M13 + M12 + M11 + M10 + M9 + M8) x 8 Table 3 Ver-1.1a 25/63 2009/11/30 ST7586S Fig. 12 Note: Temperature Gradient Compensation Please make sure to avoid any kind of heating source near ST7586S such as back light, to prevent Vop is not anticipative because of temperature compensation circuit is working. Ver-1.1a 26/63 2009/11/30 ST7586S Frequency Temperature Gradient Compensation Coefficient Register Loading Detection ST7586S will auto-switch frame rate in different temperature such as Fig. 13. TA, TB and TC are frame rate switching temperature which can be defined by customer with instruction Temperature Range. FRA, FRB, FRC and FRD are switched frame rate which also can be defined by customer with instruction Frame Rate. The frame rate range is from 18.75Hz to 170Hz. Frame Rate (Hz) TA 80 FRD 70 FRC 60 50 40 30 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Temperature (C) 5C 5C 5C TB TC FRB FRA Fig. 13 Frame Rate Ver-1.1a 27/63 2009/11/30 ST7586S RESET CIRCUIT Setting RSTB pin to "L" (hardware reset) or instruction RESET (software reset) can initialize internal function. Please note the hardware reset is not same as the software reset. Generally, VDD1 is not stable at the time that the system power is just turned ON. The hardware reset is required to initialize internal registers after VDD1 is stable. Initialization by RSTB pin is essential before operating. The default values of registers are listed below: After Hardware Reset No Change Start Address End Address Start Address End Address 00h 7Fh 00h 9Fh Sleep IN Mode Partial Mode OFF Start Address End Address 00h 9Fh Inverse Display OFF All Pixel ON Mode OFF Display OFF SEG Direction COM Direction Start Line Display Duty First Output COM N-Line Inversion Read Modify Write Vop[8:0] BIAS Booster Level SEG0 COM0 SEG383 COM159 00h 9Fh 00h 8Ch Disable 142h 1/10 x8 Table 4 After Software Reset No Change 00h 7Fh 00h 9Fh Sleep IN Mode Partial Mode OFF 00h 9Fh Inverse Display OFF All Pixel ON Mode OFF Display OFF No Change No Change 00h 9Fh 00h 8Ch Disable 142h 1/10 x8 Procedure DDRAM Content Column Address Row Address Power Save Mode Partial Mode Partial Display Area Inverse Display All Pixel ON Display ON/OFF Display Control Ver-1.1a 28/63 2009/11/30 ST7586S INSTRUCTION TABLE INSTRUCTION NOP RESET Power Save A0 0 0 0 R/W 0 0 0 COMMAND BYTE D7 0 0 0 D6 0 0 0 D5 0 0 0 D4 0 0 1 D3 0 0 0 D2 0 0 0 D1 0 0 0 D0 0 1 DESCRIPTION No operation Software reset Set power save mode SLP SLP=0: Sleep in mode SLP=1: Sleep out mode Set partial mode PTL PTL=0: Partial mode on PTL=1: Partial mode off INV Set inverse display mode INV=0: Normal display INV=1: Inverse display Set all pixel on mode AP=0: All pixel off mode AP=1: All pixel on mode Partial Mode 0 0 0 0 0 1 0 0 1 Inverse Display 0 0 0 0 1 0 0 0 0 All Pixel ON/OFF 0 0 0 0 1 0 0 0 1 AP Display ON/OFF 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 XS7 XE7 0 YS7 YE7 0 D7 0 D7 0 0 0 XS6 XE6 0 YS6 YE6 0 D6 0 D6 0 1 1 XS5 XE5 1 YS5 YE5 1 D5 1 D5 1 0 0 XS4 XE4 0 YS4 YE4 0 D4 0 D4 1 1 1 XS3 XE3 1 YS3 YE3 1 D3 1 D3 0 0 0 XS2 XE2 0 YS2 YE2 1 D2 1 D2 0 0 1 XS9 XS1 XE9 XE1 1 YS9 YS1 YE9 YE1 0 D1 1 D1 0 Set LCD display DSP DSP=0: Display off DSP=1: Display on 0 Set column address XS8 Starting column address: XS0 00hXS7Fh Ending column address: XE8 XSXE7Fh XE0 1 Set row address YS8 Starting row address: YS0 00hYS9Fh Ending row address: YE8 YSYE9FH YE0 0 D0 0 D0 0 Write display data to DDRAM Read display data from DDRAM XS15 XS14 XS13 XS12 XS11 XS10 XE15 XE14 XE13 XE12 XE11 XE10 Set Column Address 1 1 1 0 1 YS15 YS14 YS13 YS12 YS11 YS10 YE15 YE14 YE13 YE12 YE11 YE10 Set Row Address 1 1 1 0 1 0 1 0 1 Write Display Data Read Display Data Partial Display Area 1 1 1 0 1 1 1 0 Set partial area PTS15 PTS14 PTS13 PTS12 PTS11 PTS10 PTS9 PTS8 Partial display address start: 00hPTS9Fh PTS7 PTS6 PTS5 PTS4 PTS3 PTS2 PTS1 PTS0 Partial display address end: PTE15 PTE14 PTE13 PTE12 PTE11 PTE10 PTE9 PTE8 00hPTE9Fh Display Area: 64Duty160 PTE7 PTE6 PTE5 PTE4 PTE3 PTE2 PTE1 PTE0 0 TA7 SA7 BA7 0 0 TA6 SA6 BA6 0 1 TA5 SA5 BA5 1 1 TA4 SA4 BA4 1 0 TA3 SA3 BA3 0 0 TA2 SA2 BA2 1 1 TA1 SA1 BA1 1 1 Set scroll area TA0 Top Area: TA=00h~A0h Scrolling Area: SA=00h~A0h SA0 Bottom Area: BA=00h~A0h BA0 TA+SA+BA=160 0 Set scan direction of COM and SEG MY=0: COM0 COM159 MY=1: COM159 COOM0 MX=0: SEG0 SEG383 MX=1: SEG383 SEG0 Set display start line S=00h~9Fh Scroll Area Display Control 1 Start Line 0 1 0 0 0 MY 0 S7 MX 0 S6 0 1 S5 0 1 S4 0 0 S3 0 1 S2 0 1 S1 0 1 S0 Ver-1.1a 29/63 2009/11/30 ST7586S INSTRUCTION A0 R/W COMMAND BYTE D7 0 0 0 1 DT7 1 FC7 1 0 1 1 1 M D6 0 0 0 0 DT6 0 FC6 0 0 0 0 0 0 D5 1 1 0 1 DT5 1 FC5 1 0 1 1 1 0 D4 1 1 0 1 DT4 1 FC4 1 0 1 0 1 NL4 D3 1 1 0 0 DT3 0 FC3 0 0 0 0 0 NL3 D2 0 0 0 0 DT2 0 FC2 0 0 1 0 1 NL2 D1 0 1 1 0 DT1 0 FC1 1 0 0 0 NL1 D0 M 0 0 0 DT0 1 1 0 0 1 NL0 DESCRIPTION Set display mode M=0: Gray mode M=1: Monochrome mode Enable DDRAM interface Set display duty DT=03h~9Fh Display Mode Enable DDRAM Interface Display Duty First Output COM FOSC Divider Partial Display N-Line Inversion 0 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 Set first output COM FC0 FC=00h~9Fh Set FOSC dividing ratio Set partial display mode Set N-Line inversion FOD1 FOD0 Read Modify Write 0 0 1 0 1 1 1 0 0 Read modify write control RMW=0: Enable read modify RMW write RMW=1: Disable read modify write 0 Vop0 Set Vop Vop8 1 0 1 BS0 0 1 0 1 1 1 0 0 1 0 1 0 1 1 1 Vop increase one step Vop decrease one step Set BIAS system Set booster level Set Vop offset Enable analog circuit Auto read control XARD=0: Enable auto read XARD=1: Disable auto read OTP WR/RD control WR/RD=0: Enable OTP read WR/RD=1: Enable OTP write OTP control out OTP programming procedure OTP up-load procedure OTP selection control Ctrl=0: Disable OTP Ctrl=1: Enable OTP OTP programming setting 0 Set Vop Vop Increase Vop Decrease BIAS System Booster Level Vop Offset Analog Control 1 1 0 0 0 1 0 1 0 1 0 1 0 1 0 OTP WR/RD Control OTP Control Out OTP Write OTP Read OTP Selection Control OTP Programming Setting 1 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Vop7 1 1 1 1 1 0 1 0 1 1 1 0 1 1 1 1 0 1 0 1 Vop6 1 1 1 1 1 1 0 1 0 1 0 1 1 1 1 Ctrl 1 0 0 Vop5 0 0 0 0 0 0 0 0 0 1 WR /RD 1 1 1 1 0 1 0 0 Vop4 0 0 0 0 0 1 1 1 XARD 0 0 0 0 0 0 1 0 0 0 Vop3 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 1 0 1 0 Vop2 0 0 0 BS2 1 1 0 1 1 1 0 0 0 0 0 1 0 1 1 0 Vop1 0 1 1 BS1 0 1 0 0 1 1 0 0 0 1 1 0 0 0 1 BST2 BST1 BST0 VOF6 VOF5 VOF4 VOF3 VOF2 VOF1 VOF0 Auto Read Control Ver-1.1a 30/63 2009/11/30 ST7586S INSTRUCTION A0 0 Frame Rate (Gray Scale Mode) 1 1 1 1 0 Frame Rate (Monochrome Mode) 1 1 1 1 0 Temperature Range 1 1 1 0 1 1 Temperature Gradient Compensation 1 1 1 1 1 1 R/W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COMMAND BYTE D7 1 1 1 1 D6 1 1 1 TA6 TB6 TC6 1 D5 1 1 1 TA5 TB5 TC5 1 D4 1 D3 0 D2 0 D1 0 D0 0 DESCRIPTION FRA4 FRA3 FRA2 FRA1 FRA0 Frame rate setting in different FRB4 FRB3 FRB2 FRB1 FRB0 temperature range (Gray scale FRC4 FRC3 FRC2 FRC1 FRC0 mode) FRD4 FRD3 FRD2 FRD1 FRD0 1 0 0 0 1 FRA4 FRA3 FRA2 FRA1 FRA0 Frame rate setting in different FRB4 FRB3 FRB2 FRB1 FRB0 temperature range FRC4 FRC3 FRC2 FRC1 FRC0 (Monochrome mode) FRD4 FRD3 FRD2 FRD1 FRD0 1 TA4 TB4 TC4 1 0 TA3 TB3 TC3 0 0 TA2 TB2 TC2 1 1 TA1 TB1 TC1 0 0 TA0 TB0 TC0 0 Temperature range setting MT13 MT12 MT11 MT10 MT03 MT02 MT01 MT00 MT33 MT32 MT31 MT30 MT23 MT22 MT21 MT20 MT53 MT52 MT51 MT50 MT43 MT42 MT41 MT40 Set temperature gradient MT73 MT72 MT71 MT70 MT63 MT62 MT61 MT60 compensation coefficient MT93 MT92 MT91 MT90 MT83 MT82 MT81 MT80 MTB3 MTB2 MTB1 MTB0 MTA3 MTA2 MTA1 MTA0 MTD3 MTD2 MTD1 MTD0 MTC3 MTC2 MTC1 MTC0 MTF3 MTF2 MTF1 MTF0 MTE3 MTE2 MTE1 MTE0 Ver-1.1a 31/63 2009/11/30 ST7586S INSTRUCTION DESCRIPTION NOP "No Operation" instruction. ST7586S will do nothing when receiving this instruction. A0 0 R/W 0 D7 0 D6 0 D5 0 D4 0 D3 0 D2 0 D1 0 D0 0 Description No operation RESET When this instruction is issued, the software reset procedure is started. This instruction resets the software reset default value and keeps the DDRAM content. A0 0 R/W 0 D7 0 D6 0 D5 0 D4 0 D3 0 D2 0 D1 0 D0 1 Description Software reset Power Save When ST7586S enters the sleep in mode, the mode causes the LCD module entering the minimum power consumption mode. All of operations (e.g. the DC/DC converter, internal oscillator and panel scanning) are stopped. When ST7586S enters sleep out mode (exit sleep in mode), the DC/DC converter and internal oscillator are started. A0 0 R/W 0 D7 0 D6 0 D5 0 D4 1 D3 0 D2 0 D1 0 D0 SLP Description SLP=0: Sleep in mode SLP=1: Sleep out mode Partial Mode When ST7586S enters the partial display mode, the partial area is described by Partial Display Area instruction. The different partial display area setting will be changing frame rate or Vop to avoid abnormal display. A0 0 R/W 0 D7 0 D6 0 D5 0 D4 1 D3 0 D2 0 D1 1 D0 PTL Description PTL=0: Partial mode on PTL=1: Partial mode off Inverse Display This instruction would inverse the scanned data without recover the content of DDRAM. As the result, the ON and OFF status of all pixels are interchanged. A0 0 R/W 0 D7 0 D6 0 D5 1 D4 0 D3 0 D2 0 D1 0 D0 INV Description INV=0: Normal display INV=1: Inverse display All Pixel ON/OFF When ST7586S enters all pixels on or off mode, all display pixels are turned on or off regardless of the content of DDRAM. The content of DDRAM is not changed by setting All Pixel ON/OFF. After execute the instruction of Partial Mode, the display mode will exit all pixel on/off mode then enter normal mode. A0 0 R/W 0 D7 0 D6 0 D5 1 D4 0 D3 0 D2 0 D1 1 D0 AP Description AP=0: All pixel off mode AP=1: All pixel on mode Display ON/OFF This instruction turns the display ON or OFF. When ST7586S enters display off, the display output is blank regardless of the content of DDRAM. When ST7586S enters display on (exit display off), the display output is according to content of DDRAM. A0 0 Ver-1.1a R/W 0 D7 0 D6 0 D5 1 D4 0 D3 1 32/63 D2 0 D1 0 D0 DSP Description DSP=0: Display off DSP=1: Display on 2009/11/30 ST7586S Set Column Address This instruction is used to define area of DDRAM where MCU can access. The column address is automatically increased by one (+1) after each DDRAM access. After the ending column address XE[15..0], column address returns to starting column address XS[15..0]. The XS[15..0] setting that must be equal to or less than XE[15..0]. When XS[15..0] or XE[15..0] is great than 7Fh, out of DDRAM range will be ignored. A0 0 1 1 1 1 R/W 0 0 0 0 0 D7 0 XS15 XS7 XE15 XE7 D6 0 XS14 XS6 XE14 XE6 D5 1 XS13 XS5 XE13 XE5 D4 0 XS12 XS4 XE12 XE4 D3 1 XS11 XS3 XE11 XE3 D2 0 XS10 XS2 XE10 XE2 D1 1 XS9 XS1 XE9 XE1 D0 0 XS8 XS0 XE8 XE0 XS: Starting column address XE: Ending column address Description Set Row Address This instruction is used to define area of DDRAM where MCU can access. The row address is automatically increased by one (+1) after column address counter is over XE[15..0]. The row address will return to starting row address YS[15..0] immediately when the row address increases one over the ending row address YE[15..0]. The YS[15..0] setting must be equal to or less than YE[15..0]. When YS[15..0] or YE[15..0] is great than 9Fh, out of DDRAM range will be ignored. A0 0 1 1 1 1 R/W 0 0 0 0 0 D7 0 YS15 YS7 YE15 YE7 D6 0 YS14 YS6 YE14 YE6 D5 1 YS13 YS5 YE13 YE5 D4 0 YS12 YS4 YE12 YE4 D3 1 YS11 YS3 YE11 YE3 D2 0 YS10 YS2 YE10 YE2 D1 1 YS9 YS1 YE9 YE1 D0 1 YS8 YS0 YE8 YE0 YS: Starting row address YE: Ending row address Description Write Display Data This instruction is used to transfer data from MCU to DDRAM without changing status of ST7586S. The column address and row address will be reset to starting column address (XS) and starting row address (YS) when this instruction is accepted. The pre-instruction is defined to enter write DDRAM mode. The following continuously data means content of DDRAM without pre-instruction. Write Display Data would be stopped when any other instruction is accepted. A0 0 1 R/W 0 0 D7 0 D7 D6 0 D6 D5 1 D5 D4 0 D4 D3 1 D3 D2 1 D2 D1 0 D1 D0 0 D0 Description Write display data to DDRAM Read Display Data The instruction is used to transfer data from DDRAM to MCU without changing status of ST7586S. The column address and row address will be reset to staring column address (XS) and starting row address (YS) when this instruction is accepted. The pre-instruction is defined to enter read DDRAM mode. The following continuously data means content of DDRAM without pre-instruction. Read Display Data would be stopped when any other instruction is accepted. Read Display Data is only available via the parallel interface. A0 0 1 R/W 0 1 D7 0 D7 D6 0 D6 D5 1 D5 D4 0 D4 D3 1 D3 D2 1 D2 D1 1 D1 D0 0 D0 Description Read display data from DDRAM Ver-1.1a 33/63 2009/11/30 ST7586S Partial Display Area This instruction defines the display area of partial mode. There are four parameters associated with this instruction, the Partial Display Address Start PTS[15..0] and the Partial Display Address End as illustrated in Fig. 8. The instruction of Partial Display must be executed before setting the instruction of Partial Display Area A0 0 1 1 1 1 R/W 0 0 0 0 0 D7 0 PTS7 PTE7 D6 0 PTS6 PTE6 D5 1 PTS5 PTE5 D4 1 PTS4 PTE4 D3 0 PTS3 PTE3 D2 0 PTS2 PTE2 D1 0 PTS9 PTS1 PTE9 PTE1 D0 0 PTS8 PTS0 PTE8 PTE0 Description Partial display address start: 00hPTS9Fh Partial display address end: 00hPTE9Fh Display Area: 64Duty160 PTS15 PTS14 PTS13 PTS12 PTS11 PTS10 PTE15 PTE14 PTE13 PTE12 PTE11 PTE10 Scroll Area This instruction defines the scrolling area of display. The first parameter TA[7..0] describes the fixed Top Area. The second parameter SA[7..0] describes the Scrolling Area. The third parameter BA[7..0]describes the Bottom Area. This instruction setting must correspond to TA+SA+BA=160. A0 0 1 1 1 R/W 0 0 0 0 D7 0 TA7 SA7 BA7 D6 0 TA6 SA6 BA6 D5 1 TA5 SA5 BA5 D4 1 TA4 SA4 BA4 D3 0 TA3 SA3 BA3 D2 0 TA2 SA2 BA2 D1 1 TA1 SA1 BA1 D0 1 TA0 SA0 BA0 Description Top Area: TA=00h~A0h Scrolling Area: SA=00h~A0h Bottom Area: BA=00h~A0h TA+SA+BA=160 Display Control This instruction defines the write/read scanning direction of DDRAM. A0 0 1 R/W 0 0 D7 0 MY D6 0 MX D5 1 0 D4 1 0 D3 0 0 D2 1 0 D1 1 0 D0 0 0 Description MY=0: COM0 COM159 MY=1: COM159 COM0 MX=0: SEG0 SEG383 MX=1: SEG383 SEG0 Start Line This instruction sets row address of DDRAM to determine the initial display line. The display data of specified row address is displayed at the First Output COM. A0 0 1 S7 0 0 0 : 1 1 1 R/W 0 0 S6 0 0 0 : 0 0 0 D7 0 S7 S5 0 0 0 : 0 0 0 D6 0 S6 S4 0 0 0 : 1 1 1 D5 1 S5 S3 0 0 0 : 1 1 1 D4 1 S4 S2 0 0 0 : 1 1 1 D3 0 S3 S1 0 0 1 : 0 1 1 D2 1 S2 S0 0 1 0 : 1 0 1 D1 1 S1 D0 1 S0 Description S=00h~9Fh Line Address 0 1 2 : 127 158 159 Ver-1.1a 34/63 2009/11/30 ST7586S Display Mode This instruction defines the display mode is 4-level gray scale mode or monochrome mode. A0 0 R/W 0 D7 0 D6 0 D5 1 D4 1 D3 1 D2 0 D1 0 D0 M Description M=0: Gray mode M=1: Monochrome mode Enable DDRAM Interface This instruction is used to initial DDRAM interface for write data to DDRAM or read data from DDRAM. A0 0 1 R/W 0 0 D7 0 0 D6 0 0 D5 1 0 D4 1 0 D3 1 0 D2 0 0 D1 1 1 D0 0 0 Description Enable DDRAM interface Display Duty This instruction defines display duty. The parameter setting of Display Duty is the number of physical display duty decreasing by one (-1). For example, the parameter must set 9Fh when the LCD display duty is 160. A0 0 1 R/W 0 0 D7 1 DT7 D6 0 DT6 D5 1 DT5 D4 1 DT4 D3 0 DT3 D2 0 DT2 D1 0 DT1 D0 0 DT0 Description DT=03h~9Fh First Output COM This instruction defines the first output COM number that mapping to the Start Line of DDRAM. For example, the parameter of First Output COM setting is 08h and the parameter of Start Line setting is 02h means that the COM8 would output the DDRAM data at row address 2. A0 0 1 FC7 0 0 0 : 1 1 1 R/W 0 0 FC6 0 0 0 : 0 0 0 D7 1 FC7 FC5 0 0 0 : 0 0 0 D6 0 FC6 FC4 0 0 0 : 1 1 1 D5 1 FC5 FC3 0 0 0 : 1 1 1 D4 1 FC4 FC2 0 0 0 : 1 1 1 D3 0 FC3 FC1 0 0 1 : 0 1 1 D2 0 FC2 FC0 0 1 0 : 1 0 1 D1 0 FC1 D0 1 FC0 Description FC=00h~9Fh COM Number 0 1 2 : 127 158 159 Ver-1.1a 35/63 2009/11/30 ST7586S FOSC Divider This instruction is used to specify the FOSC dividing A0 0 1 FOD1 0 0 1 1 R/W 0 0 FOD0 0 1 0 1 D7 1 0 D6 0 0 D5 1 0 D4 1 0 D3 0 0 D2 0 0 D1 1 FOD1 D0 1 FOD0 Description Set FOSC dividing ratio FOSC Dividing Ratio Not Divide 2 Divisions 4 Divisions 8 Divisions Partial Display This instruction is used to set the partial display. The instruction of Partial Display must be executed before setting the instruction of Partial Display Area. A0 0 1 R/W 0 0 D7 1 1 D6 0 0 D5 1 1 D4 1 0 D3 0 0 D2 1 0 D1 0 0 D0 0 0 Description Set partial display mode N-Line Inversion This instruction is used to set the frame inverted number with range of 2 to 31. A0 0 1 M 0 1 NL4 0 0 0 : 1 1 1 R/W 0 0 D7 1 M D6 0 0 D5 1 0 D4 1 NL4 D3 0 NL3 D2 1 NL2 D1 0 NL1 D0 1 NL0 Description Set N-Line inversion N-Line Inversion Mode Inversion occurs in every frame Inversion is independent from frame NL3 0 0 0 : 1 1 1 NL2 0 0 0 : 1 1 1 NL1 0 1 1 : 0 1 1 NL0 0 0 1 : 1 0 1 Line Inversion Frame inversion 3 line inversion 4 line inversion : 30 line inversion 31 line inversion 32 line inversion Ver-1.1a 36/63 2009/11/30 ST7586S Read Modify Write This instruction is used to enter/exit read modify write mode. When entering read modify write, the display data read will not increase column address. Only the display data write operation will increase the column address. This mode is maintained until Disable Read Modify Write (B9h) is accepted. A0 0 R/W 0 D7 1 D6 0 D5 1 D4 1 D3 1 D2 0 D1 0 D0 RMW Description RMW=0: Enable read modify write RMW=1: Disable read modify write Set Row/Column Address Enable Read Modify Write Read-Modify-Write Cycle Dummy Read Data Read Modify Data Data Write (at same Column Addr.) Column Address increase No Finished? Yes Done Ver-1.1a 37/63 2009/11/30 ST7586S Set Vop This instruction is used to adjust the optimum LCD supply voltage Vop. The calculation of Vop is as shown blow: V0=3.6+(Vop[8:0]+VOF[6:0]+VopIncStep-VopDecStep)x0.04 A0 0 1 1 R/W 0 0 0 D7 1 Vop7 - D6 1 Vop6 - D5 0 Vop5 - D4 0 Vop4 - D3 0 Vop3 - D2 0 Vop2 - D1 0 Vop1 - D0 0 Vop0 Vop8 Set Vop Description The suggestion of usable V0 voltage is shown below (assume VOF[6:0]=0, VopIncStep/VopDecStep=0): Vop8 0 0 0 : 1 1 1 Vop7 0 0 0 : 0 0 0 Vop6 1 1 1 : 1 1 1 Vop5 1 1 1 : 1 1 1 Vop4 0 0 0 : 0 0 0 Vop3 0 0 0 : 0 0 1 Vop2 0 0 0 : 1 1 0 Vop1 0 0 1 : 1 1 0 Vop0 0 1 0 : 0 1 0 V0 (V) 7.44 7.48 7.52 : 17.92 17.96 18.00 Vop Increase This instruction is used to increase Vop step by one A0 0 R/W 0 D7 1 D6 1 D5 0 D4 0 D3 0 D2 0 D1 0 D0 1 Description Vop increase one step Vop Decrease This instruction is used to decrease Vop step by one A0 0 R/W 0 D7 1 D6 1 D5 0 D4 0 D3 0 D2 0 D1 1 D0 0 Description Vop decrease one step Ver-1.1a 38/63 2009/11/30 ST7586S BIAS System This instruction is used to select LCD bias ratio of the voltage to meet the requirement of driving the LCD. A0 0 1 BS2 0 0 0 0 1 1 R/W 0 0 BS1 0 0 1 1 0 0 D7 1 BS0 0 1 0 1 0 1 D6 1 D5 0 D4 0 D3 0 D2 0 BS2 D1 1 BS1 D0 1 BS0 Description Set BIAS system BIAS Ratio 1/14 1/13 1/12 1/11 1/10 1/9 Booster Level This instruction is used to control the built-in booster circuit to provide the power source of the built-in regulator. A0 0 1 BST2 0 0 0 0 1 1 1 1 R/W 0 0 BST1 0 0 1 1 0 0 1 1 D7 1 BST0 0 1 0 1 0 1 0 1 D6 1 D5 0 D4 0 D3 0 D2 1 BST2 D1 0 BST1 D0 0 BST0 Description Set booster level Booster Level x1 Booster x2 Booster x3 Booster x4 Booster x5 Booster x6 Booster x7 Booster x8 Booster Ver-1.1a 39/63 2009/11/30 ST7586S Vop Offset This instruction is used to adjust Vop offset for V0. A0 0 1 VOF6 R/W 0 0 VOF5 1 1 0 : 0 0 1 1 1 : 0 0 D7 1 0 VOF4 1 1 : 0 0 1 1 : 0 0 D6 1 VOF6 VOF3 1 1 : 0 0 1 1 : 0 0 D5 0 VOF5 VOF2 1 1 : 0 0 1 1 : 0 0 D4 0 VOF4 VOF1 1 1 : 0 0 1 1 : 0 0 D3 0 VOF3 VOF0 1 0 : 1 0 1 0 : 1 0 D2 1 VOF2 Dec. 63 62 : 1 0 -1 -2 : -63 -64 D1 1 VOF1 D0 1 VOF0 Description Set Vop offset V0 Offset (mV) +2520 +2480 : +40 0 -40 -80 : -2520 -2560 Analog Control This instruction is used to set status of analog circuit. A0 0 1 R/W 0 0 D7 1 0 D6 1 0 D5 0 0 D4 1 1 D3 0 1 D2 0 1 D1 0 0 D0 0 1 Description Enable analog circuit Auto Read Control This instruction is used to set status of OTP auto read to enable or disable. A0 0 1 R/W 0 0 D7 1 1 D6 1 0 D5 0 0 D4 1 XARD D3 0 1 D2 1 1 D1 1 1 D0 1 1 Description XARD=0: Enable auto read XARD=1: Disable auto read OTP WR/RD Control This instruction is used to set status of OTP that write to OTP or read from OTP. A0 0 1 R/W 0 0 D7 1 0 D6 1 0 D5 1 WR /RD D4 0 0 D3 0 0 D2 0 0 D1 0 0 D0 0 0 Description WR/RD=0: Enable OTP read WR/RD=1: Enable OTP write OTP Control Out This instruction is used to cancel the OTP control. A0 0 R/W 0 D7 1 D6 1 D5 1 D4 0 D3 0 D2 0 D1 0 D0 1 Description OTP control out Ver-1.1a 40/63 2009/11/30 ST7586S OTP Write This instruction is used to trigger OTP programming procedure. A0 0 R/W 0 D7 1 D6 1 D5 1 D4 0 D3 0 D2 0 D1 1 D0 0 Description OTP programming procedure OTP Read This instruction is used to trigger OTP up-load procedure. A0 0 R/W 0 D7 1 D6 1 D5 1 D4 0 D3 0 D2 0 D1 1 D0 1 Description OTP up-load procedure OTP Selection Control This instruction is used to define OTP selection control. A0 0 1 R/W 0 0 D7 1 0 D6 1 Ctrl D5 1 0 D4 0 1 D3 0 1 D2 1 0 D1 0 0 D0 0 1 Description Ctrl=0: Disable OTP Ctrl=1: Enable OTP OTP Programming Setting This instruction is used to set OTP write timing. A0 0 1 R/W 0 0 D7 1 0 D6 1 0 D5 1 0 D4 0 0 D3 0 1 D2 1 1 D1 0 1 D0 1 1 Description OTP programming setting Ver-1.1a 41/63 2009/11/30 ST7586S Frame Rate (Gray Scale Mode) When enter 4-level gray scale mode, this instruction is used to define frequency of frame rate in different temperature range as shown in Fig. 13 A0 0 1 1 1 1 FRx4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W 0 0 0 0 0 FRx3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 D7 1 FRx2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 D6 1 FRx1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D5 1 D4 1 FRA4 FRB4 FRC4 FRD4 D3 0 FRA3 FRB3 FRC3 FRD3 D2 0 FRA2 FRB2 FRC2 FRD2 D1 0 FRA1 FRB1 FRC1 FRD1 D0 0 FRA0 FRB0 FRC0 FRD0 Description FRA: FR in temp. -30 to TA C FRB: FR in temp TA to TB FRC: FR in temp. TB to TC FRD: FR in temp TC to 90 C FRx0 Frame Rate (Hz) 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 38.5 38.5 38.5 40.0 41.5 46.0 46.0 49.0 51.0 53.0 55.0 55.0 69.0 73.0 76.5 76.5 FRx4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FRx3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 FRx2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 FRx1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 FRx0 Frame Rate (Hz) 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 77.0 77.0 77.0 80.0 83.0 92.0 92.0 98.0 102.0 106.0 110.0 110.0 138.0 146.0 153.0 153.0 Ver-1.1a 42/63 2009/11/30 ST7586S Frame Rate (Monochrome Mode) When enter monochrome mode, this instruction is used to define frequency of frame rate in different temperature range as shown in Fig. 13 A0 0 1 1 1 1 FRx4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W 0 0 0 0 0 FRx3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 D7 1 FRx2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 D6 1 FRx1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D5 1 D4 1 FRA4 FRB4 FRC4 FRD4 D3 0 FRA3 FRB3 FRC3 FRD3 D2 0 FRA2 FRB2 FRC2 FRD2 D1 0 FRA1 FRB1 FRC1 FRD1 D0 1 FRA0 FRB0 FRC0 FRD0 Description FRA: FR in temp. -30 to TA C FRB: FR in temp TA to TB FRC: FR in temp. TB to TC FRD: FR in temp TC to 90 C FRx0 Frame Rate (Hz) 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 38.5 38.5 38.5 40.0 41.5 46.0 46.0 49.0 51.0 53.0 55.0 55.0 69.0 73.0 76.5 76.5 FRx4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FRx3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 FRx2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 FRx1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 FRx0 Frame Rate (Hz) 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 77.0 77.0 77.0 80.0 83.0 92.0 92.0 98.0 102.0 106.0 110.0 110.0 138.0 146.0 153.0 153.0 Temperature Range This instruction is used to define the temperature range for automatic frame rate adjustment according to current temperature as shown in Fig. 13. A0 0 1 1 1 R/W 0 0 0 0 D7 1 D6 1 TA6 TB6 TC6 D5 1 TA5 TB5 TC5 D4 1 TA4 TB4 TC4 D3 0 TA3 TB3 TC3 D2 0 TA2 TB2 TC2 D1 1 TA1 TB1 TC1 D0 0 TA0 TB0 TC0 Description TA[6 :0]=TA Temp.( C)+40 TB[6:0]=TB Temp.( C)+40 TC[6 :0]=TC Temp.( C)+40 Temp. Range Value Freq. changing point A Freq. changing point B Freq. changing point C Temp. Rising State ( C) (TA[6:0]-40)+5 (TB[6:0]-40)+5 (TC[6:0]-40)+5 Temp. Falling State ( C) TA[6:0]-40 TB[6:0]-40 TC[6:0]-40 Ver-1.1a 43/63 2009/11/30 ST7586S Temperature Gradient Compensation This instruction is used to define the temperature gradient compensation coefficient. The temperature gradient compensation coefficient setting is shown as below table. A0 0 1 1 1 1 1 1 1 1 MTx3 0 0 0 : 1 1 1 R/W 0 0 0 0 0 0 0 0 0 MTx2 0 0 0 : 1 1 1 D7 1 MT13 MT33 MT53 MT73 MT93 MTB3 MTD3 MTF3 MTx1 0 0 1 : 0 1 1 D6 1 MT12 MT32 MT52 MT72 MT92 MTB2 MTD2 MTF2 MTx0 0 1 0 : 1 0 1 D5 1 MT11 MT31 MT51 MT71 MT91 MTB1 MTD1 MTF1 D4 1 MT10 MT30 MT50 MT70 MT90 MTB0 MTD0 MTF0 D3 0 MT03 MT23 MT43 MT63 MT83 MTA3 MTC3 MTE3 D2 1 MT02 MT22 MT42 MT62 MT82 MTA2 MTC2 MTE2 D1 0 MT01 MT21 MT41 MT61 MT81 MTA1 MTC1 MTE1 D0 0 MT00 MT20 MT40 MT60 MT80 MTA0 MTC0 MTE0 Set temperature gradient compensation coefficient Description Mx (mV/ C) 0 -5 -10 : -65 -70 -75 Ver-1.1a 44/63 2009/11/30 ST7586S OPERATION FLOW Power ON Referential Operation Flow Power ON Flow Operation Sequence Case-1: RSTB=L while Power ON (1) (2) (3) (4) Function Set (by user) (1) Power Mode (SLPOUT) (2) Display OFF (3) Set Vop (4) BIAS System (5) Booster Level (6) Analog Control (7) N-Line Inversion (8) Display Mode (9) Enable DDRAM Interface (10) Display Control (11) Inversion Display Clear DDRAM by "0" (384 x 160 x 2) Function Set (by user) (1) Set Column Address (2) Set Row Address (3) Display ON Power ON Flow Case-2: RSTB=H while Power ON Note 1. 2. 3. 4. Please refer to the specification of tRW and tR. Refer to the section of RESET CIRCUIT. The detail instruction functionality is described in section of INSTRUCTION DESCRIPTION. The power stable is defined as the time that the later power (VDDI or VDDA) reaches 90% od its rated voltage. Ver-1.1a 45/63 2009/11/30 ST7586S Item Symbol Requirement Description VDDI and VDDA can be applied in any order. IC will NOT be damaged when one of VDD1 and VDD2 is ON VDD2 power ON delay tON-V2 No Limitation but another is OFF. Power stable is defined as the time that the later power (VDDI or VDDA) reaches 90% of its rated voltage. Recommend Setting: -50ms tON-V2 No Limitation. Case-1 RESB input time tON-RES tRW tON-RES Case-2 No Limitation CSB input time Note: 1. 2. If the contents of internal registers are the same as default, the related commands can be ignored. If RESB is held high or unstable during power ON, a successful hardware reset by RSTB is required after VDDI and VDDA are both stable (as illustrated in Case-2). Otherwise, correct functionality can NOT be guaranteed. tON-CS No Limitation RESB=L can be input at any time after power is stable. tRW & tR should match the timing specification of RESB. RESB has priority over CSB. Recommend Setting: 0 tON-RES 50 ms. CSB can be input at any time after power is stable. Ver-1.1a 46/63 2009/11/30 ST7586S Power OFF Referential Operation Flow Power OFF Flow Operation Sequence Case-1: Use RSTB Case-2: Power OFF at Sleep State Item Power OFF Time Case-1 Case-2 Symbol tOFF-RESB tOFF-PW Requirement 200ms tOFF-RESB 0 tOFF-PW VSS. Description Power can be turned OFF after built-in power becomes VDD1 and VDD2 can be powered down in any order. IC VDD2 power ON delay tOFF-V2 No Limitation will NOT be damaged when one of VDD1 and VDD2 is ON but another is OFF. Recommend Setting: -50ms tOFF-V2 No Limitation. Note: In Case-2, RSTB can fall to VSS at the same time as VDDI. Ver-1.1a 47/63 2009/11/30 ST7586S OTP Operation Referential OTP Burning Flow Power ON Wait Power Stable HW Reset Delay 120ms Initial LCD Module Key C1h Show Image and Fine Tune Vop C2h Adjust Vop Offset EXTB connect to VSS Set Register VPP connect to 6.5V Wait VPP Stable OTP Writing Remove 6.5V from VPP Remove VSS from EXTB Restart LCD Module Check Display Performance Note: In this section "+" and "-" key button, please execute command C1h to increase one step at Vop and execute command C2h to decrease one step at Vop. Ver-1.1a 48/63 2009/11/30 ST7586S Referential OTP Operation Code void Initialization_ST7586S(void) { Reset_ms(10); Delay_ms(120); Write(Command, 0xD7); Write(Data, 0x9F); Write(Command, 0xE0); Write(Data, 0x00); Delay_ms(10); Write(Command, 0xE3); Delay_ms(20); Write(Command, 0xE1); Write(Command, 0x11); Write(Command, 0x28); Delay_ms(50); Write(Command, 0xC0); Write(Data, 0xB9); Write(Data, 0x00); Write(Command, 0xC3); Write(Data, 0x05); Write(Command, 0xC4); Write(Data, 0x07); Write(Command, 0xD0); Write(Data, 0x1D); Write(Command, 0xB5); Write(Data, 0x00); Write(Command, 0x39); Write(Command, 0x3A); Write(Data, 0x02); Write(Command, 0x36); Write(Data, 0x00); Write(Command, 0xB0); Write(Data, 0x9F); Write(Command, 0xB4); Write(Data, 0xA0); Write(Command, 0x30); Write(Data, 0x00); Write(Data, 0x00); Write(Data, 0x00); Write(Data, 0x77); Write(Command, 0x20); Write(Command, 0x2A); Write(Data, 0x00); Write(Data, 0x00); Write(Data, 0x00); Write(Data, 0x7F); // Display Inversion OFF // Column Address Setting // SEG0 -> SEG384 // Partial Display Area = COM0 ~ COM119 // Partial Display // Duty Setting // Scan Direction Setting // Monochrome Mode // Enable DDRAM Interface // N-Line = 0 // Enable Analog Circuit // Booster = x8 // BIAS = 1/9 // Vop = B9h // OTP Control Out // Sleep Out // Display OFF // OTP Up-Load // Enable OTP Read // Disable Auto Read Ver-1.1a 49/63 2009/11/30 ST7586S Write(Command, 0x2B); Write(Data, 0x00); Write(Data, 0x00); Write(Data, 0x00); Write(Data, 0x9F); Clear_DDRAM(); Write(Command, 0x2A); Write(Data, 0x00); Write(Data, 0x00); Write(Data, 0x00); Write(Data, 0x4F); Write(Command, 0x2B); Write(Data, 0x00); Write(Data, 0x00); Write(Data, 0x00); Write(Data, 0x78); Disp_Image(); Write(Command, 0x29); } // Fill the DDRAM Data by Panel Resolution // Display ON // Row Address Setting // COM0 -> COM120 // Clear whole DDRAM by "0" (384 x 160 x 2) // Column Address Setting // SEG0 -> SEG239 // Row Address Setting // COM0 -> COM160 Ver-1.1a 50/63 2009/11/30 ST7586S void Set_OTP_Register(void) { Write(Command, 0xB5); Write(Data, 0x8C); } void Vop_Fine_Tune(v { Disp_Image(); Write(Command, 0x29); Write(Command, 0xC1); or Write(Command, 0xC2); } void OTP_Write(void) { Write(Command, 0x28); Delay_ms(50); Write(Command, 0xF1); Write(Data, 0x12); Write(Data, 0x12); Write(Data, 0x12); Write(Data, 0x12); Write(Command, 0xE4); Write(Data, 0x59); Write(Command, 0xE5); Write(Data, 0x0F); Write(Command, 0xE0); Write(Data, 0x20); Delay_ms(100); Write(Command, 0xE2); Delay_ms(100); Write(Command, 0xE1); } // Delay 100ms // OTP Write // Delay 100ms // OTP Control Out // OTP WR/RD Control // OTP Programming Setting // OTP Selection Control // Display OFF // Delay 50ms // Frame Rate = 77Hz // Display the image // Display ON // Fine tuning Vop to adjust display quality // N-Line = 13 Line Inversion (Non-Reset) Ver-1.1a 51/63 2009/11/30 ST7586S HANDLING Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is desirable to take normal precautions appropriate to handling MOS devices. ABSOLUTE MAXIMUM RATINGS VSS=0V Parameter Digital Power Supply Voltage Analog Power supply voltage LCD Power supply voltage LCD Power supply voltage LCD Power supply voltage MPU Interface Input Voltage Operating temperature Storage temperature Note: 1. 2. 3. 4. All voltages are respect to VSS unless otherwise noted (VSS=VSS1=VSS2=VSS4=VSSX). Stresses exceed the ranges listed above may cause permanent damage to IC. Parameters are valid over operating temperature range unless otherwise specified. Insure the voltage levels of V0, VG, VM, VSS and XV0 always match the correct relation: V0 VG > VM > VSS XV0 Symbol VDDI (VDD1) VDDA (VDD2~VDD5) V0-XV0 VG VM Vin TOPR TSTR Conditions -0.3 ~ 3.6 -0.3 ~ 3.6 -0.3 ~ 19 -0.3 ~ 5.5 -0.3 ~ VDDA+0.3 -0.3 ~ VDDI+0.3 -30 to +80 -40 to +125 Unit V V V V V V C C Ver-1.1a 52/63 2009/11/30 ST7586S DC CHARACTERISTICS VSS=VSS1=VSS2=VSS4=VSSX=0V and Ta = -30 ~ 85 unless otherwise specified. C, Item Digital Operating Voltage Analog Operating Voltage Input High-level Voltage Input Low-level Voltage Output High-level Voltage Output Low-level Voltage Input Leakage Current Symbol VDDI VDDA VIH VIL VOH VOL IIL IOH=1.0mA, VDD1=3.0V IOL=-1.0mA, VDD1=3.0V Vin = VDD1 or VSS Vop=16V, ON Resistance of LCD Drivers RON Ta=25 C V=10% VG=3.2V, V=10% VDDI=VDDA=3.3V, Frame Frequency Vop Voltage Output VG Voltage Output VM Voltage Output Note: 1. 2. V0, XV0 and VG include: V0I, V0O, V0S, XV0I, XV0O, XV0S, VGI, VGO & VGS. V0, XV0, VG and VM do NOT support external power supply. fFR Vop VG VM N-Line OFF, FR=0x12, Duty=1/160, Ta = 25 C VDDI=VDDA=3.3V VDDI=VDDA=3.3V VDDI=VDDA=3.3V V0-XV0 VG VM *2 *1,2 Condition Related Pin VDD1 VDD2~5 MPU Interface MPU Interface D[7:0] TE D[7:0] TE MPU Interface COM Drivers SEG Drivers - Rating Min. 1.7 2.7 0.7*VDD1 VSS1 0.8*VDD1 VSS1 -1.0 - - Typ. - - - - - - - 1.0 1.0 Max. 3.4 3.4 VDD1 0.3*VDD1 VDD1 0.2*VDD1 1.0 - - Unit V V V V V V A K K - - 1.8 0.9 77 - 18 Hz V V V *1,2 - - 5 VDDA-0.7 The current consumed by whole IC (bare die) with internal power system: Item Display ON Pattern: SNOW (Static) Sleep In Symbol Condition VDDI=VDDA=3.3V, ISS ISS 8x Booster, Vop = 16V, Bias=1/10 N-Line OFF, fFR=77Hz, Ta=25 C VDDI=VDDA=3.3V, Ta=25 C Rating Min. - - Typ. 800 20 Max. 1000 25 Unit A A Note: The current is DC characteristic of a "Bare Chip". Ver-1.1a 53/63 2009/11/30 ST7586S TIMING CHARATERISTIC System Bus Timing for 8080 MCU Interface VDD1 = 1.8V, Ta = 25 C Item Address setup time Address hold time System cycle time (WRITE) /WR L pulse width (WRITE) /WR H pulse width (WRITE) System cycle time (READ) /RD L pulse width (READ) /RD H pulse width (READ) WRITE Data setup time WRITE Data hold time READ access time READ Output disable time Note: 1. 2. 3. The input signal rise time and fall time (tr, tf) is specified at 15 ns or less. When the system cycle time is extremely fast, (tr + tf) (tCYC8 - tCCLW - tCCHW) for (tr + tf) (tCYC8 - tCCLR - tCCHR) are specified. All timing is specified using 20% and 80% of VDD1 as the reference. tCCLW and tCCLR are specified as the overlap between CSB being "L" and WR and RD being at the "L" level. D[7:0] RD /WR Signal A0 Symbol tAW8 tAH8 tCYC8 tCCLW tCCHW tCYC8 tCCLR tCCHR tDS8 tDH8 tACC8 tOH8 CL = 30 pF CL = 30 pF Condition Min. 0 0 240 100 100 500 220 220 20 20 -- 10 -- -- 100 110 Max. -- -- -- -- -- -- ns Unit Ver-1.1a 54/63 2009/11/30 ST7586S System Bus Timing for 6800 MCU Interface VDD1 = 1.8V, Ta = 25 C Item Address setup time Address hold time System cycle time (WRITE) Enable L pulse width (WRITE) Enable H pulse width (WRITE) System cycle time (READ) Enable L pulse width (READ) Enable H pulse width (READ) Write data setup time Write data hold time Read data access time Read data output disable time Note: 1. 2. 3. The input signal rise time and fall time (tr, tf) is specified at 15 ns or less. When the system cycle time is extremely fast, (tr + tf) (tCYC6 - tEWLW - tEWHW) for (tr + tf) (tCYC6 - tEWLR - tEWHR) are specified. All timing is specified using 20% and 80% of VDD1 as the reference. tEWLW and tEWLR are specified as the overlap between CSB being "L" and E. D[7:0] E Signal A0 Symbol tAW6 tAH6 tCYC6 tEWLW tEWHW tCYC6 tEWLR tEWHR tDS6 tDH6 tACC6 tOH6 CL = 16 pF CL = 16 pF Condition Min. 0 0 240 100 100 500 220 220 20 20 -- 10 -- -- 100 110 -- Max. -- -- -- -- -- ns Unit Ver-1.1a 55/63 2009/11/30 ST7586S System Bus Timing for 4-Line SPI MCU Interface First bit Last bit VDD1 = 1.8V, Ta = 25 C Item Serial clock period SCLK "H" pulse width SCLK "L" pulse width Address setup time Address hold time Data setup time Data hold time CSB-SCLK time CSB-SCLK time Note: 1. 2. The input signal rise and fall time (tr, tf) are specified at 15 ns or less. All timing is specified using 20% and 80% of VDD1 as the standard. A0 SDA CSB SCLK Signal Symbol tSCYC tSHW tSLW tSAS tSAH tSDS tSDH tCSS tCSH Condition Min. 200 140 60 20 20 20 20 30 30 Max. -- -- -- -- -- -- -- -- -- ns Unit Ver-1.1a 56/63 2009/11/30 ST7586S System Bus Timing for 3-Line SPI MCU Interface VDD1 = 1.8V, Ta = 25 C Item Serial Clock Period SCL "H" pulse width SCL "L" pulse width Data setup time Data hold time CS-SCL time CS "H" pulse width Note: 1. 2. The input signal rise and fall time (tr, tf) are specified at 15 ns or less. All timing is specified using 30% and 70% of VDD1 as the standard. SDA SCLK Signal Symbol tSCYC tSHW tSLW tSDS tSDH tCSS CSB tCSH tCHW Condition Rating Min. 200 140 60 20 20 30 30 0 Max. -- -- -- -- -- -- -- -- ns Unit Ver-1.1a 57/63 2009/11/30 ST7586S Reset Timing tRW RSTB tR Internal Status During Reset ... Reset Finished VDD1 = 1.8V, Ta = 25 C Item Reset time Reset "L" pulse width Symbol tR tRW Condition Min. 120 10 Max. -- -- Unit ms us Ver-1.1a 58/63 2009/11/30 ST7586S APPLICATION NOTE ITO Layout Guide The ITO layout suggestion is shown as below: For V0, XV0, VG, VDD and VSS Driver Side V0I V0I V0S V0O XV0O XV0S XV0I XV0I Separate by ITO FPC PIN FPC PIN Short by FPC Fig. 14 V0 ITO Layout Fig. 15 XV0 ITO Layout Driver Side VGO VGS VGI VGI VSS1 VSSX VSS2 VSS4 Separate by ITO FPC PIN FPC PIN Short by FPC Fig. 16 VG ITO Layout Fig. 17 VSS ITO Layout VDD5 VDD2 VDDX VDD3 Fig. 18 VDD4 VDD ITO Layout Ver-1.1a 59/63 2009/11/30 ST7586S For VPP This is the power source for programming the internal OTP. If the ITO resistance is too high, the operation current will cause the voltage drop while programming OTP. Please try to keep the ITO resistance as low as possible. Enhance ESD performance for COG application 1. Increase RSTB resistance: Fig. 19 2. RSTB ITO Layout Add ESD protection ring: FPC Fig. 20 Air ESD Protection Ring Ver-1.1a 60/63 2009/11/30 ST7586S Selection of Liquid Crystal Referential LCD Module Setting VDD1=2.8V, VDD2=VDD3=VDD4=VDD5=VDDX=2.8V, Panel Size=4.0", Booster Level=X8, N-Line=Frame Inversion Recommended Parameter of Liquid Crystal Duty 80 4-Level Gray Scale 160 80 Monochrome 160 BIAS 1/9 1/10 1/10 1/11 1/9 1/10 1/10 1/11 Vop Range 9.0 ~ 12.3 11.5 ~ 13.5 11.5 ~ 13.5 12.5 ~ 13.5 9.0 ~ 14.0 11.5 ~ 14.0 11.5 ~ 14.0 12.5 ~ 14.0 Display Mode In different range of partial area, the Vop and BIAS setting must within the Recommended Parameter of Liquid Crystal after consider the temperature effect and user adjustment. Note: Positive Booster: (VDD2 x BL x BE) V0 or (VDD2 x BL x BE) Vop Negative Booster: [-VDD2 x (BL - 1) x BE] XV0 or [VDD2 x (BL - 1) x BE] (Vop - VG), where VG = Vop x 2 / N Vop requirement: VDD2 x (BL - 1) x BE Vop x (N - 2) / N or Vop VDD2 x (BL - 1) x BE x N / (N-2), where N is bias rate. BL is the booster level and BE is the booster efficiency. Referential value are listed below: (assume VDD2~VDD5=2.8V and BL=X8) Module Size = 3.0"~4.0": BE=70% (Typical) Actual BE should be determined by module loading and ITO resistance value. 1.6V VG < 2 x VDD2. Recommend VG is: VDD2-VG around 0.3~0.5V. VM=VG/2 and 0.8V VM < VDD2 The ITO resistance restriction of LCD module please refers to the table of ITO Resistance Limitation. Ver-1.1a 61/63 2009/11/30 ST7586S Application Circuit Parallel 8080 Interface Ver-1.1a 62/63 2009/11/30 ST7586S REVERSION HISTORY Version 0.1 Date Redraw figures. 2009/06/29 Fix naming issue. Fix font error. 0.1a 0.2 0.3 0.3a 2009/06/30 2009/07/01 2009/07/10 2009/07/13 Add Page 52 & 53. Fix VDDI/VDDA range. Fix VDD1 naming in PAD CENTER COORDINATES. Fix pin description mistakes. Rename as ST7586S Fix typing mistakes in DC CHARACTERISTICS. Modify section of FUNCTION DESCRIPTION,. 0.4 2009/08/15 Add sections of RESET CIRCUIT, INSTRUCTION TABLE, INSTRUCTION DESCRIPTION, OPERATION FLOW and TIMING CHARATERISTIC. Modify the description of VG power pin. 0.4a 2009/09/17 Modify the range of ITO Resistance Limitation. Modify the instructions of Inverse Display and All Pixel ON/OFF. Add the display mode of 4-level gray scale. Modify the operating voltage range. Modify the bump height. Add the physical description of L-Mark. 0.5 2009/10/06 Modify the range of ITO Resistance Limitation. Modify the capacity of DDRAM. Modify the table of RESET CIRCUIT. Modify the range of operating temperature. Add the section of "Selection of Liquid Crystal". Add the OTP burning flow and the referential OTP burning code. Modify the mistake of DC CHARACTERISTICS. Modify the description of ABSOLUTE MAXIMUM RATINGS. 1.0 2009/10/28 Add the specification of TIMING CHARATERISTIC. Add the referential operation flows of Power ON and Power OFF. Remove the T.B.D mark. 1.1 2009/11/24 Modify the operating voltage range of VDD1. Modify the mistake of N-Line Inversion. 1.1a 2009/11/30 Add the instruction of Frame Rate for 4-level gray scale mode. Modify the mistake of Referential OTP Operation Code. Add figure of DDRAM Mapping. Description Ver-1.1a 63/63 2009/11/30 |
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