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73K324L CCITT V.22bis,V.23,V.22,V.21,Bell 212A Single-Chip Modem
Simplifying System IntegrationTM
DATA SHEET
JUNE 2008
DESCRIPTION
The 73K324L is a highly integrated single-chip modem IC, which provides the functions, needed to design a Quad-mode CCITT and Bell 212A compatible modem capable of operation over dial-up lines. The 73K324L adds V.23 capability to the CCITT modes of TERIDIAN Semiconductor Corporation's 73K224 one-chip modem, allowing a one-chip implementation in designs intended for European markets, which require this added Modulation mode. The 73K324L offers excellent performance and a high level of functional integration in a single IC. The device supports V.22bis, V.22, Bell 212A, V.21, and V.23 operating modes, allowing both synchronous and asynchronous operation as defined by the appropriate standard. The 73K324L is designed to appear to the Systems Engineer as a microprocessor peripheral, and will easily interface with popular one-chip microcontrollers (80C51 typical) for control of modem functions through its 8-bit multiplexed address/data bus. A serial control bus is available for applications not requiring a parallel interface. An optional package with only the serial control bus is also available. Data communications occurs through a separate serial port.
(continued)
FEATURES
* * * One chip Multi-mode CCITT V.22bis, V.22, V.21, V.23 and Bell 212A compatible modem data pump FSK (75, 300, 1200 bit/s), DPSK (600, 1200 bit/s), or QAM (2400 bit/s) encoding Pin and software compatible with other TERIDIAN Semiconductor Corporation K-Series family one-chip modems Interfaces directly with standard microprocessors (8048, 80C51 typical) Serial and parallel microprocessor bus for control Selectable asynch/synch with internal buffer/debuffer and scrambler/descrambler functions All synchronous (internal, external, slave) and Asynchronous Operating modes Adaptive equalization for optimum performance over all lines Programmable transmit attenuation (16 dB, 1 dB steps), and selectable receive boost (+18 dB) Call progress, carrier, answer tone, unscrambled mark, S1, and signal quality monitors DTMF, answer, calling, SCT and guard tone generators Test modes available: ALB, DL, RDL; Mark, Space and Alternating bit pattern generators CMOS technology for low power consumption (100 MW @ 5 V) with power-down mode (15 mW @ 5V) 4-wire full duplex operation in all modes
* * *
* * * * * * *
* BLOCK DIAGRAM
DTMF, ANSWER, GUARD & CALLING TONE GENERATOR FSK MODULATOR
BUFFER
SCRAMBLER
DI-BIT/ QUAD-BIT ENCODER
8-BIT P BUS INTERFACE
FIR PULSE SHAPER
QAM/ DPSK MODULATOR
FILTER EQUALIZER FILTER ATTENUATOR
TXA1
DEBUFFER
DESCRAMBLER
DI-BIT/ QUAD-BIT DECODER
DIGITAL SIGNAL PROCESSOR RECEIVE FUNCTIONS
FILTER
A/D
EQUALIZER
PASS BAND FILTER
ANTI-ALIAS FILTER
RXA
TXD RXD
SERIAL INTERFACE
FIXED DEMODULATOR
6dB GAIN BOOST
6dB GAIN BOOST
6dB GAIN BOOST
TONE DETECTION
Page: 1 of 30
(c) 2005, 2008 TERIDIAN Semiconductor Corporation
Rev 7.1
73K324L
CCITT V.22bis,V.23,V.22,V.21, Bell 212A Single-Chip Modem
DATA SHEET DESCRIPTION (continued)
The 73K324L offers full hardware and software compatibility with other products in TERIDIAN Semiconductor's K-Series family of single-chip modems, allowing system upgrades with a single component change. The 73K324L is ideal for use in free-standing or integral system modem products where full-duplex 2400 bit/s operation with Alternate mode capability is required. Its high functionality, low power consumption, and efficient packaging simplify design requirements and increase system reliability. A complete modem requires only the addition of the phone line interface, a control microprocessor, and RS-232 level converters for a typical system. The 73K324L is designed to provide a complete V.22bis, V.22, Bell 212A, V.21, and V.23 compatible modem on a chip. Many functions were included to simplify implementation in typical modem designs. In addition to the basic 2400 bit/s QAM, 1200/600 bit/s DPSK and 1200/300/75 bit/s FSK modulator/demodulator sections, the device also includes synch/asynch buffering, DTMF, answer, soft carrier, guard, and calling tone generator capabilities. Handshake pattern detectors simplify control of connect sequences, and precise tone detectors allow accurate detection of call progress, answer, calling, and soft carrier turn off tones. All Operating modes defined by the incorporated standards are included, and Test modes are provided. Most functions are selectable as options, and logical defaults are provided. The device can be directly interfaced to a microprocessor via its 8-bit multiplexed address/data bus for control and status monitoring. Data communications takes place through a separate serial port. Data may also be sent and received through the control registers. This simplifies designs requiring speed buffering, error control and compression. incoming signal. Adaptive equalization corrects for varying line conditions by automatically changing filter parameters to compensate for line characteristics. DPSK MODULATOR/DEMODULATOR The 73K324L modulates a serial bit stream into di-bit pairs that are represented by four possible phase shifts as prescribed by the Bell 212A/V.22 standards. The baseband signal is then filtered to reduce intersymbol interference on the bandlimited 2-wire PSTN line. Transmission occurs on either a 1200 Hz (Originate mode) or 2400 Hz carrier (Answer mode). Demodulation is the reverse of the modulation process, with the incoming analog signal eventually decoded into di-bits and converted back to a serial bit stream. The demodulator also recovers the clock, which was encoded into the analog signal during modulation. Demodulation occurs using either a 1200 Hz carrier (Answer mode or ALB Originate mode) or a 2400 Hz carrier (Originate mode or ALB Answer mode). The 73K324L use a phase locked loop coherent demodulation technique that offers excellent performance. Adaptive equalization is also used in DPSK modes for optimum operation with varying lines. FSK MODULATOR/DEMODULATOR The FSK modulator/demodulator produces a frequency modulated analog output signal using two discrete frequencies to represent the binary data. V.21 frequencies of 980 and 1180 Hz (originate mark and space), or 1650 and 1850 Hz (answer mark and space) are used in V.21 mode. V.23 mode uses 1300 and 2100 Hz for the main channel or 390 and 450 Hz for the back channel. Demodulation involves detecting the received frequencies and decoding them into the appropriate binary value. The rate converter and scrambler/descrambler are automatically bypassed in the FSK modes. PASSBAND FILTERS AND EQUALIZERS High and low band filters are included to shape the amplitude and phase response of the transmit and receive signals and to provide compromise delay equalization as well as rejection of out-of-band signals. The transmit signal filtering corresponds to a &%% raised cosine frequency response characteristic.
FUNCTIONAL DESCRIPTION
QAM MODULATOR/DEMODULATOR The 73K324L encodes incoming data into quad-bits represented by 16 possible signal points with specific phase and amplitude levels. The baseband signal is then filtered to reduce intersymbol interference on the bandlimited telephone network. The modulator transmits this encoded data using either a 1200 Hz (Originate mode) or 2400 Hz (Answer mode) carrier. The demodulator, although more complex, essentially reverses this procedure while also recovering the data clock from the
Page: 2 of 30
(c) 2005, 2008 TERIDIAN Semiconductor Corporation
Rev 7.1
73K324L
CCITT V.22bis,V.23,V.22,V.21, Bell 212A Single-Chip Modem
DATA SHEET
ASYNCHRONOUS MODE The Asynchronous mode is used for communication with asynchronous terminals which may transfer data at 600, 1200, or 2400 bit/s +1%, -2.5% even though the modem's output is limited to the nominal bit rate 0.01% in DPSK and QAM modes. When transmitting in this mode the serial data on the TXD input is passed through a rate converter which inserts or deletes stop bits in the serial bit stream in order to output a signal that is the nominal bit rate 0.01%. This signal is then routed to a data scrambler and into the analog modulator where di-bit or quad-bit encoding results in the output signal. Both the rate converter and scrambler can be bypassed for handshaking and synchronous operation as selected. Received data is processed in a similar fashion except that the rate converter now acts to reinsert any deleted stop bits and output data to the terminal at no greater than the bit rate plus 1%. An incoming break signal (low through two characters) will be recognized and passed through without incorrectly inserting a stop bit. The SYNC/ASYNC converter has an extended Overspeed mode, which allows selection of an output speed range of either +1% or +2.3%. In the extended Overspeed mode, some stop bits are output at 7/8 the normal width. Both the SYNC/ASYNC rate converter and the data descrambler are automatically bypassed in the FSK modes. SYNCHRONOUS MODE Synchronous operation is possible only in the QAM or DPSK modes. Operation is similar to that of the Asynchronous mode except that data must be synchronized to a clock and no variation in data transfer rate is allowable. Serial input data appearing at TXD must be valid on the rising edge of TXCLK. TXCLK is an internally derived 1200 or 2400 Hz signal in Internal mode and is connected internally to the RXCLK pin in Slave mode. Receive data at the RXD pin is clocked out on the falling edge of RXCLK. The asynch/synch converter is bypassed when Synchronous mode is selected and data is transmitted out at essentially the same rate as it is input. PARALLEL CONTROL INTERFACE Eight 8-bit registers are provided for control, option select, and status monitoring. These registers are addressed with the AD0, AD1, and AD2 multiplexed address lines (latched by ALE) and appear to a control microprocessor as seven consecutive memory locations. Six control registers are read/write. The detect and ID registers are read only and cannot be modified except by modem response to monitored parameters. SERIAL CONTROL INTERFACE The Serial Command mode allows access to the 73K324L control and status registers via a serial control port. In this mode the A0, A1, and A2 lines provide register addresses for data passed through the DATA pin under control of the RD and WR lines. A read operation is initiated when the RD line is taken low. The next eight cycles of EXCLK will then transfer out eight bits of the selected address location LSB first. A write takes place by shifting in eight bits of data LSB first for eight consecutive cycles of EXCLK. WR is then pulsed low and data transfer into the selected register occurs on the rising edge of WR. TONE GENERATOR The DTMF generator controls the sending of the sixteen standard DTMF tone pairs. The tone pair sent is determined by selecting TRANSMIT DTMF (bit D4) and the 4 DTMF bits (D0-D3) of the TONE register. Transmission of DTMF tones from TXA is gated by the TRANSMIT ENABLE bit of CR0 (bit D1) as with all other analog signals. FULL DUPLEX OPERATION Four-wire full duplex operation is allowed in all modes. This feature allows transmission and reception in the same band for four wire applications only.
Page: 3 of 30
(c) 2005, 2008 TERIDIAN Semiconductor Corporation
Rev 7.1
73K324L
CCITT V.22bis,V.23,V.22,V.21, Bell 212A Single-Chip Modem
DATA SHEET PIN DESCRIPTION
POWER NAME GND VDD VREF ISET TYPE I I O I DESCRIPTION System Ground. Power supply input, 5V -5% +10%. Bypass with 0.22 F and 22 F capacitors to GND. An internally generated reference voltage. Bypass with 0.22 F capacitor to GND. Chip current reference. Sets bias current for op-amps. The chip current is set by connecting this pin to VDD through a 2 M resistor. Iset should be bypassed to GND with a 0.22 F capacitor.
PARALLEL MICROPROCESSOR INTERFACE ALE AD0- AD7 CS I I/O / Tristate I Address latch enable. The falling edge of ALE latches the address on AD0-AD2 and the chip select on CS. Address/data bus. These bidirectional tri-state multi-plexed lines carry information to and from the internal registers. Chip select. A low on this pin allows a read cycle or a write cycle to occur. AD0AD7 will not be driven and no registers will be written if CS (latched) is not active. CS is latched on the falling edge of ALE. Output clock. This pin is selectable under processor control to be either the crystal frequency (for use as a processor clock) or 16 x the data rate for use as a baud rate clock in QAM/DPSK modes only. The pin defaults to the crystal frequency on reset. Interrupt. This open drain weak pull-up, output signal is used to inform the processor that a detect flag has occurred. The processor must then read the detect register to determine which detect triggered the interrupt. INT will stay active until the processor reads the detect register or does a full reset. Read. A low requests a read of the 73K324L internal registers. Data cannot be output unless both RD and the latched CS are active or low. Reset. An active high signal on this pin will put the chip into an inactive state. All control register bits (CR0, CR1, CR2, CR3, Tone) will be reset. The output of the CLK pin will be set to the crystal frequency. An internal pull down resistor permits power on reset using a capacitor to VDD. Write. A low on this informs the 73K324L that data is available on AD0-AD7 for writing into an internal register. Data is latched on the rising edge of WR. No data is written unless both WR and the latched CS are low.
CLK
O
INT
O
RD RESET
I I
WR
I
NOTE: The Serial Control mode is provided by tying ALE high and CS low. In this configuration AD7 becomes DATA and AD0, AD1 and AD2 become the address only. See the serial time diagrams on page 23.
Page: 4 of 30
(c) 2005, 2008 TERIDIAN Semiconductor Corporation
Rev 7.1
73K324L
CCITT V.22bis,V.23,V.22,V.21, Bell 212A Single-Chip Modem
DATA SHEET
RS-232 INTERFACE NAME EXCLK TYPE I DESCRIPTION External Clock. This signal is used in synchronous transmission when the external timing option has been selected. In the External Timing mode the rising edge of EXCLK is used to strobe synchronous transmit data available on the TXD pin. Also used for serial control interface. Receive Clock Tri-statable. The falling edge of this clock output is coincident with the transitions in the serial received DPSK/QAM data output. The rising edge of RXCLK can be used to latch the valid output data. RXCLK will be valid as long as a carrier is present. In V.23 or V.21 mode a clock that is 16 x 1200/75 or 16 x 300 Hz data rate is output, respectively. Received Data Output. Serial receive data is available on this pin. The data is always valid on the rising edge of RXCLK when in Synchronous mode. RXD will output constant marks if no carrier is detected. Transmit Clock Tri-statable. This signal is used in synchronous DPSK/QAM transmission to latch serial input data on the TXD pin. Data must be provided so that valid data is available on the rising edge of the TXCLK. The transmit clock is derived from different sources depending upon the Synchronization mode selection. In Internal Mode the clock is generated internally (2400 Hz for QAM, 1200 Hz for DPSK or 600 Hz for half-speed DPSK). In External Mode TXCLK is phase locked to the EXCLK pin. In Slave Mode TXCLK is phase locked to the RXCLK pin. TXCLK is always active. In V.23 or V.21 mode the output is a 16 x 1200/75 or 16 x 300 Hz clock, respectively. Transmit Data Input. Serial data for transmission is input on this pin. In Synchronous modes, the data must be valid on the rising edge of the TXCLK clock. In Asynchronous modes (2400/1200/600 bit/s, or 75/300 baud) no clocking is necessary. DPSK/QAM data must be +1%, -2.5% or +2.3%, -2.5 % in Extended Overspeed mode.
RXCLK
O/Tristate
RXD
O/ Weak Pull-up
O/Tristate
TXCLK
TXD
I
ANALOG INTERFACE RXA TXA XTL1 XTL2 I O I I/O Received modulated analog signal input from the phone line. Transmit analog output to the phone line. These pins are for the internal crystal oscillator requiring a 11.0592 MHz Parallel mode crystal. Two capacitors from these pins to ground are also required for proper crystal operation. Consult crystal manufacturer for proper values. XTL2 can also be driven from an external clock.
Page: 5 of 30
(c) 2005, 2008 TERIDIAN Semiconductor Corporation
Rev 7.1
73K324L
CCITT V.22bis,V.23,V.22,V.21, Bell 212A Single-Chip Modem
DATA SHEET REGISTER DESCRIPTIONS
Eight 8-bit internal registers are accessible for control and status monitoring. The registers are accessed in read or write operations by addressing the A0, A1 and A2 address lines in Serial mode, or the AD0, AD1 and AD2 lines in Parallel mode. The address lines are latched by ALE. Register CR0 controls the method by which data is transferred over the phone line. CR1 controls the interface between the microprocessor and the 73K324L internal state. DR is a detect register which provides an indication of monitored modem status conditions. TR, the tone control register, controls the DTMF generator, answer, guard tones, SCT, calling tone, and RXD output gate used in the modem initial connect sequence. CR2 is the primary DSP control interface and CR3 controls transmit attenuation and receive gain adjustments. All registers are read/write except for DR and ID, which are read only. Register control and status bits are identified below:
REGISTER BIT SUMMARY
ADDRESS REGISTER CONTROL REGISTER 0 CONTROL REGISTER 1 DETECT REGISTER AD - A0 D7 MODULATION OPTION TRANSMIT PATTERN 1 RECEIVE LEVEL RXD OUTPUT CONTROL D6 MODULATION TYPE 1 TRANSMIT PATTERN 0 PATTERN S1 DET TRANSMIT GUARD TONE/ SCT/CALLING TONE SPECIAL REGISTER ACCESS TRISTATE TX/RXCLK D5 MODULATION TYPE 0 ENABLE DETECT INTERRUPT RECEIVE DATA TRANSMIT ANSWER TONE DATA BIT NUMBER D4 TRANSMIT MODE 2 BYPASS SCRAMBLER/ ADD PH. EQ. (V.23) UNSCR. MARK DETECT TRANSMIT DTMF D3 TRANSMIT MODE 1 CLK CONTROL D2 TRANSMIT MODE 0 D1 TRANSMIT ENABLE D0 ANSWER/ ORIGINATE
CR0
000
CR1
001
RESET
TEST MODE 1 CALL PROGRESS DETECT DTMF1/ OVERSPEED
TEST MODE 0 SIGNAL QUALITY DTMF0/GUARD/ ANSWER/ CALLING/SCT
DR
010
CARRIER DETECT
SPECIAL TONE DETECT DTMF2/ 4 WIRE FDX
TONE CONTROL REGISTER CONTROL REGISTER 2 CONTROL REGISTER 3 SPECIAL REGISTER
TR
011
DTMF3
CR2
100
0
CALL INITIALIZE
TRANSMIT S1 RECEIVE GAIN BOOST
16 WAY
RESET DSP TRANSMIT ATTEN. 2 SQ SELECT 1
TRAIN INHIBIT TRANSMIT ATTEN. 1 SQ SELECT 0
EQUALIZER ENABLE TRANSMIT ATTEN. 0
CR3
101
TXDALT
0
TRANSMIT ATTEN. 3 TXD SOURCE
SR
101
0
TX BAUD CLOCK
RX UNSCR. DATA
0
0
ID REGISTER
ID
110
1
1
1
0
X
X
X
X
NOTE: When a register containing reserved control bits is written into, the reserved bits must be programmed as 0's. X = Undefined, mask in software.
Page: 6 of 30
(c) 2005, 2008 TERIDIAN Semiconductor Corporation
Rev 7.1
73K324L
CCITT V.22bis,V.23,V.22,V.21, Bell 212A Single-Chip Modem
DATA SHEET
REGISTER ADDRESS TABLE
ADDRESS REGISTER AD2 - AD0 D7 D6 D5 DATA BIT NUMBER D4 D3 D2 D1 D0
CONTROL REGISTER 0
CR0
000
MODULATION OPTION
MODULATION TYPE 1
MODULATION TYPE 0
TRANSMIT MODE 2
TRANSMIT MODE 1
TRANSMIT MODE 0
TRANSMIT ENABLE
ANSWER/ ORIGINATE
QAM: 0=2400 BIT/S DPSK: 0=1200 BIT/S 1=600 BIT/S FSK: 0=V.23 1=V.21
10=QAM 00=DPSK 01=FSK
0000=PWR DOWN 0001=INT SYNCH 0010=EXT SYNCH 0011=SLAVE SYNCH 0100=ASYCH 8 BITS/CHAR 0101=ASYCH 9 BITS/CHAR 0110=ASYCH 10 BITS/CHAR 0111=ASYCH 11 BITS/CHAR 1X00=FSK ENABLE DETECT INTERRUPT BYPASS SCRAMBLER/ ADD PH. EQ. (V.23) CLK CONTROL
0=DISABLE TXA OUTPUT 1=ENABLE TXA OUTPUT
0=ANSWER 1=ORIGINATE in V.23 0=BC xmit 1=MC xmit
CONTROL REGISTER 1
CR1
001
TRANSMIT PATTERN 1
TRANSMIT PATTERN 0
RESET
TEST MODE 1
TEST MODE 0
00=TX DATA 01=TX ALTERNATE 10=TX MARK 11=TX SPACE
0=OFF 1=ON
0=XTAL 0=NORMAL 1=16 X DATA 1=BYPASS SCRAMBLER RATE OUTPUT AT CLK PIN IN QAM/DPSK MODE ONLY UNSCR. MARKS DETECT CARRIER DETECT
0=NORMAL 1=RESET
00=NORMAL 01=ANALOG LOOPBACK 10=REMOTE DIGITAL LOOPBACK 11=LOCAL DIGITAL LOOPBACK CP TONE DETECT SIGNAL QUALITY INDICATOR 0=GOOD 1=BAD
DETECT REGISTER
DR
010
RECEIVE LEVEL INDICATOR
S1 PATTERN DETECT
RECEIVE DATA
SPECIAL TONE DETECT
0=SIGNAL 0=NOT PRESENT OUTPUTS BELOW 1=PATTERN RECEIVED THRESHOLD FOUND DATA STREAM 1=ABOVE THRESHOLD TONE CONTROL REGISTER RXD OUTPUT CONTROL RXD PIN 0=NORMAL 1=TRI-STATE TRANSMIT GUARD/ CALLING/ SCT TONE 0=OFF 1=ON TRANSMIT ANSWER TONE 0=OFF 1=ON TRANSMIT DTMF
0=CONDITION NOT DETECTED 1=CONDITION DETECTED
TR
011
DTMF3
DTMF2/ 4 WIRE FDX
DTMF1/ OVERSPEED
DTMF0/ GUARD/ ANSWER/ CALLING/SCT
1=TX DTMF
4 BIT CODE FOR 1 OF 16 DUAL TONE COMBINATIONS 0=NORMAL OPERATION 1=ALLOWS V.23 FULL DUPLEX OPERATION
0 - 1800 HZ 1 - 550 HZ ANSWER: 0 - 2225 HZ 1 - 2100 HZ CALLING: 0 - 1300 HZ 1 - 900 HZ SCT: GUARD:
CONTROL REGISTER 2
CR2
100
MUST BE 0
SPECIAL REGISTER ACCESS 0=ACCESS CR3 1=ACCESS SPECIAL REGISTER
CALL INITIALIZE
TRANSMIT S1
16 WAY
RESET DSP
TRAIN INHIBIT
EQUALIZER ENABLE
0=NORMAL 0=DSP IN DOTTING DEMOD MODE 1=S1 1=DSP IN CALL PROGRESS MODE
0=RX=TX 1=RX=16 WAY
0=DSP INACTIVE 1=DSP ACTIVE
0=ADAPT EQ ACTIVE 1=ADAPT EQ FROZEN
0=ADAPT EQ IN INIT 1=ADAPT EQ OK TO ADAPT
CONTROL REGISTER 3
CR3
101
TXDALT
TRISTATE TX/RXCLK 0=CLOCK DRIVEN 1=CLOCK TRISTATE
0
RECEIVE GAIN BOOST 0=NO BOOST 1=18 dB BOOST
TRANSMIT ATTEN. 3
TRANSMIT ATTEN. 2
TRANSMIT ATTEN. 1
TRANSMIT ATTEN. 0
ALTERNATE TRANSMIT DATA SOURCE SPECIAL REGISTER
0000-1111, SETS TRANSMIT ATTENUATOR 16 dB RANGE DEFAULT=0100 -10 dbM0 TXD SOURCE SQ SELECT1 SQ SELECT0
SR
101
0
TX BAUD CLOCK
RX UNSCR. DATA
0
0
OUTPUTS TXBAUD CLOCK
OUTPUTS UNSCR. DATA
0=TXD PIN 1=TX DATA CR3-D7
0010 0110 1010 1110
-5 BER -6 BER -4 BER -3 BER
ID REGISTER
10
110
1
1
1
0
X
X
X
X
00XX=73K212AL, 322L, 321L 01XX=73K221AL, 302L 10XX=73K222AL, 222BL 1100=73K224L 1110=73K324L 1100=73K224BL 1110=73K324BL
Page: 7 of 30
(c) 2005, 2008 TERIDIAN Semiconductor Corporation
Rev 7.1
73K324L
CCITT V.22bis,V.23,V.22,V.21, Bell 212A Single-Chip Modem
DATA SHEET
CONTROL REGISTER 0
D7 CR0 000 MODUL. OPTION D6 MODUL. TYPE 1 D5 MODUL. TYPE 0 D4 TRANSMIT MODE 2 D3 TRANSMIT MODE 1 D2 TRANSMIT MODE 0 D1 TRANSMIT ENABLE D0 ANSWER/ ORIGINATE
BIT NO. D0
NAME Answer/ Originate
CONDITION 0
DESCRIPTION Selects Answer mode (transmit in high band, receive in low band) or in V.23 HDX mode, receive at 1200 bit/s and transmit at 75 bit/s. Selects Originate mode (transmit in low band, receive in high band) or in V.23 HDX mode, receive at 75 bit/s and transmit at 1200 bit/s. Note: This bit works with Tone Register bits D0 and D6 to program special tones detected in the Detect Register. See Detect and Tone Registers.
1
D1
Transmit Enable
0 1
Disables transmit output at TXA. Enables transmit output at TXA. Note: Transmit Enable must be set to 1 to allow activation of Answer Tone, DTMF, or Carrier.
D5 D4 D3 D2 D5, D4, D3, D2 Transmit Mode 0 0 0 0 0 0 0 1 Selects Power Down mode. All functions are disabled except the digital interface. Internal Synchronous mode. In this mode TXCLK is an internally derived 600, 1200 or 2400 Hz signal. Serial input data appearing at TXD must be valid on the rising edge of TXCLK. Receive data is clocked out of RXD on the falling edge of RXCLK. External Synchronous mode. Operation is identical to internal synchronous, but TXCLK is connected internally to EXCLK pin, and a 600, 1200 or 2400 Hz clock must be supplied externally. Slave Synchronous mode. Same operation as other Synchronous modes. TXCLK is connected internally to the RXCLK pin in this mode. Selects Asynchronous mode - 8 bits/character (1 start bit, 6 data bits, 1 stop bit). Selects Asynchronous mode - 9 bits/character (1 start bit, 7 data bits, 1 stop bit). Selects Asynchronous mode - 10 bits/character (1 start bit, 8 data bits, 1 stop bit). Selects Asynchronous mode - 11 bits/character (1 start bit, 8 data bits, Parity and/or 1 or 2 stop bits). Selects FSK operation.
0
0
1
0
0
0
1
1
0 0 0 0 1
1 1 1 1 X
0 0 1 1 0
0 1 0 1 0
Page: 8 of 30
(c) 2005, 2008 TERIDIAN Semiconductor Corporation
Rev 7.1
73K324L
CCITT V.22bis,V.23,V.22,V.21, Bell 212A Single-Chip Modem
DATA SHEET
CONTROL REGISTER 0 (continued) BIT NO. D6,D5 NAME Modulation Type CONDITION D6 1 0 0 D7 Modulation Option 0 1 D5 0 0 1 QAM DPSK FSK QAM selects 2400 bit/s. DPSK selects 1200 bit/s. FSK selects V.23 mode. DPSK selects 600 bit/s. FSK selects V.21 mode. DESCRIPTION
CONTROL REGISTER 1
D7 CR1 001 TRANSMIT PATTERN 1 D6 TRANSMIT PATTERN 0 D5 ENABLE DETECT INT. D4 BYPASS SCRAMB/ ADD PH.EQ D3 CLK CONTROL D2 RESET D1 TEST MODE 1 D0 TEST MODE 0
BIT NO. D1, D0
NAME Test Mode
CONDITION D1 0 0 D0 0 1
DESCRIPTION Selects Normal Operating mode. Analog Loopback mode. Loops the transmitted analog signal back to the receiver, and causes the receiver to use the same carrier frequency as the transmitter. To squelch the TXA pin, transmit enable bit must be low. Tone Register bit D2 must be zero. Selects remote digital loopback. Received data is looped back to transmit data internally, and RXD is forced to a mark. Data on TXD is ignored. Selects local digital loopback. Internally loops TXD back to RXD and continues to transmit data carrier at TXA pin. Selects normal operation. Resets modem to power down state. All control register bits (CR0, CR1, CR2, CR3 and Tone) are reset to zero except CR3 bit D2. The output of the clock pin will be set to the crystal frequency. Selects 11.0592 MHz crystal echo output at CLK pin. Selects 16 X the data rate output at CLK pin in QAM and DPSK only.
1
0
1 D2 Reset 0 1
1
D3
CLK Control (Clock Control)
0 1
Page: 9 of 30
(c) 2005, 2008 TERIDIAN Semiconductor Corporation
Rev 7.1
73K324L
CCITT V.22bis,V.23,V.22,V.21, Bell 212A Single-Chip Modem
DATA SHEET
CONTROL REGISTER 1 (continued)
D7 CR1 001 TRANSMIT PATTERN 1 D6 TRANSMIT PATTERN 0 D5 ENABLE DETECT INT. D4 BYPASS SCRAMB/ ADD PH.EQ. D3 CLK CONTROL D2 RESET D1 TEST MODE 1 D0 TEST MODE 0
BIT NO. D4
NAME Bypass Scrambler/ Add Ph. Eq.
CONDITION 0 1
DESCRIPTION Selects normal operation. DPSK and QAM data is passed through scrambler. Selects Scrambler Bypass. DPSK and QAM data is routed around scrambler in the transmit path. In the V.23 mode, additional phase equalization is added to the main channel filters when D4 is set to 1. Disables interrupt at INT pin. All interrupts are normally disabled in Power Down mode. Enables INT output. An interrupt will be generated with a change in status of DR bits D1-D4 and D6. The answer tone and call progress detect interrupts are masked when the TX enable bit is set. Carrier detect is masked when TX DTMF is activated. All interrupts will be disabled if the device is in Power Down mode.
D5
Enable Detect Interrupt
0 1
D7 D7, D6 Transmit Pattern 0 0
D6 0 1 Selects normal data transmission as controlled by the state of the TXD pin. Selects an alternating mark/space transmit pattern for modem testing and handshaking. Also used for S1 pattern generation. See CR2 bit D4. Selects a constant mark transmit pattern. Selects a constant space transmit pattern.
1 1
0 1
Page: 10 of 30
(c) 2005, 2008 TERIDIAN Semiconductor Corporation
Rev 7.1
73K324L
CCITT V.22bis,V.23,V.22,V.21, Bell 212A Single-Chip Modem
DATA SHEET
DETECT REGISTER
DR 010 D7 RECEIVE LEVEL INDICATOR D6 S1 PATTERN DETECT D5 RECEIVE DATA D4 UNSCR. MARK DETECT D3 CARRIER DETECT D2 SPECIAL TONE DETECT D1 CALL PROG. DETECT D0 SIGNAL QUALITY INDICATOR
BIT NO. D0
NAME Signal Quality Indicator Call Progress Detect
CONDITION 0 1 0 1
DESCRIPTION Indicates normal received signal. Indicates low received signal quality (above average error rate). Interacts with Special Register SQ bits D2, D1. No call progress tone detected. Indicates presence of call progress tones. The call progress detection circuitry is activated by energy in the normal 350 to 620 Hz call progress band. Condition not detected Condition detected
D1
D2
Special Tone Detect
CR0 D0
0 1
TR D0 CR2 D5
1 1 0 1 D3 Carrier Detect Unscr. Mark Detect Receive Data
0 1 X X 0 1 0 1
1 1 0 0
2225 Hz 10 Hz answer tone detected in V.22bis, V.22 modes. 2100 Hz 21 Hz answer tone detected in V.22bis, V.22 modes. 900 Hz SCT tone detected in V.23 mode. 2100 Hz or 2225 Hz answer tone detected in QAM, DPSK mode. No carrier detected in the receive channel. Indicated carrier has been detected in the received channel. Should be time qualified by software. No unscrambled mark being received. Indicates detection of unscrambled marks in the received data. Should be time qualified by software. Continuously outputs the received data stream. This data is the same as that output on the RXD pin, but it is not disabled when RXD is tri-stated.
D4
D5
D6
S1 Pattern Detect
0 1
No S1 pattern being received. S1 pattern detected. Should be time qualified by software. S1 is an unscrambled double dibit (11001100...) sent in DPSK 1200 bit/s mode. Generated pattern must be properly aligned to transmitter baud clock to be detected. Received signal level below threshold, ( -25 dBm0);can use receive gain boost (+18 dB) Received signal above threshold.
D7
Receive Level Indicator
0
1
Page: 11 of 30
(c) 2005, 2008 TERIDIAN Semiconductor Corporation
Rev 7.1
73K324L
CCITT V.22bis,V.23,V.22,V.21, Bell 212A Single-Chip Modem
DATA SHEET
TONE REGISTER
D7 TR 011 RXD OUTPUT CONTR. D6 TRANSMIT GUARD/ CALLING/SCT TONE D5 TRANSMIT ANSWER TONE D4 TRANSMIT DTMF D3 DTMF 3 D2 DTMF 2/ WIRE FDX D1 DTMF 1/ OVERSPEED D0 DTMF 0/ G.T./ANSW./ CALLING/SCT TONE/SEL
BIT NO. D0, D4, D5, D6
NAME DTMF 0/Guard Tone/Answer Tone/Calling/ SCT Tone/ Transmit Select X 1 1
CONDITION D6 D5 D4 D0 X 0 0 1 0 0 X 0 1
DESCRIPTION D0 interacts with bits D6, D5, D4, and CR0 as shown. Transmit DTMF tones (overrides all other functions). Select 1800 Hz guard tone if in V.22bis or V.22 and Answer mode in CR0. Select 550 Hz guard tone if in V.22bis or V.22 and Answer mode in CR0.
Note: Bit D0 also selects the answer tone detected in Originate mode, see Detect Register Special Tone Detect (bit D2) for details. 1 X X 1 D1 DTMF 1/ Overspeed 0 1 1 0 D4 0 0 D2 DTMF 2/ 4 WIRE FDX D4 0 0 0 0 0 0 D1 0 1 D2 0 1 Selects 2-wire full-duplex or half-duplex. D2 selects 4 wire full duplex in the Modulation mode selected. The receive path corresponds to the ANS/ORIG bit CR0 D0 in terms of high or low band selection. The transmitter is in the same band as the receiver, but does not have magnitude filtering or equalization on its signal as in the receive path. 0 0 1 1 1300 Hz calling tone will be transmitted if V.22, V.22bis or V.23 Originate mode is selected in CR0. Transmit 2225 Hz Answer Tone. Must be in DPSK Answer mode. Transmit 2100 Hz Answer Tone. Must be in DPSK Answer mode. 900 Hz SCT (soft carrier turnoff) tone transmitted in V.23 75 bit/s Receive mode. (CR0 bit D0 = 1). D1 interacts with D4 as shown. Asynchronous QAM/DPSK +1% -2.5%. (Normal). Asynchronous QAM/DPSK, 2400, 1200 or 600 bit/s +2.3% -2.5%. (Extended overspeed).
NOTE:
DTMF0 - DTMF2 should be set to an appropriate state after DTMF dialing to avoid unintended operation.
Page: 12 of 30
(c) 2005, 2008 TERIDIAN Semiconductor Corporation
Rev 7.1
73K324L
CCITT V.22bis,V.23,V.22,V.21, Bell 212A Single-Chip Modem
DATA SHEET
TONE REGISTER (continued)
D7 TR 011 RXD OUTPUT CONTR. D6 TRANSMIT GUARD/ CALLING/SCT TONE D5 TRANSMIT ANSWER TONE D4 TRANSMIT DTMF D3 DTMF 3 D2 DTMF 2/ WIRE FDX D1 DTMF 1/ OVERSPEED D0 DTMF 0/ GUARD/ CALLING/SCT TONE SEL
BIT NO. D3, D2, D1, D0
NAME DTMF 3, 2, 1, 0
CONDITION D4 = 1
DESCRIPTION Programs 1 of 16 DTMF tone pairs that will be D1, D02, 1, 0 transmitted when TX DTMF and TX enable bit (CR0, bit D1) is set. Tone encoding is shown below: KEYBOARD EQUIVALENT 1 2 3 4 5 6 7 8 9 0 * # A B C D DTMF CODE D3 D2 D1 D0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 TONES LOW HIGH 697 697 697 770 770 770 852 852 852 941 941 941 697 770 852 941 1209 1336 1477 1209 1336 1477 1209 1336 1477 1336 1209 1477 1633 1633 1633 1633
D7
RXD Output Control
0 1
Enables RXD pin. Receive data will be output on RXD. Disables RXD pin. The RXD pin reverts to a high impedance with internal weak pull-up resistor.
Page: 13 of 30
(c) 2005, 2008 TERIDIAN Semiconductor Corporation
Rev 7.1
73K324L
CCITT V.22bis,V.23,V.22,V.21, Bell 212A Single-Chip Modem
DATA SHEET
CONTROL REGISTER 2
D7 CR2 100 0 D6 SPEC REG ACCESS D5 CALL INIT D4 TRANSMIT S1 D3 16 WAY D2 RESET DSP D1 TRAIN INHIBIT D0 EQUALIZER ENABLE
BIT NO. D0
NAME Equalizer Enable
CONDITION 0 1
DESCRIPTION The adaptive equalizer is in its initialized state. The adaptive equalizer is enabled. This bit is used in handshakes to control when the equalizer should calculate its coefficients. The adaptive equalizer is active. The adaptive equalizer coefficients are frozen. The DSP is inactive and all variables are initialized. The DSP is running based on the mode set by other control bits The receiver and transmitter are using the same decision plane (based on the Modulator Control Mode). The receiver, independent of the transmitter, is forced into a 16 point decision plane. Used for QAM handshaking. The transmitter when placed in alternating Mark/Space mode transmits 0101 . . . . scrambled or not dependent on the bypass scrambler bit and Modulation mode. When this bit is 1 and only when the transmitter is placed in alternating Mark/Space mode by CR1 bits D7, D6, an unscrambled repetitive double dibit pattern of 00 and 11 at 1200 bit/s (S1) is sent. The DSP is setup to do demodulation and pattern detection based on the Various mode bits. Both answer tones are detected in Demod Mode concurrently; TR D0 is ignored. The DSP decodes call progress, calling tones, unscrambled mark, and 2100 Hz and 2225 Hz answer tones. Normal CR3 access. Setting this bit and addressing CR3 allows access to the SPECIAL REGISTER. See the SPECIAL REGISTER for details. Must be 0 for normal operation.
D1 D2
Train Inhibit RESET DSP
0 1 0 1
D3
16 Way
0 1
D4
Transmit S1
0
1
D5
Call Init
0
1
D6
Special Register Access N/A
0 1
D7
0
Page: 14 of 30
(c) 2005, 2008 TERIDIAN Semiconductor Corporation
Rev 7.1
73K324L
CCITT V.22bis,V.23,V.22,V.21, Bell 212A Single-Chip Modem
DATA SHEET
CONTROL REGISTER 3
D7 CR3 101 TXDALT D6 TRISTATE TX/RXCLK D5 0 D4 RECEIVE ENABLE BOOST D3 TRANSMIT ATTEN. 3 D2 TRANSMIT ATTEN. 2 D1 TRANSMIT ATTEN. 1 D0 TRANSMIT ATTEN. 0
BIT NO. D3, D2, D1,D0 D4
NAME Transmit Attenuator Receive Gain Boost (18 dB) 0 1
CONDITION D3 D2 D1 D0 0 1 0 1 0 1 01
DESCRIPTION Sets the attenuation level of the transmitted signal in 1 dB steps. The default (D3-D0=0100) is for a transmit level of -10 dBm0. The total range is 16 dB. 18 dB receive front end boost is not used. Boost is in the path. This boost does not change reference levels. It is used to extend dynamic range by compensating for internally generated noise when receiving weak signals. The receive level detect signal and knowledge of the hybrid and transmit attenuator setting will determine when boost should be enabled. Not used. Only write zeros this location. TXCLK, RXCLK outputs driven TXCLK, RXCLK outputs in Tristate mode Alternate TX data source. See Special Register.
D5 D6 D7
Not Used Tristate
TXCLK/RXCLK
0 0 1
Spec. Reg. bit D3=1
TXDALT
ID REGISTER SPECIAL REGISTER
SR 101 D7 0 D6 TXBAUD CLOCK D5 RXUNDSCR DATA D4 0 D3 TXD SOURCE D2 SIGNAL QUALITY LEVEL SELECT1 D1 SIGNAL QUALITY LEVEL SELECT0 D0 0
BIT NO. D7, D4, D0 D6
NAME TXBAUD CLK
DESCRIPTION NOT USED AT THIS TIME. Only write ZEROs to these bits. TXBAUD clock is the transmit baud-synchronous clock that can be used to synchronize the input of arbitrary quad/di-bit patterns. The rising edge of TXBAUD signals the latching of a baud-worth of data internally. Synchronous data to be entered via the TXDALT bit, CR3 bit D7, should have data transitions that start 1/2 bit period delayed from the TXBAUD clock edges. This bit outputs the data received before going to the descrambler. This is useful for sending special unscrambled patterns that can be used for signaling.
D5
RXUNDSCR DATA
Page: 15 of 30
(c) 2005, 2008 TERIDIAN Semiconductor Corporation
Rev 7.1
73K324L
CCITT V.22bis,V.23,V.22,V.21, Bell 212A Single-Chip Modem
DATA SHEET
SPECIAL REGISTER (continued) BIT NO. D3 NAME TXD SOURCE SIGNAL QUALITY LEVEL SELECT DESCRIPTION This bit selects the transmit data source; either the TXD pin if ZERO or the TXDALT if this bit is a ONE. The TRANSMIT PATTERN bits D7 and D6 in CR1 override either of these sources. The signal quality indicator is a logical zero when the signal received is acceptable for low error rate reception. It is determined by the value of the Mean Squared Error (MSE) calculated in the decision process when compared to a given threshold. This threshold can be set to four levels of error rate. The SQI bit will be low for good or average connections. As the error rate crosses the threshold setting, the SQI bit will toggle at a 1.66 ms rate. Toggling will continue until the error rate indicates that the data pump has lost convergence and a retrain is required. At that point the SQI bit will be a ONE constantly. The SQI bit and threshold selection are valid for QAM and DPSK only. TYPICAL THRESHOLD VALUE 10-5 10-6 10-4 10-3 UNITS BER (default) BER BER BER
D2, D1
D2 0 0 1 1
D1 0 1 0 1
NOTE: This register is "mapped" and is accessed by setting CR2 bit D6 to a ONE and addressing CR3. This register provides functions to the 73K324L user that are not necessary in normal communications. Bits D7-D4 are read only, while D3-D0 are read/write. To return to normal CR3 access, CR2 bit D6 must be returned to a ZERO. ID REGISTER
ID 110 D7 ID 3 D6 ID 2 D5 ID 1 D4 ID 0 D3 X D2 X D1 X D0 X
BIT NO. D7, D6, D5, D4
NAME Device Identification Signature
CONDITION D7 D6 D5 D4 0 0 1 1 1 1 1 0 1 0 1 1 1 1 X X X 0 1 0 1 X X X 0 0 0 0
DESCRIPTION Indicates Device: 73K212AL or 73K322L or 73K321L 73K221AL or 73K302L 73K222AL, 73K222BL 73K224L 73K324L 73K224BL 73K324BL
D3-D0
Undefined
Mask in software
Page: 16 of 30
(c) 2005, 2008 TERIDIAN Semiconductor Corporation
Rev 7.1
73K324L
CCITT V.22bis,V.23,V.22,V.21, Bell 212A Single-Chip Modem
DATA SHEET ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS PARAMETER VDD Supply Voltage Storage Temperature Soldering Temperature (10 sec.) Applied Voltage RATING 7V -65 to 150C 260C -0.3 to VDD+0.3V
Note: All inputs and outputs are protected from static charge using built-in, industry standard protection devices and all outputs are short-circuit protected. RECOMMENDED OPERATING CONDITIONS PARAMETER VDD Supply voltage External Components (Refer to Application section for placement.) VREF Bypass capacitor Bias setting resistor ISET Bypass capacitor VDD Bypass capacitor 1 VDD Bypass capacitor 2 XTL1 Load Capacitance XTL2 Load Capacitance Clock Variation TA, Operating Free-Air Temperature (VREF to GND) (Placed between VDD and ISET pins) (ISET pin to GND) (VDD to GND) (VDD to GND) Depends on crystal requirements Depends on crystal requirements (11.0592 MHz) Crystal or external clock -0.01 -40 0.22 1.8 0.22 0.22 22 18 18 39 27 +0.01 85 2 2.2 F M F F F pF pF % C CONDITION MIN 4.5 NOM 5 MAX 5.5 UNIT V
Page: 17 of 30
(c) 2005, 2008 TERIDIAN Semiconductor Corporation
Rev 7.1
73K324L
CCITT V.22bis,V.23,V.22,V.21, Bell 212A Single-Chip Modem
DATA SHEET
DC ELECTRICAL CHARACTERISTICS (TA = -40C to 85C, VDD = recommended range unless otherwise noted) PARAMETER IDD, Supply Current IDD1, Active IDD2, Idle Digital Inputs VIL, Input Low Voltage VIH, Input High Voltage All Inputs except Reset XTL1, XTL2 Reset, XTL1, XTL2 IIH, Input High Current IIL, Input Low Current Reset Pull-down Current Digital Outputs VOH, Output High Voltage VOL, Output Low Voltage RXD Tri-State Pull-up Current. Capacitance Maximum Capacitive Load CLK Input Capacitance All Digital Inputs 25 10 pF pF IO = IOH Min IOUT = -0.4 mA IO = IOUT = 1.6 mA RXD = GND -2 2.4 VDD 0.4 -50 V V A VI = VDD VI = 0V Reset = VDD -200 -2 -30 -70 2.0 3.0 VDD VDD 100 V V A A A 0.8 V CONDITION CLK = 11.0592 MHz ISET Resistor = 2 M Operating with crystal oscillator < 5 pF capacitive load on CLK pin 18 25 5 mA mA MIN NOM MAX UNIT
Page: 18 of 30
(c) 2005, 2008 TERIDIAN Semiconductor Corporation
Rev 7.1
73K324L
CCITT V.22bis,V.23,V.22,V.21, Bell 212A Single-Chip Modem
DATA SHEET
DYNAMIC CHARACTERISTICS AND TIMING (TA = -40C to +85C, VDD = recommended range unless otherwise noted) PARAMETER QAM/DPSK Modulator Carrier Suppression Output Amplitude FSK Modulator/Demodulator Output Freq. Error Transmit Level TXA Output Distortion Output Bias Distortion at RXD Output Jitter at RXD Sum of Bias Distortion and Output Jitter at RXD 2100 Hz Answer Tone Generator Output Amplitude Output Distortion DTMF Generator Freq. Accuracy Output Amplitude Output Amplitude Twist Receiver Dynamic Range Call Progress Detector Detect Level Reject Level Delay Time Hold Time Hysteresis -70 dBm0 to -30 dBm0 STEP -30 dBm0 to -70 dBm0 STEP @ 460 Hz input signal 2 Low Band, ATT = 0100 High Band, ATT = 0100 High-Band to Low-Band Refer to Performance Curves In Call Init mode 460 Hz input signal -34 0 -40 25 25 dBm0 dBm0 ms ms dB ATT = 0100 (Default Level) Not in V.21 or V.23 Mode Distortion products in receive band Not in V.21 mode -0.03 -10 -8 1.0 -43 2.0 +0.25 -8 -6 3.0 -3.0 % dBm0 dBm0 dB dBm0 -11.5 -10 -9 -40 dBm0 dB CLK = 11.0592 MHz ATT = 0100 (Default) Transmit Dotting Pattern All products through BPF
Dotting Pattern measured at RXD Receive Level -20 dBm, SNR 20 dB
CONDITION Measured at TXA TX scrambled marks ATT= 0100 (default)
MIN 35 -11.5
NOM
MAX
UNIT dB
-10.0
-9
dBm0
-.31 -11.5 -10.0
+0.20 -9 -45
% dBm0 dB % % %
-10 -15 -15
+10 +15 +15
Integrated for 5 seconds Integrated for 5 seconds
NOTE: Parameters expressed in dBm0 refer to the following definition: 0 dB loss in the Transmit path from TXA to the line 2 dB gain in the Receive path from the line to RXA Refer to the Basic Box Modem diagram in the Applications section for the DAA design.
Page: 19 of 30
(c) 2005, 2008 TERIDIAN Semiconductor Corporation
Rev 7.1
73K324L
CCITT V.22bis,V.23,V.22,V.21, Bell 212A Single-Chip Modem
DATA SHEET
DYNAMIC CHARACTERISTICS AND TIMING (continued) PARAMETERS Threshold Hysteresis Delay Time FSK DPSK QAM Hold Time FSK DPSK QAM Special Tone Detectors Detect Level Delay and Hold Time 2225 or 2100 Hz answer tone Call INIT mode 2225 10 Hz 2100 21 Hz Tone Accuracy 9 Hz 6 50 ms
See definitions for D0 of Tone Register
CONDITIONS QAM/DPSK or FSK receive data All Modes 70 dBm0 to -6 dBm0 70 dBm0 to -40 dBm0 -70 dBm0 to -6 dBm0 -70 dBm0 to -40 dBm0 -70 dBm0 to -6 dBm0 -70 dBm0 to -40 dBm0 -6 dBm0 to -70 dBm0 -40 dBm0 to -70 dBm0 -6 dBm0 to -70 dBm0 -40 dBm0 to -70 dBm0 -6 dBm0 to -70 dBm0 -40 dBm0 to -70 dBm0
MIN -48 2 25 25 7 7 25 25 25 15 20 14 25 8 -48
NOM
MAX -43 37 37 17 17 37 37 37 30 29 21 32 28 -43
UNITS dBm0 dB ms ms ms ms ms ms ms ms ms ms ms ms dBm0
Carrier Detect Receive Gain Boost "On" for Lower Input Level Measurements
900 Hz SCT Receive V.23 main
channel
10 2
45
ms dB
Hysteresis PATTERN DETECTORS S1 Pattern Delay Time Hold Time Unscrambled Mark Delay Time Hold Time Receive Level Indicator Detect On Valid after Carrier Detect DPSK Mode For signals from -6 to -40 Demod or call Init Mode For signals from -6 to -40 dBm0, Demod Mode DPSK MODE
10 10 10 10 -22 1 4
55 45 45 45 -28 7
ms ms ms ms dBm0 ms
Page: 20 of 30
(c) 2005, 2008 TERIDIAN Semiconductor Corporation
Rev 7.1
73K324L
CCITT V.22bis,V.23,V.22,V.21, Bell 212A Single-Chip Modem
DATA SHEET
DYNAMIC CHARACTERISTICS AND TIMING (continued) PARAMETER Output Smoothing Filter Output Impedance Output Load TXA pin TXA pin; FSK Single Tone out for THD = -50 Db in 0.3 to 3.4 kHz range Maximum Transmitted Energy 4 kHz, Guard Tones off 10 kHz, Guard Tones off 12 kHz, Guard Tones off Anti Alias Low Pass Filter Maximum allowed Out-of-Band Signal Energy (Defines Hybrid Trans-Hybrid Loss requirements Transmit Attenuator Range of Transmit Level Step Accuracy Clock Noise Carrier Offset Capture Range Recovered Clock Capture Range Guard Tone Generator Tone Accuracy Tone Level (Below QAM/DPSK Output) Harmonic Distortion (700 to 2900 Hz) 550 Hz 1800 Hz 550 Hz 1800 Hz 550 or 1800 Hz -4.5 -7.5 +1.2 -0.8 -3.0 -6.1 -1.5 -4.5 -50 % % dB dB dB % of data rate originate or answer -.02 +.02 % Originate or Answer 5 Hz TXA pin; 153.6 kHz 1111-0000 Default ATT = 0100 (-10 dBm0) -21 -0.15 1.5 -6 +0.15 dBm0 dB mV rms Scrambled data at 2400 bit/s in opposite band Sinusoids out of band -14 -9 dBm dBm 10 50 -35 -55 -65 200 300 k pF dBm0 dBm0 dBm0 CONDITION MIN NOM MAX UNIT
Page: 21 of 30
(c) 2005, 2008 TERIDIAN Semiconductor Corporation
Rev 7.1
73K324L
CCITT V.22bis,V.23,V.22,V.21, Bell 212A Single-Chip Modem
DATA SHEET
DYNAMIC CHARACTERISTICS AND TIMING (continued) PARAMETER Timing (Refer to Timing Diagrams) Parallel Mode: TAL TLA TLC TCL TRD TLL TRDF TRW TWW TDW TWD Serial Mode: TRCK TAR TRA TRD TRDF TCKDR TWW TAW TWA TCKDW TCKW TDCK T1, T2 Note: Clock high after RD Address setup before RD low Address hold after RD low RD to data valid Data float after RD high Read data out after falling edge of EXCLK WR width Address setup before WR
Address hold after rising edge of WR
CONDITION
MIN
NOM
MAX
UNIT
CS/Addr. setup before ALE Low CS/Addr. hold after ALE Low ALE Low to RD/WR Low RD/WR Control to ALE High Data out from RD Low ALE width Data float after RD High RD width WR width Data setup before WR High Data hold after WR High
30 6 40 10 90 25 40 70 70 70 20 250 0 350 110 50 300 350 50 50 200 330 50 500 T1& T2 T1
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Write data hold after falling edge of EXCLK
WR high after falling edge of EXCLK
Data setup before falling edge of EXCLK Minimum period
T1 and T2 are the low/high periods, respectively, of EXCLK in Serial mode.
NOTE: Asserting ALE, CS, and RD or WR concurrently can cause unintentional register accesses. When using non-8031 compatible processors, care must be taken to prevent this from occurring when designing the interface logic.
Page: 22 of 30
(c) 2005, 2008 TERIDIAN Semiconductor Corporation
Rev 7.1
73K324L
CCITT V.22bis,V.23,V.22,V.21, Bell 212A Single-Chip Modem
DATA SHEET TIMING DIAGRAMS
BUS TIMING DIAGRAM (PARALLEL CONTROL MODE)
TLL ALE TLC RD WR TLA TAL AD0-AD7 CS ADDRESS READ DATA ADDRESS TRD TRDF TDW WRITE DATA TWD TRW TCL TLC TWW
READ TIMING DIAGRAM (SERIAL CONTROL MODE)
T1 EXCLK T2
TRCK RD TAR A0-A2 TRA
ADDRESS TRD TCKDR
TRDF D3 D4 D5 D6 D7
DATA
D0
D1
D2
WRITE TIMING DIAGRAM (SERIAL CONTROL MODE)
T2 EXCLK T1 TCKW TWW WR TAW TWA A0-A2 ADDRESS
TDCK DATA D0 D1 D2 D3 D4 D5 D6 D7
TCKDW
Page: 23 of 30
(c) 2005, 2008 TERIDIAN Semiconductor Corporation
Rev 7.1
73K324L
CCITT V.22bis,V.23,V.22,V.21, Bell 212A Single-Chip Modem
DATA SHEET APPLICATIONS INFORMATION
GENERAL CONSIDERATIONS Figures 1 and 2 show basic circuit diagrams for K-Series modem integrated circuits. K-Series products are designed to be used in conjunction with a control processor, a UART or RS-232 serial data interface, and a DAA phone line interface to function as a typical intelligent modem. The K-Series ICs interface directly with Intel 8048 and 80C51 microprocessors for control and status monitoring purposes. Two typical DAA arrangements are shown: one for a split 5 or 12 volt design and one for a single 5 volt design. These diagrams are for reference only and do not represent productionready modem designs.
C14 39 pF Y1 11.0592 MHZ N/C C13 18 pF +5V
K-Series devices are available with two control interface versions: one for a parallel multiplexed address/data interface, and one for a serial interface. The parallel version is intended for use with 8039/48 or 8031/51 microcontrollers from Intel or many other manufacturers. The serial interface can be used with other microcontrollers or in applications where only a limited number of port lines are available or the application does not lend itself to a multiplexed address/data interface. The parallel versions may also be used in the Serial mode, as explained in the data sheet pin description. In most applications the controller will monitor the serial data for commands from the DTE and the received data for break signals from the far end modem. In this way, commands to the modem are sent over the same line as the transmitted data. In other applications the RS-232 interface handshake lines are used for modem control.
+
C8 22 F C1 390 pF
R10 2.2M XTL1 INT CLK INT XTL1 XTL2 VDD ISET GND RD WR ALE CS VREF RXA K-SERIES LOW POWER FAMILY C6 0.1 F RXA C10 0.1 F C11 0.1 F C9 0.1 F
RS232 LEVEL CONVERTERS CA CB CC CD CF RTS CTS DSR DTR DCD
XTL2
80C51 P1.0 P1.1 P1.2 P1.3 P1.5 P1.6 P0.0-7 RD WR ALE P3.1 P3.2
R5 37.4K R4 20K LM 1458 U1A C2 300 pF R7 43.2K R6 20K C3 1000 pF
-
+
R4 5.1K R3 3.6K
P3.0 P1.7 RESET BA BB DA DD DB TXD RXD EXCLK RXCLK TXCLK
TXA C7 0.1 F RESET TXA +5V C12 1 F
V+ LM 1458 U1B + V-
U5, U6 MC145406
-
R1 475 1% D3, D4 4.7V ZENER C4 0.033 F
T1 MIDCOM 671-8005 C5 0.47 F 250V U2 4N35 D1 IN4004 +5V K1 D2 IN914 +5 R8 22K
T
VR1 MOV V250L20
R R9 10K Q1 2N2222A 22K
FIGURE 1: Basic Box Modem with Dual-Supply Hybrid
Page: 24 of 30
(c) 2005, 2008 TERIDIAN Semiconductor Corporation
Rev 7.1
73K324L
CCITT V.22bis,V.23,V.22,V.21, Bell 212A Single-Chip Modem
DATA SHEET APPLICATIONS INFORMATION (continued)
DIRECT ACCESS ARRANGEMENT (DAA) The telephone line interfaces show two examples of how the "hybrid" may be implemented. The split supply design (Figure 1) is a typical two op-amp hybrid. The receive op-amp serves two purposes. It supplies gain to amplify the receive signal to the proper level for the modem's detectors and demodulator, and it removes the transmitted signal from the receive signal present at the transformer. This is done by supplying a portion of the transmitted signal to the non-inverting input of the receive op-amp at the same amplitude as the signal appearing at the transformer, making the transmit signal Common mode. The single-supply hybrid is more complex than the dual-supply version described above, but its use eliminates the need for a second power supply. This circuit (Figure 2) uses a bridged drive to allow undistorted signals to be sent with a single 5 volt supply. C1
390 pF R4 37.4K 1% C3 0.1 F RXA C4 0.0047 F R1 20K 1%
Because DTMF tones utilize a higher amplitude than data, these signals will clip if a single-ended drive approach is used. The bridged driver uses an extra op-amp (U1A) to invert the signal coming from the gain setting op-amp (U1B) before sending it to the other leg of the transformer. Each op-amp then supplies half the drive signal to the transformer. The receive amplifier (U1C) picks off its signal at the junction of the impedance matching resistor and the transformer. Because the bottom leg of the transformer is being driven in one direction by U1A and the resistor is driven in the opposite direction at the same time by U1B, the junction of the transformer and resistor remains relatively constant and the receive signal is unaffected. DESIGN CONSIDERATIONS TERIDIAN Semiconductor's 1-chip modem products include all basic modem functions. This makes these devices adaptable for use in a variety of applications, and as easy to control as conventional digital bus peripherals.
8
* U1C
+
9 10
R5 3.3K
R2 20K 1%
+5V 5 6
+ -
4 7 11
R3 475 1% T1 MIDCOM 671-8005
Note: Op-amp U1 must be rated for single 5V operation. R10 & R11 values depend on Op-amp
* U1B
T C10 0.47 F 250V +5V
R6 22.1K C6 0.1 F TXA R9 20K 1% R8 20K 1% 2 3 +5V VOLTAGE REFERENCE K1 R10* D4 IN914 D1 IN4004 R7 20K 1% C5 750 pF C2 0.033 F
U2 4N35
R13 22K
D2 3.3V ZENERS D3 1 +5V
VR1 MOV V250L20
R12 22K
+
* U1A
R R14 10K Q1 2N2222A
R11*
C7 0.1 F
+
C8 10 F
HOOK RING
FIGURE 2: Single 5V Hybrid Version
Page: 25 of 30
(c) 2005, 2008 TERIDIAN Semiconductor Corporation
Rev 7.1
73K324L
CCITT V.22bis,V.23,V.22,V.21, Bell 212A Single-Chip Modem
DATA SHEET
Unlike digital logic circuitry, modem designs must properly contend with precise frequency tolerances and very low level analog signals, to ensure acceptable performance. Using good analog circuit design practices will generally result in a sound design. Following are additional recommendations, which should be taken into consideration when starting new designs. CRYSTAL OSCILLATOR The K-Series crystal oscillator requires a Parallel mode (antiresonant) crystal, which operates at 11.0592 MHz. It is important that this frequency be maintained to within 0.01% accuracy. In order for a Parallel mode crystal to operate correctly and to specification, it must have a load capacitor connected to the junction of each of the crystal and internal inverter connections, terminated to ground. The values of these capacitors depend primarily on the crystal's characteristics, and to a lesser degree on the internal inverter circuit. The values used affect the accuracy and start up characteristics of the oscillator. LAYOUT CONSIDERATIONS Good analog/digital design rules must be used to control system noise in order to obtain highest performance in modem designs. The more digital circuitry present on the PC board, the more this attention to noise control is needed. The modem should be treated as a high impedance analog device. A 22 F electrolytic capacitor in parallel with a 0.22 F ceramic capacitor between VDD and GND is recommended. Liberal use of ground planes and larger traces on power and ground are also highly favored. High-speed digital circuits tend to generate a significant amount of EMI (Electro-Magnetic Interference), which must be minimized in order to meet regulatory agency limitations. To accomplish this, high speed digital devices should be locally bypassed, and the telephone line interface and K-Series device should be located close to each other near the area of the board where the phone line connection is accessed. To avoid problems, power supply and ground traces should be routed separately to the analog and digital functions on the board, and digital signals should not be routed near low level or high impedance analog traces. The analog and digital grounds should only connect at one point near the K-Series device ground pin to avoid ground loops. The K-Series modem IC's should have both high frequency and low frequency bypassing as close to the package as possible. The ISET resistor and bypass capacitor need to be as close to device as possible. MODEM PERFORMANCE CHARACTERISTICS The curves presented here define modem IC performance under a variety of line conditions while inducing disturbances that are typical of those encountered during data transmission on public service telephone lines. Test data was taken using an AEA Electronics' "Autotest I" modem test set and line simulator, operating under computer control. All tests were run full duplex, using a Hayes 2400 SmartmodemTM as the reference modem. A 511 pseudo-random-bit pattern was used for each data point. Noise was C-message weighted and all signal-to-noise (S/N) ratios reflect total power measurements similar to the CCITT V.56 measurement specification. The individual tests are defined as follows. BER vs. S/N This test measures the ability of the modem to operate over noisy lines with a minimum of datatransfer errors. Since some noise is generated in the best of dial-up lines, the modem must operate with the lowest S/N ratio possible. Better modem performance is indicated by test curves that are closest to the BER axis. A narrow spread between curves representing the four line parameters indicates minimal variation in performance while operating over a range of aberrant operating conditions. Typically, a modem will exhibit better BER-performance test curves receiving in the low band than in the high band. BER vs. Receive Level This test measures the dynamic range of the modem. Because signal levels vary widely over dialup lines, the widest possible dynamic range is desirable. The minimum Bell specification calls for 36 dB of dynamic range. S/N ratios are held constant at the indicated values while the receive level is lowered from a very high to very low signal levels. The width of the "bowl" of these curves, taken at the BER point, is the measure of dynamic range.
Page: 26 of 30
(c) 2005, 2008 TERIDIAN Semiconductor Corporation
Rev 7.1
73K324L
CCITT V.22bis,V.23,V.22,V.21, Bell 212A Single-Chip Modem
DATA SHEET
73K324L BER vs S/N
PRELIMINARY
10-2
HIGH BAND RECEIVE -30 dBm QAM OPERATION 2400 bit/s
73K324L BER vs S/N
PRELIMINARY
10-2
3002 LOW BAND RECEIVE -30 dBm QAM OPERATION 2400 bit/s C2
10-3
C2
10-3
BIT ERROR RATE
BIT ERROR RATE
FLAT
10-4
10-4
FLAT C1
10-5
3002
10-5
C1
10-6 10 11 12 13 14 15 16 17 18 19 20 21 22 SIGNAL TO NOISE (dB)
10-6 10 11 12 13 14 15 16 17 18 19 20 21 22 SIGNAL TO NOISE (dB)
73K324L BER vs S/N
PRELIMINARY
10-2
3002 HIGH BAND RECEIVE -30 dBm DPSK OPERATION 1200 bit/s
73K324L BER vs S/N
PRELIMINARY
10-2
3002 LOW BAND RECEIVE -30 dBm DPSK OPERATION 1200 bit/s
C2
10-3
C1
C2
10-3
BIT ERROR RATE
10-4
BIT ERROR RATE
10-4
10-5
10-5
C1 FLAT FLAT
10-6 4 5 6 7 8 9 10 11 12 13 14 15 16
10-6 4 5 6 7 8 9 10 11 12 13 14 15 16
SIGNAL TO NOISE (dB)
SIGNAL TO NOISE (dB)
Page: 27 of 30
(c) 2005, 2008 TERIDIAN Semiconductor Corporation
Rev 7.1
73K324L
CCITT V.22bis,V.23,V.22,V.21, Bell 212A Single-Chip Modem
DATA SHEET
73K324L BER vs S/N
PRELIMINARY
10-2 10-2
73K324L BER vs S/N
PRELIMINARY
QAM OPERATION 2400 bit/s
V.23 MAIN CHANNEL 1200 bit/s BACK CHANNEL 75 bit/s OPERATION FSK
10-3
10-3
BIT ERROR RATE
10-4
BIT ERROR RATE
10-4
10-5
10-5
BACK CHANNEL 75 bit/s
MAIN CHANNEL 1200 bit/s
10-6
-60 -55 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 -0
10-6
0 1 2 3 4 5 6 7 8 9 10 11 12
RECEIVE LEVEL (dBm)
SNR LEVELS
Page: 28 of 30
(c) 2005, 2008 TERIDIAN Semiconductor Corporation
Rev 7.1
73K324L
CCITT V.22bis,V.23,V.22,V.21, Bell 212A Single-Chip Modem
DATA SHEET MECHANICAL SPECIFICATIONS
28-Pin DIP
28-Pin PLCC
0.495 (12.573) 0.485 (12.319) 0.075 (1.905) 0.065 (1.651)
PIN NO. 1 IDENT.
0.165 (4.191) 0.180 (4.572)
0.495 (12.573) 0.485 (12.319)
0.456 (11.650) 0.450 (11.430) 0.016 (0.406) 0.020 (0.508)
0.050 (1.270) 0.045 (1.140) 0.020 (0.508)
0.390 (9.906) 0.430 (10.922)
0.456 (11.650) 0.450 (11.430)
Page: 29 of 30
(c) 2005, 2008 TERIDIAN Semiconductor Corporation
Rev 7.1
73K324L
CCITT V.22bis,V.23,V.22,V.21, Bell 212A Single-Chip Modem
DATA SHEET PACKAGE PIN DESIGNATIONS
(Top View)
VREF AD0 XTL2 XTL1 CLK GND
CAUTION: Use handling procedures necessary for a static sensitive component.
4
3
2
1
28 27 26 25 24 23 22 21 20 19
RXA
AD1 AD2 AD3 AD4 AD5 AD6 AD7
5 6 7 8 9 10 11
RESET ISET RXCLK RXD TXD CS EXCLK
12 13 14 15 16 17 18
ALE
WR
RD
VDD
28-Pin PLCC 73K324L-28IH
ORDERING INFORMATION
PART DESCRIPTION
73K324L 28-Pin Plastic Lead-Free Chip Carrier 73K324L 28-Pin Plastic Lead-Free Tape / Reel
ORDER NO.
73K324L-28IH/F 73K324L-28IHR/F
TXCLK
TXA
INT
PACKAGE MARK
73K324L-28IH 73K324L-28IH
No responsibility is assumed by TERIDIAN Semiconductor Corporation for use of this product nor for any infringements of patents and trademarks or other rights of third parties resulting from its use. No license is granted under any patents, patent rights or trademarks of TERIDIAN Semiconductor Corporation, and the company reserves the right to make changes in specifications at any time without notice. Accordingly, the reader is cautioned to verify that the data sheet is current before placing orders. TERIDIAN Semiconductor Corporation, 6440 Oak Canyon Rd., Irvine, CA 92618-5201, (714) 508-8800, FAX: (714) 508-8877, www.teridiansemi.com Protected by the following patents: (4,777,453) (4,789,995) (4,870,370) (4,847,868) (4,866,739) (c)2005, 2008 TERIDIAN Semiconductor Corporation
06/20/08- rev. 7.1
Page: 30 of 30
(c) 2005, 2008 TERIDIAN Semiconductor Corporation
Rev 7.1

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