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PSMN1R2-25YL
N-channel 25 V 1.2 m logic level MOSFET in LFPAK
Rev. 01 -- 25 June 2009 Product data sheet
1. Product profile
1.1 General description
Logic level N-channel MOSFET in LFPAK package qualified to 150 C. This product is designed and qualified for use in a wide range of industrial, communications and domestic equipment.
1.2 Features and benefits
Advanced TrenchMOS provides low RDSon and low gate charge High efficiency gains in switching power converters Improved mechanical and thermal characteristics LFPAK provides maximum power density in a Power SO8 package
1.3 Applications
DC-to-DC converters Lithium-ion battery protection Load switching Motor control Server power supplies
1.4 Quick reference data
Table 1. VDS ID Ptot Tj Quick reference Conditions Tmb = 25 C; VGS = 10 V; see Figure 1 Tmb = 25 C; see Figure 2 [1] Min -55 VGS = 10 V; Tj(init) = 25 C; ID = 100 A; Vsup 25 V; RGS = 50 ; unclamped VGS = 4.5 V; ID = 25 A; VDS = 12 V; see Figure 12; see Figure 13 Typ Max 25 100 121 150 677 Unit V A W C mJ drain-source voltage Tj 25 C; Tj 150 C drain current total power dissipation junction temperature Symbol Parameter
Avalanche ruggedness EDS(AL)S non-repetitive drain-source avalanche energy Dynamic characteristics QGD QG(tot) gate-drain charge total gate charge 11.9 50.6 nC nC
NXP Semiconductors
PSMN1R2-25YL
N-channel 25 V 1.2 m logic level MOSFET in LFPAK
Quick reference ...continued Conditions VGS = 10 V; ID = 15 A; Tj = 100 C; see Figure 11 VGS = 10 V; ID = 15 A; Tj = 25 C; see Figure 10 Min Typ 0.9 Max 1.6 1.2 Unit m m
Table 1.
Symbol Parameter Static characteristics RDSon drain-source on-state resistance
[1]
Continuous current is limited by package.
2. Pinning information
Table 2. Pin 1 2 3 4 mb S S S G D Pinning information Symbol Description source source source gate drain
mbb076
Simplified outline
Graphic symbol
D
G S
1
2
3
4
SOT1023 (LFPAK2)
3. Ordering information
Table 3. Ordering information Package Name PSMN1R2-25YL LFPAK2 Description Plastic single-ende surface-mounted package (LFPAK2); 4 leads Version SOT1023 Type number
PSMN1R2-25YL_1
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 01 -- 25 June 2009
2 of 13
NXP Semiconductors
PSMN1R2-25YL
N-channel 25 V 1.2 m logic level MOSFET in LFPAK
4. Limiting values
Table 4. Symbol VDS VDGR VGS ID IDM Ptot Tstg Tj Tsld(M) Limiting values Parameter drain-source voltage drain-gate voltage gate-source voltage drain current peak drain current total power dissipation storage temperature junction temperature peak soldering temperature source current peak source current Tmb = 25 C; tp 10 s; pulsed; Tmb = 25 C [1] VGS = 10 V; Tmb = 100 C; see Figure 1 VGS = 10 V; Tmb = 25 C; see Figure 1 tp 10 s; pulsed; Tmb = 25 C; see Figure 3 Tmb = 25 C; see Figure 2 [1] [1] Conditions Tj 25 C; Tj 150 C Tj 25 C; Tj 150 C; RGS = 20 k Min -20 -55 -55 Max 25 25 20 100 100 815 121 150 150 260 Unit V V V A A A W C C C
In accordance with the Absolute Maximum Rating System (IEC 60134).
Source-drain diode IS ISM EDS(AL)S 100 815 677 A A mJ
Avalanche ruggedness non-repetitive VGS = 10 V; Tj(init) = 25 C; ID = 100 A; Vsup 25 V; drain-source avalanche RGS = 50 ; unclamped energy
[1]
Continuous current is limited by package.
300 ID (A) 200
003aad139
120 Pder (%) 80
03aa15
100
40
0 0 50 100 150 Tmb (C) 200
0 0 50 100 150 Tmb (C) 200
Fig 1.
Continuous drain current as a function of mounting base temperature
Fig 2.
Normalized total power dissipation as a function of mounting base temperature
PSMN1R2-25YL_1
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 01 -- 25 June 2009
3 of 13
NXP Semiconductors
PSMN1R2-25YL
N-channel 25 V 1.2 m logic level MOSFET in LFPAK
104 ID (A) 103 Limit Rdson = VDS / ID 10 us 10
2
003aad199
100 us DC 1 ms 10 ms 100 ms
10
1
10-1 10-1
1
10
VDS (V)
102
Fig 3.
Safe operating area; continuous and peak drain currents as a function of drain-source voltage
5. Thermal characteristics
Table 5. Symbol Rth(j-mb) Thermal characteristics Parameter Conditions Min Typ 0.4 Max 1 Unit K/W thermal resistance from see Figure 4 junction to mounting base
1 Zth (j-mb) (K/W) 10
-1
003aad142
= 0.5 0.2 0.1 0.05
10-2
0.02
tp T
single shot 10-3
P
=
tp T
t
10
-4
10-6
10-5
10-4
10-3
10-2
10-1
1
tp (s)
10
Fig 4.
Transient thermal impedance from junction to mounting base as a function of pulse duration
PSMN1R2-25YL_1
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 01 -- 25 June 2009
4 of 13
NXP Semiconductors
PSMN1R2-25YL
N-channel 25 V 1.2 m logic level MOSFET in LFPAK
6. Characteristics
Table 6. Symbol V(BR)DSS VGS(th) Characteristics Parameter drain-source breakdown voltage gate-source threshold voltage Conditions ID = 250 A; VGS = 0 V; Tj = 25 C ID = 250 A; VGS = 0 V; Tj = -55 C ID = 1 mA; VDS = VGS; Tj = 25 C; see Figure 8; see Figure 9 ID = 1 mA; VDS = VGS; Tj = 150 C; see Figure 9 ID = 1 mA; VDS = VGS; Tj = -55 C; see Figure 9 IDSS IGSS RDSon drain leakage current gate leakage current drain-source on-state resistance VDS = 25 V; VGS = 0 V; Tj = 25 C VDS = 25 V; VGS = 0 V; Tj = 150 C VGS = 16 V; VDS = 0 V; Tj = 25 C VGS = -16 V; VDS = 0 V; Tj = 25 C VGS = 4.5 V; ID = 15 A; Tj = 25 C; see Figure 10 VGS = 10 V; ID = 15 A; Tj = 100 C; see Figure 11 VGS = 10 V; ID = 15 A; Tj = 150 C; see Figure 11 VGS = 10 V; ID = 15 A; Tj = 25 C; see Figure 10 RG QG(tot) gate resistance total gate charge f = 1 MHz ID = 25 A; VDS = 12 V; VGS = 10 V; see Figure 12; see Figure 13 ID = 25 A; VDS = 12 V; VGS = 4.5 V; see Figure 12; see Figure 13 QGS QGS(th) QGS(th-pl) QGD VGS(pl) Ciss Coss Crss gate-source charge pre-threshold gate-source charge post-threshold gate-source charge gate-drain charge gate-source plateau voltage input capacitance output capacitance reverse transfer capacitance VDS = 12 V; see Figure 12 VDS = 12 V; VGS = 0 V; f = 1 MHz; Tj = 25 C; see Figure 14 ID = 25 A; VDS = 12 V; VGS = 4.5 V; see Figure 12; see Figure 13 Dynamic characteristics 105 50.6 19.3 8.1 4.5 11.9 2.6 6380 1640 644 nC nC nC nC nC nC V pF pF pF Min 25 22 1.3 0.65 Typ 1.7 1.2 0.9 0.94 Max 2.15 2.45 1.5 500 100 100 1.85 1.6 2.1 1.2 Unit V V V V V A A nA nA m m m m
Static characteristics
PSMN1R2-25YL_1
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 01 -- 25 June 2009
5 of 13
NXP Semiconductors
PSMN1R2-25YL
N-channel 25 V 1.2 m logic level MOSFET in LFPAK
Table 6. Symbol td(on) tr td(off) tf VSD trr Qr
[1]
Characteristics ...continued Parameter turn-on delay time rise time turn-off delay time fall time source-drain voltage reverse recovery time recovered charge IS = 25 A; VGS = 0 V; Tj = 25 C; see Figure 15 IS = 20 A; dIS/dt = -100 A/s; VGS = 0 V; VDS = 20 V Conditions VDS = 12 V; RL = 0.5 ; VGS = 4.5 V; RG(ext) = 5.6 Min Typ 69 125 94 56 0.78 52 66 Max 1.2 Unit ns ns ns ns V ns nC
Source-drain diode
Tested to JEDEC standards where applicable.
100 ID (A) 80
003aad128
12 RDS(on) (m) 10
003aad140
8
60
6
40 Tj = 150 C 20 25 C
4
2
0 0 1 2 3 VGS (V) 4
0 0 5 10 15 VGS (V) 20
Fig 5.
Transfer characteristics: drain current as a function of gate-source voltage; typical values
Fig 6.
Drain-source on-state resistance as a function of gate-source voltage; typical values
PSMN1R2-25YL_1
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 01 -- 25 June 2009
6 of 13
NXP Semiconductors
PSMN1R2-25YL
N-channel 25 V 1.2 m logic level MOSFET in LFPAK
120 ID (A) 90 10 3.5 VGS (V) = 3
003aad131
10-1 ID (A) 10-2
003aab271
2.8
10-3
min
typ
max
60
10-4
2.6 30 2.4 2.2 0 0 1 2 3 VDS (V) 4
10-6 0 1 2 VGS (V) 3 10-5
Fig 7.
Output characteristics: drain current as a function of drain-source voltage; typical values
003a a c337
Fig 8.
Sub-threshold drain current as a function of gate-source voltage
10
003aad132
3 VGS (th) (V) 2 max
RDS(on) (m) 8
2.6
2.8
6 typ min 1 3.5 2 VGS (V) = 10 0 -60 0 0 60 120 Tj (C) 180 0 20 40 60 80 ID (A) 100 4 3
Fig 9.
Gate-source threshold voltage as a function of junction temperature
Fig 10. Drain-source on-state resistance as a function of drain current; typical values
PSMN1R2-25YL_1
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 01 -- 25 June 2009
7 of 13
NXP Semiconductors
PSMN1R2-25YL
N-channel 25 V 1.2 m logic level MOSFET in LFPAK
2 a
03aa27
VDS ID
1.5
VGS(pl) VGS(th) VGS QGS1 QGS2 QGD QG(tot)
003aaa508
1
0.5
QGS
0 -60
0
60
120
Tj (C)
180
Fig 12. Gate charge waveform definitions
Fig 11. Normalized drain-source on-state resistance factor as a function of junction temperature
10 VGS (V) 8
003aad134
104 C (pF)
003aad135
Ciss
6
VDS = 12V 103
Coss
4
Crss
2
0 0 40 80 QG (nC) 120
102 10-1
1
10
VDS (V)
102
Fig 13. Gate-source voltage as a function of gate charge; typical values
Fig 14. Input, output and reverse transfer capacitances as a function of drain-source voltage; typical values
PSMN1R2-25YL_1
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 01 -- 25 June 2009
8 of 13
NXP Semiconductors
PSMN1R2-25YL
N-channel 25 V 1.2 m logic level MOSFET in LFPAK
100 IS (A) 80
003aad133
60
40
Tj = 150 C 25 C
20
0 0 0.2 0.4 0.6 0.8 VSD (V) 1
Fig 15. Source (diode forward) current as a function of source-drain (diode forward) voltage; typical values
PSMN1R2-25YL_1
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 01 -- 25 June 2009
9 of 13
NXP Semiconductors
PSMN1R2-25YL
N-channel 25 V 1.2 m logic level MOSFET in LFPAK
7. Package outline
Plastic single-ended surface-mounted package (LFPAK2); 4 leads SOT1023
E b1
A c1
A
E1 b2 (3x)
mounting base D H
D1
L 1 e 2 3 4 b X w A c
A1
C detail X Lp yC
0 Dimensions Unit mm A A1 b b1 b2 c c1
2.5 scale D(1) D1(1) E(1) E1(1) 3.7 1.27 3.5 e
5 mm
H 6.2 5.9
L 1.3 0.8
Lp 0.85
w 0.25
y 0.1
8 0
sot1023_po
max 1.10 0.15 0.50 4.41 0.25 0.30 4.70 4.45 5.30 0.85 nom min 0.95 0.00 0.35 3.62 0.19 0.24 4.45 4.95
0.40
Note 1. Plastic or metal protrusions of 0.15 mm per side are not included. Outline version SOT1023 References IEC JEDEC JEITA European projection
Issue date 08-10-13 09-05-26
Fig 16. Package outline SOT1023
PSMN1R2-25YL_1 (c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 01 -- 25 June 2009
10 of 13
NXP Semiconductors
PSMN1R2-25YL
N-channel 25 V 1.2 m logic level MOSFET in LFPAK
8. Revision history
Table 7. Revision history Release date 20090625 Data sheet status Product data sheet Change notice Supersedes Document ID PSMN1R2-25YL_1
PSMN1R2-25YL_1
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 01 -- 25 June 2009
11 of 13
NXP Semiconductors
PSMN1R2-25YL
N-channel 25 V 1.2 m logic level MOSFET in LFPAK
9. Legal information
9.1 Data sheet status
Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification.
Document status [1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]
Please consult the most recently issued document before initiating or completing a design. The term 'short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
9.2
Definitions
Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.
Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Quick reference data -- The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control -- This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities.
9.3
Disclaimers
General -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk.
9.4
Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. TrenchMOS -- is a trademark of NXP B.V.
10. Contact information
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com
PSMN1R2-25YL_1
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 01 -- 25 June 2009
12 of 13
NXP Semiconductors
PSMN1R2-25YL
N-channel 25 V 1.2 m logic level MOSFET in LFPAK
11. Contents
1 1.1 1.2 1.3 1.4 2 3 4 5 6 7 8 9 9.1 9.2 9.3 9.4 10 Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . .1 General description . . . . . . . . . . . . . . . . . . . . . .1 Features and benefits . . . . . . . . . . . . . . . . . . . . .1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Quick reference data . . . . . . . . . . . . . . . . . . . . .1 Pinning information . . . . . . . . . . . . . . . . . . . . . . .2 Ordering information . . . . . . . . . . . . . . . . . . . . . .2 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . .3 Thermal characteristics . . . . . . . . . . . . . . . . . . .4 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Package outline . . . . . . . . . . . . . . . . . . . . . . . . .10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . 11 Legal information. . . . . . . . . . . . . . . . . . . . . . . .12 Data sheet status . . . . . . . . . . . . . . . . . . . . . . .12 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Contact information. . . . . . . . . . . . . . . . . . . . . .12
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'.
(c) NXP B.V. 2009.
All rights reserved.
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 25 June 2009 Document identifier: PSMN1R2-25YL_1

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