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| dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 Data Sheet High-Performance, 16-bit Digital Signal Controllers 2009 Microchip Technology Inc. Preliminary DS70591B Note the following details of the code protection feature on Microchip devices: * * * Microchip products meet the specification contained in their particular Microchip Data Sheet. Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable." * * Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, rfPIC and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Octopus, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, PIC32 logo, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. (c) 2009, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company's quality system processes and procedures are for its PIC(R) MCUs and dsPIC(R) DSCs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001:2000 certified. DS70591B-page 2 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 High-Performance, 16-Bit Digital Signal Controllers Operating Range: * Up to 40 MIPS operation (at 3.0-3.6V): - Industrial temperature range (-40C to +85C) - Extended temperature range (-40C to +125C) Digital I/O: * * * * * * Up to 85 programmable digital I/O pins Wake-up/Interrupt-on-Change for up to 24 pins Output pins can drive voltage from 3.0V to 3.6V Up to 5V output with open drain configuration 5V tolerant digital input pins 16 mA source/sink on all PWM pins High-Performance DSC CPU: * * * * * * * * * Modified Harvard architecture C compiler optimized instruction set 16-bit wide data path 24-bit wide instructions Linear program memory addressing up to 4M instruction words Linear data memory addressing up to 64 Kbytes 83 base instructions: mostly 1 word/1 cycle Two 40-bit accumulators with rounding and saturation options Flexible and powerful addressing modes: - Indirect - Modulo - Bit-Reversed Software stack 16 x 16 fractional/integer multiply operations 32/16 and 16/16 divide operations Single-cycle multiply and accumulate: - Accumulator write back for DSP operations - Dual data fetch Up to 16-bit shifts for up to 40-bit data On-Chip Flash and SRAM: * Flash program memory (up to 64 Kbytes) * Data SRAM (up to 8 Kbytes) * Boot and General Security for program Flash Peripheral Features: * Timer/Counters, up to five 16-bit timers - Can pair up to make one 32-bit timer * Input Capture (up to four channels): - Capture on up, down or both edges - 16-bit capture input functions - 4-deep FIFO on each capture * Output Compare (up to four channels): - Single or Dual 16-bit Compare mode - 16-bit Glitchless PWM mode * 4-wire SPI (up to two modules): - Framing supports I/O interface to simple codecs - 1-deep FIFO buffer - Supports 8-bit and 16-bit data - Supports all serial clock formats and sampling modes * I2CTM (up to two modules): - Supports Full Multi-Master Slave mode - 7-bit and 10-bit addressing - Bus collision detection and arbitration - Integrated signal conditioning - Slave address masking * * * * * Direct Memory Access (DMA): * 4-channel hardware DMA * 1 Kbyte dual ported DMA buffer area (DMA RAM) to store data transferred via DMA: - Allows data transfer between RAM and a peripheral while CPU is executing code (no cycle stealing) * Most peripherals support DMA 2009 Microchip Technology Inc. Preliminary DS70591B-page 3 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 Peripheral Features (Continued) * UART (up to two modules): - Interrupt on address bit detect - Interrupt on UART error - Wake-up on Start bit from Sleep mode - 4-character TX and RX FIFO buffers - LIN bus support - IrDA(c) encoding and decoding in hardware - High-Speed Baud mode - Hardware Flow Control with CTS and RTS * Enhanced CAN (ECANTM module) 2.0B active: - Up to eight transmit and up to 32 receive buffers - 16 receive filters and three masks - Loopback, Listen Only and Listen All - Messages modes for diagnostics and bus monitoring - Wake-up on CAN message - Automatic processing of Remote Transmission Requests - FIFO mode using DMA - DeviceNetTM addressing support * Quadrature Encoder Interface (up to 2 modules): - Phase A, Phase B, and index pulse input - 16-bit up/down position counter - Count direction status - Position Measurement (x2 and x4) mode - Programmable digital noise filters on inputs - Alternate 16-bit Timer/Counter mode - Interrupt on position counter rollover/underflow Independent Fault/Current-Limit inputs Output override control Special Event Trigger PWM capture feature Prescaler for input clock Dual Trigger from PWM TO ADC PWMxL, PWMxH output pin swapping On-the-Fly PWM Frequency, Duty cycle and Phase Shift changes * Disabling of Individual PWM generators * Leading-Edge Blanking (LEB) functionality * * * * * * * * High-Speed Analog Comparator: * Up to four Analog Comparators: - 20 ns response time - 10-bit DAC for each analog comparator - DACOUT pin to provide DAC output - Programmable output polarity - Selectable input source - ADC sample and convert capability * PWM module interface: - PWM Duty Cycle Control - PWM Period Control - PWM Fault Detect Interrupt Controller: * * * * 5-cycle latency Up to five external interrupts Seven programmable priority levels Five processor exceptions High-Speed PWM Module Features: * Up to nine PWM generators with up to 18 outputs * Primary and Secondary time-base * Individual time base and duty cycle for each of the PWM output * Dead time for rising and falling edges: - Duty cycle resolution of 1.04 ns - Dead-time resolution of 1.04 ns * Phase shift resolution of 1.04 ns * Frequency resolution of 1.04 ns * PWM modes supported: - Standard Edge-Aligned - True Independent Output - Complementary - Center-Aligned - Push-Pull - Multi-Phase - Variable Phase - Fixed Off-Time - Current Reset - Current-Limit High-Speed 10-bit ADC: * 10-bit resolution * Up to 24 input channels grouped into 12 conversion pairs * Two internal reference monitoring inputs grouped into a pair * Successive Approximation Register (SAR) converters for parallel conversions of analog pairs: - 4 Msps for devices with two SARs - 2 Msps for devices with one SAR * Dedicated result buffer for each analog channel * Independent trigger source section for each analog input conversion pairs Power Management: * On-chip 2.5V voltage regulator * Switch between clock sources in real time * Idle, Sleep, and Doze modes with fast wake-up DS70591B-page 4 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 CMOS Flash Technology: * * * * * Low-power, high-speed Flash technology Fully static design 3.3V (10%) operating voltage Industrial and Extended temperature Low power consumption Application Examples: * * * * * * * * * AC-to-DC Converters Automotive HID Battery Chargers DC-to-DC Converters Digital Lighting Induction Cooking LED Ballast Renewable Power/Pure Sine Wave Inverters Uninterruptible Power Supply (UPS) System Management: * Flexible clock options: - External, crystal, resonator, internal RC - Phase-Locked Loop (PLL) with 120 MHz VCO - Primary Crystal Oscillator (OSC) in the range of 3 MHz to 40 MHz - Secondary oscillator (SOSC) - Internal Low-Power RC (LPRC) oscillator at a frequency of 32.767 kHz - Internal Fast RC (FRC) oscillator at a frequency of 7.37 MHz * Power-on Reset (POR) * Brown-out Reset (BOR) * Power-up Timer (PWRT) * Oscillator Start-up Timer (OST) * Watchdog Timer with its RC oscillator * Fail-Safe Clock Monitor * Reset by multiple sources * In-Circuit Serial ProgrammingTM (ICSPTM) * Reference Oscillator Output Packaging: * * * * 64-pin QFN (9x9x0.9 mm) 64-pin TQFP (10x10x1 mm) 80-pin TQFP (12x12x1 mm) 100-pin TQFP (14x14x1 mm and 12x12x1 mm) Note: See the dsPIC33FJ32GS406/606/608/ 610 and DSPIC33FJ64GS406/606/608/ 610 Controller Families table for exact peripheral features per device. 2009 Microchip Technology Inc. Preliminary DS70591B-page 5 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 PRODUCT FAMILIES The device names, pin counts, memory sizes, and peripheral availability of each device are listed in Table 1. The following pages show their pinout diagrams. TABLE 1: dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 CONTROLLER FAMILIES Program Flash Memory (Kbytes) Quadrature Encoder Interface ADC Sample and Hold (S&H) Circuit Analog Comparator Analog-to-Digital Inputs External Interrupts Output Compare DMA Channels Input Capture RAM (Bytes) DAC Output 16-bit Timer dsPIC33FJ32GS406 64 dsPIC33FJ32GS606 64 dsPIC33FJ32GS608 80 dsPIC33FJ32GS610 100 DSPIC33FJ64GS406 64 dsPIC33FJ64GS606 64 dsPIC33FJ64GS608 80 dsPIC33FJ64GS610 100 Note 1: 32 32 32 32 64 4K 4K 4K 4K 8K 5 5 5 5 5 5 5 5 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 2 2 2 2 2 2 2 2 1 2 2 2 1 2 2 2 2 2 2 2 2 2 2 2 0 0 0 0 0 1 1 1 0 0 0 0 0 4 4 4 6x2 6x2 8x2 9x2 6x2 6x2 8x2 9x2 0 4 4 4 0 4 4 4 5 5 5 5 5 5 5 5 0 1 1 1 0 1 1 1 2 2 2 2 2 2 2 2 SARs Device 1 2 2 2 1 2 2 2 5 6 6 6 5 6 6 6 16 16 18 24 16 16 18 24 58 58 74 85 58 58 74 85 PT, MR PT, MR PT PT, PF PT, MR PT, MR PT PT, PF 64 9K(1) 64 9K(1) 64 9K(1) RAM size is inclusive of 1 Kbyte DMA RAM. DS70591B-page 6 Preliminary 2009 Microchip Technology Inc. Packages ECANTM I/O Pins UART PWM I2CTM Pins SPI dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 Pin Diagrams 64-Pin TQFP PWM3L/RE4 PWM2H/RE3 PWM2L/RE2 PWM1H1/RE1 PWM1L1/FLT8/RE0 RF1 SYNCI4/RF0 VDD VCAP/VDDCORE PWM5H/UPDN1/CN16/RD7 PWM5L/CN15/RD6 PWM6H/CN14/RD5 PWM6L/CN13/RD4 OC4/SYNCO1/RD3 OC3/FLT7/SYNCI3/RD2 OC2/SYNCO2/FLT6/RD1 = Pins are up to 5V tolerant 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 PWM3H/RE5 PWM4L/RE6 PWM4H/RE7 SCK2/FLT12/CN8/RG6 SDI2/FLT11/CN9/RG7 SDO2/FLT10/CN10/RG8 MCLR SS2/FLT9/SYNCI2/T5CK/CN11/RG9 VSS VDD AN5/AQEB1/CN7/RB5 AN4/AQEA1/CN6/RB4 AN3/AINDX1/CN5/RB3 AN2/ASS1/CN4/RB2 PGEC3/B/AN1/CN3/RB1 PGED3/AN0/CN2/RB0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 dsPIC33FJ32GS406 DSPIC33FJ64GS406 PGEC2/SOSCO/T1CK/CN0/RC14 PGED2/SOSCI/T4CK/CN1/RC13 OC1/QEB1/FLT5/RD0 IC4/QEA1/FLT4/INT4/RD11 IC3/INDX1/FLT3/INT3/RD10 IC2/FLT2/U1CTS/INT2/RD9 IC1/FLT1/SYNCI1/INT1/RD8 VSS OSC2/REFCLKO/CLKO/RC15 OSC1/CLKIN/RC12 VDD SCL1/RG2 SDA1/RG3 U1RTS/SCK1/INT0/RF6 U1RX/SDI1/RF2 U1TX/SDO1/RF3 2009 Microchip Technology Inc. PGEC1/AN6/OCFA/RB6 PGED1/AN7/RB7 AVDD AVSS AN8/U2CTS/RB8 AN9/RB9 TMS/AN10/RB10 TDO/AN11/RB11 VSS VDD TCK/AN12/RB12 TDI/AN13/RB13 AN14/SS1/U2RTS/RB14 AN15/OCFB/CN12/RB15 U2RX/SDA2/FLT17/CN17/RF4 U2TX/SCL2/FLT18/CN18/RF5 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Preliminary DS70591B-page 7 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 Pin Diagrams (Continued) 64-Pin QFN PWM3L/RE4 PWM2H/RE3 PWM2L/RE2 PWM1H1/RE1 PWM1L1/FLT8/RE0 RF1 SYNCI4/RF0 VDD VCAP/VDDCORE PWM5H/UPDN1/CN16/RD7 PWM5L/CN15/RD6 PWM6H/CN14/RD5 PWM6L/CN13/RD4 OC4/SYNCO1/RD3 OC3/FLT7/SYNCI3/RD2 OC2/SYNCO2/FLT6/RD1 = Pins are up to 5V tolerant 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 PWM3H/RE5 PWM4L/RE6 PWM4H/RE7 SCK2/FLT12/CN8/RG6 SDI2/FLT11/CN9/RG7 SDO2/FLT10/CN10/RG8 MCLR SS2/FLT9/SYNCI2/T5CK/CN11/RG9 VSS VDD AN5/AQEB1/CN7/RB5 AN4/AQEA1/CN6/RB4 AN3/AINDX1/CN5/RB3 AN2/ASS1/CN4/RB2 PGEC3/B/AN1/CN3/RB1 PGED3/AN0/CN2/RB0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 dsPIC33FJ32GS406 DSPIC33FJ64GS406 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 PGEC2/SOSCO/T1CK/CN0/RC14 PGED2/SOSCI/T4CK/CN1/RC13 OC1/QEB1/FLT5/RD0 IC4/QEA1/FLT4/INT4/RD11 IC3/INDX1/FLT3/INT3/RD10 IC2/FLT2/U1CTS/INT2/RD9 IC1/FLT1/SYNCI1/INT1/RD8 VSS OSC2/REFCLKO/CLKO/RC15 OSC1/CLKIN/RC12 VDD SCL1/RG2 SDA1/RG3 U1RTS/SCK1/INT0/RF6 U1RX/SDI1/RF2 U1TX/SDO1/RF3 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 PGEC1/AN6/OCFA/RB6 PGED1/AN7/RB7 AVDD AVss AN8/U2CTS/RB8 AN9/RB9 TMS/AN10/RB10 TDO/AN11/RB11 VSS VDD TCK/AN12/RB12 TDI/AN13/RB13 AN14/SS1/U2RTS/RB14 AN15/OCFB/CN12/RB15 U2RX/SDA2/FLT17/CN17/RF4 U2TX/SCL2/FLT18/CN18/RF5 Note: The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally. DS70591B-page 8 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 Pin Diagrams (Continued) 64-Pin TQFP = Pins are up to 5V tolerant 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 PWM3L/RE4 PWM2H/RE3 PWM2L/RE2 PWM1H1/RE1 PWM1L1/FLT8/RE0 RF1 SYNCI4/RF0 VDD VCAP/VDDCORE PWM5H/UPDN1/CN16/RD7 PWM5L/CN15/RD6 PWM6H/CN14/RD5 PWM6L/CN13/RD4 OC4/SYNCO1/RD3 OC3/FLT7/SYNCI3/RD2 OC2/SYNCO2/FLT6/RD1 PWM3H/RE5 PWM4L/RE6 PWM4H/RE7 SCK2/FLT12/CN8/RG6 SDI2/FLT11/CN9/RG7 SDO2/FLT10/CN10/RG8 MCLR SS2/FLT9/SYNCI2/T5CK/CN11/RG9 VSS VDD AN5/CMP3B/AQEB1/CN7/RB5 AN4/CMP2C/CMP3A/AQEA1/CN6/RB4 AN3/CMP2B/AINDX1/CN5/RB3 AN2/CMP1C/CMP2A/ASS1/CN4/RB2 PGEC3/B/AN1/CMP1B/CN3/RB1 PGED3/AN0/CMP1A/CMP4C/CN2/RB0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 dsPIC33FJ32GS606 PGEC2/SOSCO/T1CK/CN0/RC14 PGED2/SOSCI/T4CK/CN1/RC13 OC1/QEB1/FLT5/RD0 IC4/QEA1/FLT4/INT4/RD11 IC3/INDX1/FLT3/INT3/RD10 IC2/FLT2/U1CTS/INT2/RD9 IC1/FLT1/SYNCI1/INT1/RD8 VSS OSC2/REFCLKO/CLKO/RC15 OSC1/CLKIN/RC12 VDD SCL1/RG2 SDA1/RG3 U1RTS/SCK1/INT0/RF6 U1RX/SDI1/RF2 U1TX/SDO1/RF3 2009 Microchip Technology Inc. PGEC1/AN6/CMP3C/CMP4A/OCFA/RB6 PGED1/AN7/CMP4B/RB7 AVdd AVSS AN8/U2CTS/RB8 AN9/DACOUT/RB9 TMS/AN10/RB10 TDO/AN11/EXTREF/RB11 VSS VDD TCK/AN12/CMP1D/RB12 TDI/AN13/CMP2D/RB13 AN14/CMP3D/SS1/U2RTS/RB14 AN15/CMP4D/OCFB/CN12/RB15 U2RX/SDA2/FLT17/CN17/RF4 U2TX/SCL2/FLT18/CN18/RF5 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Preliminary DS70591B-page 9 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 Pin Diagrams (Continued) 64-Pin TQFP PWM3L/RE4 PWM2H/RE3 PWM2L/RE2 PWM1H1/RE1 PWM1L1/FLT8/RE0 C1TX/RF1 C1RX/SYNCI4/RF0 VDD VCAP/VDDCORE PWM5H/UPDN1/CN16/RD7 PWM5L/CN15/RD6 PWM6H/CN14/RD5 PWM6L/CN13/RD4 OC4/SYNCO1/RD3 OC3/FLT7/SYNCI3/RD2 OC2/SYNCO2/FLT6/RD1 = Pins are up to 5V tolerant 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 PWM3H/RE5 PWM4L/RE6 PWM4H/RE7 SCK2/FLT12/CN8/RG6 SDI2/FLT11/CN9/RG7 SDO2/FLT10/CN10/RG8 MCLR SS2/FLT9/SYNCI2/T5CK/CN11/RG9 VSS VDD AN5/CMP3B/AQEB1/CN7/RB5 AN4/CMP2C/CMP3A/AQEA1/CN6/RB4 AN3/CMP2B/AINDX1/CN5/RB3 AN2/CMP1C/CMP2A/ASS1/CN4/RB2 PGEC3/B/AN1/CMP1B/CN3/RB1 PGED3/AN0/CMP1A/CMP4C/CN2/RB0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 dsPIC33FJ64GS606 PGEC2/SOSCO/T1CK/CN0/RC14 PGED2/SOSCI/T4CK/CN1/RC13 OC1/QEB1/FLT5/RD0 IC4/QEA1/FLT4/INT4/RD11 IC3/INDX1/FLT3/INT3/RD10 IC2/FLT2/U1CTS/INT2/RD9 IC1/FLT1/SYNCI1/INT1/RD8 VSS OSC2/REFCLKO/CLKO/RC15 OSC1/CLKIN/RC12 VDD SCL1/RG2 SDA1/RG3 U1RTS/SCK1/INT0/RF6 U1RX/SDI1/RF2 U1TX/SDO1/RF3 PGEC1/AN6/CMP3C/CMP4A/OCFA/RB6 PGED1/AN7/CMP4B/RB7 AVdd AVSS AN8/U2CTS/RB8 AN9/DACOUT/RB9 TMS/AN10/RB10 TDO/AN11/EXTREF/RB11 VSS VDD TCK/AN12/CMP1D/RB12 TDI/AN13/CMP2D/RB13 AN14/CMP3D/SS1/U2RTS/RB14 AN15/CMP4D/OCFB/CN12/RB15 U2RX/SDA2/FLT17/CN17/RF4 U2TX/SCL2/FLT18/CN18/RF5 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 DS70591B-page 10 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 Pin Diagrams (Continued) 64-Pin QFN = Pins are up to 5V tolerant PWM3L/RE4 PWM2H/RE3 PWM2L/RE2 PWM1H1/RE1 PWM1L1/FLT8/RE0 RF1 SYNCI4/RF0 VDD VCAP/VDDCORE PWM5H/UPDN1/CN16/RD7 PWM5L/CN15/RD6 PWM6H/CN14/RD5 PWM6L/CN13/RD4 OC4/SYNCO1/RD3 OC3/FLT7/SYNCI3/RD2 OC2/SYNCO2/FLT6/RD1 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 PWM3H/RE5 PWM4L/RE6 PWM4H/RE7 SCK2/FLT12/CN8/RG6 SDI2/FLT11/CN9/RG7 SDO2/FLT10/CN10/RG8 MCLR SS2/FLT9/SYNCI2/T5CK/CN11/RG9 VSS VDD AN5/CMP3B/AQEB1/CN7/RB5 AN4/CMP2C/CMP3A/AQEA1/CN6/RB4 AN3/CMP2B/AINDX1/CN5/RB3 AN2/CMP1C/CMP2A/ASS1/CN4/RB2 PGEC3/B/AN1/CMP1B/CN3/RB1 PGED3/AN0/CMP1A/CMP4C/CN2/RB0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 dsPIC33FJ32GS606 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 PGEC2/SOSCO/T1CK/CN0/RC14 PGED2/SOSCI/T4CK/CN1/RC13 OC1/QEB1/FLT5/RD0 IC4/QEA1/FLT4/INT4/RD11 IC3/INDX1/FLT3/INT3/RD10 IC2/FLT2/U1CTS/INT2/RD9 IC1/FLT1/SYNCI1/INT1/RD8 VSS OSC2/REFCLKO/CLKO/RC15 OSC1/CLKIN/RC12 VDD SCL1/RG2 SDA1/RG3 U1RTS/SCK1/INT0/RF6 U1RX/SDI1/RF2 U1TX/SDO1/RF3 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 PGEC1/AN6/CMP3C/CMP4A/OCFA/RB6 PGED1/AN7/CMP4B/RB7 AVDD AVSS AN8/U2CTS/RB8 AN9/DACOUT/RB9 TMS/AN10/RB10 TDO/AN11/EXTREF/RB11 VSS VDD TCK/AN12/CMP1D/RB12 TDI/AN13/CMP2D/RB13 AN14/CMP3D/SS1/U2RTS/RB14 AN15/CMP4D/OCFB/CN12/RB15 U2RX/SDA2/FLT17/CN17/RF4 U2TX/SCL2FLT18//CN18/RF5 Note: The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally. 2009 Microchip Technology Inc. Preliminary DS70591B-page 11 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 Pin Diagrams (Continued) 64-Pin QFN PWM3L/RE4 PWM2H/RE3 PWM2L/RE2 PWM1H1/RE1 PWM1L1/FLT8/RE0 C1TX/RF1 C1RX/SYNCI4/RF0 VDD VCAP/VDDCORE PWM5H/UPDN1/CN16/RD7 PWM5L/CN15/RD6 PWM6H/CN14/RD5 PWM6L/CN13/RD4 OC4/SYNCO1/RD3 OC3/FLT7/SYNCI3/RD2 OC2/SYNCO2/FLT6/RD1 = Pins are up to 5V tolerant 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 PWM3H/RE5 PWM4L/RE6 PWM4H/RE7 SCK2/FLT12/CN8/RG6 SDI2/FLT11/CN9/RG7 SDO2/FLT10/CN10/RG8 MCLR SS2/FLT9/SYNCI2/T5CK/CN11/RG9 VSS VDD AN5/CMP3B/AQEB1/CN7/RB5 AN4/CMP2C/CMP3A/AQEA1/CN6/RB4 AN3/CMP2B/AINDX1/CN5/RB3 AN2/CMP1C/CMP2A/ASS1/CN4/RB2 PGEC3/B/AN1/CMP1B/CN3/RB1 PGED3/AN0/CMP1A/CMP4C/CN2/RB0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 PGEC2/SOSCO/T1CK/CN0/RC14 PGED2/SOSCI/T4CK/CN1/RC13 OC1/QEB1/FLT5/RD0 IC4/QEA1/FLT4/INT4/RD11 IC3/INDX1/FLT3/INT3/RD10 IC2/FLT2/U1CTS/INT2/RD9 IC1/FLT1/SYNCI1/INT1/RD8 VSS OSC2/REFCLKO/CLKO/RC15 OSC1/CLKIN/RC12 VDD SCL1/RG2 SDA1/RG3 U1RTS/SCK1/INT0/RF6 U1RX/SDI1/RF2 U1TX/SDO1/RF3 dsPIC33FJ64GS606 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 PGEC1/AN6/CMP3C/CMP4A/OCFA/RB6 PGED1/AN7/CMP4B/RB7 AVDD AVSS AN8/U2CTS/RB8 AN9/DACOUT/RB9 TMS/AN10/RB10 TDO/AN11/EXTREF/RB11 VSS VDD TCK/AN12/CMP1D/RB12 TDI/AN13/CMP2D/RB13 AN14/CMP3D/SS1/U2RTS/RB14 AN15/CMP4D/OCFB/CN12/RB15 U2RX/SDA2/FLT17/CN17/RF4 U2TX/SCL2/FLT18/CN18/RF5 Note: The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally. DS70591B-page 12 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 Pin Diagrams (Continued) 80-Pin TQFP QEA2/RD12 PWM7H/OC4/SYNCO1/RD3 OC3/FLT7/RD2 OC2/SYNCO2/FLT6/RD1 64 63 62 61 PWM5H/UPDN1/CN16/RD7 = Pins are up to 5V tolerant INDX2SYNCI4//RG0 PWM1L1/FLT8/RE0 PWM3L/RE4 PWM2L/RE2 PWM1H1/RE1 PWM2H/RE3 80 79 78 77 76 75 74 73 72 71 70 RF1 RF0 VDD VCAP/VDDCORE QEB2/RG1 69 68 67 66 65 PWM6H/CN14/RD5 PWM6L/CN13/RD4 PWM7L/CN19/RD13 PWM5L/CN15/RD6 PWM3H/RE5 PWM4L/RE6 PWM4H/RE7 AN16/T2CK/RC1 AN17/T3CK/RC2 SCK2/FLT12/CN8/RG6 SDI2/FLT11/CN9/RG7 SDO2/FLT10/CN10/RG8 MCLR SS2/FLT9/T5CK/CN11/RG9 VSS VDD TMS/FLT13/INT1/RE8 TDO/FLT14/INT2/RE9 AN5/CMP3B/AQEB1/CN7/RB5 AN4/CMP2C/CMP3A/AQEA1/CN6/RB4 AN3/CMP2B/AINDX1/CN5/RB3 AN2/CMP1C/CMP2A/ASS1/CN4/RB2 PGEC3/AN1/CMP1B/CN3/RB1 PGED3/AN0/CMP1A/CMP4C/CN2/RB0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 PGEC2/SOSCO/T1CK/CN0/RC14 PGED2/SOSCI/T4CK/CN1/RC13 OC1/QEB1/FLT5/RD0 IC4/QEA1/FLT4/RD11 IC3/INDX1/FLT3/RD10 IC2/FLT2/RD9 IC1/FLT1/SYNCI1/RD8 SDA2/INT4/FLT19/RA15 SCL2/INT3/FLT20/RA14 VSS OSC2/REFCLKO/CLKO/RC15 OSC1/CLKIN/RC12 VDD SCL1/RG2 SDA1/RG3 SCK1/INT0/RF6 SDI1/RF7 SDO1/RF8 U1RX/RF2 U1TX/RF3 dsPIC33FJ32GS608 23 24 25 26 27 28 29 30 31 32 21 22 33 34 35 36 37 38 U1RTS/FLT16/SYNCI2/CN21/RD15 39 U2RX/FLT17/CN17/RF4 AVDD PGEC1/AN6CMP3C/CMP4A//OCFA/RB6 PWM8L/RA9 AN8/U2CTS/RB8 VDD AN14/CMP3D/SS1/U2RTS/RB14 AVSS PGED1/AN7/CMP4B/RB7 PWM8H/RA10 VSS TCK/AN12/CMP1D/RB12 TDI/AN13/CMP2D/RB13 2009 Microchip Technology Inc. Preliminary AN15/CMP4D/OCFB/CN12/RB15 U1CTS/FLT15/SYNCI3/CN20/RD14 U2TX/FLT18/CN18/RF5 AN9/DACOUT/RB9 AN10/RB10 AN11/EXTREF/RB11 40 DS70591B-page 13 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 Pin Diagrams (Continued) 80-Pin TQFP = Pins are up to 5V tolerant INDX2SYNCI4//RG0 PWM1L1/FLT8/RE0 PWM3L/RE4 PWM2L/RE2 PWM1H1/RE1 PWM2H/RE3 80 79 78 77 76 75 74 73 72 71 70 C1TX/RF1 C1RX/RF0 VDD VCAP/VDDCORE QEB2/RG1 69 68 67 66 65 PWM6H/CN14/RD5 PWM6L/CN13/RD4 PWM7L/CN19/RD13 64 63 62 61 QEA2/RD12 PWM7H/OC4/SYNCO1/RD3 OC3/FLT7/RD2 OC2/SYNCO2/FLT6/RD1 PWM5H/UPDN1/CN16/RD7 PWM5L/CN15/RD6 PWM3H/RE5 PWM4L/RE6 PWM4H/RE7 AN16/T2CK/RC1 AN17/T3CK/RC2 SCK2/FLT12/CN8/RG6 SDI2/FLT11/CN9/RG7 SDO2/FLT10/CN10/RG8 MCLR SS2/FLT9/T5CK/CN11/RG9 VSS VDD TMS/FLT13/INT1/RE8 TDO/FLT14/INT2/RE9 AN5/CMP3B/AQEB1/CN7/RB5 AN4/CMP2C/CMP3A/AQEA1/CN6/RB4 AN3/CMP2B/AINDX1/CN5/RB3 AN2/CMP1C/CMP2A/ASS1/CN4/RB2 PGEC3/AN1/CMP1B/CN3/RB1 PGED3/AN0/CMP1A/CMP4C/CN2/RB0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 60 59 58 57 56 55 54 53 52 PGEC2/SOSCO/T1CK/CN0/RC14 PGED2/SOSCI/T4CK/CN1/RC13 OC1/QEB1/FLT5/RD0 IC4/QEA1/FLT4/RD11 IC3/INDX1/FLT3/RD10 IC2/FLT2/RD9 IC1/FLT1/SYNCI1/RD8 SDA2/INT4/FLT19/RA15 SCL2/INT3/FLT20/RA14 VSS OSC2/REFCLKO/CLKO/RC15 OSC1/CLKIN/RC12 VDD SCL1/RG2 SDA1/RG3 SCK1/INT0/RF6 SDI1/RF7 SDO1/RF8 U1RX/RF2 U1TX/RF3 dsPIC33FJ64GS608 51 50 49 48 47 46 45 44 43 42 41 23 24 25 26 27 28 29 30 31 32 21 22 33 34 35 36 37 38 U1RTS/FLT16/SYNCI2/CN21/RD15 39 U2RX/FLT17/CN17/RF4 AVSS AVDD VSS PWM8H/RA10 VDD PGEC1/AN6CMP3C/CMP4A//OCFA/RB6 AN14/CMP3D/SS1/U2RTS/RB14 TCK/AN12/CMP1D/RB12 TDI/AN13/CMP2D/RB13 DS70591B-page 14 Preliminary AN15/CMP4D/OCFB/CN12/RB15 U1CTS/FLT15/SYNCI3/CN20/RD14 PGED1/AN7/CMP4B/RB7 U2TX/FLT18/CN18/RF5 AN8/U2CTS/RB8 AN11/EXTREF/RB11 AN9/DACOUT/RB9 PWM8L/RA9 AN10/RB10 40 2009 Microchip Technology Inc. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 Pin Diagrams (Continued) 100-Pin TQFP PWM3L/RE4 PWM2H/RE3 PWM2L/RE2 PWM9L/RG13 PWM9H/RG12 SYNCO1/FLT23/RG14 PWM1H/RE1 PW/M1L/FLT8/RE0 AN23/CN23/RA7 AN22/CN22/RA6 INDX2/RG0 QEB2/RG1 RF1 RF0 VDD VCAP/VDDCORE PWM5H/UPDN1/CN16/RD7 PWM5L/CN15/RD6 PWM6H/CN14/RD5 PWM6L/CN13/RD4 PWM7L/CN19/RD13 QEA2/RD12 PWM7H/OC4/RD3 OC3/FLT7/RD2 OC2/SYNCO2/FLT6/RD1 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 = Pins are up to 5V tolerant SYNCI1/RG15 VDD PWM3H/RE5 PWM4L/RE6 PWM4H/RE7 AN16/T2CK/RC1 AN17/T3CK/RC2 AN18/T4CK/RC3 AN19/T5CK/RC4 SCK2/FLT12/CN8/RG6 SDI2/FLT11/CN9/RG7 SDO2/FLT10/CN10/RG8 MCLR SS2/FLT9/CN11/RG9 VSS VDD TMS/RA0 AN20/FLT13/INT1/RE8 AN21/FLT14/INT2/RE9 AN5/CMP3B/AQEB1/CN7/RB5 AN4/CMP2C/CMP3A/AQEA1/CN6/RB4 AN3/CMP2B/AINDX1/CN5/RB3 AN2/CMP1C/CMP2A/ASS1/CN4/RB2 PGEC3/AN1/CMP1B/CN3/RB1 PGED3/AN0/CMP1A/CMP4C/CN2/RB0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 dsPIC33FJ32GS610 Vss PGEC2/SOSCO/T1CK/CN0/RC14 PGED2/SOSCI/CN1/RC13 OC1/QEB1/FLT5/RD0 IC4/QEA1/FLT4/RD11 IC3/INDX1/FLT3/RD10 IC2/FLT2/RD9 IC1/FLT1/RD8 INT4/FLT19/SYNCI4/RA15 INT3/FLT20/RA14 VSS OSC2/REFCLKO/CLKO/RC15 OSC1/CLKIN/RC12 VDD TDO/RA5 TDI/RA4 SDA2/FLT21/RA3 SCL2/FLT22/RA2 SCL1/RG2 SDA1/RG3 SCK1/INT0/RF6 SDI1/RF7 SDO1/RF8 U1RX/RF2 U1TX/RF3 2009 Microchip Technology Inc. PGEC1/AN6/CMP3C/CMP4A//OCFA/RB6 PGED1/AN7/CMP4B/RB7 PWM8L/RA9 PWM8H/RA10 AVDD AVSS AN8/RB8 AN9/DACOUT/RB9 AN10/RB10 AN11/EXTREF/RB11 VSS VDD TCK/RA1 U2RTS/RF13 U2CTS/RF12 AN12/CMP1D/RB12 AN13/CMP2D/RB13 AN14/CMP3D/SS1/RB14 AN15/CMP4D/OCFB/CN12/RB15 VSS VDD U1CTS/FLT15/SYNCI3/CN20/RD14 U1RTS/FLT16/SYNCI2/CN21/RD15 U2RX/FLT17/CN17/RF4 U2TX/FLT18/CN18/RF5 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Preliminary DS70591B-page 15 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 Pin Diagrams (Continued) 100-Pin TQFP = Pins are up to 5V tolerant PWM3L/RE4 PWM2H/RE3 PWM2L/RE2 PWM9L/RG13 PWM9H/RG12 SYNCO1/FLT23/RG14 PWM1H/RE1 PW/M1L/FLT8/RE0 AN23/CN23/RA7 AN22/CN22/RA6 INDX2/RG0 QEB2/RG1 C1TX/RF1 C1RX/RF0 VDD VCAP/VDDCORE PWM5H/UPDN1/CN16/RD7 PWM5L/CN15/RD6 PWM6H/CN14/RD5 PWM6L/CN13/RD4 PWM7L/CN19/RD13 QEA2/RD12 PWM7H/OC4/RD3 OC3/FLT7/RD2 OC2/SYNCO2/FLT6/RD1 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 SYNCI1/RG15 VDD PWM3H/RE5 PWM4L/RE6 PWM4H/RE7 AN16/T2CK/RC1 AN17/T3CK/RC2 AN18/T4CK/RC3 AN19/T5CK/RC4 SCK2/FLT12/CN8/RG6 SDI2/FLT11/CN9/RG7 SDO2/FLT10/CN10/RG8 MCLR SS2/FLT9/CN11/RG9 VSS VDD TMS/RA0 AN20/FLT13/INT1/RE8 AN21/FLT14/INT2/RE9 AN5/CMP3B/AQEB1/CN7/RB5 AN4/CMP2C/CMP3A/AQEA1/CN6/RB4 AN3/CMP2B/AINDX1/CN5/RB3 AN2/CMP1C/CMP2A/ASS1/CN4/RB2 PGEC3/AN1/CMP1B/CN3/RB1 PGED3/AN0/CMP1A/CMP4C/CN2/RB0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 Vss PGEC2/SOSCO/T1CK/CN0/RC14 PGED2/SOSCI/CN1/RC13 OC1/QEB1/FLT5/RD0 IC4/QEA1/FLT4/RD11 IC3/INDX1/FLT3/RD10 IC2/FLT2/RD9 IC1/FLT1/RD8 INT4/FLT19/SYNCI4/RA15 INT3/FLT20/RA14 VSS OSC2/REFCLKO/CLKO/RC15 OSC1/CLKIN/RC12 VDD TDO/RA5 TDI/RA4 SDA2/FLT21/RA3 SCL2/FLT22/RA2 SCL1/RG2 SDA1/RG3 SCK1/INT0/RF6 SDI1/RF7 SDO1/RF8 U1RX/RF2 U1TX/RF3 dsPIC33FJ64GS610 DS70591B-page 16 PGEC1/AN6/CMP3C/CMP4A//OCFA/RB6 PGED1/AN7/CMP4B/RB7 PWM8L/RA9 PWM8H/RA10 AVDD AVSS AN8/RB8 AN9/DACOUT/RB9 AN10/RB10 AN11/EXTREF/RB11 VSS VDD TCK/RA1 U2RTS/RF13 U2CTS/RF12 AN12/CMP1D/RB12 AN13/CMP2D/RB13 AN14/CMP3D/SS1/RB14 AN15/CMP4D/OCFB/CN12/RB15 VSS VDD U1CTS/FLT15/SYNCI3/CN20/RD14 U1RTS/FLT16/SYNCI2/CN21/RD15 U2RX/FLT17/CN17/RF4 U2TX/FLT18/CN18/RF5 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 Table of Contents dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 Product Families ............................................................... 6 1.0 Device Overview ........................................................................................................................................................................ 19 2.0 Guidelines for Getting Started with 16-bit Digital Signal Controllers .......................................................................................... 25 3.0 CPU............................................................................................................................................................................................ 35 4.0 Memory Organization ................................................................................................................................................................. 47 5.0 Flash Program Memory............................................................................................................................................................ 109 6.0 Resets ..................................................................................................................................................................................... 115 7.0 Interrupt Controller ................................................................................................................................................................... 123 8.0 Direct Memory Access (DMA) .................................................................................................................................................. 177 9.0 Oscillator Configuration ......................................................................................................................................................... 187 10.0 Power-Saving Features............................................................................................................................................................ 199 11.0 I/O Ports .................................................................................................................................................................................. 209 12.0 Timer1 ...................................................................................................................................................................................... 211 13.0 Timer2/3/4/5 features .............................................................................................................................................................. 213 14.0 Input Capture............................................................................................................................................................................ 219 15.0 Output Compare....................................................................................................................................................................... 221 16.0 High-Speed PWM..................................................................................................................................................................... 225 17.0 Quadrature Encoder Interface (QEI) Module ........................................................................................................................... 255 18.0 Serial Peripheral Interface (SPI)............................................................................................................................................... 259 19.0 Inter-Integrated Circuit (I2CTM) ................................................................................................................................................. 265 20.0 Universal Asynchronous Receiver Transmitter (UART) ........................................................................................................... 273 21.0 Enhanced CAN (ECANTM) Module........................................................................................................................................... 279 22.0 High-Speed 10-bit Analog-to-Digital Converter (ADC) ............................................................................................................. 305 23.0 High-Speed Analog Comparator .............................................................................................................................................. 329 24.0 Special Features ...................................................................................................................................................................... 333 25.0 Instruction Set Summary .......................................................................................................................................................... 341 26.0 Development Support............................................................................................................................................................... 349 27.0 Electrical Characteristics .......................................................................................................................................................... 353 28.0 Packaging Information.............................................................................................................................................................. 389 Appendix A: Migrating from dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 to dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 Device............................................................................403 Appendix B: Revision History............................................................................................................................................................. 404 Index ................................................................................................................................................................................................. 407 The Microchip Web Site ..................................................................................................................................................................... 413 Customer Change Notification Service .............................................................................................................................................. 413 Customer Support .............................................................................................................................................................................. 413 Reader Response .............................................................................................................................................................................. 414 Product Identification System ............................................................................................................................................................ 415 2009 Microchip Technology Inc. Preliminary DS70591B-page 17 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: * Microchip's Worldwide Web site; http://www.microchip.com * Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. DS70591B-page 18 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 1.0 Note: DEVICE OVERVIEW This data sheet summarizes the features of the dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the "dsPIC33F/PIC24H Family Reference Manual". Please see the Microchip web site (www.microchip.com) for the latest dsPIC33F/PIC24H Family Reference Manual sections. This document contains device-specific information for the following dsPIC33F Digital Signal Controller (DSC) devices: * * * * * * * * dsPIC33FJ32GS406 dsPIC33FJ32GS606 dsPIC33FJ32GS608 dsPIC33FJ32GS610 DSPIC33FJ64GS406 dsPIC33FJ64GS606 dsPIC33FJ64GS608 dsPIC33FJ64GS610 The dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 families of devices contain extensive Digital Signal Processor (DSP) functionality with a high-performance 16-bit microcontroller (MCU) architecture. Figure 1-1 shows a general block diagram of the core and peripheral modules in the dsPIC33FJ32GS406/ 606/608/610 and DSPIC33FJ64GS406/606/608/610 devices. Table 1-1 lists the functions of the various pins shown in the pinout diagrams. 2009 Microchip Technology Inc. Preliminary DS70591B-page 19 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 FIGURE 1-1: PSV & Table Data Access Control Block Interrupt Controller 8 23 23 PCU PCH PCL Program Counter Loop Stack Control Control Logic Logic X RAM Address Latch Y RAM Address Latch DMA Controller 16 BLOCK DIAGRAM Y Data Bus X Data Bus 16 Data Latch DMA RAM PORTA 16 16 16 Data Latch 16 PORTB 23 16 16 16 PORTC Address Latch Address Generator Units Program Memory EA MUX Data Latch 24 ROM Latch 16 Literal Data PORTD 16 Instruction Decode & Control Control Signals to Various Blocks OSC2/CLKO OSC1/CLKI Timing Generation FRC/LPRC Oscillators Precision Band Gap Reference Voltage Regulator Power-up Timer Oscillator Start-up Timer Power-on Reset Watchdog Timer Brown-out Reset Instruction Reg 16 PORTE DSP Engine 16 x 16 W Register Array 16 PORTF Divide Support 16-bit ALU 16 PORTG VCAP/VDDCORE VDD, VSS MCLR Timers 1-5 UART1,2 ECAN1 ADC1 OC1-4 PWM 9x2 Analog Comparator 1-4 IC1-4 QEI1,2 CNx I2C1,2 SPI1,2 Note: Not all pins or features are implemented on all device pinout configurations. See pinout diagrams for the specific pins and features present on each device. DS70591B-page 20 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 TABLE 1-1: Pin Name AN0-AN23 CLKI CLKO PINOUT I/O DESCRIPTIONS Pin Type I I O Buffer Type Analog Analog input channels Description ST/CMOS External clock source input. Always associated with OSC1 pin function. -- Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. Optionally functions as CLKO in RC and EC modes. Always associated with OSC2 pin function. ST/CMOS Oscillator crystal input. ST buffer when configured in RC mode; CMOS otherwise. -- Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. Optionally functions as CLKO in RC and EC modes. ST/CMOS 32.768 kHz low-power oscillator crystal input; CMOS otherwise. -- 32.768 kHz low-power oscillator crystal output. ST ST -- ST ST ST ST CMOS ST ST -- ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST Change notification inputs. Can be software programmed for internal weak pull-ups on all inputs. ECAN1 bus receive pin. ECAN1 bus transmit pin. Capture inputs 1/4 Quadrature Encoder Index Pulse input. Quadrature Encoder Phase A input in QEI mode. Auxiliary Timer External Clock/Gate input in Timer mode. Quadrature Encoder Phase A input in QEI mode. Auxiliary Timer External Clock/Gate input in Timer mode. Position Up/Down Counter Direction State. Compare Fault A input (for Compare Channels 1 and 2) Compare Fault B input (for Compare Channels 3 and 4) Compare Outputs 1 through 4 External Interrupt 0 External Interrupt 1 External Interrupt 2 External Interrupt 3 External Interrupt 4 PORTA is a bidirectional I/O port PORTB is a bidirectional I/O port PORTC is a bidirectional I/O port PORTD is a bidirectional I/O port PORTE is a bidirectional I/O port PORTF is a bidirectional I/O port PORTG is a bidirectional I/O port Timer1 External Clock Input Timer2 External Clock Input Timer3 External Clock Input Timer4 External Clock Input Timer5 External Clock Input Analog = Analog input P = Power I = Input O = Output OSC1 OSC2 SOSCI SOSCO CN0-CN23 C1RX C1TX IC1-IC4 INDX1, INDX2, AINDX1 QEA1, QEA2, AQEA1 QEB1, QEB2, AQEB1 UPDN1 OCFA OCFB OC1-OC4 INT0 INT1 INT2 INT3 INT4 RA0-RA15 RB0-RB15 RC0-RC15 RD0-RD15 RE0-RE9 RF0-RF13 RG0-RG15 T1CK T2CK T3CK T4CK T5CK I I/O I O I I O I I I I O I I O I I I I I I/O I/O I/O I/O I/O I/O I/O I I I I I Legend: CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels TTL = Transistor-Transistor Logic 2009 Microchip Technology Inc. Preliminary DS70591B-page 21 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 TABLE 1-1: Pin Name U1CTS U1RTS U1RX U1TX U2CTS U2RTS U2RX U2TX SCK1 SDI1 SDO1 SS1, ASS1 SCK2 SDI2 SDO2 SS2 SCL1 SDA1 SCL2 SDA2 TMS TCK TDI TDO CMP1A CMP1B CMP1C CMP1D CMP2A CMP2B CMP2C CMP2D CMP3A CMP3B CMP3C CMP3D CMP4A CMP4B CMP4C CMP4D DACOUT EXTREF REFCLK PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Type I O I O I O I O I/O I O I/O I/O I O I/O I/O I/O I/O I/O I I I O I I I I I I I I I I I I I I I I 0 I 0 Buffer Type ST -- ST -- ST -- ST -- ST ST -- ST ST ST -- ST ST ST ST ST TTL TTL TTL -- Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog -- Analog -- UART1 clear to send UART1 ready to send UART1 receive UART1 transmit UART2 clear to send UART2 ready to send UART2 receive UART2 transmit Synchronous serial clock input/output for SPI1 SPI1 data in SPI1 data out SPI1 slave synchronization or frame pulse I/O Synchronous serial clock input/output for SPI2 SPI2 data in SPI2 data out SPI2 slave synchronization or frame pulse I/O Synchronous serial clock input/output for I2C1 Synchronous serial data input/output for I2C1 Synchronous serial clock input/output for I2C2 Synchronous serial data input/output for I2C2 JTAG Test mode select pin JTAG test clock input pin JTAG test data input pin JTAG test data output pin Comparator 1 Channel A Comparator 1 Channel B Comparator 1 Channel C Comparator 1 Channel D Comparator 2 Channel A Comparator 2 Channel B Comparator 2 Channel C Comparator 2 Channel D Comparator 3 Channel A Comparator 3 Channel B Comparator 3 Channel C Comparator 3 Channel D Comparator 4 Channel A Comparator 4 Channel B Comparator 4 Channel C Comparator 4 Channel D DAC output voltage External Voltage Reference Input for the Reference DACs REFCLK output signal is a postscaled derivative of the system clock Analog = Analog input P = Power I = Input O = Output Description Legend: CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels TTL = Transistor-Transistor Logic DS70591B-page 22 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 TABLE 1-1: Pin Name FLT1-FLT23 SYNCI1-SYNCI4 SYNCO1-SYNCO2 PWM1L PWM1H PWM2L PWM2H PWM3L PWM3H PWM4L PWM4H PWM5L PWM5H PWM6L PWM6H PWM7L PWM7H PWM8L PWM8H PWM9L PWM9H PGED1 PGEC1 PGED2 PGEC2 PGED3 PGEC3 MCLR AVDD AVSS VDD VCAP/VDDCORE VSS PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Type I I O O O O O O O O O O O O O O O O O O O I/O I I/O I I/O I I/P P P P P P Buffer Type ST ST -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- ST ST ST ST ST ST ST P P -- -- -- Description Fault Inputs to PWM Module External synchronization signal to PWM Master Time Base PWM Master Time Base for external device synchronization PWM1 Low output PWM1 High output PWM2 Low output PWM2 High output PWM3 Low output PWM3 High output PWM4 Low output PWM4 High output PWM5 Low output PWM5 High output PWM6 Low output PWM6 High output PWM7 Low output PWM7 High output PWM8 Low output PWM8 High output PWM9 Low output PWM9 High output Data I/O pin for programming/debugging communication Channel 1 Clock input pin for programming/debugging communication Channel 1 Data I/O pin for programming/debugging communication Channel 2 Clock input pin for programming/debugging communication Channel 2 Data I/O pin for programming/debugging communication Channel 3 Clock input pin for programming/debugging communication Channel 3 Master Clear (Reset) input. This pin is an active-low Reset to the device. Positive supply for analog modules Ground reference for analog modules Positive supply for peripheral logic and I/O pins CPU logic filter capacitor connection Ground reference for logic and I/O pins Analog = Analog input P = Power I = Input O = Output Legend: CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels TTL = Transistor-Transistor Logic 2009 Microchip Technology Inc. Preliminary DS70591B-page 23 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 NOTES: DS70591B-page 24 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 2.0 GUIDELINES FOR GETTING STARTED WITH 16-BIT DIGITAL SIGNAL CONTROLLERS 2.2 Decoupling Capacitors The use of decoupling capacitors on every pair of power supply pins, such as VDD, VSS, AVDD, and AVSS is required. Consider the following criteria when using decoupling capacitors: * Value and type of capacitor: Recommendation of 0.1 F (100 nF), 10-20V. This capacitor should be a low-ESR and have resonance frequency in the range of 20 MHz and higher. It is recommended that ceramic capacitors be used. * Placement on the printed circuit board: The decoupling capacitors should be placed as close to the pins as possible. It is recommended to place the capacitors on the same side of the board as the device. If space is constricted, the capacitor can be placed on another layer on the PCB using a via; however, ensure that the trace length from the pin to the capacitor is within one-quarter inch (6 mm) in length. * Handling high frequency noise: If the board is experiencing high frequency noise, upward of tens of MHz, add a second ceramic-type capacitor in parallel to the above described decoupling capacitor. The value of the second capacitor can be in the range of 0.01 F to 0.001 F. Place this second capacitor next to the primary decoupling capacitor. In high-speed circuit designs, consider implementing a decade pair of capacitances as close to the power and ground pins as possible. For example, 0.1 F in parallel with 0.001 F. * Maximizing performance: On the board layout from the power supply circuit, run the power and return traces to the decoupling capacitors first, and then to the device pins. This ensures that the decoupling capacitors are first in the power chain. Equally important is to keep the trace length between the capacitor and the power pins to a minimum, thereby reducing PCB track inductance. Note 1: This data sheet summarizes the features of the dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the "dsPIC33F/PIC24H Family Reference Manual". Please see the Microchip web site (www.microchip.com) for the latest dsPIC33F/PIC24H Family Reference Manual sections. 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 "Memory Organization" in this data sheet for device-specific register and bit information. 2.1 Basic Connection Requirements Getting started with the dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 family of 16-bit Digital Signal Controllers (DSC) requires attention to a minimal set of device pin connections before proceeding with development. The following is a list of pin names, which must always be connected: * All VDD and VSS pins (see Section 2.2 "Decoupling Capacitors") * All AVDD and AVSS pins (regardless if ADC module is not used) (see Section 2.2 "Decoupling Capacitors") * VCAP/VDDCORE (see Section 2.3 "Capacitor on Internal Voltage Regulator (VCAP/VDDCORE)") * MCLR pin (see Section 2.4 "Master Clear (MCLR) Pin") * PGECx/PGEDx pins used for In-Circuit Serial ProgrammingTM (ICSPTM) and debugging purposes (see Section 2.5 "ICSP Pins") * OSC1 and OSC2 pins when external oscillator source is used (see Section 2.6 "External Oscillator Pins") 2009 Microchip Technology Inc. Preliminary DS70591B-page 25 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 FIGURE 2-1: RECOMMENDED MINIMUM CONNECTION 0.1 F Ceramic 2.4 Master Clear (MCLR) Pin The MCLR pin provides for two specific device functions: * Device Reset * Device programming and debugging. During device programming and debugging, the resistance and capacitance that can be added to the pin must be considered. Device programmers and debuggers drive the MCLR pin. Consequently, specific voltage levels (VIH and VIL) and fast signal transitions must not be adversely affected. Therefore, specific values of R and C will need to be adjusted based on the application and PCB requirements. VDD VCAP/VDDCORE R R1 MCLR C dsPIC33F VSS VDD VDD VSS AVDD AVSS VDD VSS VDD VSS 0.1 F Ceramic 0.1 F Ceramic 10 0.1 F Ceramic 0.1 F Ceramic For example, as shown in Figure 2-2, it is recommended that the capacitor C, be isolated from the MCLR pin during programming and debugging operations. Place the components shown in Figure 2-2 within one-quarter inch (6 mm) from the MCLR pin. 2.2.1 TANK CAPACITORS FIGURE 2-2: On boards with power traces running longer than six inches in length, it is suggested to use a tank capacitor for integrated circuits including DSCs to supply a local power source. The value of the tank capacitor should be determined based on the trace resistance that connects the power supply source to the device, and the maximum current drawn by the device in the application. In other words, select the tank capacitor so that it meets the acceptable voltage sag at the device. Typical values range from 4.7 F to 47 F. EXAMPLE OF MCLR PIN CONNECTIONS VDD R R1 JP C MCLR dsPIC33F 2.3 Capacitor on Internal Voltage Regulator (VCAP/VDDCORE) Note 1: A low-ESR (< 5 Ohms) capacitor is required on the VCAP/VDDCORE pin, which is used to stabilize the voltage regulator output voltage. The VCAP/VDDCORE pin must not be connected to VDD, and must have a capacitor between 4.7 F and 10 F, 16V connected to ground. The type can be ceramic or tantalum. Refer to Section 27.0 "Electrical Characteristics" for additional information. The placement of this capacitor should be close to the VCAP/VDDCORE. It is recommended that the trace length not exceed one-quarter inch (6 mm). Refer to Section 24.2 "On-Chip Voltage Regulator" for details. R 10 k is recommended. A suggested starting value is 10 k. Ensure that the MCLR pin VIH and VIL specifications are met. R1 470 will limit any current flowing into MCLR from the external capacitor C, in the event of MCLR pin breakdown, due to Electrostatic Discharge (ESD) or Electrical Overstress (EOS). Ensure that the MCLR pin VIH and VIL specifications are met. 2: DS70591B-page 26 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 2.5 ICSP Pins 2.6 External Oscillator Pins The PGECx and PGEDx pins are used for In-Circuit Serial ProgrammingTM (ICSPTM) and debugging purposes. It is recommended to keep the trace length between the ICSP connector and the ICSP pins on the device as short as possible. If the ICSP connector is expected to experience an ESD event, a series resistor is recommended, with the value in the range of a few tens of Ohms, not to exceed 100 Ohms. Pull-up resistors, series diodes, and capacitors on the PGCx and PGDx pins are not recommended as they will interfere with the programmer/debugger communications to the device. If such discrete components are an application requirement, they should be removed from the circuit during programming and debugging. Alternatively, refer to the AC/DC characteristics and timing requirements information in the respective device Flash programming specification for information on capacitive loading limits and pin input voltage high (VIH) and input low (VIL) requirements. Ensure that the "Communication Channel Select" (i.e., PGECx/PGEDx pins) programmed into the device matches the physical connections for the ICSP to MPLAB(R) ICD 2, MPLAB(R) ICD 3, or MPLAB(R) REAL ICETM. For more information on ICD 2, ICD 3, and REAL ICE connection requirements, refer to the following documents that are available on the Microchip web site. * "MPLAB(R) ICD 2 In-Circuit Debugger User's Guide" DS51331 * "Using MPLAB(R) ICD 2" (poster) DS51265 * "MPLAB(R) ICD 2 Design Advisory" DS51566 * "Using MPLAB(R) ICD 3" (poster) DS51765 * "MPLAB(R) ICD 3 Design Advisory" DS51764 * "MPLAB(R) REAL ICETM In-Circuit Debugger User's Guide" DS51616 * "Using MPLAB(R) REAL ICETM" (poster) DS51749 Many DSCs have options for at least two oscillators: a high-frequency primary oscillator and a low-frequency secondary oscillator (refer to Section 9.0 "Oscillator Configuration" for details). The oscillator circuit should be placed on the same side of the board as the device. Also, place the oscillator circuit close to the respective oscillator pins, not exceeding one-half inch (12 mm) distance between them. The load capacitors should be placed next to the oscillator itself, on the same side of the board. Use a grounded copper pour around the oscillator circuit to isolate them from surrounding circuits. The grounded copper pour should be routed directly to the MCU ground. Do not run any signal traces or power traces inside the ground pour. Also, if using a two-sided board, avoid any traces on the other side of the board where the crystal is placed. A suggested layout is shown in Figure 2-3. FIGURE 2-3: SUGGESTED PLACEMENT OF THE OSCILLATOR CIRCUIT Main Oscillator 13 Guard Ring Guard Trace Secondary Oscillator 14 15 16 17 18 19 20 2009 Microchip Technology Inc. Preliminary DS70591B-page 27 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 2.7 Oscillator Value Conditions on Device Start-up If your application needs to use certain A/D pins as analog input pins during the debug session, the user application must clear the corresponding bits in the ADPCFG and ADPCFG2 registers during initialization of the ADC module. When MPLAB ICD 2, ICD 3, or REAL ICE is used as a programmer, the user application firmware must correctly configure the ADPCFG and ADPCFG2 registers. Automatic initialization of these registers is only done during debugger operation. Failure to correctly configure the register(s) will result in all A/D pins being recognized as analog input pins, resulting in the port value being read as a logic '0', which may affect user application functionality. If the PLL of the target device is enabled and configured for the device start-up oscillator, the maximum oscillator source frequency must be limited to 4 MHz < FIN < 8 MHz to comply with device PLL start-up conditions. This means that if the external oscillator frequency is outside this range, the application must start-up in the FRC mode first. The default PLL settings after a POR with an oscillator frequency outside this range will violate the device operating speed. Once the device powers up, the application firmware can initialize the PLL SFRs, CLKDIV, and PLLDBF to a suitable value, and then perform a clock switch to the Oscillator + PLL clock source. Note that clock switching must be enabled in the device Configuration Word. 2.9 Unused I/Os Unused I/O pins should be configured as outputs and driven to a logic-low state. Alternatively, connect a 1k to 10k resistor to VSS on unused pins and drive the output to logic low. 2.8 Configuration of Analog and Digital Pins During ICSP Operations If MPLAB ICD 2, ICD 3, or REAL ICE is selected as a debugger, it automatically initializes all of the A/D input pins (ANx) as "digital" pins, by setting all bits in the ADPCFG and ADPCFG2 registers. The bits in the registers that correspond to the A/D pins that are initialized by MPLAB ICD 2, ICD 3, or REAL ICE, must not be cleared by the user application firmware; otherwise, communication errors will result between the debugger and the device. 2.10 Typical Application Connection Examples Examples of typical application connections are shown in Figure 2-4 through Figure 2-11. DS70591B-page 28 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 FIGURE 2-4: DIGITAL PFC IPFC VHV_BUS |VAC| k1 VAC k3 k2 FET Driver ADC Channel ADC Channel PWM Output ADC Channel dsPIC33FJ32GS406 FIGURE 2-5: BOOST CONVERTER IMPLEMENTATION VINPUT IPFC VOUTPUT k1 k3 k2 FET Driver ADC Channel ADC Channel PWM Output ADC Channel dsPIC33FJ32GS406 2009 Microchip Technology Inc. Preliminary DS70591B-page 29 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 FIGURE 2-6: SINGLE-PHASE SYNCHRONOUS BUCK CONVERTER 12V Input 5V Output I5V k7 FET Driver k1 k2 FIGURE 2-7: 12V Input MULTI-PHASE SYNCHRONOUS BUCK CONVERTER 3.3V Output PWM PWM ADC Channel Analog Comp. ADC Channel dsPIC33FJ32GS606 k7 FET Driver FET Driver k6 PWM PWM PWM PWM ADC Channel PWM PWM FET Driver k3 k4 k5 Analog Comparator dsPIC33FJ32GS608 Analog Comparator Analog Comparator ADC Channel DS70591B-page 30 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 FIGURE 2-8: OFF-LINE UPS VDC Full-Bridge Inverter Push-Pull Converter VBAT VOUT+ + VOUTGND GND FET Driver FET Driver k2 k1 FET Driver FET Driver FET Driver FET Driver k4 k5 PWM k3 ADC PWM ADC ADC or Analog Comp. PWM PWM PWM PWM ADC ADC dsPIC33FJ64GS610 ADC k6 PWM FET Driver + Battery Charger 2009 Microchip Technology Inc. Preliminary DS70591B-page 31 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 FIGURE 2-9: INTERLEAVED PFC VOUT+ |VAC| k4 VAC k1 k2 k3 VOUTFET Driver FET Driver ADC Channel PWM ADC Channel PWM ADC Channel ADC Channel ADC Channel dsPIC33FJ32GS608 DS70591B-page 32 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 FIGURE 2-10: PHASE-SHIFTED FULL-BRIDGE CONVERTER VIN+ Gate 6 Gate 3 Gate 1 VOUT+ S1 S3 VOUTGate 4 Gate 5 Gate 6 Gate 5 Gate 2 VIN- FET Driver k1 Gate 1 FET Driver Gate 3 FET Driver PWM Analog Ground PWM ADC Channel PWM k2 S1 ADC Channel dsPIC33FJ32GS606 S3 Gate 2 Gate 4 2009 Microchip Technology Inc. Preliminary DS70591B-page 33 FIGURE 2-11: Isolation Barrier VOUT IZVT AC-TO-DC POWER SUPPLY WITH PFC AND THREE OUTPUTS (12V, 5V, AND 3.3V) ZVT with Current Doubler Synchronous Rectifier PWM PWM PWM PWM PWM PWM PWM PWM PWM PWM DS70591B-page 34 3.3V Multi-Phase Buck Stage 12V Input I3.3V_1 3.3V Output k4 I5V FET Driver k5 k6 k7 FET Driver FET Driver I3.3V_3 k11 FET Driver VHV_BUS FET Driver FET Driver 5V Buck Stage 5V Output I3.3V_2 ADC ADC Channel Channel PWM PWM UART RX ADC Channel Analog Comp. ADC Channel Primary Controller dsPIC33FJ64GS610 ADC Ch. ADC Ch. PWM Output ADC Ch. PWM PWM Analog Comparator FET Driver k8 Analog Comparator Analog Comparator ADC Channel k9 k10 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 Preliminary Secondary Controller dsPIC33FJ64GS610 FET Driver UART TX k3 VHV_BUS IPFC PFC Stage k2 VAC k1 2009 Microchip Technology Inc. |VAC| dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 3.0 CPU cycle. As a result, three parameter instructions can be supported, allowing A + B = C operations to be executed in a single cycle. A block diagram of the CPU is shown in Figure 3-1, and the programmer's model for the dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 is shown in Figure 3-2. Note 1: This data sheet summarizes the features of the dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 2. "CPU" (DS70204) in the "dsPIC33F/PIC24H Family Reference Manual", which is available from the Microchip web site (www.microchip.com). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 "Memory Organization" in this data sheet for device-specific register and bit information. The dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 CPU module has a 16-bit (data) modified Harvard architecture with an enhanced instruction set, including significant support for DSP. The CPU has a 24-bit instruction word with a variable length opcode field. The Program Counter (PC) is 23 bits wide and addresses up to 4M x 24 bits of user program memory space. The actual amount of program memory implemented varies from device to device. A single-cycle instruction prefetch mechanism is used to help maintain throughput and provides predictable execution. All instructions execute in a single cycle, with the exception of instructions that change the program flow, the double-word move (MOV.D) instruction and the table instructions. Overhead-free program loop constructs are supported using the DO and REPEAT instructions, both of which are interruptible at any point. The dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 devices have sixteen, 16-bit working registers in the programmer's model. Each of the working registers can serve as a data, address or address offset register. The sixteenth working register (W15) operates as a software Stack Pointer (SP) for interrupts and calls. There are two classes of instruction in the dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 devices: MCU and DSP. These two instruction classes are seamlessly integrated into a single CPU. The instruction set includes many addressing modes and is designed for optimum C compiler efficiency. For most instructions, the dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 is capable of executing a data (or program data) memory read, a working register (data) read, a data memory write and a program (instruction) memory read per instruction 3.1 Data Addressing Overview The data space can be addressed as 32K words or 64 Kbytes and is split into two blocks, referred to as X and Y data memory. Each memory block has its own independent Address Generation Unit (AGU). The MCU class of instructions operates solely through the X memory AGU, which accesses the entire memory map as one linear data space. Certain DSP instructions operate through the X and Y AGUs to support dual operand reads, which splits the data address space into two parts. The X and Y data space boundary is device-specific. Overhead-free circular buffers (Modulo Addressing mode) are supported in both X and Y address spaces. The Modulo Addressing removes the software boundary checking overhead for DSP algorithms. Furthermore, the X AGU circular addressing can be used with any of the MCU class of instructions. The X AGU also supports Bit-Reversed Addressing to greatly simplify input or output data reordering for radix-2 FFT algorithms. The upper 32 Kbytes of the data space memory map can optionally be mapped into program space at any 16K program word boundary defined by the 8-bit Program Space Visibility Page (PSVPAG) register. The program-to-data space mapping feature lets any instruction access program space as if it were data space. 3.2 DSP Engine Overview The DSP engine features a high-speed, 17-bit by 17-bit multiplier, a 40-bit ALU, two 40-bit saturating accumulators and a 40-bit bidirectional barrel shifter. The barrel shifter is capable of shifting a 40-bit value up to 16 bits, right or left, in a single cycle. The DSP instructions operate seamlessly with all other instructions and have been designed for optimal realtime performance. The MAC instruction and other associated instructions can concurrently fetch two data operands from memory while multiplying two W registers and accumulating and optionally saturating the result in the same cycle. This instruction functionality requires that the RAM data space be split for these instructions and linear for all others. Data space partitioning is achieved in a transparent and flexible manner through dedicating certain working registers to each address space. 2009 Microchip Technology Inc. Preliminary DS70591B-page 35 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 3.3 Special MCU Features The dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 supports 16/16 and 32/16 divide operations, both fractional and integer. All divide instructions are iterative operations. They must be executed within a REPEAT loop, resulting in a total execution time of 19 instruction cycles. The divide operation can be interrupted during any of those 19 cycles without loss of data. A 40-bit barrel shifter is used to perform up to a 16-bit left or right shift in a single cycle. The barrel shifter can be used by both MCU and DSP instructions. The dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 features a 17-bit by 17-bit single-cycle multiplier that is shared by both the MCU ALU and DSP engine. The multiplier can perform signed, unsigned and mixed sign multiplication. Using a 17-bit by 17-bit multiplier for 16-bit by 16-bit multiplication not only allows you to perform mixed sign multiplication, it also achieves accurate results for special operations, such as (-1.0) x (-1.0). FIGURE 3-1: dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 CPU CORE BLOCK DIAGRAM PSV & Table Data Access Control Block Interrupt Controller 8 23 23 PCU PCH PCL Program Counter Loop Stack Control Control Logic Logic 16 Y Data Bus X Data Bus 16 16 Data Latch X RAM Address Latch 16 Data Latch Y RAM Address Latch 16 23 16 Address Latch 16 Address Generator Units Program Memory EA MUX Data Latch 24 ROM Latch 16 Literal Data 16 Instruction Decode & Control Instruction Reg 16 Control Signals to Various Blocks DSP Engine Divide Support 16 x 16 W Register Array 16 16-Bit ALU 16 To Peripheral Modules DS70591B-page 36 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 FIGURE 3-2: PROGRAMMER'S MODEL D15 W0/WREG W1 W2 W3 W4 DSP Operand Registers W5 W6 W7 W8 DSP Address Registers W9 W10 W11 W12/DSP Offset W13/DSP Write Back W14/Frame Pointer W15/Stack Pointer SPLIM AD39 DSP Accumulators PC22 0 TBLPAG 7 PSVPAG 0 Program Space Visibility Page Address 15 RCOUNT 15 DCOUNT 22 DOSTART 22 DOEND 15 CORCON OA OB SA SB OAB SAB DA SRH DC IPL2 IPL1 IPL0 RA SRL N OV 0 Core Configuration Register DO Loop End Address 0 DO Loop Start Address 0 DO Loop Counter 0 REPEAT Loop Counter Data Table Page Address ACCA ACCB PC0 0 7 Program Counter AD31 Stack Pointer Limit Register AD15 AD0 Working Registers DO Shadow Legend D0 PUSH.S Shadow Z C STATUS Register 2009 Microchip Technology Inc. Preliminary DS70591B-page 37 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 3.4 CPU Control Registers SR: CPU STATUS REGISTER R-0 OB R/C-0 SA(1) R/C-0 SB (1) REGISTER 3-1: R-0 OA bit 15 R/W-0(2) bit 7 Legend: C = Clearable bit S = Settable bit `1' = Bit is set bit 15 R-0 OAB R/C-0 SAB (1,4) R -0 DA R/W-0 DC bit 8 R/W-0(3) IPL<2:0> (2) R/W-0(3) R-0 RA R/W-0 N R/W-0 OV R/W-0 Z R/W-0 C bit 0 R = Readable bit W = Writable bit `0' = Bit is cleared U = Unimplemented bit, read as `0' -n = Value at POR x = Bit is unknown OA: Accumulator A Overflow Status bit 1 = Accumulator A overflowed 0 = Accumulator A has not overflowed OB: Accumulator B Overflow Status bit 1 = Accumulator B overflowed 0 = Accumulator B has not overflowed SA: Accumulator A Saturation `Sticky' Status bit(1) 1 = Accumulator A is saturated or has been saturated at some time 0 = Accumulator A is not saturated SB: Accumulator B Saturation `Sticky' Status bit(1) 1 = Accumulator B is saturated or has been saturated at some time 0 = Accumulator B is not saturated OAB: OA || OB Combined Accumulator Overflow Status bit 1 = Accumulators A or B have overflowed 0 = Neither Accumulators A or B have overflowed SAB: SA || SB Combined Accumulator `Sticky' Status bit(1,4) 1 = Accumulators A or B are saturated or have been saturated at some time in the past 0 = Neither Accumulator A or B are saturated DA: DO Loop Active bit 1 = DO loop in progress 0 = DO loop not in progress DC: MCU ALU Half Carry/Borrow bit 1 = A carry-out from the 4th low-order bit (for byte-sized data) or 8th low-order bit (for word-sized data) of the result occurred 0 = No carry-out from the 4th low-order bit (for byte-sized data) or 8th low-order bit (for word-sized data) of the result occurred This bit can be read or cleared (not set). The IPL<2:0> bits are concatenated with the IPL<3> bit (CORCON<3>) to form the CPU Interrupt Priority Level (IPL). The value in parentheses indicates the IPL if IPL<3> = 1. User interrupts are disabled when IPL<3> = 1. The IPL<2:0> Status bits are read-only when NSTDIS = 1 (INTCON1<15>). Clearing this bit will clear SA and SB. bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 Note 1: 2: 3: 4: DS70591B-page 38 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 REGISTER 3-1: bit 7-5 SR: CPU STATUS REGISTER (CONTINUED) IPL<2:0>: CPU Interrupt Priority Level Status bits(2) 111 = CPU Interrupt Priority Level is 7 (15), user interrupts disabled 110 = CPU Interrupt Priority Level is 6 (14) 101 = CPU Interrupt Priority Level is 5 (13) 100 = CPU Interrupt Priority Level is 4 (12) 011 = CPU Interrupt Priority Level is 3 (11) 010 = CPU Interrupt Priority Level is 2 (10) 001 = CPU Interrupt Priority Level is 1 (9) 000 = CPU Interrupt Priority Level is 0 (8) RA: REPEAT Loop Active bit 1 = REPEAT loop in progress 0 = REPEAT loop not in progress N: MCU ALU Negative bit 1 = Result was negative 0 = Result was non-negative (zero or positive) OV: MCU ALU Overflow bit This bit is used for signed arithmetic (2's complement). It indicates an overflow of a magnitude that causes the sign bit to change state. 1 = Overflow occurred for signed arithmetic (in this arithmetic operation) 0 = No overflow occurred Z: MCU ALU Zero bit 1 = An operation that affects the Z bit has set it at some time in the past 0 = The most recent operation that affects the Z bit has cleared it (i.e., a non-zero result) C: MCU ALU Carry/Borrow bit 1 = A carry-out from the Most Significant bit of the result occurred 0 = No carry-out from the Most Significant bit of the result occurred This bit can be read or cleared (not set). The IPL<2:0> bits are concatenated with the IPL<3> bit (CORCON<3>) to form the CPU Interrupt Priority Level (IPL). The value in parentheses indicates the IPL if IPL<3> = 1. User interrupts are disabled when IPL<3> = 1. The IPL<2:0> Status bits are read-only when NSTDIS = 1 (INTCON1<15>). Clearing this bit will clear SA and SB. bit 4 bit 3 bit 2 bit 1 bit 0 Note 1: 2: 3: 4: 2009 Microchip Technology Inc. Preliminary DS70591B-page 39 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 REGISTER 3-2: U-0 -- bit 15 R/W-0 SATA bit 7 Legend: R = Readable bit 0' = Bit is cleared bit 15-13 bit 12 CORCON: CORE CONTROL REGISTER U-0 -- U-0 -- R/W-0 US R/W-0 EDT(1) R-0 R-0 DL<2:0> R-0 bit 8 R/W-0 SATB R/W-1 SATDW R/W-0 ACCSAT R/C-0 IPL3(2) R/W-0 PSV R/W-0 RND R/W-0 IF bit 0 C = Clearable bit W = Writable bit `x = Bit is unknown -n = Value at POR `1' = Bit is set U = Unimplemented bit, read as `0' bit 11 bit 10-8 Unimplemented: Read as `0' US: DSP Multiply Unsigned/Signed Control bit 1 = DSP engine multiplies are unsigned 0 = DSP engine multiplies are signed EDT: Early DO Loop Termination Control bit(1) 1 = Terminate executing DO loop at end of current loop iteration 0 = No effect DL<2:0>: DO Loop Nesting Level Status bits 111 = 7 DO loops active * * * bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 001 = 1 DO loop active 000 = 0 DO loops active SATA: ACCA Saturation Enable bit 1 = Accumulator A saturation enabled 0 = Accumulator A saturation disabled SATB: ACCB Saturation Enable bit 1 = Accumulator B saturation enabled 0 = Accumulator B saturation disabled SATDW: Data Space Write from DSP Engine Saturation Enable bit 1 = Data space write saturation enabled 0 = Data space write saturation disabled ACCSAT: Accumulator Saturation Mode Select bit 1 = 9.31 saturation (super saturation) 0 = 1.31 saturation (normal saturation) IPL3: CPU Interrupt Priority Level Status bit 3(2) 1 = CPU Interrupt Priority Level is greater than 7 0 = CPU Interrupt Priority Level is 7 or less PSV: Program Space Visibility in Data Space Enable bit 1 = Program space visible in data space 0 = Program space not visible in data space RND: Rounding Mode Select bit 1 = Biased (conventional) rounding enabled 0 = Unbiased (convergent) rounding enabled IF: Integer or Fractional Multiplier Mode Select bit 1 = Integer mode enabled for DSP multiply ops 0 = Fractional mode enabled for DSP multiply ops This bit will always read as `0'. The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU Interrupt Priority Level. Note 1: 2: DS70591B-page 40 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 3.5 Arithmetic Logic Unit (ALU) 3.5.2 DIVIDER The dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 ALU is 16 bits wide and is capable of addition, subtraction, bit shifts and logic operations. Unless otherwise mentioned, arithmetic operations are 2's complement in nature. Depending on the operation, the ALU can affect the values of the Carry (C), Zero (Z), Negative (N), Overflow (OV) and Digit Carry (DC) Status bits in the SR register. The C and DC Status bits operate as Borrow and Digit Borrow bits, respectively, for subtraction operations. The ALU can perform 8-bit or 16-bit operations, depending on the mode of the instruction that is used. Data for the ALU operation can come from the W register array or data memory, depending on the addressing mode of the instruction. Likewise, output data from the ALU can be written to the W register array or a data memory location. Refer to the "16-bit MCU and DSC Programmer's Reference Manual" (DS70157) for information on the SR bits affected by each instruction. The dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 CPU incorporates hardware support for both multiplication and division. This includes a dedicated hardware multiplier and support hardware for 16-bit-divisor division. The divide block supports 32-bit/16-bit and 16-bit/16-bit signed and unsigned integer divide operations with the following data sizes: * * * * 32-bit signed/16-bit signed divide 32-bit unsigned/16-bit unsigned divide 16-bit signed/16-bit signed divide 16-bit unsigned/16-bit unsigned divide The quotient for all divide instructions ends up in W0 and the remainder in W1. 16-bit signed and unsigned DIV instructions can specify any W register for both the 16-bit divisor (Wn) and any W register (aligned) pair (W(m + 1):Wm) for the 32-bit dividend. The divide algorithm takes one cycle per bit of divisor, so both 32-bit/ 16-bit and 16-bit/16-bit instructions take the same number of cycles to execute. 3.6 DSP Engine The DSP engine consists of a high-speed, 17-bit x 17-bit multiplier, a barrel shifter and a 40-bit adder/ subtracter (with two target accumulators, round and saturation logic). The dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 is a single-cycle instruction flow architecture; therefore, concurrent operation of the DSP engine with MCU instruction flow is not possible. However, some MCU ALU and DSP engine resources can be used concurrently by the same instruction (for example, ED, EDAC). The DSP engine can also perform inherent accumulator-to-accumulator operations that require no additional data. These instructions are ADD, SUB and NEG. The DSP engine has options selected through bits in the CPU Core Control register (CORCON), as listed below: * * * * * * Fractional or integer DSP multiply (IF) Signed or unsigned DSP multiply (US) Conventional or convergent rounding (RND) Automatic saturation on/off for ACCA (SATA) Automatic saturation on/off for ACCB (SATB) Automatic saturation on/off for writes to data memory (SATDW) * Accumulator Saturation mode selection (ACCSAT) A block diagram of the DSP engine is shown in Figure 3-3. 3.5.1 MULTIPLIER Using the high-speed, 17-bit x 17-bit multiplier of the DSP engine, the ALU supports unsigned, signed or mixed sign operation in several MCU multiplication modes: * * * * * * * 16-bit x 16-bit signed 16-bit x 16-bit unsigned 16-bit signed x 5-bit (literal) unsigned 16-bit unsigned x 16-bit unsigned 16-bit unsigned x 5-bit (literal) unsigned 16-bit unsigned x 16-bit signed 8-bit unsigned x 8-bit unsigned 2009 Microchip Technology Inc. Preliminary DS70591B-page 41 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 TABLE 3-1: CLR ED EDAC MAC MAC MOVSAC MPY MPY MPY.N MSC DSP INSTRUCTIONS SUMMARY Instruction A=0 A = (x - y)2 A = A + (x - y)2 A = A + (x * y) A = A + x2 No change in A A=x*y A=x2 A=-x*y A=A-x*y Algebraic Operation ACC Write Back Yes No No Yes No Yes No No No Yes FIGURE 3-3: DSP ENGINE BLOCK DIAGRAM 40 Carry/Borrow Out Carry/Borrow In 40-bit Accumulator A 40-bit Accumulator B Saturate Adder Negate 40 Barrel Shifter 40 S a Round t 16 u Logic r a t e 40 40 16 40 Sign-Extend Y Data Bus 32 Zero Backfill 33 32 16 17-Bit Multiplier/Scaler 16 16 To/From W Array DS70591B-page 42 Preliminary 2009 Microchip Technology Inc. X Data Bus dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 3.6.1 MULTIPLIER 3.6.2.1 Adder/Subtracter, Overflow and Saturation The 17-bit x 17-bit multiplier is capable of signed or unsigned operation and can multiplex its output using a scaler to support either 1.31 fractional (Q31) or 32-bit integer results. Unsigned operands are zero-extended into the 17th bit of the multiplier input value. Signed operands are sign-extended into the 17th bit of the multiplier input value. The output of the 17-bit x 17-bit multiplier/scaler is a 33-bit value that is sign-extended to 40 bits. Integer data is inherently represented as a signed 2's complement value, where the Most Significant bit (MSb) is defined as a sign bit. The range of an N-bit 2's complement integer is -2N-1 to 2N-1 - 1. * For a 16-bit integer, the data range is -32768 (0x8000) to 32767 (0x7FFF) including 0. * For a 32-bit integer, the data range is -2,147,483,648 (0x8000 0000) to 2,147,483,647 (0x7FFF FFFF). When the multiplier is configured for fractional multiplication, the data is represented as a 2's complement fraction, where the MSb is defined as a sign bit and the radix point is implied to lie just after the sign bit (QX format). The range of an N-bit 2's complement fraction with this implied radix point is -1.0 to (1 - 21-N). For a 16-bit fraction, the Q15 data range is -1.0 (0x8000) to 0.999969482 (0x7FFF) including 0 and has a precision of 3.01518x10-5. In Fractional mode, the 16 x 16 multiply operation generates a 1.31 product that has a precision of 4.65661 x 10-10. The same multiplier is used to support the MCU multiply instructions, which include integer 16-bit signed, unsigned and mixed sign multiply operations. The MUL instruction can be directed to use byte or word-sized operands. Byte operands will direct a 16-bit result, and word operands will direct a 32-bit result to the specified register(s) in the W array. The adder/subtracter is a 40-bit adder with an optional zero input into one side, and either true or complement data into the other input. * In the case of addition, the Carry/Borrow input is active-high and the other input is true data (not complemented). * In the case of subtraction, the Carry/Borrow input is active-low and the other input is complemented. The adder/subtracter generates Overflow Status bits, SA/SB and OA/OB, which are latched and reflected in the STATUS register: * Overflow from bit 39: this is a catastrophic overflow in which the sign of the accumulator is destroyed. * Overflow into guard bits, 32 through 39: this is a recoverable overflow. This bit is set whenever all the guard bits are not identical to each other. The adder has an additional saturation block that controls accumulator data saturation, if selected. It uses the result of the adder, the Overflow Status bits described previously and the SAT 3.6.2 DATA ACCUMULATORS AND ADDER/SUBTRACTER The data accumulator consists of a 40-bit adder/ subtracter with automatic sign extension logic. It can select one of two accumulators (A or B) as its preaccumulation source and post-accumulation destination. For the ADD and LAC instructions, the data to be accumulated or loaded can be optionally scaled using the barrel shifter prior to accumulation. 2009 Microchip Technology Inc. Preliminary DS70591B-page 43 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 The SA and SB bits are modified each time data passes through the adder/subtracter, but can only be cleared by the user application. When set, they indicate that the accumulator has overflowed its maximum range (bit 31 for 32-bit saturation or bit 39 for 40-bit saturation) and will be saturated (if saturation is enabled). When saturation is not enabled, SA and SB default to bit 39 overflow and thus, indicate that a catastrophic overflow has occurred. If the COVTE bit in the INTCON1 register is set, SA and SB bits will generate an arithmetic warning trap when saturation is disabled. The Overflow and Saturation Status bits can optionally be viewed in the STATUS Register (SR) as the logical OR of OA and OB (in bit OAB) and the logical OR of SA and SB (in bit SAB). Programmers can check one bit in the STATUS register to determine if either accumulator has overflowed, or one bit to determine if either accumulator has saturated. This is useful for complex number arithmetic, which typically uses both accumulators. The device supports three Saturation and Overflow modes: * Bit 39 Overflow and Saturation: When bit 39 overflow and saturation occurs, the saturation logic loads the maximally positive 9.31 (0x7FFFFFFFFF) or maximally negative 9.31 value (0x8000000000) into the target accumulator. The SA or SB bit is set and remains set until cleared by the user application. This condition is referred to as `super saturation' and provides protection against erroneous data or unexpected algorithm problems (such as gain calculations). * Bit 31 Overflow and Saturation: When bit 31 overflow and saturation occurs, the saturation logic then loads the maximally positive 1.31 value (0x007FFFFFFF) or maximally negative 1.31 value (0x0080000000) into the target accumulator. The SA or SB bit is set and remains set until cleared by the user application. When this Saturation mode is in effect, the guard bits are not used, so the OA, OB or OAB bits are never set. * Bit 39 Catastrophic Overflow: The bit 39 Overflow Status bit from the adder is used to set the SA or SB bit, which remains set until cleared by the user application. No saturation operation is performed, and the accumulator is allowed to overflow, destroying its sign. If the COVTE bit in the INTCON1 register is set, a catastrophic overflow can initiate a trap exception. * W13, Register Direct: The rounded contents of the non-target accumulator are written into W13 as a 1.15 fraction. * [W13] + = 2, Register Indirect with Post-Increment: The rounded contents of the non-target accumulator are written into the address pointed to by W13 as a 1.15 fraction. W13 is then incremented by 2 (for a word write). 3.6.3.1 Round Logic The round logic is a combinational block that performs a conventional (biased) or convergent (unbiased) round function during an accumulator write (store). The Round mode is determined by the state of the RND bit in the CORCON register. It generates a 16-bit, 1.15 data value that is passed to the data space write saturation logic. If rounding is not indicated by the instruction, a truncated 1.15 data value is stored and the least significant word is simply discarded. Conventional rounding zero-extends bit 15 of the accumulator and adds it to the ACCxH word (bits 16 through 31 of the accumulator). * If the ACCxL word (bits 0 through 15 of the accumulator) is between 0x8000 and 0xFFFF (0x8000 included), ACCxH is incremented. * If ACCxL is between 0x0000 and 0x7FFF, ACCxH is left unchanged. A consequence of this algorithm is that over a succession of random rounding operations, the value tends to be biased slightly positive. Convergent (or unbiased) rounding operates in the same manner as conventional rounding, except when ACCxL equals 0x8000. In this case, the Least Significant bit (bit 16 of the accumulator) of ACCxH is examined: * If it is `1', ACCxH is incremented. * If it is `0', ACCxH is not modified. Assuming that bit 16 is effectively random in nature, this scheme removes any rounding bias that may accumulate. The SAC and SAC.R instructions store either a truncated (SAC), or rounded (SAC.R) version of the contents of the target accumulator to data memory via the X bus, subject to data saturation (see Section 3.6.3.2 "Data Space Write Saturation"). For the MAC class of instructions, the accumulator writeback operation functions in the same manner, addressing combined MCU (X and Y) data space though the X bus. For this class of instructions, the data is always subject to rounding. 3.6.3 ACCUMULATOR `WRITE BACK' The MAC class of instructions (with the exception of MPY, MPY.N, ED and EDAC) can optionally write a rounded version of the high word (bits 31 through 16) of the accumulator that is not targeted by the instruction into data space memory. The write is performed across the X bus into combined X and Y address space. The following addressing modes are supported: DS70591B-page 44 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 3.6.3.2 Data Space Write Saturation 3.6.4 BARREL SHIFTER In addition to adder/subtracter saturation, writes to data space can also be saturated, but without affecting the contents of the source accumulator. The data space write saturation logic block accepts a 16-bit, 1.15 fractional value from the round logic block as its input, together with overflow status from the original source (accumulator) and the 16-bit round adder. These inputs are combined and used to select the appropriate 1.15 fractional value as output to write to data space memory. If the SATDW bit in the CORCON register is set, data (after rounding or truncation) is tested for overflow and adjusted accordingly: * For input data greater than 0x007FFF, data written to memory is forced to the maximum positive 1.15 value, 0x7FFF. * For input data less than 0xFF8000, data written to memory is forced to the maximum negative 1.15 value, 0x8000. The Most Significant bit of the source (bit 39) is used to determine the sign of the operand being tested. If the SATDW bit in the CORCON register is not set, the input data is always passed through unmodified under all conditions. The barrel shifter can perform up to 16-bit arithmetic or logic right shifts, or up to 16-bit left shifts in a single cycle. The source can be either of the two DSP accumulators or the X bus (to support multi-bit shifts of register or memory data). The shifter requires a signed binary value to determine both the magnitude (number of bits) and direction of the shift operation. A positive value shifts the operand right. A negative value shifts the operand left. A value of `0' does not modify the operand. The barrel shifter is 40 bits wide, thereby obtaining a 40-bit result for DSP shift operations and a 16-bit result for MCU shift operations. Data from the X bus is presented to the barrel shifter between bit positions 16 and 31 for right shifts, and between bit positions 0 and 16 for left shifts. 2009 Microchip Technology Inc. Preliminary DS70591B-page 45 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 NOTES: DS70591B-page 46 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 4.0 Note: MEMORY ORGANIZATION This data sheet summarizes the features of the dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the dsPIC33F/PIC24H Family Reference Manual, "Section 4. Program Memory" (DS70202), which is available from the Microchip web site (www.microchip.com). 4.1 Program Address Space The program address memory space of the dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 devices is 4M instructions. The space is addressable by a 24-bit value derived either from the 23-bit Program Counter (PC) during program execution, or from table operation or data space remapping as described in Section 4.6 "Interfacing Program and Data Memory Spaces". User application access to the program memory space is restricted to the lower half of the address range (0x000000 to 0x7FFFFF). The exception is the use of TBLRD/TBLWT operations, which use TBLPAG<7> to permit access to the Configuration bits and Device ID sections of the configuration memory space. The memory maps for the dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 devices are shown in Figure 4-1. The dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 architecture features separate program and data memory spaces and buses. This architecture also allows the direct access to program memory from the data space during code execution. FIGURE 4-1: PROGRAM MEMORY MAPS FOR dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 DEVICES DSPIC33FJ64GS406/606/608/610 0x000000 GOTO Instruction 0x000002 Reset Address 0x000004 Interrupt Vector Table 0x0000FE 0x000100 Reserved 0x000104 Alternate Vector Table 0x0001FE 0x000200 User Program Flash Memory (21760 instructions) 0x00ABFE 0x00AC00 Unimplemented (Read `0's) 0x7FFFFE 0x800000 User Memory Space Unimplemented (Read `0's) 0x7FFFFE 0x800000 Reserved Configuration Memory Space 0xF7FFFE 0xF80000 0xF80017 0xF80018 Configuration Memory Space User Memory Space dsPIC33FJ32GS406/606/608/610 0x000000 GOTO Instruction 0x000002 Reset Address 0x000004 Interrupt Vector Table 0x0000FE 0x000100 Reserved 0x000104 Alternate Vector Table 0x0001FE 0x000200 User Program Flash Memory (11008 instructions) 0x0057FE 0x005800 Reserved 0xF7FFFE 0xF80000 0xF80017 0xF80018 Device Configuration Registers Device Configuration Registers Reserved Reserved DEVID (2) Reserved 0xFEFFFE 0xFF0000 0xFF0002 0xFFFFFE 0xFEFFFE DEVID (2) Reserved 0xFF0000 0xFF0002 0xFFFFFE 2009 Microchip Technology Inc. Preliminary DS70591B-page 47 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 4.1.1 PROGRAM MEMORY ORGANIZATION 4.1.2 INTERRUPT AND TRAP VECTORS The program memory space is organized in word-addressable blocks. Although it is treated as 24 bits wide, it is more appropriate to think of each address of the program memory as a lower and upper word, with the upper byte of the upper word being unimplemented. The lower word always has an even address, while the upper word has an odd address (see Figure 4-2). Program memory addresses are always word-aligned on the lower word, and addresses are incremented or decremented by two during the code execution. This arrangement provides compatibility with data memory space addressing and makes data in the program memory space accessible. All dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 devices reserve the addresses between 0x00000 and 0x000200 for hard-coded program execution vectors. A hardware Reset vector is provided to redirect code execution from the default value of the PC on device Reset to the actual start of code. A GOTO instruction is programmed by the user application at 0x000000, with the actual address for the start of code at 0x000002. The dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 devices also have two interrupt vector tables, located from 0x000004 to 0x0000FF and 0x000100 to 0x0001FF. These vector tables allow each of the device interrupt sources to be handled by separate Interrupt Service Routines (ISRs). A more detailed discussion of the interrupt vector tables is provided in Section 7.1 "Interrupt Vector Table". FIGURE 4-2: msw Address 0x000001 0x000003 0x000005 0x000007 PROGRAM MEMORY ORGANIZATION most significant word 23 00000000 00000000 00000000 00000000 Program Memory `Phantom' Byte (read as `0') Instruction Width 16 least significant word 8 0 0x000000 0x000002 0x000004 0x000006 PC Address (lsw Address) DS70591B-page 48 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 4.2 Data Address Space All word accesses must be aligned to an even address. Misaligned word data fetches are not supported, so care must be taken when mixing byte and word operations, or translating from 8-bit MCU code. If a misaligned read or write is attempted, an address error trap is generated. If the error occurred on a read, the instruction underway is completed. If the error occurred on a write, the instruction is executed but the write does not occur. In either case, a trap is then executed, allowing the system and/or user application to examine the machine state prior to execution of the address Fault. All byte loads into any W register are loaded into the Least Significant Byte. The Most Significant Byte is not modified. A sign-extend instruction (SE) is provided to allow user applications to translate 8-bit signed data to 16-bit signed values. Alternatively, for 16-bit unsigned data, user applications can clear the MSB of any W register by executing a zero-extend (ZE) instruction on the appropriate address. The dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 CPU has a separate 16-bit-wide data memory space. The data space is accessed using separate Address Generation Units (AGUs) for read and write operations. The data memory maps is shown in Figure 4-3. All Effective Addresses (EAs) in the data memory space are 16 bits wide and point to bytes within the data space. This arrangement gives a data space address range of 64 Kbytes or 32K words. The lower half of the data memory space (that is, when EA<15> = 0) is used for implemented memory addresses, while the upper half (EA<15> = 1) is reserved for the Program Space Visibility area (see Section 4.6.3 "Reading Data From Program Memory Using Program Space Visibility"). The dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 devices implement up to 9 Kbytes of data memory. Should an EA point to a location outside of this area, an all-zero word or byte will be returned. 4.2.1 DATA SPACE WIDTH 4.2.3 SFR SPACE The data memory space is organized in byte addressable, 16-bit wide blocks. Data is aligned in data memory and registers as 16-bit words, but all data space EAs resolve to bytes. The Least Significant Bytes (LSBs) of each word have even addresses, while the Most Significant Bytes (MSBs) have odd addresses. The first 2 Kbytes of the Near Data Space, from 0x0000 to 0x07FF, is primarily occupied by Special Function Registers (SFRs). These are used by the dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 core and peripheral modules for controlling the operation of the device. SFRs are distributed among the modules that they control, and are generally grouped together by module. Much of the SFR space contains unused addresses; these are read as `0'. Note: The actual set of peripheral features and interrupts varies by the device. Refer to the corresponding device tables and pinout diagrams for device-specific information. 4.2.2 DATA MEMORY ORGANIZATION AND ALIGNMENT To maintain backward compatibility with PIC(R) MCU devices and improve data space memory usage efficiency, the dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 instruction set supports both word and byte operations. As a consequence of byte accessibility, all effective address calculations are internally scaled to step through word-aligned memory. For example, the core recognizes that Post-Modified Register Indirect Addressing mode [Ws++] that results in a value of Ws + 1 for byte operations and Ws + 2 for word operations. Data byte reads will read the complete word that contains the byte, using the LSB of any EA to determine which byte to select. The selected byte is placed onto the LSB of the data path. That is, data memory and registers are organized as two parallel byte-wide entities with shared (word) address decode but separate write lines. Data byte writes only write to the corresponding side of the array or register that matches the byte address. 4.2.4 NEAR DATA SPACE The 8 Kbyte area between 0x0000 and 0x1FFF is referred to as the near data space. Locations in this space are directly addressable via a 13-bit absolute address field within all memory direct instructions. Additionally, the whole data space is addressable using MOV instructions, which support Memory Direct Addressing mode with a 16-bit address field, or by using Indirect Addressing mode using a working register as an Address Pointer. 2009 Microchip Technology Inc. Preliminary DS70591B-page 49 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 FIGURE 4-3: DATA MEMORY MAP FOR DEVICES WITH 4 KB RAM MSB Address MSb 2 Kbyte SFR Space 0x0001 SFR Space 0x07FF 0x0801 0x0FFF 0x1001 0x17FF 0x1801 X Data RAM (X) Y Data RAM (Y) 0x07FE 0x0800 0x0FFE 0x1000 0x17FE 0x1800 6 Kbyte Near Data Space LSB Address LSb 0x0000 16 bits 0x8001 0x8000 Optionally Mapped into Program Memory X Data Unimplemented (X) 0xFFFF 0xFFFE DS70591B-page 50 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 FIGURE 4-4: DATA MEMORY MAP FOR DEVICES WITH 8 KB RAM MSB Address MSb 2 Kbyte SFR Space 0x0001 SFR Space 0x07FF 0x0801 0x17FF 0x1801 Y Data RAM (Y) 0x1FFF 0x2001 0x27FF 0x2801 0x1FFE 0x2000 0x27FE 0x2800 X Data RAM (X) 0x07FE 0x0800 0x17FE 0x1800 8 Kbyte Near Data Space LSB Address LSb 0x0000 16 bits 0x8001 0x8000 X Data Unimplemented (X) Optionally Mapped into Program Memory 0xFFFF 0xFFFE 2009 Microchip Technology Inc. Preliminary DS70591B-page 51 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 FIGURE 4-5: DATA MEMORY MAP FOR DEVICES WITH 9 KB RAM MSB Address MSb 2 Kbyte SFR Space 0x0001 SFR Space 0x07FF 0x0801 0x17FF 0x1801 Y Data RAM (Y) 0x1FFF 0x2001 0x27FF 0x2801 0x2BFF 0x2C01 0x8001 DMA RAM 0x1FFE 0x2000 0x27FE 0x2800 0x2BFE 0x2C00 0x8000 X Data RAM (X) 0x07FE 0x0800 0x17FE 0x1800 8 Kbyte Near Data Space LSB Address LSb 0x0000 16 bits Optionally Mapped into Program Memory X Data Unimplemented (X) 0xFFFF 0xFFFE DS70591B-page 52 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 4.2.5 X AND Y DATA SPACES 4.2.6 DMA RAM The core has two data spaces, X and Y. These data spaces can be considered either separate (for some DSP instructions), or as one unified linear address range (for MCU instructions). The data spaces are accessed using two Address Generation Units (AGUs) and separate data paths. This feature allows certain instructions to concurrently fetch two words from RAM, thereby enabling efficient execution of DSP algorithms such as Finite Impulse Response (FIR) filtering and Fast Fourier Transform (FFT). The X data space is used by all instructions and supports all addressing modes. X data space has separate read and write data buses. The X read data bus is the read data path for all instructions that view data space as combined X and Y address space. It is also the X data prefetch path for the dual operand DSP instructions (MAC class). The Y data space is used in concert with the X data space by the MAC class of instructions (CLR, ED, EDAC, MAC, MOVSAC, MPY, MPY.N and MSC) to provide two concurrent data read paths. Both the X and Y data spaces support Modulo Addressing mode for all instructions, subject to addressing mode restrictions. Bit-Reversed Addressing mode is only supported for writes to X data space. All data memory writes, including in DSP instructions, view data space as combined X and Y address space. The boundary between the X and Y data spaces is device-dependent and is not user-programmable. All effective addresses are 16 bits wide and point to bytes within the data space. Therefore, the data space address range is 64 Kbytes, or 32K words, though the implemented memory locations vary by device. Some devices contain 1 Kbyte of dual ported DMA RAM, which is located at the end of Y data space. Memory locations that are part of Y data RAM and are in the DMA RAM space are accessible simultaneously by the CPU and the DMA controller module. DMA RAM is utilized by the DMA controller to store data to be transferred to various peripherals using DMA, as well as data transferred from various peripherals using DMA. The DMA RAM can be accessed by the DMA controller without having to steal cycles from the CPU. When the CPU and the DMA controller attempt to concurrently write to the same DMA RAM location, the hardware ensures that the CPU is given precedence in accessing the DMA RAM location. Therefore, the DMA RAM provides a reliable means of transferring DMA data without ever having to stall the CPU. 2009 Microchip Technology Inc. Preliminary DS70591B-page 53 TABLE 4-1: Bit 14 Working Register 0 Working Register 1 Working Register 2 Working Register 3 Working Register 4 Working Register 5 Working Register 6 Working Register 7 Working Register 8 Working Register 9 Working Register 10 Working Register 11 Working Register 12 Working Register 13 Working Register 14 Working Register 15 Stack Pointer Limit Register ACCAL ACCAH ACCA<39> ACCA<39> ACCBL ACCBH ACCB<39> ACCB<39> -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- DCOUNT<15:0> DOSTARTL<15:1> -- -- OB -- YMODEN -- -- -- US SA SB -- -- -- OAB EDT -- -- -- -- -- SAB -- DOENDL<15:1> -- DA DL<2:0> BWM<3:0> -- DC -- IPL2 SATA -- IPL1 SATB IPL0 SATDW YWM<3:0> RA ACCSAT DOENDH N IPL3 OV PSV Z RND XWM<3:0> C IF -- -- -- DOSTARTH<5:0> 0 0 ACCB<39> ACCB<39> ACCB<39> ACCB<39> ACCB<39> -- -- -- ACCBU Program Counter High Byte Register Table Page Address Pointer Register Program Memory Visibility Page Address Pointer Register Program Counter Low Word Register ACCA<39> ACCA<39> ACCA<39> ACCA<39> ACCA<39> ACCAU Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0800 xxxx xxxx xxxx xxxx xxxx xxxx xxxx 0000 0000 0000 0000 xxxx xxxx xxxx 00xx xxxx 00xx 0000 0000 0000 CPU CORE REGISTER MAP SFR Name SFR Addr Bit 15 WREG0 0000 WREG1 0002 DS70591B-page 54 WREG2 0004 WREG3 0006 WREG4 0008 WREG5 000A WREG6 000C WREG7 000E WREG8 0010 WREG9 0012 WREG10 0014 WREG11 0016 WREG12 0018 WREG13 001A WREG14 001C WREG15 001E SPLIM 0020 ACCAL 0022 ACCAH 0024 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 Preliminary -- -- -- Repeat Loop Counter Register ACCAU 0026 ACCA<39> ACCBL 0028 ACCBH 002A ACCBU 002C ACCB<39> PCL 002E PCH 0030 -- TBLPAG 0032 -- PSVPAG 0034 -- RCOUNT 0036 DCOUNT 0038 DOSTARTL 003A DOSTARTH 003C -- DOENDL 003E DOENDH 0040 -- SR 0042 OA CORCON 0044 -- MODCON 0046 XMODEN 2009 Microchip Technology Inc. Legend: x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. TABLE 4-1: Bit 14 XS<15:1> XE<15:1> YS<15:1> YE<15:1> XB<14:0> -- Disable Interrupts Counter Register 0 1 0 1 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 CPU CORE REGISTER MAP (CONTINUED) All Resets xxxx xxxx xxxx xxxx xxxx xxxx SFR Name SFR Addr Bit 15 XMODSRT 0048 XMODEND 004A YMODSRT 004C YMODEND 004E XBREV 0050 BREN DISICNT 0052 -- 2009 Microchip Technology Inc. Legend: x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 Preliminary DS70591B-page 55 TABLE 4-2: Bit 13 CN13IE -- CN8PUE -- CN7PUE CN6PUE CN5PUE CN4PUE CN3PUE CN2PUE CN1PUE -- -- -- -- -- CN23IE CN22IE CN21IE CN20IE CN19IE CN18IE CN17IE CN16IE CN0PUE CN12IE CN11IE CN10IE CN9IE CN8IE CN7IE CN6IE CN5IE CN4IE CN3IE CN2IE CN1IE CN0IE Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets 0000 0000 0000 0000 CHANGE NOTIFICATION REGISTER MAP FOR dsPIC33FJ32GS608/610 AND dsPIC33FJ64GS608/610 DEVICES File Name SFR Addr Bit 15 Bit 14 CNEN1 0060 CN15IE CN14IE CNEN2 0062 -- -- -- -- -- -- -- DS70591B-page 56 CN23PUE CN22PUE CN21PUE CN20PUE CN19PUE CN18PUE CN17PUE CN16PUE Bit 13 CN13IE -- CN8PUE -- CN23PUE CN22PUE -- -- CN7PUE CN6PUE CN5PUE CN4PUE -- -- -- -- -- CN23IE CN22IE -- -- CN12IE CN11IE CN10IE CN9IE CN8IE CN7IE CN6IE CN5IE CN4IE CN3IE -- CN3PUE -- Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 CN2IE CN18IE CN2PUE Bit 1 CN1IE CN17IE CN1PUE Bit 0 CN0IE CN16IE CN0PUE CN18PUE CN17PUE CN16PUE All Resets 0000 0000 0000 0000 -- -- -- -- -- CNPU1 0068 CN15PUE CN14PUE CN13PUE CN12PUE CN11PUE CN10PUE CN9PUE CNPU2 006A -- -- Legend: x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. TABLE 4-3: CHANGE NOTIFICATION REGISTER MAP FOR dsPIC33FJ32GS406/606 AND DSPIC33FJ64GS406/606 DEVICES File Name SFR Addr Bit 15 Bit 14 CNEN1 0060 CN15IE CN14IE CNEN2 0062 -- -- CNPU1 0068 CN15PUE CN14PUE CN13PUE CN12PUE CN11PUE CN10PUE CN9PUE CNPU2 006A -- -- dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 Preliminary Legend: x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. 2009 Microchip Technology Inc. TABLE 4-4: Bit 13 OVATE -- SPI1IF OC4IF -- QEI1IF -- -- -- -- SPI1IE OC4IE -- -- -- -- -- AC2IE -- -- -- -- -- -- -- -- -- -- -- -- -- -- QEI1IP<2:0> U2EIP<2:0> C1TXIP<2:0> -- -- -- ADCP9IP<2:0> -- -- -- -- -- -- -- -- -- PWM9IE -- -- PWM8IE ADCP7IE IC1IP<2:0> IC2IP<2:0> SPI1EIP<2:0> ADIP<2:0> MI2C1IP<2:0> -- OC3IP<2:0> INT2IP<2:0> SPI2IP<2:0> IC3IP<2:0> SI2C2IP<2:0> INT3IP<2:0> PSEMIP<2:0> U1EIP<2:0> -- PSESMIP<2:0> ADCP8IP<2:0> -- -- C1TXIE -- INT4IE INT3IE IC4IE IC3IE -- -- PWM7IE ADCP6IE -- -- -- QEI1IE -- -- -- -- OC1IP<2:0> OC2IP<2:0> SPI1IP<2:0> DMA1IP<2:0> AC1IP<2:0> -- OC4IP<2:0> U2RXIP<2:0> C1RXIP<2:0> IC4IP<2:0> MI2C2IP<2:0> INT4IP<2:0> -- -- -- AC4IE AC3IE -- -- PSESMIE -- PSEMIE -- -- -- OC3IE DMA2IE INT1IE DMA3IE SPI1EIE T3IE T2IE OC2IE IC2IE DMA0IE -- -- -- -- ADCP7IF ADCP6IF AC4IF AC3IF AC2IF PWM9IF PWM8IF PWM7IF PWM6IF T1IE CNIE C1IE -- -- PWM6IE -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- PSESMIF -- -- C1TXIF -- -- -- PSEMIF -- -- INT4IF INT3IF -- -- MI2C2IF U2EIF -- -- -- IC4IF IC3IF DMA3IF C1IF C1RXIF OC3IF DMA2IF -- -- -- INT1IF CNIF AC1IF SPI1EIF T3IF T2IF OC2IF IC2IF DMA0IF T1IF OC1IF IC1IF MI2C1IF SPI2IF SI2C2IF U1EIF -- -- -- -- -- INT4EP INT3EP INT2EP INT1EP OVBTE COVTE SFTACERR DIV0ERR DMACERR MATHERR ADDRERR STKERR OSCFAIL -- INT0EP INT0IF SI2C1IF SPI2EIF -- -- -- PWM5IF PWM4IF PWM3IF OC1IE AC1IE C1RXIE MI2C2IE U2EIE IC1IE MI2C1IE SPI2IE SI2C2IE U1EIE ADCP11IE ADCP10IE ADCP9IE ADCP8IE INT0IE SI2C1IE SPI2EIE -- -- -- PWM5IE PWM4IE PWM3IE ADCP5IE ADCP4IE ADCP3IE ADCP2IE INT0IP<2:0> DMA0IP<2:0> T3IP<2:0> U1TXIP<2:0> SI2C1IP<2:0> INT1IP<2:0> DMA2IP<2:0> T5IP<2:0> SPI2EIP<2:0> DMA3IP<2:0> -- -- -- -- -- -- -- -- -- -- -- -- -- -- Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33FJ64GS610 DEVICES All Resets 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 4444 4444 0444 0044 4444 0004 4444 4444 4444 0444 0440 0440 0440 0440 0400 4040 4440 File Name -- ADIF INT2IF -- -- -- -- -- -- U1TXIE T5IE -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- QEI2IE -- -- T4IE U1RXIE -- -- -- -- -- ADIE INT2IE -- -- -- -- -- T1IP<2:0> T2IP<2:0> U1RXIP<2:0> -- CNIP<2:0> -- T4IP<2:0> U2TXIP<2:0> C1IP<2:0> -- -- -- -- -- -- QEI2IP<2:0> -- QEI2IF -- -- -- -- T5IF T4IF U1TXIF U1RXIF -- -- SFR Addr Bit 15 Bit 14 INTCON1 0080 NSTDIS OVAERR OVBERR COVAERR COVBERR INTCON2 0082 ALTIVT DISI IFS0 0084 -- DMA1IF IFS1 0086 U2TXIF U2RXIF IFS2 0088 -- -- IFS3 008A -- -- 2009 Microchip Technology Inc. ADCP11IF ADCP10IF ADCP9IF ADCP8IF ADCP5IF ADCP4IF ADCP3IF ADCP2IF IFS4 008C -- -- IFS5 008E PWM2IF PWM1IF ADCP12IF IFS6 0090 ADCP1IF ADCP0IF IFS7 0092 -- -- IEC0 0094 -- DMA1IE IEC1 0096 U2TXIE U2RXIE IEC2 0098 -- -- IEC3 009A -- -- IEC4 009C -- -- IEC5 009E PWM2IE PWM1IE ADCP12IE IEC6 00A0 ADCP1IE ADCP0IE IEC7 00A2 -- -- dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 Preliminary IPC0 00A4 -- IPC1 00A6 -- IPC2 00A8 -- IPC3 00AA -- -- IPC4 00AC -- IPC5 00AE -- -- IPC6 00B0 -- IPC7 00B2 -- IPC8 00B4 -- IPC9 00B6 -- -- IPC12 00BC -- -- IPC13 00BE -- -- IPC14 00C0 -- -- IPC16 00C4 -- -- IPC17 00C6 -- -- IPC18 00C8 -- IPC20 00CC -- ADCP10IP<2:0> DS70591B-page 57 Legend: x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. TABLE 4-4: Bit 13 -- PWM2IP<2:0> PWM6IP<2:0> AC2IP<2:0> -- ADCP1IP<2:0> ADCP5IP<2:0> -- -- -- ILR<3:0> -- VECNUM<6:0> -- -- -- -- -- -- ADCP7IP<2:0> -- -- ADCP4IP<2:0> -- ADCP3IP<2:0> -- -- ADCP0IP<2:0> -- -- -- -- -- -- -- ADCP2IP<2:0> ADCP6IP<2:0> -- -- -- -- -- -- AC4IP<2:0> -- -- PWM9IP<2:0> -- PWM8IP<2:0> -- PWM7IP<2:0> AC3IP<2:0> -- -- PWM5IP<2:0> -- PWM4IP<2:0> -- PWM3IP<2:0> -- PWM1IP<2:0> -- -- -- -- -- -- -- -- -- -- -- -- -- -- ADCP12IP<2:0> -- ADCP11IP<2:0> Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets 0044 4400 4444 4444 0044 4400 4444 0044 0000 INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33FJ64GS610 DEVICES (CONTINUED) File Name SFR Addr Bit 15 Bit 14 IPC21 00CE -- -- IPC23 00D2 -- DS70591B-page 58 IPC24 00D4 -- IPC25 00D6 -- IPC26 00D8 -- -- IPC27 00DA -- IPC28 00DC -- IPC29 00DE -- -- INTTREG 00E0 -- -- Legend: x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 Preliminary 2009 Microchip Technology Inc. TABLE 4-5: Bit 13 OVATE -- SPI1IF OC4IF -- -- -- -- -- AC2IF -- T2IE -- -- -- -- -- AC2IE -- -- -- -- -- -- -- -- -- -- -- -- -- INT4IP<2:0> QEI1IP<2:0> U2EIP<2:0> C1TXIP<2:0> -- -- -- -- -- -- -- -- -- -- -- -- -- -- PWM8IE ADCP7IE IC1IP<2:0> IC2IP<2:0> SPI1EIP<2:0> ADIP<2:0> MI2C1IP<2:0> -- OC3IP<2:0> INT2IP<2:0> SPI2IP<2:0> IC3IP<2:0> SI2C2IP<2:0> INT3IP<2:0> PSEMIP<2:0> U1EIP<2:0> -- PSESMIP<2:0> -- -- C1TXIE -- INT4IE INT3IE IC4IE IC3IE -- -- -- PWM7IE ADCP6IE -- -- INT1IE DMA3IE OC2IE IC2IE DMA0IE -- ADCP7IF ADCP6IF -- PWM8IF PWM7IF PWM6IF ADCP5IF T1IE CNIE C1IE -- -- -- PWM6IE ADCP5IE -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- C1TXIF -- -- -- INT4IF INT3IF -- -- MI2C2IF U2EIF -- PWM5IF OC1IE AC1IE C1RXIE MI2C2IE U2EIE -- PWM5IE IC4IF IC3IF DMA3IF C1IF C1RXIF -- -- INT1IF CNIF AC1IF -- QEI1IF -- -- -- -- SPI1IE OC4IE -- QEI1IE -- -- -- -- OC1IP<2:0> OC2IP<2:0> SPI1IP<2:0> DMA1IP<2:0> AC1IP<2:0> -- OC4IP<2:0> U2RXIP<2:0> C1RXIP<2:0> IC4IP<2:0> MI2C2IP<2:0> -- -- -- AC4IE AC3IE -- -- PSESMIE -- PSEMIE -- -- -- OC3IE DMA2IE SPI1EIE T3IE -- -- AC4IF AC3IF -- -- PSESMIF -- PSEMIF -- -- -- OC3IF DMA2IF SPI1EIF T3IF T2IF OC2IF IC2IF DMA0IF T1IF OC1IF IC1IF MI2C1IF SPI2IF SI2C2IF U1EIF ADCP8IF -- -- -- -- -- INT4EP INT3EP INT2EP INT1EP OVBTE COVTE SFTACERR DIV0ERR DMACERR MATHERR ADDRERR STKERR OSCFAIL -- INT0EP INT0IF SI2C1IF SPI2EIF -- -- -- PWM4IF PWM3IF ADCP4IF ADCP3IF ADCP2IF IC1IE SPI2IE SI2C2IE U1EIE ADCP8IE INT0IE MI2C1IE SI2C1IE SPI2EIE -- -- -- PWM4IE PWM3IE ADCP4IE ADCP3IE ADCP2IE INT0IP<2:0> DMA0IP<2:0> T3IP<2:0> U1TXIP<2:0> SI2C1IP<2:0> INT1IP<2:0> DMA2IP<2:0> T5IP<2:0> SPI2EIP<2:0> DMA3IP<2:0> -- -- -- -- -- -- -- -- -- -- -- -- Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33FJ64GS608 DEVICES All Resets 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 4444 4444 4444 4444 4444 0004 4444 4444 4444 0444 0440 0440 0440 0440 0400 4040 SFR Name SFR Addr Bit 15 Bit 14 INTCON1 0080 NSTDIS OVAERR OVBERR COVAERR COVBERR -- ADIF INT2IF -- -- -- -- -- -- U1TXIE T5IE -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- QEI2IE -- -- T4IE U1RXIE -- -- -- -- -- ADIE INT2IE -- -- -- -- -- T1IP<2:0> T2IP<2:0> U1RXIP<2:0> -- CNIP<2:0> -- T4IP<2:0> U2TXIP<2:0> C1IP<2:0> -- -- -- -- -- -- QEI2IP<2:0> -- QEI2IF -- -- -- -- T5IF T4IF U1TXIF U1RXIF -- -- INTCON2 0082 ALTIVT DISI IFS0 0084 -- DMA1IF IFS1 0086 U2TXIF U2RXIF IFS2 0088 -- -- IFS3 008A -- -- 2009 Microchip Technology Inc. IFS4 008C -- -- IFS5 008E PWM2IF PWM1IF ADCP12IF IFS6 0090 ADCP1IF ADCP0IF IFS7 0092 -- -- IEC0 0094 -- DMA1IE IEC1 0096 U2TXIE U2RXIE IEC2 0098 -- -- IEC3 009A -- -- IEC4 009C -- -- IEC5 009E PWM2IE PWM1IE ADCP12IE IEC6 00A0 ADCP1IE ADCP0IE IEC7 00A2 -- -- dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 Preliminary IPC0 00A4 -- IPC1 00A6 -- IPC2 00A8 -- IPC3 00AA -- -- IPC4 00AC -- IPC5 00AE -- -- IPC6 00B0 -- IPC7 00B2 -- IPC8 00B4 -- IPC9 00B6 -- -- IPC12 00BC -- -- IPC13 00BE -- -- IPC14 00C0 -- -- IPC16 00C4 -- -- IPC17 00C6 -- -- IPC18 00C8 -- DS70591B-page 59 Legend: x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. TABLE 4-5: Bit 13 -- -- PWM2IP<2:0> PWM6IP<2:0> AC2IP<2:0> -- ADCP1IP<2:0> ADCP5IP<2:0> -- -- -- ILR<3:0> -- VECNUM<6:0> -- -- -- -- -- -- ADCP7IP<2:0> -- -- ADCP4IP<2:0> -- ADCP3IP<2:0> -- -- ADCP0IP<2:0> -- -- -- -- -- -- -- -- -- -- -- -- AC4IP<2:0> -- -- -- -- -- -- PWM8IP<2:0> -- -- PWM5IP<2:0> -- PWM4IP<2:0> -- PWM3IP<2:0> PWM7IP<2:0> AC3IP<2:0> -- ADCP2IP<2:0> ADCP6IP<2:0> -- -- PWM1IP<2:0> -- -- -- -- -- -- -- -- -- -- -- -- -- ADCP12IP -- -- -- -- -- -- -- -- -- -- -- ADCP8IP<2:0> -- -- -- -- Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets 0040 0040 4400 4444 4044 0044 4400 4444 0044 0000 INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33FJ64GS608 DEVICES (CONTINUED) SFR Name SFR Addr Bit 15 Bit 14 IPC20 00CC -- -- IPC21 00CE -- -- DS70591B-page 60 IPC23 00D2 -- IPC24 00D4 -- IPC25 00D6 -- IPC26 00D8 -- -- IPC27 00DA -- IPC28 00DC -- IPC29 00DE -- -- INTTREG 00E0 -- -- Legend: x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 Preliminary 2009 Microchip Technology Inc. TABLE 4-6: Bit 13 OVATE -- SPI1IF OC4IF -- -- -- -- -- AC2IF -- T2IE -- -- -- -- -- AC2IE -- -- -- -- -- -- -- -- -- -- -- -- -- INT4IP<2:0> QEI1IP<2:0> U2EIP<2:0> C1TXIP<2:0> -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- IC1IP<2:0> IC2IP<2:0> SPI1EIP<2:0> ADIP<2:0> MI2C1IP<2:0> -- OC3IP<2:0> INT2IP<2:0> SPI2IP<2:0> IC3IP<2:0> SI2C2IP<2:0> INT3IP<2:0> PSEMIP<2:0> U1EIP<2:0> -- PSESMIP<2:0> -- -- C1TXIE -- INT4IE INT3IE IC4IE IC3IE -- -- -- -- ADCP6IE -- -- INT1IE DMA3IE OC2IE IC2IE DMA0IE -- -- ADCP6IF -- -- -- PWM6IF T1IE CNIE C1IE -- -- -- PWM6IE -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- C1TXIF -- -- -- INT4IF INT3IF -- -- MI2C2IF U2EIF -- IC4IF IC3IF DMA3IF C1IF C1RXIF -- -- INT1IF CNIF AC1IF -- QEI1IF -- -- -- -- SPI1IE OC4IE -- QEI1IE -- -- -- -- OC1IP<2:0> OC2IP<2:0> SPI1IP<2:0> DMA1IP<2:0> AC1IP<2:0> -- OC4IP<2:0> U2RXIP<2:0> C1RXIP<2:0> IC4IP<2:0> MI2C2IP<2:0> -- -- -- AC4IE AC3IE -- -- PSESMIE -- PSEMIE -- -- -- OC3IE DMA2IE SPI1EIE T3IE -- -- AC4IF AC3IF -- -- PSESMIF -- PSEMIF -- -- -- OC3IF DMA2IF SPI1EIF T3IF T2IF OC2IF IC2IF DMA0IF T1IF OC1IF IC1IF MI2C1IF SPI2IF SI2C2IF U1EIF ADCP8IF -- -- -- -- -- INT4EP INT3EP INT2EP INT1EP OVBTE COVTE SFTACERR DIV0ERR DMACERR MATHERR ADDRERR STKERR OSCFAIL -- INT0EP INT0IF SI2C1IF SPI2EIF -- -- -- PWM5IF PWM4IF PWM3IF OC1IE AC1IE C1RXIE MI2C2IE U2EIE -- IC1IE MI2C1IE SPI2IE SI2C2IE U1EIE ADCP8IE INT0IE SI2C1IE SPI2EIE -- -- -- PWM5IE PWM4IE PWM3IE ADCP5IE ADCP4IE ADCP3IE ADCP2IE INT0IP<2:0> DMA0IP<2:0> T3IP<2:0> U1TXIP<2:0> SI2C1IP<2:0> INT1IP<2:0> DMA2IP<2:0> T5IP<2:0> SPI2EIP<2:0> DMA3IP<2:0> -- -- -- -- -- -- -- -- -- -- -- -- Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33FJ64GS606 DEVICES All Resets 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 4444 4444 4444 4444 4444 0004 4444 4444 4444 0444 0440 0440 0440 0440 0400 4040 SFR Name SFR Addr Bit 15 Bit 14 INTCON1 0080 NSTDIS OVAERR OVBERR COVAERR COVBERR -- ADIF INT2IF -- -- -- -- -- -- U1TXIE T5IE -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- QEI2IE -- -- T4IE U1RXIE -- -- -- -- -- ADIE INT2IE -- -- -- -- -- T1IP<2:0> T2IP<2:0> U1RXIP<2:0> -- CNIP<2:0> -- T4IP<2:0> U2TXIP<2:0> C1IP<2:0> -- -- -- -- -- -- QEI2IP<2:0> -- QEI2IF -- -- -- -- T5IF T4IF U1TXIF U1RXIF -- -- INTCON2 0082 ALTIVT DISI IFS0 0084 -- DMA1IF IFS1 0086 U2TXIF U2RXIF IFS2 0088 -- -- IFS3 008A -- -- 2009 Microchip Technology Inc. ADCP5IF ADCP4IF ADCP3IF ADCP2IF IFS4 008C -- -- IFS5 008E PWM2IF PWM1IF ADCP12IF IFS6 0090 ADCP1IF ADCP0IF IFS7 0092 -- -- IEC0 0094 -- DMA1IE IEC1 0096 U2TXIE U2RXIE IEC2 0098 -- -- IEC3 009A -- -- IEC4 009C -- -- IEC5 009E PWM2IE PWM1IE ADCP12IE IEC6 00A0 ADCP1IE ADCP0IE IEC7 00A2 -- -- dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 Preliminary IPC0 00A4 -- IPC1 00A6 -- IPC2 00A8 -- IPC3 00AA -- -- IPC4 00AC -- IPC5 00AE -- -- IPC6 00B0 -- IPC7 00B2 -- IPC8 00B4 -- IPC9 00B6 -- -- IPC12 00BC -- -- IPC13 00BE -- -- IPC14 00C0 -- -- IPC16 00C4 -- -- IPC17 00C6 -- -- IPC18 00C8 -- DS70591B-page 61 Legend: x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. TABLE 4-6: Bit 13 -- -- PWM2IP<2:0> PWM6IP<2:0> AC2IP<2:0> -- ADCP1IP<2:0> ADCP5IP<2:0> -- -- -- ILR<3:0> -- VECNUM<6:0> -- -- -- -- -- -- -- -- -- -- -- ADCP4IP<2:0> -- ADCP3IP<2:0> -- -- ADCP0IP<2:0> -- -- -- -- -- -- -- -- -- -- -- -- AC4IP<2:0> -- -- -- -- -- -- -- -- -- -- -- -- AC3IP<2:0> -- ADCP2IP<2:0> ADCP6IP<2:0> -- -- PWM5IP<2:0> -- PWM4IP<2:0> -- PWM3IP<2:0> -- -- PWM1IP<2:0> -- -- -- -- -- -- -- -- -- -- -- -- -- -- ADCP12IP<2:0> -- -- -- -- -- -- -- -- -- -- ADCP8IP<2:0> -- -- -- -- Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets 0040 0040 4400 4444 4000 0044 4400 4444 0004 0000 INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33FJ64GS606 DEVICES (CONTINUED) SFR Name SFR Addr Bit 15 Bit 14 IPC20 00CC -- -- IPC21 00CE -- -- DS70591B-page 62 IPC23 00D2 -- IPC24 00D4 -- IPC25 00D6 -- IPC26 00D8 -- -- IPC27 00DA -- IPC28 00DC -- IPC29 00DE -- -- INTTREG 00E0 -- -- Legend: x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 Preliminary 2009 Microchip Technology Inc. TABLE 4-7: Bit 13 OVATE -- -- IC2IF -- IC3IF INT3IF -- -- -- -- IC2IE -- IC3IE INT3IE -- -- -- -- IC1IP<2:0> IC2IP<2:0> SPI1EIP<2:0> -- -- -- -- -- -- -- -- -- INT4IP<2:0> QEI1IP<2:0> U2EIP<2:0> -- -- -- -- -- -- -- -- -- -- -- -- ADIP<2:0> MI2C1IP<2:0> -- OC3IP<2:0> INT2IP<2:0> SPI2IP<2:0> IC3IP<2:0> SI2C2IP<2:0> INT3IP<2:0> PSEMIP<2:0> U1EIP<2:0> PSESMIP<2:0> ADCP8IP<2:0> -- -- -- -- -- -- ADCP6IE INT1IE -- ADCP6IF -- PWM6IF T1IE CNIE -- -- -- -- PWM6IE -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- MI2C2IF U2EIF -- -- -- -- INT1IF CNIF -- -- T1IF OC1IF IC1IF MI2C1IF SPI2IF SI2C2IF U1EIF ADCP8IF INT4EP INT3EP INT2EP INT1EP MATHERR ADDRERR STKERR OSCFAIL -- SPI1IF OC4IF -- -- -- -- -- -- -- T3IE -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- INT4IE -- IC4IE -- -- T2IE OC2IE -- -- -- -- -- -- -- -- -- INT4IF -- IC4IF -- -- -- QEI1IF -- -- -- -- SPI1IE OC4IE -- QEI1IE -- -- -- -- OC1IP<2:0> OC2IP<2:0> SPI1IP<2:0> -- -- -- OC4IP<2:0> U2RXIP<2:0> -- -- IC4IP<2:0> MI2C2IP<2:0> -- -- -- -- -- -- PSESMIE PSEMIE -- OC3IE SPI1EIE -- -- -- PSESMIF PSEMIF -- OC3IF SPI1EIF T3IF T2IF OC2IF -- -- -- -- OVBTE COVTE SFTACERR DIV0ERR -- INT0EP INT0IF SI2C1IF SPI2EIF -- -- -- PWM5IF PWM4IF PWM3IF OC1IE -- -- MI2C2IE U2EIE -- IC1IE MI2C1IE SPI2IE SI2C2IE U1EIE ADCP8IE INT0IE SI2C1IE SPI2EIE -- -- -- PWM5IE PWM4IE PWM3IE ADCP5IE ADCP4IE ADCP3IE ADCP2IE INT0IP<2:0> -- T3IP<2:0> U1TXIP<2:0> SI2C1IP<2:0> INT1IP<2:0> -- T5IP<2:0> SPI2EIP<2:0> -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33FJ32GS406 AND DSPIC33FJ64GS406 DEVICES All Resets 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 4444 4440 4444 0044 4444 0004 4440 4444 0044 0440 0440 0440 0440 0440 0040 0040 SFR Name SFR Addr Bit 15 Bit 14 INTCON1 0080 -- ADIF INT2IF -- -- -- -- -- -- U1TXIE T5IE -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- T4IE U1RXIE -- -- -- -- -- ADIE INT2IE -- -- -- -- -- T1IP<2:0> T2IP<2:0> U1RXIP<2:0> -- CNIP<2:0> -- T4IP<2:0> U2TXIP<2:0> -- -- -- -- -- -- -- -- -- -- -- -- -- -- T5IF T4IF U1TXIF U1RXIF -- -- NSTDIS OVAERR OVBERR COVAERR COVBERR INTCON2 0082 ALTIVT DISI IFS0 0084 -- -- IFS1 0086 U2TXIF U2RXIF IFS2 0088 -- -- IFS3 008A -- -- 2009 Microchip Technology Inc. ADCP5IF ADCP4IF ADCP3IF ADCP2IF IFS4 008C -- -- IFS5 008E PWM2IF PWM1IF ADCP12IF IFS6 0090 ADCP1IF ADCP0IF IFS7 0092 -- -- IEC0 0094 -- -- IEC1 0096 U2TXIE U2RXIE IEC2 0098 -- -- IEC3 009A -- -- IEC4 009C -- -- IEC5 009E PWM2IE PWM1IE ADCP12IE IEC6 00A0 ADCP1IE ADCP0IE IEC7 00A2 -- -- dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 Preliminary IPC0 00A4 -- IPC1 00A6 -- IPC2 00A8 -- IPC3 00AA -- -- IPC4 00AC -- IPC5 00AE -- -- IPC6 00B0 -- IPC7 00B2 -- IPC8 00B4 -- -- IPC9 00B6 -- -- IPC12 00BC -- -- IPC13 00BE -- -- IPC14 00C0 -- -- IPC16 00C4 -- -- IPC18 00C8 -- -- IPC20 00CC -- -- DS70591B-page 63 Legend: x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. TABLE 4-7: Bit 13 -- PWM2IP<2:0> PWM6IP<2:0> ADCP1IP<2:0> ADCP5IP<2:0> -- -- -- ILR<3:0> -- VECNUM<6:0> -- -- -- -- -- -- -- -- -- -- -- ADCP4IP<2:0> -- ADCP3IP<2:0> -- -- ADCP0IP<2:0> -- -- -- -- -- -- -- ADCP2IP<2:0> ADCP6IP<2:0> -- PWM5IP<2:0> -- PWM4IP<2:0> -- PWM3IP<2:0> -- -- PWM1IP<2:0> -- -- -- -- -- -- -- -- -- -- -- -- -- -- ADCP12IP<2:0> -- -- -- -- Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets 0040 4400 4444 4400 4444 0004 0000 INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33FJ32GS406 AND DSPIC33FJ64GS406 DEVICES (CONTINUED) SFR Name SFR Addr Bit 15 Bit 14 IPC21 00CE -- -- IPC23 00D2 -- DS70591B-page 64 IPC24 00D4 -- IPC27 00DA -- IPC28 00DC -- IPC29 00DE -- -- INTTREG 00E0 -- -- Legend: x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 Preliminary 2009 Microchip Technology Inc. TABLE 4-8: Bit 13 OVATE -- -- IC2IF -- IC3IF INT3IF -- -- PWM7IF -- INT1IE -- -- -- PWM7IE ADCP7IE ADCP6IE IC1IP<2:0> IC2IP<2:0> SPI1EIP<2:0> ADIP<2:0> -- -- -- -- -- -- -- -- -- INT4IP<2:0> QEI1IP<2:0> U2EIP<2:0> -- -- ADCP9IP<2:0> -- -- -- -- -- -- -- MI2C1IP<2:0> -- OC3IP<2:0> INT2IP<2:0> SPI2IP<2:0> IC3IP<2:0> SI2C2IP<2:0> INT3IP<2:0> PSEMIP<2:0> U1EIP<2:0> PSESMIP<2:0> ADCP8IP<2:0> -- T1IE CNIE -- -- -- PWM6IE ADCP5IE -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- PWM6IF ADCP5IF ADCP7IF ADCP6IF IC2IE -- IC3IE INT3IE -- -- -- -- -- -- MI2C2IF U2EIF PWM5IF ADCP4IF OC1IE AC1IE -- MI2C2IE U2EIE ADCP11IE ADCP10IE ADCP9IE PWM5IE ADCP4IE -- -- -- INT1IF CNIF AC1IF -- T1IF OC1IF IC1IF MI2C1IF SPI2IF SI2C2IF U1EIF ADCP8IF PWM4IF IC1IE MI2C1IE SPI2IE SI2C2IE U1EIE ADCP8IE PWM4IE INT0IP<2:0> -- T3IP<2:0> U1TXIP<2:0> SI2C1IP<2:0> INT1IP<2:0> -- T5IP<2:0> SPI2EIP<2:0> -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- INT4EP INT3EP INT2EP INT1EP MATHERR ADDRERR STKERR OSCFAIL -- SPI1IF OC4IF -- -- -- -- -- AC3IF -- T3IE -- -- -- -- -- AC3IE -- -- -- -- -- -- -- -- AC2IE -- -- -- -- -- INT4IE -- IC4IE -- -- T2IE OC2IE -- -- AC2IF PWM9IF PWM8IF -- -- -- -- -- INT4IF -- IC4IF -- -- -- QEI1IF -- -- -- -- SPI1IE OC4IE -- QEI1IE -- -- -- -- OC1IP<2:0> OC2IP<2:0> SPI1IP<2:0> -- AC1IP<2:0> -- OC4IP<2:0> U2RXIP<2:0> -- -- IC4IP<2:0> MI2C2IP<2:0> -- -- -- AC4IE -- PSESMIE PSEMIE -- OC3IE SPI1EIE -- AC4IF -- PSESMIF PSEMIF -- OC3IF SPI1EIF T3IF T2IF OC2IF -- -- -- -- OVBTE COVTE SFTACERR DIV0ERR -- INT0EP INT0IF SI2C1IF SPI2EIF -- -- -- PWM3IF ADCP3IF ADCP2IF INT0IE SI2C1IE SPI2EIE -- -- -- PWM3IE ADCP3IE ADCP2IE Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33FJ32GS610 DEVICES All Resets 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 4444 4440 4444 0044 4444 0004 4440 4444 0044 0440 0440 0440 0440 0440 4040 4440 SFR Name SFR Addr Bit 15 Bit 14 INTCON1 0080 NSTDIS OVAERR OVBERR COVAERR COVBERR -- ADIF INT2IF -- -- -- -- -- -- U1TXIE T5IE -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- QEI2IE -- -- T4IE U1RXIE -- -- -- -- -- ADIE INT2IE -- -- -- -- -- T1IP<2:0> T2IP<2:0> U1RXIP<2:0> -- CNIP<2:0> -- T4IP<2:0> U2TXIP<2:0> -- -- -- -- -- -- QEI2IP<2:0> ADCP10IP<2:0> -- QEI2IF -- -- -- -- T5IF T4IF U1TXIF U1RXIF -- -- INTCON2 0082 ALTIVT DISI IFS0 0084 -- -- IFS1 0086 U2TXIF U2RXIF IFS2 0088 -- -- IFS3 008A -- -- 2009 Microchip Technology Inc. ADCP11IF ADCP10IF ADCP9IF PWM9IE PWM8IE IFS4 008C -- -- IFS5 008E PWM2IF PWM1IF ADCP12IF IFS6 0090 ADCP1IF ADCP0IF IFS7 0092 -- -- IEC0 0094 -- -- IEC1 0096 U2TXIE U2RXIE IEC2 0098 -- -- IEC3 009A -- -- IEC4 009C -- -- IEC5 009E PWM2IE PWM1IE ADCP12IE IEC6 00A0 ADCP1IE ADCP0IE IEC7 00A2 -- -- dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 Preliminary IPC0 00A4 -- IPC1 00A6 -- IPC2 00A8 -- IPC3 00AA -- -- IPC4 00AC -- IPC5 00AE -- -- IPC6 00B0 -- IPC7 00B2 -- IPC8 00B4 -- -- IPC9 00B6 -- -- IPC12 00BC -- -- IPC13 00BE -- -- IPC14 00C0 -- -- IPC16 00C4 -- -- IPC18 00C8 -- IPC20 00CC -- DS70591B-page 65 Legend: x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. TABLE 4-8: Bit 13 -- PWM2IP<2:0> PWM6IP<2:0> AC2IP<2:0> -- ADCP1IP<2:0> ADCP5IP<2:0> -- -- -- ILR<3:0> -- VECNUM<6:0> -- -- -- -- -- -- ADCP7IP<2:0> -- -- ADCP4IP<2:0> -- ADCP3IP<2:0> -- -- ADCP0IP<2:0> -- -- -- -- -- -- -- -- -- -- -- -- AC4IP<2:0> -- -- ADCP2IP<2:0> ADCP6IP<2:0> -- PWM9IP<2:0> -- PWM8IP<2:0> -- PWM7IP<2:0> AC3IP<2:0> -- -- PWM5IP<2:0> -- PWM4IP<2:0> -- PWM3IP<2:0> -- PWM1IP<2:0> -- -- -- -- -- -- -- -- -- -- -- -- -- -- ADCP12IP<2:0> -- ADCP11IP<2:0> Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets 0044 4400 4444 4444 0044 4400 4444 0044 0000 INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33FJ32GS610 DEVICES (CONTINUED) SFR Name SFR Addr Bit 15 Bit 14 IPC21 00CE -- -- IPC23 00D2 -- DS70591B-page 66 IPC24 00D4 -- IPC25 00D6 -- IPC26 00D8 -- -- IPC27 00DA -- IPC28 00DC -- IPC29 00DE -- -- INTTREG 00E0 -- -- Legend: x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 Preliminary 2009 Microchip Technology Inc. TABLE 4-9: Bit 13 OVATE -- -- IC2IF -- IC3IF INT3IF -- -- PWM8IF ADCP7IF ADCP6IF IC2IE -- IC3IE INT3IE -- -- PWM8IE IC1IP<2:0> IC2IP<2:0> SPI1EIP<2:0> -- -- -- -- -- -- -- -- -- -- INT4IP<2:0> QEI1IP<2:0> U2EIP<2:0> -- -- -- -- -- -- -- -- -- -- -- -- ADIP<2:0> MI2C1IP<2:0> -- OC3IP<2:0> INT2IP<2:0> SPI2IP<2:0> IC3IP<2:0> SI2C2IP<2:0> INT3IP<2:0> PSEMIP<2:0> U1EIP<2:0> PSESMIP<2:0> ADCP8IP<2:0> -- INT1IE -- -- -- -- PWM7IE ADCP7IE ADCP6IE -- PWM7IF -- -- PWM6IF T1IE CNIE -- -- -- -- PWM6IE -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- U2EIF -- -- -- -- MI2C2IF INT1IF CNIF AC1IF -- T1IF OC1IF IC1IF SPI2IF SI2C2IF U1EIF ADCP8IF INT4EP INT3EP INT2EP INT1EP MATHERR ADDRERR STKERR OSCFAIL -- SPI1IF OC4IF -- -- -- -- -- AC3IF -- T3IE -- -- -- -- -- AC3IE -- -- -- -- -- -- -- AC2IE -- -- -- -- -- -- INT4IE -- IC4IE -- -- T2IE OC2IE -- -- AC2IF -- -- -- -- -- -- INT4IF -- IC4IF -- -- -- QEI1IF -- -- -- -- SPI1IE OC4IE -- QEI1IE -- -- -- -- OC1IP<2:0> OC2IP<2:0> SPI1IP<2:0> -- AC1IP<2:0> -- OC4IP<2:0> U2RXIP<2:0> -- -- IC4IP<2:0> MI2C2IP<2:0> -- -- -- AC4IE -- PSESMIE PSEMIE -- OC3IE SPI1EIE -- AC4IF -- PSESMIF PSEMIF -- OC3IF SPI1EIF T3IF T2IF OC2IF -- -- -- -- OVBTE COVTE SFTACERR DIV0ERR -- INT0EP INT0IF SPI2EIF -- -- -- PWM5IF PWM4IF PWM3IF OC1IE -- -- U2EIE -- IC1IE SPI2IE MI2C2IE SI2C2IE U1EIE ADCP8IE INT0IE MI2C1IE SI2C1IE SPI2EIE -- -- -- PWM5IE PWM4IE PWM3IE INT0IP<2:0> -- T3IP<2:0> U1TXIP<2:0> SI2C1IP<2:0> INT1IP<2:0> -- T5IP<2:0> SPI2EIP<2:0> -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33FJ32GS608 All Resets 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 ADCP5IE ADCP4IE ADCP3IE ADCP2IE 0000 4444 4440 4444 0044 4444 0004 4440 4444 0044 0440 0440 0440 0440 0440 4040 0040 SFR Name SFR Addr Bit 15 Bit 14 INTCON1 0080 -- ADIF INT2IF -- -- -- -- -- -- U1TXIE T5IE -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- QEI2IE -- -- T4IE U1RXIE -- -- -- -- -- ADIE INT2IE -- -- -- -- -- T1IP<2:0> T2IP<2:0> U1RXIP<2:0> -- CNIP<2:0> -- T4IP<2:0> U2TXIP<2:0> -- -- -- -- -- -- QEI2IP<2:0> -- -- QEI2IF -- -- -- -- T5IF T4IF U1TXIF U1RXIF -- -- NSTDIS OVAERR OVBERR COVAERR COVBERR INTCON2 0082 ALTIVT DISI IFS0 0084 -- -- IFS1 0086 U2TXIF U2RXIF MI2C1IF SI2C1IF IFS2 0088 -- -- IFS3 008A -- -- 2009 Microchip Technology Inc. IFS4 008C -- -- IFS5 008E PWM2IF PWM1IF ADCP12IF IFS6 0090 ADCP1IF ADCP0IF IFS7 0092 -- -- ADCP5IF ADCP4IF ADCP3IF ADCP2IF 0000 IEC0 0094 -- -- IEC1 0096 U2TXIE U2RXIE IEC2 0098 -- -- IEC3 009A -- -- IEC4 009C -- -- IEC5 009E PWM2IE PWM1IE ADCP12IE IEC6 00A0 ADCP1IE ADCP0IE IEC7 00A2 -- -- dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 Preliminary IPC0 00A4 -- IPC1 00A6 -- IPC2 00A8 -- IPC3 00AA -- -- IPC4 00AC -- IPC5 00AE -- -- IPC6 00B0 -- IPC7 00B2 -- IPC8 00B4 -- -- IPC9 00B6 -- -- IPC12 00BC -- -- IPC13 00BE -- -- IPC14 00C0 -- -- IPC16 00C4 -- -- IPC18 00C8 -- IPC20 00CC -- -- DS70591B-page 67 Legend: x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. TABLE 4-9: Bit 13 -- PWM2IP<2:0> PWM6IP<2:0> AC2IP<2:0> -- ADCP1IP<2:0> ADCP5IP<2:0> -- -- -- ILR<3:0> -- VECNUM<6:0> -- -- -- -- -- -- ADCP7IP<2:0> -- -- ADCP4IP<2:0> -- ADCP3IP<2:0> -- -- ADCP0IP<2:0> -- -- -- -- -- -- -- -- -- -- -- -- AC4IP<2:0> -- -- ADCP2IP<2:0> ADCP6IP<2:0> -- -- -- -- -- PWM8IP<2:0> -- PWM7IP<2:0> AC3IP<2:0> -- -- PWM5IP<2:0> -- PWM4IP<2:0> -- PWM3IP<2:0> -- PWM1IP<2:0> -- -- -- -- -- -- -- -- -- -- -- -- -- -- ADCP12IP<2:0> -- -- -- -- Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets 0040 4400 4444 4044 0044 4400 4444 0044 0000 INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33FJ32GS608 (CONTINUED) SFR Name SFR Addr Bit 15 Bit 14 IPC21 00CE -- -- IPC23 00D2 -- DS70591B-page 68 IPC24 00D4 -- IPC25 00D6 -- IPC26 00D8 -- -- IPC27 00DA -- IPC28 00DC -- IPC29 00DE -- -- INTTREG 00E0 -- -- Legend: x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 Preliminary 2009 Microchip Technology Inc. TABLE 4-10: Bit 13 OVATE -- -- IC2IF -- IC3IF INT3IF -- -- -- -- IC2IE -- IC3IE INT3IE -- -- -- -- IC1IP<2:0> IC2IP<2:0> SPI1EIP<2:0> -- -- -- -- -- -- -- -- -- -- INT4IP<2:0> QEI1IP<2:0> U2EIP<2:0> -- -- -- -- -- -- -- -- -- -- -- -- ADIP<2:0> MI2C1IP<2:0> -- OC3IP<2:0> INT2IP<2:0> SPI2IP<2:0> IC3IP<2:0> SI2C2IP<2:0> INT3IP<2:0> PSEMIP<2:0> U1EIP<2:0> PSESMIP<2:0> ADCP8IP<2:0> -- -- -- -- -- -- ADCP6IE INT1IE -- ADCP6IF -- PWM6IF T1IE CNIE -- -- -- -- PWM6IE -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- MI2C2IF U2EIF -- -- -- -- INT1IF CNIF AC1IF -- T1IF OC1IF IC1IF MI2C1IF SPI2IF SI2C2IF U1EIF ADCP8IF INT4EP INT3EP INT2EP INT1EP MATHERR ADDRERR STKERR OSCFAIL -- SPI1IF OC4IF -- -- -- -- -- AC3IF -- T3IE -- -- -- -- -- AC3IE -- -- -- -- -- -- -- AC2IE -- -- -- -- -- -- INT4IE -- IC4IE -- -- T2IE OC2IE -- -- AC2IF -- -- -- -- -- -- INT4IF -- IC4IF -- -- -- QEI1IF -- -- -- -- SPI1IE OC4IE -- QEI1IE -- -- -- -- OC1IP<2:0> OC2IP<2:0> SPI1IP<2:0> -- AC1IP<2:0> -- OC4IP<2:0> U2RXIP<2:0> -- -- IC4IP<2:0> MI2C2IP<2:0> -- -- -- AC4IE -- PSESMIE PSEMIE -- OC3IE SPI1EIE -- AC4IF -- PSESMIF PSEMIF -- OC3IF SPI1EIF T3IF T2IF OC2IF -- -- -- -- OVBTE COVTE SFTACERR DIV0ERR -- INT0EP INT0IF SI2C1IF SPI2EIF -- -- -- PWM5IF PWM4IF PWM3IF OC1IE AC1IE -- MI2C2IE U2EIE -- IC1IE MI2C1IE SPI2IE SI2C2IE U1EIE ADCP8IE INT0IE SI2C1IE SPI2EIE -- -- -- PWM5IE PWM4IE PWM3IE ADCP5IE ADCP4IE ADCP3IE ADCP2IE INT0IP<2:0> -- T3IP<2:0> U1TXIP<2:0> SI2C1IP<2:0> INT1IP<2:0> -- T5IP<2:0> SPI2EIP<2:0> -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33FJ32GS606 DEVICES All Resets 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 4444 4440 4444 0044 4444 0004 4440 4444 0044 0440 0440 0440 0440 0440 4040 0040 SFR Name SFR Addr Bit 15 Bit 14 INTCON1 0080 NSTDIS OVAERR OVBERR COVAERR COVBERR -- ADIF INT2IF -- -- -- -- -- -- U1TXIE T5IE -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- QEI2IE -- -- T4IE U1RXIE -- -- -- -- -- ADIE INT2IE -- -- -- -- -- T1IP<2:0> T2IP<2:0> U1RXIP<2:0> -- CNIP<2:0> -- T4IP<2:0> U2TXIP<2:0> -- -- -- -- -- -- QEI2IP<2:0> -- -- QEI2IF -- -- -- -- T5IF T4IF U1TXIF U1RXIF -- -- INTCON2 0082 ALTIVT DISI IFS0 0084 -- -- IFS1 0086 U2TXIF U2RXIF IFS2 0088 -- -- IFS3 008A -- -- 2009 Microchip Technology Inc. ADCP5IF ADCP4IF ADCP3IF ADCP2IF IFS4 008C -- -- IFS5 008E PWM2IF PWM1IF ADCP12IF IFS6 0090 ADCP1IF ADCP0IF IFS7 0092 -- -- IEC0 0094 -- -- IEC1 0096 U2TXIE U2RXIE IEC2 0098 -- -- IEC3 009A -- -- IEC4 009C -- -- IEC5 009E PWM2IE PWM1IE ADCP12IE IEC6 00A0 ADCP1IE ADCP0IE IEC7 00A2 -- -- dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 Preliminary IPC0 00A4 -- IPC1 00A6 -- IPC2 00A8 -- IPC3 00AA -- -- IPC4 00AC -- IPC5 00AE -- -- IPC6 00B0 -- IPC7 00B2 -- IPC8 00B4 -- -- IPC9 00B6 -- -- IPC12 00BC -- -- IPC13 00BE -- -- IPC14 00C0 -- -- IPC16 00C4 -- -- IPC18 00C8 -- IPC20 00CC -- -- DS70591B-page 69 Legend: x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. TABLE 4-10: Bit 13 -- PWM2IP<2:0> PWM6IP<2:0> AC2IP<2:0> -- ADCP1IP<2:0> ADCP5IP<2:0> -- -- -- ILR<3:0> -- VECNUM<6:0> -- -- -- -- -- -- -- -- -- -- -- ADCP4IP<2:0> -- ADCP3IP<2:0> -- -- ADCP0IP<2:0> -- -- -- -- -- -- -- -- -- -- -- -- AC4IP<2:0> -- -- ADCP2IP<2:0> ADCP6IP<2:0> -- -- -- -- -- -- -- -- -- -- -- AC3IP<2:0> -- -- PWM5IP<2:0> -- PWM4IP<2:0> -- PWM3IP<2:0> -- -- PWM1IP<2:0> -- -- -- -- -- -- -- -- -- -- -- -- -- -- ADCP12IP<2:0> -- -- -- -- Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets 0040 4400 4444 4000 0044 4400 4444 0004 0000 INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33FJ32GS606 DEVICES (CONTINUED) SFR Name SFR Addr Bit 15 Bit 14 IPC21 00CE -- -- IPC23 00D2 -- DS70591B-page 70 IPC24 00D4 -- IPC25 00D6 -- IPC26 00D8 -- -- IPC27 00DA -- IPC28 00DC -- IPC29 00DE -- -- INTTREG 00E0 -- -- Legend: x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 Preliminary 2009 Microchip Technology Inc. TABLE 4-11: Bit 13 Timer1 Register Period Register 1 -- Timer2 Register Timer3 Holding Register (for 32-bit timer operations only) Timer3 Register Period Register 2 Period Register 3 -- -- Timer4 Register Timer5 Holding Register (for 32-bit timer operations only) Timer5 Register Period Register 4 Period Register 5 -- -- TSIDL -- -- -- -- -- -- TSIDL -- -- -- -- -- -- TGATE TGATE TCKPS<1:0> TCKPS<1:0> T32 -- -- -- TCS TCS -- -- TSIDL -- -- -- -- -- -- TGATE TCKPS<1:0> TSIDL -- -- -- -- -- -- TGATE TCKPS<1:0> T32 -- -- -- TCS TCS -- -- TSIDL -- -- -- -- -- -- TGATE TCKPS<1:0> -- TSYNC TCS -- Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TIMERS REGISTER MAP All Resets xxxx FFFF 0000 xxxx xxxx xxxx FFFF FFFF 0000 0000 xxxx xxxx xxxx FFFF FFFF 0000 0000 SFR Name SFR Addr Bit 15 Bit 14 TMR1 0100 PR1 0102 T1CON 0104 TON TMR2 0106 TMR3HLD 0108 2009 Microchip Technology Inc. Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Input 1 Capture Register -- -- -- -- ICSIDL -- -- ICSIDL -- -- -- -- ICSIDL -- -- -- -- -- -- ICSIDL -- -- -- -- -- -- -- -- ICTMR Input 2 Capture Register ICTMR Input 3 Capture Register ICTMR Input 4 Capture Register ICTMR ICI<1:0> ICOV ICBNE ICM<2:0> ICI<1:0> ICOV ICBNE ICM<2:0> ICI<1:0> ICOV ICBNE ICM<2:0> ICI<1:0> ICOV ICBNE ICM<2:0> TMR3 010A PR2 010C PR3 010E T2CON 0110 TON T3CON 0112 TON TMR4 0114 TMR5HLD 0116 TMR5 0118 PR4 011A PR5 011C T4CON 011E TON T5CON 0120 TON dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 Preliminary Legend: x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. TABLE 4-12: INPUT CAPTURE REGISTER MAP All Resets xxxx 0000 xxxx 0000 xxxx 0000 xxxx 0000 SFR Name SFR Addr Bit 15 Bit 14 IC1BUF 0140 IC1CON 0142 -- IC2BUF 0144 IC2CON 0146 -- IC3BUF 0148 IC3CON 014A -- IC4BUF 014C IC4CON 014E -- DS70591B-page 71 Legend: x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. TABLE 4-13: Bit 13 Output Compare 1 Secondary Register Output Compare 1 Register -- Output Compare 2 Secondary Register Output Compare 2 Register -- Output Compare 3 Secondary Register Output Compare 3 Register -- Output Compare 4 Secondary Register Output Compare 4 Register -- OCSIDL -- -- -- -- -- -- -- -- OCFLT OCTSEL OCM<2:0> OCSIDL -- -- -- -- -- -- -- -- OCFLT OCTSEL OCM<2:0> OCSIDL -- -- -- -- -- -- -- -- OCFLT OCTSEL OCM<2:0> OCSIDL -- -- -- -- -- -- -- -- OCFLT OCTSEL OCM<2:0> Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets xxxx xxxx 0000 xxxx xxxxx 0000 xxxx xxxx 0000 xxxx xxxxx 0000 OUTPUT COMPARE REGISTER MAP SFR Name SFR Addr Bit 15 Bit 14 OC1RS 0180 DS70591B-page 72 Bit 14 -- QEISIDL -- Position Counter<15:0> Maximum Count<15:0> -- -- IMV<1:0> CEID QEOUT INDX UPDN QEIM<2:0> SWPAB PCDOUT -- TQGATE QECK<2:0> Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 TQCKPS<1:0> -- Bit 2 POSRES -- Bit 1 TQCS -- Bit 0 UPDN_SRC -- All Resets 0000 0000 0000 FFFF Bit 14 -- QEISIDL -- -- -- IMV<1:0> INDX UPDN QEIM<2:0> CEID -- Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 SWPAB QEOUT Position Counter<15:0> Maximum Count<15:0> Bit 6 PCDOUT Bit 5 TQGATE QECK<2:0> Bit 4 Bit 3 TQCKPS<1:0> -- Bit 2 POSRES -- Bit 1 TQCS -- Bit 0 UPDN_SRC -- All Resets 0000 0000 0000 FFFF OC1R 0182 OC1CON 0184 -- OC2RS 0186 OC2R 0188 OC2CON 018A -- OC3RS 018C OC3R 018E OC3CON 0190 -- OC4RS 0192 OC4R 0194 OC4CON 0196 -- Legend: x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. TABLE 4-14: QEI1 REGISTER MAP SFR Name Addr. Bit 15 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 Preliminary QEI1CON 01E0 CNTERR DFLT1CON 01E2 -- POS1CNT 01E4 MAX1CNT 01E6 Legend: u = uninitialized bit, -- = unimplemented, read as `0' TABLE 4-15: QEI2 REGISTER MAP SFR Name Addr. Bit 15 QEI2CON 01F0 CNTERR DFLT2CON 01F2 -- POS2CNT 01F4 MAX2CNT 01F6 2009 Microchip Technology Inc. Legend: u = uninitialized bit, -- = unimplemented, read as `0' TABLE 4-16: Bit 14 -- -- PTPER<15:0> SEVTCMP<15:3> MDC<15:0> -- -- PTPER<15:0> SSEVTCMP<15:3> -- -- -- -- -- CHOP<9:3> -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- SESTAT SEIEN EIPU SYNCPOL SYNCOEN SYNCEN SYNCSRC<2:0> SEVTPS<3:0> PCLKDIV<2:0> -- -- -- -- -- -- -- -- -- -- -- -- -- -- PTSIDL SESTAT SEIEN EIPU SYNCPOL SYNCOEN SYNCEN SYNCSRC<2:0> SEVTPS<3:0> PCLKDIV<2:0> Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 HIGH-SPEED PWM REGISTER MAP All Resets 0000 0000 FFF8 0000 0000 0000 0000 FFF8 0000 0000 File Name Addr Offset Bit 15 PTCON 0400 PTEN PTCON2 0402 -- PTPER 0404 SEVTCMP 0406 MDC 040A 2009 Microchip Technology Inc. Bit 13 FLTIEN POLL CLSRC<4:0> PDC1<15:0> PHASE1<15:0> -- -- DTR1<13:0> ALTDTR1<13:0> SDC1<15:0> SPHASE1<15:0> TRGCMP<15:3> -- -- -- -- DTM -- STRGCMP<15:3> PWMCAP1<15:3> PLR -- -- -- -- BLANKSEL<3:0> PLF FLTLEBEN CLLEBEN -- -- -- LEB<11:3> -- -- CHOPSEL<3:0> -- BCH BCL BPHH -- -- TRGSTRT<5:0> -- -- BPHL -- -- -- BPLH -- -- -- BPLL -- CHOPHEN CHOPLEN -- -- CLPOL CLMOD PMOD<1:0> OVRENH OVRENL CLIEN TRGIEN ITB MDCS DTC<1:0> OVRDAT<1:0> Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 DTCP FLTSRC<4:0> Bit 4 -- FLTDAT<1:0> Bit 3 MTBS Bit 2 CAM CLDAT<1:0> FLTPOL Bit 1 XPRES SWAP Bit 0 IUE OSYNC FLTMOD<1:0> POLH STCON 040E -- STCON2 0410 -- STPER 0412 SSEVTCMP 0414 CHOP 041A CHPCLKEN Legend: x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. TABLE 4-17: HIGH-SPEED PWM GENERATOR 1 REGISTER MAP All Resets 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 File Name Addr Offset Bit 15 Bit 14 PWMCON1 0420 FLTSTAT CLSTAT TRGSTAT dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 Preliminary IOCON1 0422 PENH PENL FCLCON1 0424 IFLTMOD PDC1 0426 PHASE1 0428 DTR1 042A -- ALTDTR1 042C -- SDC1 042E SPHASE1 0430 TRIG1 0432 TRGCON1 0434 TRGDIV<3:0> STRIG1 0436 PWMCAP1 0438 LEBCON1 043A PHR PHF LEBDLY1 043C -- AUXCON1 043E HRPDIS HRDDIS DS70591B-page 73 Legend: x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. TABLE 4-18: Bit 13 TRGSTAT POLH CLSRC<4:0> PDC2<15:0> PHASE2<15:0> -- -- SDC2<15:0> SPHASE2<15:0> TRGCMP<15:3> -- STRGCMP<15:3> PWMCAP2<15:3> PLR -- -- -- BLANKSEL<3:0> -- -- -- LEB<11:3> CHOPSEL<3:0> PLF FLTLEBEN CLLEBEN -- -- -- -- BCH BCL BPHH -- -- -- -- DTM -- -- TRGSTRT<5:0> -- -- BPHL -- -- -- BPLH -- -- -- BPLL -- CHOPHEN CHOPLEN -- -- ALTDTR2<13:0> DTR2<13:0> CLPOL CLMOD FLTSRC<4:0> FLTPOL POLL PMOD<1:0> OVRENH OVRENL OVRDAT<1:0> FLTDAT<1:0> CLDAT<1:0> SWAP FLTMOD<1:0> FLTIEN CLIEN TRGIEN ITB MDCS DTC<1:0> DTCP -- MTBS CAM XPRES IUE OSYNC Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 HIGH-SPEED PWM GENERATOR 2 REGISTER MAP File Name Addr Offset Bit 15 Bit 14 PWMCON2 0440 FLTSTAT CLSTAT DS70591B-page 74 IOCON2 0442 PENH PENL FCLCON2 0444 IFLTMOD PDC2 0446 PHASE2 0448 DTR2 044A -- ALTDTR2 044C -- SDC2 044E SPHASE2 0450 TRIG2 0452 TRGCON2 0454 TRGDIV<3:0> STRIG2 0456 PWMCAP2 0458 LEBCON2 045A PHR PHF LEBDLY2 045C -- AUXCON2 045E HRPDIS HRDDIS dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 Preliminary Legend: x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. 2009 Microchip Technology Inc. TABLE 4-19: Bit 13 TRGSTAT POLH CLSRC<4:0> PDC3<15:0> PHASE3<15:0> -- -- SDC3<15:0> SPHASE3<15:0> TRGCMP<15:3> TRGDIV<3:0> STRGCMP<15:3> PWMCAP3<15:3> PLR -- -- -- BLANKSEL<3:0> -- -- -- LEB<11:3> CHOPSEL<3:0> PLF FLTLEBEN CLLEBEN -- -- -- -- BCH BCL BPHH -- -- -- -- -- DTM -- -- TRGSTRT<5:0> -- -- BPHL -- -- -- BPLH -- -- -- BPLL -- CHOPHEN CHOPLEN -- -- ALTDTR3<13:0> DTR3<13:0> CLPOL CLMOD FLTSRC<4:0> FLTPOL POLL PMOD<1:0> OVRENH OVRENL OVRDAT<1:0> FLTDAT<1:0> CLDAT<1:0> SWAP FLTIEN CLIEN TRGIEN ITB MDCS DTC<1:0> DTCP -- MTBS CAM XPRES IUE OSYNC Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 HIGH-SPEED PWM GENERATOR 3 REGISTER MAP All Resets 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 File Name Addr Offset Bit 15 Bit 14 PWMCON3 0460 FLTSTAT CLSTAT IOCON3 0462 PENH PENL FCLCON3 0464 IFLTMOD FLTMOD<1:0> PDC3 0466 PHASE3 0468 2009 Microchip Technology Inc. DTR3 046C -- ALTDTR3 046C -- SDC3 046E SPHASE3 0470 TRIG3 0472 TRGCON3 0474 STRIG3 0476 PWMCAP3 0478 LEBCON3 047A PHR PHF LEBDLY3 047C -- AUXCON3 047E HRPDIS HRDDIS dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 Preliminary Legend: x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. DS70591B-page 75 TABLE 4-20: Bit 13 TRGSTAT POLH CLSRC<4:0> PDC4<15:0> PHASE4<15:0> -- -- SDC4<15:0> SPHASE4<15:0> TRGCMP<15:3> -- STRGCMP<15:3> PWMCAP4<15:3> PLR -- -- -- BLANKSEL<3:0> -- -- -- LEB<11:3> CHOPSEL<3:0> PLF FLTLEBEN CLLEBEN -- -- -- -- BCH BCL BPHH -- -- -- -- DTM -- -- TRGSTRT<5:0> -- -- BPHL -- -- -- BPLH -- -- -- BPLL -- CHOPHEN CHOPLEN -- -- ALTDTR4<13:0> DTR4<13:0> CLPOL CLMOD FLTSRC<4:0> FLTPOL POLL PMOD<1:0> OVRENH OVRENL OVRDAT<1:0> FLTDAT<1:0> CLDAT<1:0> SWAP FLTMOD<1:0> FLTIEN CLIEN TRGIEN ITB MDCS DTC<1:0> DTCP -- MTBS CAM XPRES IUE OSYNC Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 HIGH-SPEED PWM GENERATOR 4 REGISTER MAP File Name Addr Offset Bit 15 Bit 14 PWMCON4 0480 FLTSTAT CLSTAT DS70591B-page 76 IOCON4 0482 PENH PENL FCLCON4 0484 IFLTMOD PDC4 0486 PHASE4 0488 DTR4 048A -- ALTDTR4 048A -- SDC4 048E SPHASE4 0490 TRIG4 0492 TRGCON4 0494 TRGDIV<3:0> STRIG4 0496 PWMCAP4 0498 LEBCON4 049A PHR PHF LEBDLY4 049C -- AUXCON4 049E HRPDIS HRDDIS dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 Preliminary Legend: x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. 2009 Microchip Technology Inc. TABLE 4-21: Bit 13 TRGSTAT POLH CLSRC<4:0> PDC5<15:0> PHASE5<15:0> -- -- SDC5<15:0> SPHASE5<15:0> TRGCMP<15:3> -- STRGCMP<15:3> PWMCAP5<15:3> PLR -- -- -- BLANKSEL<3:0> -- -- -- LEB<11:3> CHOPSEL<3:0> PLF FLTLEBEN CLLEBEN -- -- -- -- BCH BCL BPHH -- -- -- -- DTM -- -- TRGSTRT<5:0> -- -- BPHL -- -- -- BPLH -- -- -- BPLL -- CHOPHEN CHOPLEN -- -- ALTDTR5<13:0> DTR5<13:0> CLPOL CLMOD FLTSRC<4:0> FLTPOL POLL PMOD<1:0> OVRENH OVRENL OVRDAT<1:0> FLTDAT<1:0> CLDAT<1:0> SWAP FLTIEN CLIEN TRGIEN ITB MDCS DTC<1:0> DTCP -- MTBS CAM XPRES IUE OSYNC Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 HIGH-SPEED PWM GENERATOR 5 REGISTER MAP All Resets 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 File Name Addr Offset Bit 15 Bit 14 PWMCON5 04A0 FLTSTAT CLSTAT IOCON5 04A2 PENH PENL FCLCON5 04A4 IFLTMOD FLTMOD<1:0> PDC5 04A6 PHASE5 04A8 2009 Microchip Technology Inc. DTR5 04AA -- ALTDTR5 04AA -- SDC5 04AE SPHASE5 04B0 TRIG5 04B2 TRGCON5 04B4 TRGDIV<3:0> STRIG5 04B6 PWMCAP5 04B8 LEBCON5 04BA PHR PHF LEBDLY5 04BC -- AUXCON5 04BE HRPDIS HRDDIS dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 Preliminary Legend: x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. DS70591B-page 77 TABLE 4-22: Bit 13 TRGSTAT POLH CLSRC<4:0> PDC6<15:0> PHASE6<15:0> -- -- SDC6<15:0> SPHASE6<15:0> TRGCMP<15:3> -- STRGCMP<15:3> PWMCAP6<15:3> PLR -- -- -- BLANKSEL<3:0> -- -- -- LEB<11:3> CHOPSEL<3:0> PLF FLTLEBEN CLLEBEN -- -- -- -- BCH BCL BPHH -- -- -- -- DTM -- -- TRGSTRT<5:0> -- -- BPHL -- -- -- BPLH -- -- -- BPLL -- CHOPHEN CHOPLEN -- -- ALTDTR6<13:0> DTR6<13:0> CLPOL CLMOD FLTSRC<4:0> FLTPOL POLL PMOD<1:0> OVRENH OVRENL OVRDAT<1:0> FLTDAT<1:0> CLDAT<1:0> SWAP FLTMOD<1:0> FLTIEN CLIEN TRGIEN ITB MDCS DTC<1:0> DTCP -- MTBS CAM XPRES IUE OSYNC Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 HIGH-SPEED PWM GENERATOR 6 REGISTER MAP File Name Addr Offset Bit 15 Bit 14 PWMCON6 04C0 FLTSTAT CLSTAT DS70591B-page 78 IOCON6 04C2 PENH PENL FCLCON6 04C4 IFLTMOD PDC6 04C6 PHASE6 04C8 DTR6 04CA -- ALTDTR6 04CA -- SDC6 04CE SPHASE6 04D0 TRIG6 04D2 TRGCON6 04D4 TRGDIV<3:0> STRIG6 04D6 PWMCAP6 04D8 LEBCON6 04DA PHR PHF LEBDLY6 04DC -- AUXCON6 04DE HRPDIS HRDDIS dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 Preliminary Legend: x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. 2009 Microchip Technology Inc. TABLE 4-23: Bit 13 TRGSTAT POLH CLSRC<4:0> PDC7<15:0> PHASE7<15:0> -- -- SDC7<15:0> SPHASE7<15:0> TRGCMP<15:3> -- STRGCMP<15:3> PWMCAP7<15:3> PLR -- -- -- BLANKSEL<3:0> -- -- -- LEB<11:3> CHOPSEL<3:0> PLF FLTLEBEN CLLEBEN -- -- -- -- BCH BCL BPHH -- -- -- -- DTM -- -- TRGSTRT<5:0> -- -- BPHL -- -- -- BPLH -- -- -- BPLL -- CHOPHEN CHOPLEN -- -- ALTDTR7<13:0> DTR7<13:0> CLPOL CLMOD FLTSRC<4:0> FLTPOL POLL PMOD<1:0> OVRENH OVRENL OVRDAT<1:0> FLTDAT<1:0> CLDAT<1:0> SWAP FLTIEN CLIEN TRGIEN ITB MDCS DTC<1:0> DTCP -- MTBS CAM XPRES IUE OSYNC Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 HIGH-SPEED PWM GENERATOR 7 REGISTER MAP (EXCLUDES dsPIC33FJ32GS406 AND DSPIC33FJ64GS406 DEVICES) All Resets 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 File Name Addr Offset Bit 15 Bit 14 PWMCON7 04E0 FLTSTAT CLSTAT IOCON7 04E2 PENH PENL FCLCON7 04E4 IFLTMOD FLTMOD<1:0> PDC7 04E6 PHASE7 04E8 2009 Microchip Technology Inc. DTR7 04EA -- ALTDTR7 04EA -- SDC7 04EE SPHASE7 04F0 TRIG7 04F2 TRGCON7 04F4 TRGDIV<3:0> STRIG7 04F6 PWMCAP7 04F8 LEBCON7 04FA PHR PHF LEBDLY7 04FC -- AUXCON7 04FE HRPDIS HRDDIS dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 Preliminary Legend: x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. DS70591B-page 79 TABLE 4-24: Bit 13 TRGSTAT POLH CLSRC<4:0> PDC8<15:0> PHASE8<15:0> -- -- SDC8<15:0> SPHASE8<15:0> TRGCMP<15:3> -- STRGCMP<15:3> PWMCAP8<15:3> PLR -- -- -- BLANKSEL<3:0> -- -- -- LEB<11:3> CHOPSEL<3:0> PLF FLTLEBEN CLLEBEN -- -- -- -- BCH BCL BPHH -- -- -- -- DTM -- -- TRGSTRT<5:0> -- -- BPHL -- -- -- BPLH -- -- -- BPLL -- CHOPHEN CHOPLEN -- -- ALTDTR8<13:0> DTR8<13:0> CLPOL CLMOD FLTSRC<4:0> FLTPOL POLL PMOD<1:0> OVRENH OVRENL OVRDAT<1:0> FLTDAT<1:0> CLDAT<1:0> SWAP FLTMOD<1:0> FLTIEN CLIEN TRGIEN ITB MDCS DTC<1:0> DTCP -- MTBS CAM XPRES IUE OSYNC Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 HIGH-SPEED PWM GENERATOR 8 REGISTER MAP (EXCLUDES dsPIC33FJ32GS406 AND DSPIC33FJ64GS406 DEVICES) File Name Addr Offset Bit 15 Bit 14 PWMCON8 0500 FLTSTAT CLSTAT DS70591B-page 80 IOCON8 0502 PENH PENL FCLCON8 0504 IFLTMOD PDC8 0506 PHASE8 0508 DTR8 050A -- ALTDTR8 050A -- SDC8 050E SPHASE8 0510 TRIG8 0512 TRGCON8 0514 TRGDIV<3:0> STRIG8 0516 PWMCAP8 0518 LEBCON8 051A PHR PHF LEBDLY8 051C -- AUXCON8 051E HRPDIS HRDDIS dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 Preliminary Legend: x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. 2009 Microchip Technology Inc. TABLE 4-25: Bit 13 TRGSTAT POLH CLSRC<4:0> PDC9<15:0> PHASE9<15:0> -- -- SDC9<15:0> SPHASE9<15:0> TRGCMP<15:3> -- STRGCMP<15:3> PWMCAP9<15:3> PLR -- -- -- BLANKSEL<3:0> -- -- -- LEB<11:3> CHOPSEL<3:0> PLF FLTLEBEN CLLEBEN -- -- -- -- BCH BCL BPHH -- -- -- -- DTM -- -- TRGSTRT<5:0> -- -- BPHL -- -- -- BPLH -- -- -- BPLL -- CHOPHEN CHOPLEN -- -- ALTDTR9<13:0> DTR9<13:0> CLPOL CLMOD FLTSRC<4:0> FLTPOL POLL PMOD<1:0> OVRENH OVRENL OVRDAT<1:0> FLTDAT<1:0> CLDAT<1:0> SWAP FLTIEN CLIEN TRGIEN ITB MDCS DTC<1:0> DTCP -- MTBS CAM XPRES IUE OSYNC Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 HIGH-SPEED PWM GENERATOR 9 REGISTER MAP FOR dsPIC33FJ32GS610 AND dsPIC33FJ64GS610 DEVICES All Resets 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 File Name Addr Offset Bit 15 Bit 14 PWMCON9 0520 FLTSTAT CLSTAT IOCON9 0522 PENH PENL FCLCON9 0524 IFLTMOD FLTMOD<1:0> PDC9 0526 PHASE9 0528 2009 Microchip Technology Inc. Bit 13 -- -- -- I2CSIDL SCLREL -- -- -- -- -- -- -- -- -- -- -- BCL GCSTAT IPMIEN A10M DISSLW -- -- -- -- SMEN ADD10 GCEN IWCOL STREN I2COV -- -- -- -- -- ACKDT D_A -- -- -- -- -- Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Receive Register Transmit Register Baud Rate Generator Register ACKEN P Address Register Address Mask Register RCEN S PEN R_W RSEN RBF SEN TBF Bit 2 Bit 1 Bit 0 -- -- -- -- -- -- DTR9 052A -- ALTDTR9 052A -- SDC9 052E SPHASE9 0530 TRIG9 0532 TRGCON9 0534 TRGDIV<3:0> STRIG9 0536 PWMCAP9 0538 LEBCON9 053A PHR PHF LEBDLY9 053C -- AUXCON9 053E HRPDIS HRDDIS dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 Preliminary Legend: x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. TABLE 4-26: I2C1 REGISTER MAP All Resets 0000 00FF 0000 1000 0000 0000 0000 SFR Name SFR Addr Bit 15 Bit 14 I2C1RCV 0200 -- I2C1TRN 0202 -- I2C1BRG 0204 -- I2C1CON 0206 I2CEN I2C1STAT 0208 ACKSTAT TRSTAT I2C1ADD 020A -- I2C1MSK 020C -- Legend: x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. DS70591B-page 81 TABLE 4-27: Bit 13 -- -- -- I2CSIDL SCLREL -- -- -- -- -- -- Address Mask Register -- -- -- Address Register -- -- BCL GCSTAT ADD10 IWCOL I2COV D_A P S R_W RBF IPMIEN A10M DISSLW SMEN GCEN STREN ACKDT ACKEN RCEN PEN RSEN -- -- -- -- Baud Rate Generator Register SEN TBF -- -- -- -- -- Transmit Register -- -- -- -- -- Receive Register Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets 0000 00FF 0000 1000 0000 0000 0000 I2C2 REGISTER MAP SFR Name -- -- -- -- -- -- SFR Addr Bit 15 Bit 14 I2C2RCV 0210 -- DS70591B-page 82 Bit 13 USIDL -- -- -- Baud Rate Generator Prescaler -- -- -- -- -- -- UTXBRK UTXEN UTXBF TRMT URXISEL<1:0> ADDEN -- -- IREN RTSMD -- UEN1 UEN0 WAKE LPBACK ABAUD URXINV RIDLE Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 BRGH PERR Bit 2 Bit 1 PDSEL<1:0> FERR OERR Bit 0 STSEL URXDA All Resets 0000 0110 xxxx 0000 0000 -- -- -- UART Transmit Register UART Receive Register Bit 13 USIDL UTXISEL0 -- -- -- -- -- -- Baud Rate Generator Prescaler -- -- -- -- -- UTXBRK UTXEN UTXBF TRMT IREN RTSMD -- UEN1 UEN0 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 WAKE Bit 6 LPBACK URXISEL<1:0> Bit 5 ABAUD ADDEN Bit 4 URXINV RIDLE Bit 3 BRGH PERR UART Transmit Register UART Receive Register Bit 2 Bit 1 PDSEL<1:0> FERR OERR Bit 0 STSEL URXDA All Resets 0000 0110 xxxx 0000 0000 -- -- -- I2C2TRN 0212 -- I2C2BRG 0214 -- I2C2CON 0216 I2CEN I2C2STAT 0218 ACKSTAT TRSTAT I2C2ADD 021A -- I2C2MSK 021C -- Legend: x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. TABLE 4-28: UART1 REGISTER MAP SFR Name SFR Addr Bit 15 Bit 14 U1MODE 0220 UARTEN U1STA 0222 UTXISEL1 UTXINV UTXISEL0 U1TXREG 0224 -- U1RXREG 0226 -- dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 Preliminary U1BRG 0228 Legend: x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. TABLE 4-29: UART2 REGISTER MAP SFR Name SFR Addr Bit 15 Bit 14 U2MODE 0230 UARTEN U2STA 0232 UTXISEL1 UTXINV U2TXREG 0234 -- U2RXREG 0236 -- U2BRG 0238 2009 Microchip Technology Inc. Legend: x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. TABLE 4-30: Bit 13 SPISIDL -- FRMPOL SPI1 Transmit and Receive Buffer Register -- -- -- -- -- -- -- -- -- -- -- FRMDLY DISSCK DISSDO MODE16 SMP CKE SSEN CKP MSTEN SPRE<2:0> -- -- -- -- -- -- SPIROV -- -- -- -- SPITBF SPIRBF -- Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SPI1 REGISTER MAP All Resets 0000 0000 0000 0000 SFR Name -- -- SFR Addr Bit 15 Bit 14 SPI1STAT 0240 SPIEN SPI1CON1 0242 -- PPRE<1:0> SPI1CON2 0244 FRMEN SPIFSD SPI1BUF 0248 2009 Microchip Technology Inc. Bit 13 SPISIDL -- FRMPOL SPI2 Transmit and Receive Buffer Register -- -- -- -- -- -- -- -- DISSCK DISSDO MODE16 SMP CKE SSEN CKP MSTEN -- -- -- -- -- -- -- SPIROV -- -- Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 -- SPRE<2:0> -- -- Bit 2 -- Bit 1 SPITBF FRMDLY Bit 0 SPIRBF PPRE<1:0> -- -- -- Legend: x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. TABLE 4-31: SPI2 REGISTER MAP All Resets 0000 0000 0000 0000 SFR Name SFR Addr Bit 15 Bit 14 SPI2STAT 0260 SPIEN SPI2CON1 0262 -- SPI2CON2 0264 FRMEN SPIFSD SPI2BUF 0268 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 Preliminary Legend: x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. DS70591B-page 83 TABLE 4-32: Bit 13 ADSIDL PCFG13 -- -- ADBASE<15:1> SWTRG1 SWTRG3 SWTRG5 SWTRG7 SWTRG9 TRGSRC11<4:0> -- ADC Data Buffer 0 ADC Data Buffer 1 ADC Data Buffer 2 ADC Data Buffer 3 ADC Data Buffer 4 ADC Data Buffer 5 ADC Data Buffer 6 ADC Data Buffer 7 ADC Data Buffer 8 ADC Data Buffer 9 ADC Data Buffer 10 ADC Data Buffer 11 ADC Data Buffer 12 ADC Data Buffer 13 ADC Data Buffer 14 ADC Data Buffer 15 ADC Data Buffer 16 ADC Data Buffer 17 ADC Data Buffer 18 ADC Data Buffer 19 ADC Data Buffer 20 ADC Data Buffer 21 -- -- -- -- IRQEN12 PEND12 SWTRG12 IRQEN10 PEND10 SWTRG10 -- TRGSRC9<4:0> IRQEN8 PEND8 SWTRG8 TRGSRC7<4:0> IRQEN6 PEND6 SWTRG6 TRGSRC5<4:0> IRQEN4 PEND4 SWTRG4 TRGSRC3<4:0> IRQEN2 PEND2 SWTRG2 TRGSRC2<4:0> TRGSRC4<4:0> TRGSRC6<4:0> TRGSRC8<4:0> TRGSRC10<4:0> TRGSRC12<4:0> TRGSRC1<4:0> IRQEN0 PEND0 SWTRG0 TRGSRC0<4:0> P12RDY P11RDY P10RDY P9RDY P8RDY P7RDY P6RDY P5RDY P4RDY P3RDY P2RDY P1RDY -- -- -- -- -- PCFG23 PCFG22 PCFG21 PCFG20 PCFG12 PCFG11 PCFG10 PCFG9 PCFG8 PCFG7 PCFG6 PCFG5 PCFG4 PCFG3 PCFG2 PCFG1 PCFG0 P0RDY -- SLOWCLK -- GSWTRG -- FORM EIE ORDER SEQSAMP ASYNCSAMP -- ADCS<2:0> Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets 0003 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx HIGH-SPEED 10-BIT ADC REGISTER MAP FOR dsPIC33FJ32GS610 AND dsPIC33FJ64GS610 DEVICES ONLY SFR SFR Name Addr Bit 15 Bit 14 ADCON 0300 ADON -- DS70591B-page 84 PCFG19 PCFG18 PCFG17 PCFG16 ADPCFG 0302 PCFG15 PCFG14 ADPCFG2 0304 -- -- ADSTAT 0306 -- -- ADBASE 0308 ADCPC0 030A IRQEN1 PEND1 ADCPC1 030C IRQEN3 PEND3 ADCPC2 030E IRQEN5 PEND5 ADCPC3 0310 IRQEN7 PEND7 ADCPC4 0312 IRQEN9 PEND9 ADCPC5 0314 IRQEN11 PEND11 SWTRG11 ADCPC6 0316 -- -- ADCBUF0 0340 ADCBUF1 0342 ADCBUF2 0344 ADCBUF3 0346 ADCBUF4 0348 ADCBUF5 034A dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 Preliminary ADCBUF6 034C ADCBUF7 034E ADCBUF8 0350 ADCBUF9 0352 ADCBUF10 0354 ADCBUF11 0356 ADCBUF12 0358 ADCBUF13 035A ADCBUF14 035C ADCBUF15 035E ADCBUF16 0360 ADCBUF17 0362 ADCBUF18 0364 ADCBUF19 0366 ADCBUF20 0368 ADCBUF21 036A 2009 Microchip Technology Inc. Legend: x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. TABLE 4-32: Bit 13 ADC Data Buffer 22 ADC Data Buffer 23 ADC Data Buffer 24 ADC Data Buffer 25 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 HIGH-SPEED 10-BIT ADC REGISTER MAP FOR dsPIC33FJ32GS610 AND dsPIC33FJ64GS610 DEVICES ONLY (CONTINUED) All Resets xxxx xxxx xxxx xxxx SFR Name SFR Addr Bit 15 Bit 14 ADCBUF22 036C ADCBUF23 036E ADCBUF24 0370 ADCBUF25 0372 2009 Microchip Technology Inc. Legend: x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 Preliminary DS70591B-page 85 TABLE 4-33: Bit 13 ADSIDL PCFG13 -- -- ADBASE<15:1> SWTRG1 SWTRG3 SWTRG5 SWTRG7 -- -- ADC Data Buffer 0 ADC Data Buffer 1 ADC Data Buffer 2 ADC Data Buffer 3 ADC Data Buffer 4 ADC Data Buffer 5 ADC Data Buffer 6 ADC Data Buffer 7 ADC Data Buffer 8 ADC Data Buffer 9 ADC Data Buffer 10 ADC Data Buffer 11 ADC Data Buffer 12 ADC Data Buffer 13 ADC Data Buffer 14 ADC Data Buffer 15 ADC Data Buffer 16 ADC Data Buffer 17 ADC Data Buffer 24 ADC Data Buffer 25 -- -- -- -- -- IRQEN12 PEND12 SWTRG12 -- -- -- -- -- IRQEN8 PEND8 SWTRG8 TRGSRC7<4:0> IRQEN6 PEND6 SWTRG6 TRGSRC5<4:0> IRQEN4 PEND4 SWTRG4 TRGSRC3<4:0> IRQEN2 PEND2 SWTRG2 TRGSRC1<4:0> IRQEN0 PEND0 SWTRG0 TRGSRC0<4:0> TRGSRC2<4:0> TRGSRC4<4:0> TRGSRC6<4:0> TRGSRC8<4:0> TRGSRC12<4:0> P12RDY -- -- -- P8RDY P7RDY P6RDY P5RDY P4RDY P3RDY P2RDY P1RDY -- -- -- -- -- -- -- -- -- -- -- PCFG12 PCFG11 PCFG10 PCFG9 PCFG8 PCFG7 PCFG6 PCFG5 PCFG4 PCFG3 PCFG2 PCFG1 PCFG0 P0RDY -- SLOWCLK -- GSWTRG -- FORM EIE ORDER SEQSAMP ASYNCSAMP -- ADCS<2:0> PCFG17 PCFG16 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets 0003 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx HIGH-SPEED 10-BIT ADC REGISTER MAP FOR dsPIC33FJ32GS608 AND dsPIC33FJ64GS608 DEVICES SFR SFR Name Addr Bit 15 Bit 14 ADCON 0300 ADON -- DS70591B-page 86 ADPCFG 0302 PCFG15 PCFG14 ADPCFG2 0304 -- -- ADSTAT 0306 -- -- ADBASE 0308 ADCPC0 030A IRQEN1 PEND1 ADCPC1 030C IRQEN3 PEND3 ADCPC2 030E IRQEN5 PEND5 ADCPC3 0310 IRQEN7 PEND7 ADCPC4 0312 -- -- ADCPC6 0316 -- -- ADCBUF0 0340 ADCBUF1 0342 ADCBUF2 0344 ADCBUF3 0346 ADCBUF4 0348 ADCBUF5 034A ADCBUF6 034C dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 Preliminary ADCBUF7 034E ADCBUF8 0350 ADCBUF9 0352 ADCBUF10 0354 ADCBUF11 0356 ADCBUF12 0358 ADCBUF13 035A ADCBUF14 035C ADCBUF15 035E ADCBUF16 0360 ADCBUF17 0362 ADCBUF24 0370 ADCBUF25 0372 2009 Microchip Technology Inc. Legend: x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. TABLE 4-34: Bit 13 ADSIDL SLOWCLK PCFG12 P12RDY ADBASE<15:1> TRGSRC1<4:0> TRGSRC3<4:0> TRGSRC5<4:0> TRGSRC7<4:0> -- ADC Data Buffer 0 ADC Data Buffer 1 ADC Data Buffer 2 ADC Data Buffer 3 ADC Data Buffer 4 ADC Data Buffer 5 ADC Data Buffer 6 ADC Data Buffer 7 ADC Data Buffer 8 ADC Data Buffer 9 ADC Data Buffer 10 ADC Data Buffer 11 ADC Data Buffer 12 ADC Data Buffer 13 ADC Data Buffer 14 ADC Data Buffer 15 ADC Data Buffer 24 ADC Data Buffer 25 -- -- -- -- IRQEN12 PEND12 SWTRG12 IRQEN6 PEND6 SWTRG6 IRQEN4 PEND4 SWTRG4 IRQEN2 PEND2 SWTRG2 IRQEN0 PEND0 SWTRG0 TRGSRC0<4:0> TRGSRC2<4:0> TRGSRC4<4:0> TRGSRC6<4:0> TRGSRC12<4:0> -- -- -- -- P7RDY P6RDY P5RDY P4RDY P3RDY P2RDY P1RDY PCFG11 PCFG10 PCFG9 PCFG8 PCFG7 PCFG6 PCFG5 PCFG4 PCFG3 PCFG2 PCFG1 -- -- GSWTRG -- FORM EIE ORDER SEQSAMP ASYNCSAMP -- ADCS<2:0> PCFG0 P0RDY -- Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 HIGH-SPEED 10-BIT ADC REGISTER MAP FOR dsPIC33FJ32GS406/606 AND DSPIC33FJ64GS406/606 DEVICES All Resets 0003 0000 0000 0000 0000 0000 0000 0000 0000 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx SFR Name SFR Addr Bit 15 Bit 14 ADCON 0300 ADON -- ADPCFG 0302 PCFG15 PCFG14 PCFG13 ADSTAT 0306 -- -- ADBASE 0308 ADCPC0 030A IRQEN1 PEND1 SWTRG1 ADCPC1 030C IRQEN3 PEND3 SWTRG3 2009 Microchip Technology Inc. -- ADCPC2 030E IRQEN5 PEND5 SWTRG5 ADCPC3 0310 IRQEN7 PEND7 SWTRG7 ADCPC6 0316 -- -- ADCBUF0 0340 ADCBUF1 0342 ADCBUF2 0344 ADCBUF3 0346 ADCBUF4 0348 ADCBUF5 034A ADCBUF6 034C ADCBUF7 034E ADCBUF8 0350 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 Preliminary ADCBUF9 0352 ADCBUF10 0354 ADCBUF11 0356 ADCBUF12 0358 ADCBUF13 035A ADCBUF14 035C ADCBUF15 035E ADCBUF24 0370 ADCBUF25 0372 Legend: x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. DS70591B-page 87 TABLE 4-35: Bit 13 DIR -- STA<15:0> STB<15:0> PAD<15:0> -- DIR -- -- STA<15:0> STB<15:0> PAD<15:0> -- DIR -- -- STA<15:0> STB<15:0> PAD<15:0> -- DIR -- -- STA<15:0> STB<15:0> PAD<15:0> -- -- -- -- LSTCH<3:0> -- PWCOL3 PWCOL2 PWCOL1 PWCOL0 -- -- -- -- -- DSADR<15:0> -- -- CNT<9:0> -- -- -- -- XWCOL3 XWCOL2 XWCOL1 XWCOL0 PPST3 PPST2 PPST1 PPST0 -- -- -- -- -- -- -- -- -- -- HALF NULLW -- -- -- CNT<9:0> AMODE<1:0> -- IRQSEL<6:0> -- MODE<1:0> -- -- -- -- -- -- -- AMODE<1:0> -- -- -- HALF NULLW -- -- -- CNT<9:0> -- IRQSEL<6:0> -- MODE<1:0> -- -- -- IRQSEL<6:0> -- -- -- -- AMODE<1:0> -- -- -- -- -- HALF NULLW -- -- -- CNT<9:0> MODE<1:0> -- -- -- -- -- -- IRQSEL<6:0> HALF NULLW -- -- -- -- -- AMODE<1:0> -- -- MODE<1:0> Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets 0000 007F 0000 0000 0000 0000 0000 007F 0000 0000 0000 0000 0000 007F 0000 0000 0000 0000 0000 007F 0000 0000 0000 0000 0000 0F00 0000 DMA REGISTER MAP File Name Addr Bit 15 Bit 14 DMA0CON 0380 CHEN SIZE DS70591B-page 88 DMA0REQ 0382 FORCE -- DMA0STA 0384 DMA0STB 0386 DMA0PAD 0388 DMA0CNT 038A -- -- DMA1CON 038C CHEN SIZE DMA1REQ 038E FORCE -- DMA1STA 0390 DMA1STB 0392 DMA1PAD 0394 DMA1CNT 0396 -- -- DMA2CON 0398 CHEN SIZE DMA2REQ 039A FORCE -- DMA2STA 039C DMA2STB 039E DMA2PAD 03A0 DMA2CNT 03A2 -- -- dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 Preliminary DMA3CON 03A4 CHEN SIZE DMA3REQ 03A6 FORCE -- DMA3STA 03A8 DMA3STB 03AA DMA3PAD 03AC DMA3CNT 03AE -- -- DMACS0 03E0 -- -- DMACS1 03E2 -- -- DSADR 03E4 2009 Microchip Technology Inc. Legend: -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. TABLE 4-36: Bit 14 -- -- -- -- FSA<4:0> FNRB<5:0> ERRIF ERRIE RERRCNT<7:0> -- SEG2PH<2:0> FLTEN10 F4MSK<1:0> F12MSK<1:0> F11MSK<1:0> F3MSK<1:0> F2MSK<1:0> F10MSK<1:0> FLTEN9 FLTEN8 FLTEN7 FLTEN6 FLTEN5 FLTEN4 SEG2PHTS SAM SEG1PH<2:0> FLTEN3 F1MSK<1:0> F9MSK<1:0> -- -- SJW<1:0> BRP<5:0> PRSEG<2:0> FLTEN2 FLTEN1 FLTEN0 F0MSK<1:0> F8MSK<1:0> -- FIFOIE -- FIFOIF RBOVIF RBOVIE RBIF RBIE TBIF TBIE FBP<5:0> TXBO -- TERRCNT<7:0> -- WAKFIL FLTEN14 FLTEN13 FLTEN12 F6MSK<1:0> F14MSK<1:0> F13MSK<1:0> F5MSK<1:0> FLTEN11 -- -- -- -- -- -- -- -- -- -- -- IVRIE WAKIE TXBP RXBP TXWAR RXWAR EWARN IVRIF WAKIF -- -- -- -- -- -- -- -- -- -- -- -- -- FILHIT<4:0> -- ICODE<6:0> -- -- -- -- -- -- -- -- -- DNCNT<4:0> CSIDL ABAT -- REQOP<2:0> OPMODE<2:0> -- CANCAP -- -- WIN Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ECAN1 REGISTER MAP WHEN C1CTRL1.WIN = 0 OR 1 All Resets 0480 0000 0000 0000 0000 0000 0000 0000 0000 0000 FFFF 0000 0000 File Name Addr Bit 15 C1CTRL1 0600 -- C1CTRL2 0602 -- C1VEC 0604 -- C1FCTRL 0606 DMABS<2:0> C1FIFO 0608 -- 2009 Microchip Technology Inc. Bit 13 See definition when WIN = x RXFUL8 RXOVF8 RXFUL7 RXOVF7 TXEN0 TXEN2 TXEN4 TX7PRI<1:0> TXEN6 Received Data Word Transmit Data Word RXFUL6 RXOVF6 TXABT0 TXABT2 TXABT4 TXABT6 RXFUL5 RXOVF5 RXFUL4 RXOVF4 TXLARB0 TXERR0 TXLARB2 TXERR2 TXLARB4 TXERR4 TXLARB6 TXERR6 RXFUL3 RXOVF3 TXREQ0 TXREQ2 TXREQ4 TXREQ6 RXFUL2 RXOVF2 RTREN0 RTREN2 RTREN4 RTREN6 RXFUL1 RXOVF1 RXFUL0 RXOVF0 TX0PRI<1:0> TX2PRI<1:0> TX4PRI<1:0> TX6PRI<1:0> Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TXLARB1 TXLARB3 TXLARB5 TXLARB7 TXERR7 TXREQ7 RTREN7 TXERR5 TXREQ5 RTREN5 TXERR3 TXREQ3 RTREN3 TXERR1 TXREQ1 RTREN1 TX1PRI<1:0> TX3PRI<1:0> TX5PRI<1:0> C1INTF 060A -- C1INTE 060C -- C1EC 060E C1CFG1 0610 -- C1CFG2 0612 -- C1FEN1 0614 FLTEN15 C1FMSKSEL1 0618 F7MSK<1:0> C1FMSKSEL2 061A F15MSK<1:0> Legend: -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. TABLE 4-37: ECAN1 REGISTER MAP WHEN C1CTRL1.WIN = 0 All Resets dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 Preliminary File Name Addr Bit 15 Bit 14 0600061E C1RXFUL1 0620 RXFUL15 RXFUL14 RXFUL13 RXFUL12 RXFUL11 RXFUL10 RXFUL9 0000 0000 0000 0000 0000 0000 0000 0000 xxxx xxxx C1RXFUL2 0622 RXFUL31 RXFUL30 RXFUL29 RXFUL28 RXFUL27 RXFUL26 RXFUL25 RXFUL24 RXFUL23 RXFUL22 RXFUL21 RXFUL20 RXFUL19 RXFUL18 RXFUL17 RXFUL16 C1RXOVF1 0628 RXOVF15 RXOVF14 RXOVF13 RXOVF12 RXOVF11 RXOVF10 RXOVF9 C1RXOVF2 062A RXOVF31 RXOVF30 RXOVF29 RXOVF28 RXOVF27 RXOVF26 RXOVF25 RXOVF24 RXOVF23 RXOVF22 RXOVF21 RXOVF20 RXOVF19 RXOVF18 RXOVF17 RXOVF16 C1TR01CON 0630 TXEN1 TXABT1 C1TR23CON 0632 TXEN3 TXABT3 C1TR45CON 0634 TXEN5 TXABT5 C1TR67CON 0636 TXEN7 TXABT7 C1RXD 0640 C1TXD 0642 DS70591B-page 89 Legend: x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. TABLE 4-38: Bit 13 See definition when WIN = x F3BP<3:0> F7BP<3:0> F11BP<3:0> F14BP<3:0> SID<10:3> -- EID<7:0> SID<2:0> -- EID<7:0> SID<2:0> -- EID<7:0> SID<2:0> -- -- -- -- -- -- SID<2:0> SID<2:0> SID<2:0> SID<2:0> SID<2:0> SID<2:0> -- -- -- -- -- -- SID<2:0> SID<2:0> SID<2:0> SID<2:0> SID<2:0> EXIDE EXIDE EID<7:0> EXIDE EID<7:0> EXIDE EID<7:0> EXIDE EID<7:0> EXIDE EID<7:0> EXIDE EID<7:0> EXIDE EID<7:0> EXIDE EID<7:0> EXIDE EID<7:0> EXIDE EID<7:0> EXIDE -- EID<17:16> -- EID<17:16> -- EID<17:16> -- EID<17:16> -- EID<17:16> -- EID<17:16> -- EID<17:16> -- EID<17:16> -- EID<17:16> -- EID<17:16> -- -- EID<17:16> EID<17:16> EID<7:0> MIDE -- EID<17:16> MIDE -- EID<17:16> MIDE -- EID<15:8> SID<10:3> EID<15:8> SID<10:3> EID<15:8> SID<10:3> EID<15:8> SID<10:3> EID<15:8> SID<10:3> EID<15:8> SID<10:3> EID<15:8> SID<10:3> EID<15:8> SID<10:3> EID<15:8> SID<10:3> EID<15:8> SID<10:3> EID<15:8> SID<10:3> EID<15:8> SID<10:3> EID<15:8> SID<10:3> EID<15:8> SID<10:3> SID<2:0> F13BP<3:0> F12BP<3:0> EID<17:16> F10BP<3:0> F9BP<3:0> F8BP<3:0> F6BP<3:0> F5BP<3:0> F4BP<3:0> F2BP<3:0> F1BP<3:0> F0BP<3:0> 0000 0000 0000 0000 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets ECAN1 REGISTER MAP WHEN C1CTRL1.WIN = 1 File Name Addr Bit 15 Bit 14 0600061E DS70591B-page 90 C1BUFPNT1 0620 C1BUFPNT2 0622 C1BUFPNT3 0624 C1BUFPNT4 0626 F15BP<3:0> C1RXM0SID 0630 C1RXM0EID 0632 C1RXM1SID 0634 C1RXM1EID 0636 C1RXM2SID 0638 C1RXM2EID 063A C1RXF0SID 0640 C1RXF0EID 0642 C1RXF1SID 0644 C1RXF1EID 0646 C1RXF2SID 0648 C1RXF2EID 064A dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 Preliminary C1RXF3SID 064C C1RXF3EID 064E C1RXF4SID 0650 C1RXF4EID 0652 C1RXF5SID 0654 C1RXF5EID 0656 C1RXF6SID 0658 C1RXF6EID 065A C1RXF7SID 065C C1RXF7EID 065E C1RXF8SID 0660 C1RXF8EID 0662 C1RXF9SID 0664 C1RXF9EID 0666 C1RXF10SID 0668 C1RXF10EID 066A C1RXF11SID 066C 2009 Microchip Technology Inc. Legend: x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. TABLE 4-38: Bit 13 EID<15:8> SID<10:3> -- EID<7:0> SID<2:0> -- EID<7:0> SID<2:0> -- EID<7:0> SID<2:0> -- EID<7:0> EXIDE -- EID<17:16> EXIDE -- EID<17:16> EXIDE -- EID<17:16> EXIDE -- EID<15:8> SID<10:3> EID<15:8> SID<10:3> EID<15:8> SID<10:3> EID<15:8> SID<2:0> EID<17:16> EID<7:0> Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ECAN1 REGISTER MAP WHEN C1CTRL1.WIN = 1 (CONTINUED) All Resets xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx File Name Addr Bit 15 Bit 14 C1RXF11EID 066E C1RXF12SID 0670 C1RXF12EID 0672 C1RXF13SID 0674 C1RXF13EID 0676 C1RXF14SID 0678 2009 Microchip Technology Inc. C1RXF14EID 067A C1RXF15SID 067C C1RXF15EID 067E Legend: x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 Preliminary DS70591B-page 91 TABLE 4-39: Bit 14 -- -- -- -- -- -- -- -- -- -- -- -- CMREF<9:0> CMPSIDL -- -- -- -- DACOE INSEL<1:0> EXTREF -- CMPSTAT -- -- -- -- CMREF<9:0> CMPPOL RANGE CMPSIDL -- -- -- -- DACOE INSEL<1:0> EXTREF -- CMPSTAT -- CMPPOL -- -- -- CMREF<9:0> RANGE CMPSIDL -- -- -- -- DACOE INSEL<1:0> EXTREF -- CMPSTAT -- CMPPOL -- -- -- CMREF<9:0> RANGE CMPSIDL -- -- -- -- DACOE INSEL<1:0> EXTREF -- CMPSTAT -- CMPPOL RANGE Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets 0000 0000 0000 0000 0000 0000 0000 0000 ANALOG COMPARATOR CONTROL REGISTER MAP File Name ADR Bit 15 CMPCON1 0540 CMPON CMPDAC1 0542 -- DS70591B-page 92 Bit 13 -- -- -- -- -- -- ODCA10 ODCA9 -- -- -- ODCA5 -- -- LATA10 LATA9 -- LATA7 LATA6 LATA5 -- -- RA10 RA9 -- RA7 RA6 RA5 -- -- TRISA10 TRISA9 -- TRISA7 TRISA6 TRISA5 TRISA4 RA4 LATA4 ODCA4 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 TRISA3 RA3 LATA3 -- Bit 2 TRISA2 RA2 LATA2 -- Bit 1 TRISA1 RA1 LATA1 ODCA1 Bit 0 TRISA0 RA0 LATA0 ODCA0 All Resets C6FF xxxx 0000 0000 Bit 13 -- -- -- -- -- -- ODCA10 ODCA9 -- -- LATA10 LATA9 -- -- -- -- RA10 RA9 -- -- -- TRISA10 TRISA9 -- -- -- -- -- Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 -- -- -- -- Bit 5 -- -- -- -- Bit 4 -- -- -- -- Bit 3 -- -- -- -- Bit 2 -- -- -- -- Bit 1 -- -- -- -- Bit 0 -- -- -- -- All Resets C600 xxxx 0000 0000 CMPCON2 0544 CMPON CMPDAC2 0546 -- CMPCON3 0548 CMPON CMPDAC3 054A -- CMPCON4 054C CMPON CMPDAC4 054E -- TABLE 4-40: PORTA REGISTER MAP FOR dsPIC33FJ32GS610 AND dsPIC33FJ64GS610 DEVICES SFR Name SFR Addr Bit 15 Bit 14 TRISA 02C0 TRISA15 TRISA14 PORTA 02C2 RA15 RA14 LATA 02C4 LATA15 LATA14 ODCA 02C6 ODCA15 ODCA14 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 Preliminary Legend: x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. TABLE 4-41: PORTA REGISTER MAP FOR dsPIC33FJ32GS608 AND dsPIC33FJ64GS608 DEVICES SFR Name SFR Addr Bit 15 Bit 14 TRISA 02C0 TRISA15 TRISA14 PORTA 02C2 RA15 RA14 LATA 02C4 LATA15 LATA14 ODCA 02C6 ODCA15 ODCA14 2009 Microchip Technology Inc. Legend: x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. TABLE 4-42: Bit 13 TRISB13 RB13 LATB13 LATB12 LATB11 LATB10 LATB9 LATB8 LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 RB12 RB11 RB10 RB9 RB8 RB7 RB6 RB5 RB4 RB3 RB2 RB1 TRISB12 TRISB11 TRISB10 TRISB9 TRISB8 TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 RB0 LATB0 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PORTB REGISTER MAP All Resets FFFF xxxx 0000 SFR Name SFR Addr Bit 15 Bit 14 TRISB 02C8 TRISB15 TRISB14 PORTB 02CA RB15 RB14 LATB 02CC LATB15 LATB14 Legend: x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. 2009 Microchip Technology Inc. Bit 13 TRISC13 RC13 -- -- -- -- -- -- -- -- LATC4 -- -- -- -- -- -- RC4 LATC13 LATC12 RC12 TRISC12 -- -- -- -- -- -- -- TRISC4 TRISC3 RC3 LATC3 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 TRISC2 RC2 LATC2 Bit 1 TRISC1 RC1 LATC1 Bit 0 -- -- -- Bit 13 TRISC13 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- RC13 LATC13 LATC12 RC12 TRISC12 -- -- -- Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 -- -- -- Bit 4 -- -- -- Bit 3 -- -- -- Bit 2 TRISC2 RC2 LATC2 Bit 1 TRISC1 RC1 LATC1 Bit 0 -- -- -- Bit 13 TRISC13 -- -- -- -- -- -- RC13 LATC13 LATC12 RC12 TRISC12 Bit 12 Bit 11 Bit 10 Bit 9 -- -- -- Bit 8 -- -- -- Bit 7 -- -- -- Bit 6 -- -- -- Bit 5 -- -- -- Bit 4 -- -- -- Bit 3 -- -- -- Bit 2 -- -- -- Bit 1 -- -- -- Bit 0 -- -- -- TABLE 4-43: PORTC REGISTER MAP FOR dsPIC33FJ32GS610 AND dsPIC33FJ64GS610 DEVICES All Resets F01E xxxx 0000 SFR Name SFR Addr Bit 15 Bit 14 TRISC 02D0 TRISC15 TRISC14 PORTC 02D2 RC15 RC14 LATC 02D4 LATC15 LATC14 Legend: x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. TABLE 4-44: PORTC REGISTER MAP FOR dsPIC33FJ32GS608 AND dsPIC33FJ64GS608 DEVICES All Resets F006 xxxx 0000 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 Preliminary SFR Name SFR Addr Bit 15 Bit 14 TRISC 02D0 TRISC15 TRISC14 PORTC 02D2 RC15 RC14 LATC 02D4 LATC15 LATC14 Legend: x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. TABLE 4-45: PORTC REGISTER MAP FOR dsPIC33FJ32GS406/606 AND DSPIC33FJ64GS406/606 DEVICES All Resets F000 xxxx 0000 SFR Name SFR Addr Bit 15 Bit 14 TRISC 02D0 TRISC15 TRISC14 PORTC 02D2 RC15 RC14 LATC 02D4 LATC15 LATC14 DS70591B-page 93 Legend: x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. TABLE 4-46: Bit 13 TRISD11 RD11 LATD11 ODCD11 ODCD10 ODCD9 ODCD8 ODCD7 ODCD6 ODCD5 ODCD4 ODCD3 ODCD2 ODCD1 LATD10 LATD9 LATD8 LATD7 LATD6 LATD5 LATD4 LATD3 LATD2 LATD1 RD10 RD9 RD8 RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 LATD0 ODCD0 TRISD10 TRISD9 TRISD8 TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets FFFF xxxx 0000 0000 PORTD REGISTER MAP FOR dsPIC33FJ32GS608/610 AND dsPIC33FJ64GS608/610 DEVICES SFR Name SFR Addr Bit 15 Bit 14 TRISD RD13 LATD13 ODCD13 ODCD12 LATD12 RD12 02D8 TRISD15 TRISD14 TRISD13 TRISD12 PORTD 02DA RD15 RD14 DS70591B-page 94 Bit 13 -- -- -- -- -- ODCD11 ODCD10 ODCD9 ODCD8 ODCD7 ODCD6 ODCD5 ODCD4 -- LATD11 LATD10 LATD9 LATD8 LATD7 LATD6 LATD5 LATD4 -- RD11 RD10 RD9 RD8 RD7 RD6 RD5 RD4 -- TRISD11 TRISD10 TRISD9 TRISD8 TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 RD3 LATD3 ODCD3 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 TRISD2 RD2 LATD2 ODCD2 Bit 1 TRISD1 RD1 LATD1 ODCD1 Bit 0 TRISD0 RD0 LATD0 ODCD0 All Resets 0FFF xxxx 0000 0000 Bit 13 -- -- -- -- -- -- -- -- -- -- -- -- LATE9 LATE8 -- -- -- RE9 RE8 RE7 LATE7 ODCE7 -- -- -- TRISE9 TRISE8 TRISE7 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 TRISE6 RE6 LATE6 ODCE6 Bit 5 TRISE5 RE5 LATE5 ODCE5 Bit 4 TRISE4 RE4 LATE4 ODCE4 Bit 3 TRISE3 RE3 LATE3 ODCE3 Bit 2 TRISE2 RE2 LATE2 ODCE2 Bit 1 TRISE1 RE1 LATE1 ODCE1 Bit 0 TRISE0 RE0 LATE0 ODCE0 All Resets 03FF xxxx 0000 0000 Bit 13 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Bit 12 Bit 11 Bit 10 Bit 9 -- -- -- -- Bit 8 -- -- -- -- Bit 7 TRISE7 RE7 LATE7 ODCE7 Bit 6 TRISE6 RE6 LATE6 ODCE6 Bit 5 TRISE5 RE5 LATE5 ODCE5 Bit 4 TRISE4 RE4 LATE4 ODCE4 Bit 3 TRISE3 RE3 LATE3 ODCE3 Bit 2 TRISE2 RE2 LATE2 ODCE2 Bit 1 TRISE1 RE1 LATE1 ODCE1 Bit 0 TRISE0 RE0 LATE0 ODCE0 All Resets 00FF xxxx 0000 0000 LATD 02DC LATD15 LATD14 ODCD 02DE ODCD15 ODCD14 Legend: x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. TABLE 4-47: PORTD REGISTER MAP FOR dsPIC33FJ32GS406/606 AND DSPIC33FJ64GS406/606 DEVICES SFR Name SFR Addr Bit 15 Bit 14 TRISD 02D8 -- -- PORTD 02DA -- -- LATD 02DC -- -- ODCD 02DE -- -- Legend: x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 Preliminary TABLE 4-48: PORTE REGISTER MAP FOR dsPIC33FJ32GS608/610 AND dsPIC33FJ64GS608/610 DEVICES SFR Name SFR Addr Bit 15 Bit 14 TRISE 02E0 -- -- PORTE 02E2 -- -- LATE 02E4 -- -- ODCE 02E6 -- -- Legend: x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. TABLE 4-49: PORTE REGISTER MAP FOR dsPIC33FJ32GS406/606 AND DSPIC33FJ64GS406/606 DEVICES SFR Name SFR Addr Bit 15 Bit 14 TRISE 02E0 -- -- PORTE 02E2 -- -- LATE 02E4 -- -- ODCE 02E6 -- -- 2009 Microchip Technology Inc. Legend: x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. TABLE 4-50: Bit 13 TRISF13 RF13 LATF13 ODCF13 ODCF12 -- -- -- ODCF8 ODCF7 ODCF6 -- -- ODCF3 ODCF2 LATF12 -- -- -- LATF8 LATF7 LATF6 LATF5 LATF4 LATF3 LATF2 LATF1 ODCF1 RF12 -- -- -- RF8 RF7 RF6 RF5 RF4 RF3 RF2 RF1 TRISF12 -- -- -- TRISF8 TRISF7 TRISF6 TRISF5 TRISF4 TRISF3 TRISF2 TRISF1 TRISF0 RF0 LATF0 -- Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PORTF REGISTER MAP FOR dsPIC33FJ32GS610 AND dsPIC33FJ64GS610 DEVICES All Resets 30FF xxxx 0000 0000 SFR Name SFR Addr Bit 15 Bit 14 TRISF 02E8 -- -- PORTF 02EA -- -- LATF 02EC -- -- ODCF 02EE -- -- 2009 Microchip Technology Inc. Bit 13 -- -- -- -- -- -- -- -- ODCF8 ODCF7 ODCF6 -- -- -- -- -- LATF8 LATF7 LATF6 LATF5 -- -- -- -- -- RF8 RF7 RF6 RF5 RF4 LATF4 -- -- -- -- TRISF8 TRISF7 TRISF6 TRISF5 TRISF4 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 TRISF3 RF3 LATF3 ODCF3 Bit 2 TRISF2 RF2 LATF2 ODCF2 Bit 1 TRISF1 RF1 LATF1 ODCF1 Bit 0 TRISF0 RF0 LATF0 -- Bit 13 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 TRISF6 RF6 LATF6 ODCF6 Bit 5 TRISF5 RF5 LATF5 -- Bit 4 TRISF4 RF4 LATF4 -- Bit 3 TRISF3 RF3 LATF3 ODCF3 Bit 2 TRISF2 RF2 LATF2 ODCF2 Bit 1 TRISF1 RF1 LATF1 ODCF1 Bit 0 TRISF0 RF0 LATF0 -- Bit 13 -- -- -- -- Bit 12 Bit 11 Bit 10 -- -- -- -- Bit 9 TRISG9 RG9 LATG9 ODCG9 Bit 8 TRISG8 RG8 LATG8 ODCG8 Bit 7 TRISG7 RG7 LATG7 ODCG7 Bit 6 TRISG6 RG6 LATG6 ODCG6 Bit 5 -- -- -- -- Bit 4 -- -- -- -- Bit 3 TRISG3 RG3 LATG3 -- Bit 2 TRISG2 RG2 LATG2 -- Bit 1 TRISG1 RG1 LATG1 ODCG1 Bit 0 TRISG0 RG0 LATG0 ODCG0 RG13 LATG13 LATG12 RG12 Legend: x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. TABLE 4-51: PORTF REGISTER MAP FOR dsPIC33FJ32GS608 AND dsPIC33FJ64GS608 DEVICES All Resets 01FF xxxx 0000 0000 SFR Name SFR Addr Bit 15 Bit 14 TRISF 02E8 -- -- PORTF 02EA -- -- LATF 02EC -- -- ODCF 02EE -- -- Legend: x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 Preliminary TABLE 4-52: PORTF REGISTER MAP FOR dsPIC33FJ32GS406/606 AND DSPIC33FJ64GS406/606 DEVICES All Resets 007F xxxx 0000 0000 SFR Name SFR Addr Bit 15 Bit 14 TRISF 02E8 -- -- PORTF 02EA -- -- LATF 02EC -- -- ODCF 02EE -- -- Legend: x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. TABLE 4-53: PORTG REGISTER MAP FOR dsPIC33FJ32GS610 AND dsPIC33FJ64GS610 DEVICES All Resets F3CF xxxx 0000 0000 SFR Name SFR Addr Bit 15 Bit 14 TRISG 02F0 TRISG15 TRISG14 TRISG13 TRISG12 PORTG 02F2 RG15 RG14 LATG 02F4 LATG15 LATG14 ODCG 02F6 ODCG15 ODCG14 ODCG13 ODCG12 DS70591B-page 95 Legend: x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. TABLE 4-54: Bit 13 -- -- -- -- -- -- -- ODCG9 ODCG8 ODCG7 ODCG6 -- -- -- -- ODCG1 -- -- -- LATG9 LATG8 LATG7 LATG6 -- -- LATG3 LATG2 LATG1 -- -- -- RG9 RG8 RG7 RG6 -- -- RG3 RG2 RG1 RG0 LATG0 ODCG0 -- -- -- TRISG9 TRISG8 TRISG7 TRISG6 -- -- TRISG3 TRISG2 TRISG1 TRISG0 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets 03CF xxxx 0000 0000 PORTG REGISTER MAP FOR dsPIC33FJ32GS608 AND dsPIC33FJ64GS608 DEVICES SFR Name SFR Addr Bit 15 Bit 14 TRISG 02F0 -- -- PORTG 02F2 -- -- DS70591B-page 96 Bit 13 -- -- -- -- -- -- -- ODCG9 ODCG8 ODCG7 ODCG6 -- -- -- -- -- LATG9 LATG8 LATG7 LATG6 -- -- -- -- -- RG9 RG8 RG7 RG6 -- -- -- -- -- TRISG9 TRISG8 TRISG7 TRISG6 -- -- TRISG3 RG3 LATG3 -- Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 TRISG2 RG2 LATG2 -- Bit 1 -- -- -- -- Bit 0 -- -- -- -- All Resets 03CC xxxx 0000 0000 Bit 13 -- COSC<2:0> DOZE<2:0> -- -- -- SELACLK -- -- APSTSCLR<2:0> ROSSLP ROSEL RODIV<3:0> -- -- -- -- -- -- -- -- -- -- -- -- -- ASRCSEL -- -- FRCSEL -- -- -- -- DOZEN FRCDIV<2:0> -- NOSC<2:0> CLKLOCK -- -- -- -- VREGS EXTR SWR -- Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 SWDTEN LOCK -- PLLDIV<8:0> TUN<5:0> -- -- -- -- -- -- -- -- Bit 4 WDTO -- Bit 3 SLEEP CF Bit 2 IDLE -- PLLPRE<4:0> Bit 1 BOR -- Bit 0 POR OSWEN All Resets xxxx(1) 0300(2) 0040 0030 0000 0000 2300 PLLPOST<1:0> LATG 02F4 -- -- ODCG 02F6 -- -- Legend: x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. TABLE 4-55: PORTG REGISTER MAP FOR dsPIC33FJ32GS406/606 AND DSPIC33FJ64GS406/606 DEVICES SFR Name SFR Addr Bit 15 Bit 14 TRISG 02F0 -- -- PORTG 02F2 -- -- LATG 02F4 -- -- ODCG 02F6 -- -- Legend: x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 Preliminary TABLE 4-56: SYSTEM CONTROL REGISTER MAP SFR Name SFR Addr Bit 15 Bit 14 RCON 0740 TRAPR IOPUWR OSCCON 0742 -- CLKDIV 0744 ROI PLLFBD 0746 -- OSCTUN 0748 -- REFOCON 074E ROON ACLKCON 0750 ENAPLL APLLCK 2009 Microchip Technology Inc. Legend: Note 1: 2: x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. The RCON register reset values are dependent on type of reset. The OSCCON register reset values are dependent on the FOSC configuration bits, and on type of reset. TABLE 4-57: Bit 13 WRERR -- -- -- -- -- -- NVMKEY<7:0> -- -- -- -- -- -- ERASE -- -- NVMOP<3:0> Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 NVM REGISTER MAP All Resets 0000(1) 0000 SFR Name Addr Bit 15 Bit 14 NVMCON 0760 WR WREN NVMKEY 0766 -- -- Legend: Note 1: x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. Reset value shown is for POR only. Value on other Reset states is dependent on the state of memory write or erase operations at the time of Reset. 2009 Microchip Technology Inc. Bit 13 T3MD -- IC1MD -- -- -- -- -- -- -- -- CMP1MD -- -- -- -- -- -- -- -- QEI2MD -- -- -- -- -- I2C1MD U2MD U1MD -- -- -- -- -- CMP4MD CMP3MD CMP2MD -- -- -- -- -- -- CMPMD -- -- IC4MD IC3MD IC2MD T2MD T1MD QEI1MD PWMMD SPI2MD SPI1MD OC4MD -- REFOMD -- -- Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 -- OC3MD -- -- -- -- Bit 1 C1MD OC2MD I2C2MD -- -- -- Bit 0 ADCMD OC1MD -- -- -- PWM9MD Bit 13 T3MD -- IC1MD -- -- CMP1MD -- -- -- -- -- CMP4MD CMP3MD CMP2MD -- -- -- -- -- -- CMPMD -- -- IC4MD IC3MD IC2MD T2MD T1MD QEI1MD PWMMD Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 I2C1MD -- -- -- -- -- Bit 6 U2MD -- -- -- -- -- Bit 5 U1MD -- QEI2MD -- -- -- Bit 4 Bit 3 SPI2MD SPI1MD -- -- -- -- -- OC4MD -- REFOMD -- -- Bit 2 -- OC3MD -- -- -- -- Bit 1 -- OC2MD I2C2MD -- -- -- Bit 0 ADCMD OC1MD -- -- -- PWM9MD TABLE 4-58: PMD REGISTER MAP FOR dsPIC33FJ64GS610 DEVICES All Resets 0000 0000 0000 0000 0000 0000 SFR Name SFR Addr Bit 15 Bit 14 PMD1 0770 T5MD T4MD PMD2 0772 -- -- PMD3 0774 -- -- PMD4 0776 -- -- PMD6 077A PWM8MD PWM7MD PWM6MD PWM5MD PWM4MD PWM3MD PWM2MD PWM1MD PMD7 077C -- -- dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 Preliminary Legend: x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. TABLE 4-59: PMD REGISTER MAP FOR dsPIC33FJ32GS610 DEVICES All Resets 0000 0000 0000 0000 0000 0000 SFR Name SFR Addr Bit 15 Bit 14 PMD1 0770 T5MD T4MD PMD2 0772 -- -- PMD3 0774 -- -- PMD4 0776 -- -- PMD6 077A PWM8MD PWM7MD PWM6MD PWM5MD PWM4MD PWM3MD PWM2MD PWM1MD PMD7 077C -- -- Legend: x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. DS70591B-page 97 TABLE 4-60: Bit 13 T3MD -- IC1MD -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- CMP1MD -- -- -- -- REFOMD -- -- -- -- QEI2MD -- -- -- I2C2MD -- -- -- -- -- -- -- -- OC4MD OC3MD OC2MD OC1MD I2C1MD U2MD U1MD SPI2MD SPI1MD -- C1MD ADCMD -- -- -- -- -- CMP4MD CMP3MD CMP2MD -- -- -- -- -- -- CMPMD -- -- IC4MD IC3MD IC2MD T2MD T1MD QEI1MD PWMMD Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets 0000 0000 0000 0000 0000 0000 PMD REGISTER MAP FOR dsPIC33FJ64GS608 DEVICES SFR Name SFR Addr Bit 15 Bit 14 PMD1 0770 T5MD T4MD PMD2 0772 -- -- DS70591B-page 98 Bit 13 T3MD -- -- -- -- -- -- -- -- -- -- -- CMP4MD CMP3MD CMP2MD CMP1MD -- -- -- -- -- -- -- -- -- -- CMPMD -- -- -- -- QEI2MD -- IC4MD IC3MD IC2MD IC1MD -- -- -- -- -- -- -- -- T2MD T1MD QEI1MD PWMMD -- I2C1MD U2MD U1MD Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 -- OC4MD -- REFOMD -- -- OC3MD -- -- -- -- Bit 1 -- OC2MD I2C2MD -- -- -- Bit 0 ADCMD OC1MD -- -- -- -- All Resets 0000 0000 0000 0000 0000 0000 SPI2MD SPI1MD Bit 13 T3MD -- -- -- -- -- -- -- -- -- -- -- CMPMD -- -- IC4MD IC3MD IC2MD T2MD T1MD QEI1MD PWMMD -- IC1MD -- -- Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 I2C1MD -- -- -- -- -- Bit 6 U2MD -- -- -- -- -- Bit 5 U1MD -- QEI2MD -- -- -- Bit 4 Bit 3 SPI2MD SPI1MD -- -- -- -- -- OC4MD -- REFOMD -- -- Bit 2 -- -- -- -- -- Bit 1 C1MD OC3MD OC2MD I2C2MD -- -- -- Bit 0 ADCMD OC1MD -- -- -- -- All Resets 0000 0000 0000 0000 0000 0000 PWM6MD PWM5MD PWM4MD PWM3MD PWM2MD PWM1MD CMP4MD CMP3MD CMP2MD CMP1MD PMD3 0774 -- -- PMD4 0776 -- -- PMD6 077A PWM8MD PWM7MD PWM6MD PWM5MD PWM4MD PWM3MD PWM2MD PWM1MD PMD7 077C -- -- Legend: x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. TABLE 4-61: PMD REGISTER MAP FOR dsPIC33FJ32GS608 DEVICES SFR Name SFR Addr Bit 15 Bit 14 PMD1 0770 T5MD T4MD PMD2 0772 -- -- PMD3 0774 -- -- PMD4 0776 -- -- PMD6 077A PWM8MD PWM7MD PWM6MD PWM5MD PWM4MD PWM3MD PWM2MD PWM1MD PMD7 077C -- -- dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 Preliminary Legend: x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. TABLE 4-62: PMD REGISTER MAP FOR dsPIC33FJ64GS606 DEVICES SFR Name SFR Addr Bit 15 Bit 14 PMD1 0770 T5MD T4MD PMD2 0772 -- -- PMD3 0774 -- -- PMD4 0776 -- -- PMD6 077A -- -- PMD7 077C -- -- 2009 Microchip Technology Inc. Legend: x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. TABLE 4-63: Bit 13 T3MD -- IC1MD -- -- -- -- -- -- -- -- -- -- -- -- -- -- CMP1MD -- -- -- -- REFOMD -- -- -- -- -- -- QEI2MD -- -- -- I2C2MD -- -- -- -- OC4MD OC3MD OC2MD I2C1MD U2MD U1MD SPI2MD SPI1MD -- -- -- -- -- PWM6MD PWM5MD PWM4MD PWM3MD PWM2MD PWM1MD -- -- CMP4MD CMP3MD CMP2MD -- -- -- -- -- -- CMPMD -- -- IC4MD IC3MD IC2MD T2MD T1MD QEI1MD PWMMD ADCMD OC1MD -- -- -- -- Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PMD REGISTER MAP FOR dsPIC33FJ32GS606 DEVICES All Resets 0000 0000 0000 0000 0000 0000 SFR Name SFR Addr Bit 15 Bit 14 PMD1 0770 T5MD T4MD PMD2 0772 -- -- PMD3 0774 -- -- PMD4 0776 -- -- PMD6 077A -- -- PMD7 077C -- -- 2009 Microchip Technology Inc. Bit 13 T3MD -- -- -- PWM6MD PWM5MD PWM4MD PWM3MD PWM2MD PWM1MD -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- IC4MD IC3MD IC2MD IC1MD -- -- -- QEI2MD T2MD T1MD QEI1MD PWMMD -- I2C1MD U2MD U1MD Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 -- -- -- -- -- OC4MD -- REFOMD -- -- -- -- Bit 1 -- OC3MD OC2MD I2C2MD -- -- Bit 0 ADCMD OC1MD -- -- -- SPI2MD SPI1MD Legend: x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. TABLE 4-64: PMD REGISTER MAP FOR dsPIC33FJ32GS406 AND DSPIC33FJ64GS406 DEVICES All Resets 0000 0000 0000 0000 0000 SFR Name SFR Addr Bit 15 Bit 14 PMD1 0770 T5MD T4MD PMD2 0772 -- -- PMD3 0774 -- -- PMD4 0776 -- -- PMD6 077A -- -- dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 Preliminary Legend: x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. DS70591B-page 99 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 4.2.7 SOFTWARE STACK 4.3 Instruction Addressing Modes In addition to its use as a working register, the W15 register in the dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 devices is also used as a software Stack Pointer. The Stack Pointer always points to the first available free word and grows from lower to higher addresses. It predecrements for stack pops and post-increments for stack pushes, as shown in Figure 4-6. For a PC push during any CALL instruction, the MSb of the PC is zero-extended before the push, ensuring that the MSb is always clear. Note: A PC push during exception processing concatenates the SRL register to the MSb of the PC prior to the push. The addressing modes shown in Table 4-65 form the basis of the addressing modes optimized to support the specific features of individual instructions. The addressing modes provided in the MAC class of instructions differ from those in the other instruction types. 4.3.1 FILE REGISTER INSTRUCTIONS The Stack Pointer Limit register (SPLIM) associated with the Stack Pointer sets an upper address boundary for the stack. SPLIM is uninitialized at Reset. As is the case for the Stack Pointer, SPLIM<0> is forced to `0' because all stack operations must be word-aligned. Whenever an EA is generated using W15 as a source or destination pointer, the resulting address is compared with the value in SPLIM. If the contents of the Stack Pointer (W15) and the SPLIM register are equal and a push operation is performed, a stack error trap will not occur. The stack error trap will occur on a subsequent push operation. For example, to cause a stack error trap when the stack grows beyond address 0x1800 in RAM, initialize the SPLIM with the value 0x17FE. Similarly, a Stack Pointer underflow (stack error) trap is generated when the Stack Pointer address is found to be less than 0x0800. This prevents the stack from interfering with the Special Function Register (SFR) space. A write to the SPLIM register should not be immediately followed by an indirect read operation using W15. Most file register instructions use a 13-bit address field (f) to directly address data present in the first 8192 bytes of data memory (near data space). Most file register instructions employ a working register, W0, which is denoted as WREG in these instructions. The destination is typically either the same file register or WREG (with the exception of the MUL instruction), which writes the result to a register or register pair. The MOV instruction allows additional flexibility and can access the entire data space. 4.3.2 MCU INSTRUCTIONS The three-operand MCU instructions are of the form: Operand 3 = Operand 1 FIGURE 4-6: 0x0000 15 CALL STACK FRAME 0 Stack Grows Toward Higher Address PC<15:0> 000000000 PC<22:16> W15 (before CALL) W15 (after CALL) POP : [--W15] PUSH : [W15++] DS70591B-page 100 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 TABLE 4-65: FUNDAMENTAL ADDRESSING MODES SUPPORTED Description The address of the file register is specified explicitly. The contents of a register are accessed directly. The contents of Wn forms the Effective Address (EA). The contents of Wn forms the EA. Wn is post-modified (incremented or decremented) by a constant value. Wn is pre-modified (incremented or decremented) by a signed constant value to form the EA. Addressing Mode File Register Direct Register Direct Register Indirect Register Indirect Post-Modified Register Indirect Pre-Modified Register Indirect with Register Offset The sum of Wn and Wb forms the EA. (Register Indexed) Register Indirect with Literal Offset The sum of Wn and a literal forms the EA. 4.3.3 MOVE AND ACCUMULATOR INSTRUCTIONS 4.3.4 MAC INSTRUCTIONS Move instructions and the DSP accumulator class of instructions provide a greater degree of addressing flexibility than other instructions. In addition to the addressing modes supported by most MCU instructions, move and accumulator instructions also support Register Indirect with Register Offset Addressing mode, also referred to as Register Indexed mode. Note: For the MOV instructions, the addressing mode specified in the instruction can differ for the source and destination EA. However, the 4-bit Wb (Register Offset) field is shared by both source and destination (but typically only used by one). The dual source operand DSP instructions (CLR, ED, EDAC, MAC, MPY, MPY.N, MOVSAC and MSC), also referred to as MAC instructions, use a simplified set of addressing modes to allow the user application to effectively manipulate the data pointers through register indirect tables. The two-source operand prefetch registers must be members of the set {W8, W9, W10, W11}. For data reads, W8 and W9 are always directed to the X RAGU, and W10 and W11 are always directed to the Y AGU. The effective addresses generated (before and after modification) must, therefore, be valid addresses within X data space for W8 and W9 and Y data space for W10 and W11. Note: Register Indirect with Register Offset Addressing mode is available only for W9 (in X space) and W11 (in Y space). In summary, the following addressing modes are supported by move and accumulator instructions: * * * * * * * * Register Direct Register Indirect Register Indirect Post-modified Register Indirect Pre-modified Register Indirect with Register Offset (Indexed) Register Indirect with Literal Offset 8-bit Literal 16-bit Literal Note: Not all instructions support all the addressing modes given above. Individual instructions may support different subsets of these addressing modes. In summary, the following addressing modes are supported by the MAC class of instructions: * * * * * Register Indirect Register Indirect Post-Modified by 2 Register Indirect Post-Modified by 4 Register Indirect Post-Modified by 6 Register Indirect with Register Offset (Indexed) 4.3.5 OTHER INSTRUCTIONS Besides the addressing modes outlined previously, some instructions use literal constants of various sizes. For example, BRA (branch) instructions use 16-bit signed literals to specify the branch destination directly, whereas the DISI instruction uses a 14-bit unsigned literal field. In some instructions, such as ADD Acc, the source of an operand or result is implied by the opcode itself. Certain operations, such as NOP, do not have any operands. 2009 Microchip Technology Inc. Preliminary DS70591B-page 101 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 4.4 Modulo Addressing Note: Modulo Addressing mode is a method used to provide an automated means to support circular data buffers using hardware. The objective is to remove the need for software to perform data address boundary checks when executing tightly looped code, as is typical in many DSP algorithms. Modulo Addressing can operate in either data or program space (since the data pointer mechanism is essentially the same for both). One circular buffer can be supported in each of the X (which also provides the pointers into program space) and Y data spaces. Modulo Addressing can operate on any W register pointer. However, it is not advisable to use W14 or W15 for Modulo Addressing since these two registers are used as the Stack Frame Pointer and Stack Pointer, respectively. In general, any particular circular buffer can be configured to operate in only one direction as there are certain restrictions on the buffer start address (for incrementing buffers), or end address (for decrementing buffers), based upon the direction of the buffer. The only exception to the usage restrictions is for buffers that have a power-of-two length. As these buffers satisfy the start and end address criteria, they can operate in a bidirectional mode (that is, address boundary checks are performed on both the lower and upper address boundaries). Y space Modulo Addressing EA calculations assume word-sized data (LSb of every EA is always clear). The length of a circular buffer is not directly specified. It is determined by the difference between the corresponding start and end addresses. The maximum possible length of the circular buffer is 32K words (64 Kbytes). 4.4.2 W ADDRESS REGISTER SELECTION The Modulo and Bit-Reversed Addressing Control register, MODCON<15:0>, contains enable flags as well as a W register field to specify the W Address registers. The XWM and YWM fields select the registers that will operate with Modulo Addressing: * If XWM = 15, X RAGU and X WAGU Modulo Addressing is disabled. * If YWM = 15, Y AGU Modulo Addressing is disabled. The X Address Space Pointer W register (XWM), to which Modulo Addressing is to be applied, is stored in MODCON<3:0> (see Table 4-1). Modulo Addressing is enabled for X data space when XWM is set to any value other than `15' and the XMODEN bit is set at MODCON<15>. The Y Address Space Pointer W register (YWM) to which Modulo Addressing is to be applied is stored in MODCON<7:4>. Modulo Addressing is enabled for Y data space when YWM is set to any value other than `15' and the YMODEN bit is set at MODCON<14>. 4.4.1 START AND END ADDRESS The Modulo Addressing scheme requires that a starting and ending address be specified and loaded into the 16-bit Modulo Buffer Address registers: XMODSRT, XMODEND, YMODSRT and YMODEND (see Table 4-1). FIGURE 4-7: Byte Address 0x1100 MODULO ADDRESSING OPERATION EXAMPLE MOV MOV MOV MOV MOV MOV MOV MOV #0x1100, W0 W0, XMODSRT #0x1163, W0 W0, MODEND #0x8001, W0 W0, MODCON #0x0000, W0 #0x1110, W1 ;set modulo start address ;set modulo end address ;enable W1, X AGU for modulo ;W0 holds buffer fill value ;point W1 to buffer ;fill the 50 buffer locations ;fill the next location ;increment the fill value 0x1163 DO AGAIN, #0x31 MOV W0, [W1++] AGAIN: INC W0, W0 Start Addr = 0x1100 End Addr = 0x1163 Length = 0x0032 words DS70591B-page 102 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 4.4.3 MODULO ADDRESSING APPLICABILITY If the length of a bit-reversed buffer is M = 2N bytes, the last `N' bits of the data buffer start address must be zeros. XB<14:0> is the Bit-Reversed Address modifier, or `pivot point,' which is typically a constant. In the case of an FFT computation, its value is equal to half of the FFT data buffer size. Note: All bit-reversed EA calculations assume word-sized data (LSb of every EA is always clear). The XB value is scaled accordingly to generate compatible (byte) addresses. Modulo Addressing can be applied to the Effective Address (EA) calculation associated with any W register. Address boundaries check for addresses equal to: * The upper boundary addresses for incrementing buffers * The lower boundary addresses for decrementing buffers It is important to realize that the address boundaries check for addresses less than or greater than the upper (for incrementing buffers) and lower (for decrementing buffers) boundary addresses (not just equal to). Address changes can, therefore, jump beyond boundaries and still be adjusted correctly. Note: The modulo corrected effective address is written back to the register only when Pre-Modify or Post-Modify Addressing mode is used to compute the effective address. When an address offset (such as [W7 + W2]) is used, Modulo Address correction is performed but the contents of the register remain unchanged. When enabled, Bit-Reversed Addressing is executed only for Register Indirect with Pre-Increment or Post-Increment Addressing and word-sized data writes. It will not function for any other addressing mode or for byte-sized data, and normal addresses are generated instead. When Bit-Reversed Addressing is active, the W Address Pointer is always added to the address modifier (XB), and the offset associated with the Register Indirect Addressing mode is ignored. In addition, as word-sized data is a requirement, the LSb of the EA is ignored (and always clear). Note: Modulo Addressing and Bit-Reversed Addressing should not be enabled together. If an application attempts to do so, Bit-Reversed Addressing will assume priority when active for the X WAGU and X WAGU, Modulo Addressing will be disabled. However, Modulo Addressing will continue to function in the X RAGU. 4.5 Bit-Reversed Addressing Bit-Reversed Addressing mode is intended to simplify data re-ordering for radix-2 FFT algorithms. It is supported by the X AGU for data writes only. The modifier, which can be a constant value or register contents, is regarded as having its bit order reversed. The address source and destination are kept in normal order. Thus, the only operand requiring reversal is the modifier. 4.5.1 BIT-REVERSED ADDRESSING IMPLEMENTATION If Bit-Reversed Addressing has already been enabled by setting the BREN (XBREV<15>) bit, a write to the XBREV register should not be immediately followed by an indirect read operation using the W register that has been designated as the bit-reversed pointer. Bit-Reversed Addressing mode is enabled in any of these situations: * BWM bits (W register selection) in the MODCON register are any value other than `15' (the stack cannot be accessed using Bit-Reversed Addressing) * The BREN bit is set in the XBREV register * The addressing mode used is Register Indirect with Pre-Increment or Post-Increment 2009 Microchip Technology Inc. Preliminary DS70591B-page 103 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 FIGURE 4-8: BIT-REVERSED ADDRESS EXAMPLE Sequential Address b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 0 Bit Locations Swapped Left-to-Right Around Center of Binary Value b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b1 b2 b3 b4 0 Bit-Reversed Address Pivot Point XB = 0x0008 for a 16-Word Bit-Reversed Buffer TABLE 4-66: A3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 A2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 BIT-REVERSED ADDRESS SEQUENCE (16-ENTRY) Normal Address A1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Decimal 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 A3 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 A2 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 Bit-Reversed Address A1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 A0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Decimal 0 8 4 12 2 10 6 14 1 9 5 13 3 11 7 15 DS70591B-page 104 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 4.6 Interfacing Program and Data Memory Spaces 4.6.1 ADDRESSING PROGRAM SPACE The dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 architecture uses a 24-bit-wide program space and a 16-bit-wide data space. The architecture is also a modified Harvard scheme, meaning that data can also be present in the program space. To use this data successfully, it must be accessed in a way that preserves the alignment of information in both spaces. Aside from normal execution, the dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 architecture provides two methods by which program space can be accessed during operation: * Using table instructions to access individual bytes or words anywhere in the program space * Remapping a portion of the program space into the data space (Program Space Visibility) Table instructions allow an application to read or write to small areas of the program memory. This capability makes the method ideal for accessing data tables that need to be updated periodically. It also allows access to all bytes of the program word. The remapping method allows an application to access a large block of data on a read-only basis, which is ideal for look-ups from a large table of static data. The application can only access the least significant word of the program word. Since the address ranges for the data and program spaces are 16 and 24 bits, respectively, a method is needed to create a 23-bit or 24-bit program address from 16-bit data registers. The solution depends on the interface method to be used. For table operations, the 8-bit Table Page register (TBLPAG) is used to define a 32K word region within the program space. This is concatenated with a 16-bit EA to arrive at a full 24-bit program space address. In this format, the Most Significant bit of TBLPAG is used to determine if the operation occurs in the user memory (TBLPAG<7> = 0) or the configuration memory (TBLPAG<7> = 1). For remapping operations, the 8-bit Program Space Visibility Register (PSVPAG) is used to define a 16K word page in the program space. When the Most Significant bit of the EA is `1', PSVPAG is concatenated with the lower 15 bits of the EA to form a 23-bit program space address. Unlike table operations, this limits remapping operations strictly to the user memory area. Table 4-67 and Figure 4-9 show how the program EA is created for table operations and remapping accesses from the data EA. Here, P<23:0> refers to a program space word, and D<15:0> refers to a data space word. TABLE 4-67: PROGRAM SPACE ADDRESS CONSTRUCTION Access Space User User Configuration Program Space Address <23> 0 0xx xxxx TBLPAG<7:0> 0xxx xxxx TBLPAG<7:0> 1xxx xxxx 0 0 PSVPAG<7:0> xxxx xxxx <22:16> <15> PC<22:1> xxxx xxxx xxxx xxx0 Data EA<15:0> xxxx xxxx xxxx xxxx Data EA<15:0> xxxx xxxx xxxx xxxx Data EA<14:0>(1) xxx xxxx xxxx xxxx <14:1> <0> 0 Access Type Instruction Access (Code Execution) TBLRD/TBLWT (Byte/Word Read/Write) Program Space Visibility (Block Remap/Read) Note 1: User Data EA<15> is always `1' in this case, but is not used in calculating the program space address. Bit 15 of the address is PSVPAG<0>. 2009 Microchip Technology Inc. Preliminary DS70591B-page 105 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 FIGURE 4-9: DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION Program Counter(1) 0 Program Counter 23 bits EA 0 1/0 Table Operations(2) 1/0 TBLPAG 8 bits 24 bits 16 bits Select Program Space Visibility(1) (Remapping) 0 PSVPAG 8 bits 1 EA 0 15 bits 23 bits User/Configuration Space Select Byte Select Note 1: The Least Significant bit (LSb) of program space addresses is always fixed as `0' to maintain word alignment of data in the program and data spaces. 2: Table operations are not required to be word-aligned. Table read operations are permitted in the configuration memory space. DS70591B-page 106 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 4.6.2 DATA ACCESS FROM PROGRAM MEMORY USING TABLE INSTRUCTIONS - In Byte mode, either the upper or lower byte of the lower program word is mapped to the lower byte of a data address. The upper byte is selected when Byte Select is `1'; the lower byte is selected when it is `0'. * TBLRDH (Table Read High): - In Word mode, this instruction maps the entire upper word of a program address (P<23:16>) to a data address. Note that D<15:8>, the `phantom byte', will always be `0'. - In Byte mode, this instruction maps the upper or lower byte of the program word to D<7:0> of the data address, in the TBLRDL instruction. The data is always `0' when the upper `phantom' byte is selected (Byte Select = 1). Similarly, two table instructions, TBLWTH and TBLWTL, are used to write individual bytes or words to a program space address. The details of their operation are explained in Section 5.0 "Flash Program Memory". For all table operations, the area of program memory space to be accessed is determined by the Table Page register (TBLPAG). TBLPAG covers the entire program memory space of the device, including user and configuration spaces. When TBLPAG<7> = 0, the table page is located in the user memory space. When TBLPAG<7> = 1, the page is located in configuration space. The TBLRDL and TBLWTL instructions offer a direct method of reading or writing the lower word of any address within the program space without going through data space. The TBLRDH and TBLWTH instructions are the only method to read or write the upper 8 bits of a program space word as data. The PC is incremented by two for each successive 24-bit program word. This allows program memory addresses to directly map to data space addresses. Program memory can thus be regarded as two 16-bit-wide word address spaces, residing side by side, each with the same address range. TBLRDL and TBLWTL access the space that contains the least significant data word. TBLRDH and TBLWTH access the space that contains the upper data byte. Two table instructions are provided to move byte or word-sized (16-bit) data to and from program space. Both function as either byte or word operations. * TBLRDL (Table Read Low): - In Word mode, this instruction maps the lower word of the program space location (P<15:0>) to a data address (D<15:0>). FIGURE 4-10: TBLPAG ACCESSING PROGRAM MEMORY WITH TABLE INSTRUCTIONS Program Space 02 23 15 0 0x000000 00000000 00000000 00000000 00000000 23 16 8 0 0x020000 0x030000 `Phantom' Byte TBLRDH.B (Wn<0> = 0) TBLRDL.B (Wn<0> = 1) TBLRDL.B (Wn<0> = 0) TBLRDL.W The address for the table operation is determined by the data EA within the page defined by the TBLPAG register. Only read operations are shown; write operations are also valid in the user memory area. 0x800000 2009 Microchip Technology Inc. Preliminary DS70591B-page 107 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 4.6.3 READING DATA FROM PROGRAM MEMORY USING PROGRAM SPACE VISIBILITY 24-bit program word are used to contain the data. The upper 8 bits of any program space location used as data should be programmed with `1111 1111' or `0000 0000' to force a NOP. This prevents possible issues should the area of code ever be accidentally executed. Note: PSV access is temporarily disabled during table reads/writes. The upper 32 Kbytes of data space may optionally be mapped into any 16K word page of the program space. This option provides transparent access to stored constant data from the data space without the need to use special instructions (such as TBLRDL/H). Program space access through the data space occurs if the Most Significant bit of the data space EA is `1' and program space visibility is enabled by setting the PSV bit in the Core Control register (CORCON<2>). The location of the program memory space to be mapped into the data space is determined by the Program Space Visibility Page register (PSVPAG). This 8-bit register defines any one of 256 possible pages of 16K words in program space. In effect, PSVPAG functions as the upper 8 bits of the program memory address, with the 15 bits of the EA functioning as the lower bits. By incrementing the PC by 2 for each program memory word, the lower 15 bits of data space addresses directly map to the lower 15 bits in the corresponding program space addresses. Data reads to this area add a cycle to the instruction being executed, since two program memory fetches are required. Although each data space address 8000h and higher maps directly into a corresponding program memory address (see Figure 4-11), only the lower 16 bits of the For operations that use PSV and are executed outside a REPEAT loop, the MOV and MOV.D instructions require one instruction cycle in addition to the specified execution time. All other instructions require two instruction cycles in addition to the specified execution time. For operations that use PSV, and are executed inside a REPEAT loop, these instances require two instruction cycles in addition to the specified execution time of the instruction: * Execution in the first iteration * Execution in the last iteration * Execution prior to exiting the loop due to an interrupt * Execution upon re-entering the loop after an interrupt is serviced Any other iteration of the REPEAT loop will allow the instruction using PSV to access data, to execute in a single cycle. FIGURE 4-11: PROGRAM SPACE VISIBILITY OPERATION When CORCON<2> = 1 and EA<15> = 1: Program Space PSVPAG 02 23 15 0 0x000000 0x010000 0x018000 The data in the page designated by PSVPAG is mapped into the upper half of the data memory space... Data Space 0x0000 Data EA<14:0> 0x8000 PSV Area ...while the lower 15 bits of the EA specify an exact address within 0xFFFF the PSV area. This corresponds exactly to the same lower 15 bits of the actual program space address. 0x800000 DS70591B-page 108 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 5.0 FLASH PROGRAM MEMORY and three other lines for power (VDD), ground (VSS) and Master Clear (MCLR). This allows customers to manufacture boards with unprogrammed devices and then program the digital signal controller just before shipping the product. This also allows the most recent firmware or a custom firmware to be programmed. RTSP is accomplished using TBLRD (table read) and TBLWT (table write) instructions. With RTSP, the user application can write program memory data, either in blocks or `rows' of 64 instructions (192 bytes) at a time, or a single program memory word, and erase program memory in blocks or `pages' of 512 instructions (1536 bytes) at a time. Note 1: This data sheet summarizes the features of the dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 5. "Flash Programming" (DS70191) in the "dsPIC33F/PIC24H Family Reference Manual", which is available from the Microchip web site (www.microchip.com). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 "Memory Organization" in this data sheet for device-specific register and bit information. The dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 devices contain internal Flash program memory for storing and executing application code. The memory is readable, writable and erasable during normal operation over the entire VDD range. Flash memory can be programmed in two ways: * In-Circuit Serial ProgrammingTM (ICSPTM) programming capability * Run-Time Self-Programming (RTSP) ICSP allows a dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 device to be serially programmed while in the end application circuit. This is done with two lines for programming clock and programming data (one of the alternate programming pin pairs: PGC1/PGD1, PGC2/PGD2 or PGC3/PGD3), 5.1 Table Instructions and Flash Programming Regardless of the method used, all programming of Flash memory is done with the table read and table write instructions. These allow direct read and write access to the program memory space from the data memory while the device is in normal operating mode. The 24-bit target address in the program memory is formed using bits<7:0> of the TBLPAG register and the Effective Address (EA) from a W register specified in the table instruction, as shown in Figure 5-1. The TBLRDL and the TBLWTL instructions are used to read or write to bits<15:0> of program memory. TBLRDL and TBLWTL can access program memory in both Word and Byte modes. The TBLRDH and TBLWTH instructions are used to read or write to bits<23:16> of program memory. TBLRDH and TBLWTH can also access program memory in Word or Byte mode. FIGURE 5-1: ADDRESSING FOR TABLE REGISTERS 24 bits Using Program Counter 0 Program Counter 0 Working Reg EA Using Table Instruction 1/0 TBLPAG Reg 8 bits 16 bits User/Configuration Space Select 24-bit EA Byte Select 2009 Microchip Technology Inc. Preliminary DS70591B-page 109 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 5.2 RTSP Operation 5.3 Programming Operations The dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 Flash program memory array is organized into rows of 64 instructions or 192 bytes. RTSP allows the user application to erase a page of memory, which consists of eight rows (512 instructions) at a time, and to program one row or one word at a time. Table 27-12 shows typical erase and programming times. The 8-row erase pages and single row write rows are edge-aligned from the beginning of program memory, on boundaries of 1536 bytes and 192 bytes, respectively. The program memory implements holding buffers that can contain 64 instructions of programming data. Prior to the actual programming operation, the write data must be loaded into the buffers sequentially. The instruction words loaded must always be from a group of 64 boundary. The basic sequence for RTSP programming is to set up a Table Pointer, then do a series of TBLWT instructions to load the buffers. Programming is performed by setting the control bits in the NVMCON register. A total of 64 TBLWTL and TBLWTH instructions are required to load the instructions. All of the table write operations are single-word writes (two instruction cycles) because only the buffers are written. A programming cycle is required for programming each row. A complete programming sequence is necessary for programming or erasing the internal Flash in RTSP mode. The processor stalls (waits) until the programming operation is finished. The programming time depends on the FRC accuracy (see Table 27-20) and the value of the FRC Oscillator Tuning register (see Register 9-4). Use the following formula to calculate the minimum and maximum values for the Row Write Time, Page Erase Time, and Word Write Cycle Time parameters (see Table 27-12). EQUATION 5-1: PROGRAMMING TIME T ------------------------------------------------------------------------------------------------------------------------7.37 MHz FRC Accuracy % FRC Tuning % For example, if the device is operating at +125C, the FRC accuracy will be 5%. If the TUN<5:0> bits (see Register 9-4) are set to `b000000, the Minimum Row Write Time is: 11064 Cycles T RW = ----------------------------------------------------------------------------- = 1.43ms 7.37 MHz 1 + 0.05 1 - 0 and, the Maximum Row Write Time is: 11064 Cycles T RW = ----------------------------------------------------------------------------- = 1.58ms 7.37 MHz 1 - 0.05 1 - 0 Setting the WR bit (NVMCON<15>) starts the operation, and the WR bit is automatically cleared when the operation is finished. 5.4 Control Registers Two SFRs are used to read and write the program Flash memory: NVMCON and NVMKEY. The NVMCON register (Register 5-1) controls which blocks are to be erased, which memory type is to be programmed and the start of the programming cycle. NVMKEY is a write-only register that is used for write protection. To start a programming or erase sequence, the user application must consecutively write 0x55 and 0xAA to the NVMKEY register. Refer to Section 5.3 "Programming Operations" for further details. DS70591B-page 110 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 REGISTER 5-1: R/SO-0(1) WR bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15 SO = Settable Only bit W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0(1) ERASE U-0 -- U-0 -- R/W-0(1) R/W-0(1) R/W-0(1) NVMCON: FLASH MEMORY CONTROL REGISTER R/W-0(1) WREN R/W-0(1) WRERR U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 R/W-0(1) bit 0 NVMOP<3:0>(2) WR: Write Control bit 1 = Initiates a Flash memory program or erase operation. The operation is self-timed and the bit is cleared by hardware once operation is complete. 0 = Program or erase operation is complete and inactive WREN: Write Enable bit 1 = Enable Flash program/erase operations 0 = Inhibit Flash program/erase operations WRERR: Write Sequence Error Flag bit 1 = An improper program or erase sequence attempt or termination has occurred (bit is set automatically on any set attempt of the WR bit) 0 = The program or erase operation completed normally Unimplemented: Read as `0' ERASE: Erase/Program Enable bit 1 = Perform the erase operation specified by NVMOP<3:0> on the next WR command 0 = Perform the program operation specified by NVMOP<3:0> on the next WR command Unimplemented: Read as `0' NVMOP<3:0>: NVM Operation Select bits(2) If ERASE = 1: 1111 = Memory bulk erase operation 1101 = Erase general segment 0011 = No operation 0010 = Memory page erase operation 0001 = No operation 0000 = Erase a single Configuration register byte If ERASE = 0: 1111 = No operation 1101 = No operation 0011 = Memory word program operation 0010 = No operation 0001 = Memory row program operation 0000 = Program a single Configuration register byte bit 14 bit 13 bit 12-7 bit 6 bit 5-4 bit 3-0 Note 1: 2: These bits can only be Reset on POR. All other combinations of NVMOP<3:0> are unimplemented. 2009 Microchip Technology Inc. Preliminary DS70591B-page 111 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 REGISTER 5-2: U-0 -- bit 15 W-0 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-8 bit 7-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown W-0 W-0 W-0 W-0 W-0 W-0 W-0 bit 0 NVMKEY: NON-VOLATILE MEMORY KEY REGISTER U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 NVMKEY<7:0> Unimplemented: Read as `0' NVMKEY<7:0>: Key Register bits (write-only) DS70591B-page 112 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 5.4.1 PROGRAMMING ALGORITHM FOR FLASH PROGRAM MEMORY 4. 5. Write the first 64 instructions from data RAM into the program memory buffers (see Example 5-2). Write the program block to Flash memory: a) Set the NVMOP bits to `0001' to configure for row programming. Clear the ERASE bit and set the WREN bit. b) Write 0x55 to NVMKEY. c) Write 0xAA to NVMKEY. d) Set the WR bit. The programming cycle begins and the CPU stalls for the duration of the write cycle. When the write to Flash memory is done, the WR bit is cleared automatically. Repeat steps 4 and 5, using the next available 64 instructions from the block in data RAM by incrementing the value in TBLPAG, until all 512 instructions are written back to Flash memory. One row of program Flash memory can be programmed at a time. To achieve this, it is necessary to erase the 8-row erase page that contains the desired row. The general process is: 1. 2. 3. Read eight rows of program memory (512 instructions) and store in data RAM. Update the program data in RAM with the desired new data. Erase the block (see Example 5-1): a) Set the NVMOP bits (NVMCON<3:0>) to `0010' to configure for block erase. Set the ERASE (NVMCON<6>) and WREN (NVMCON<14>) bits. b) Write the starting address of the page to be erased into the TBLPAG and W registers. c) Write 0x55 to NVMKEY. d) Write 0xAA to NVMKEY. e) Set the WR bit (NVMCON<15>). The erase cycle begins and the CPU stalls for the duration of the erase cycle. When the erase is done, the WR bit is cleared automatically. 6. For protection against accidental operations, the write initiate sequence for NVMKEY must be used to allow any erase or program operation to proceed. After the programming command has been executed, the user application must wait for the programming time until programming is complete. The two instructions following the start of the programming sequence should be NOPs, as shown in Example 5-3. EXAMPLE 5-1: ERASING A PROGRAM MEMORY PAGE ; ; Initialize NVMCON ; ; ; ; ; ; ; ; ; ; ; ; ; Set up NVMCON for block erase operation MOV #0x4042, W0 MOV W0, NVMCON ; Init pointer to row to be ERASED MOV #tblpage(PROG_ADDR), W0 MOV W0, TBLPAG MOV #tbloffset(PROG_ADDR), W0 TBLWTL W0, [W0] DISI #5 MOV MOV MOV MOV BSET NOP NOP #0x55, W0 W0, NVMKEY #0xAA, W1 W1, NVMKEY NVMCON, #WR Initialize PM Page Boundary SFR Initialize in-page EA[15:0] pointer Set base address of erase block Block all interrupts with priority <7 for next 5 instructions Write the 55 key Write the AA key Start the erase sequence Insert two NOPs after the erase command is asserted 2009 Microchip Technology Inc. Preliminary DS70591B-page 113 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 EXAMPLE 5-2: LOADING THE WRITE BUFFERS ; Set up NVMCON for row programming operations MOV #0x4001, W0 ; MOV W0, NVMCON ; Initialize NVMCON ; Set up a pointer to the first program memory location to be written ; program memory selected, and writes enabled MOV #0x0000, W0 ; MOV W0, TBLPAG ; Initialize PM Page Boundary SFR MOV #0x6000, W0 ; An example program memory address ; Perform the TBLWT instructions to write the latches ; 0th_program_word MOV #LOW_WORD_0, W2 ; MOV #HIGH_BYTE_0, W3 ; TBLWTL W2, [W0] ; Write PM low word into program latch TBLWTH W3, [W0++] ; Write PM high byte into program latch ; 1st_program_word MOV #LOW_WORD_1, W2 ; MOV #HIGH_BYTE_1, W3 ; TBLWTL W2, [W0] ; Write PM low word into program latch TBLWTH W3, [W0++] ; Write PM high byte into program latch ; 2nd_program_word MOV #LOW_WORD_2, W2 ; MOV #HIGH_BYTE_2, W3 ; TBLWTL W2, [W0] ; Write PM low word into program latch TBLWTH W3, [W0++] ; Write PM high byte into program latch * * * ; 63rd_program_word MOV #LOW_WORD_31, W2 ; MOV #HIGH_BYTE_31, W3 ; TBLWTL W2, [W0] ; Write PM low word into program latch TBLWTH W3, [W0++] ; Write PM high byte into program latch EXAMPLE 5-3: DISI MOV MOV MOV MOV BSET NOP NOP #5 INITIATING A PROGRAMMING SEQUENCE ; Block all interrupts with priority <7 ; for next 5 instructions ; ; ; ; ; ; Write the 55 key Write the AA key Start the erase sequence Insert two NOPs after the erase command is asserted #0x55, W0 W0, NVMKEY #0xAA, W1 W1, NVMKEY NVMCON, #WR DS70591B-page 114 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 6.0 RESETS A simplified block diagram of the Reset module is shown in Figure 6-1. Any active source of reset will make the SYSRST signal active. On system Reset, some of the registers associated with the CPU and peripherals are forced to a known Reset state and some are unaffected. Note: Refer to the specific peripheral section or Section 3.0 "CPU" of this data sheet for register Reset states. Note 1: This data sheet summarizes the features of the dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 8. "Reset" (DS70192) in the "dsPIC33F/PIC24H Family Reference Manual", which is available from the Microchip web site (www.microchip.com). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 "Memory Organization" in this data sheet for device-specific register and bit information. The Reset module combines all Reset sources and controls the device Master Reset Signal, SYSRST. The following is a list of device Reset sources: * * * * * * * POR: Power-on Reset BOR: Brown-out Reset MCLR: Master Clear Pin Reset SWR: Software RESET Instruction WDTO: Watchdog Timer Reset TRAPR: Trap Conflict Reset IOPUWR: Illegal Condition Device Reset - Illegal Opcode Reset - Uninitialized W Register Reset - Security Reset All types of device Reset sets a corresponding status bit in the RCON register to indicate the type of Reset (see Register 6-1). A POR clears all the bits, except for the POR bit (RCON<0>), that are set. The user application can set or clear any bit at any time during code execution. The RCON bits only serve as status bits. Setting a particular Reset status bit in software does not cause a device Reset to occur. The RCON register also has other bits associated with the Watchdog Timer and device power-saving states. The function of these bits is discussed in other sections of this manual. Note: The status bits in the RCON register should be cleared after they are read so that the next RCON register value after a device Reset is meaningful. FIGURE 6-1: RESET SYSTEM BLOCK DIAGRAM RESET Instruction Glitch Filter MCLR WDT Module Sleep or Idle BOR SYSRST POR VDD Internal Regulator VDD Rise Detect Trap Conflict Illegal Opcode Uninitialized W Register 2009 Microchip Technology Inc. Preliminary DS70591B-page 115 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 REGISTER 6-1: R/W-0 TRAPR bit 15 R/W-0 EXTR bit 7 Legend: R = Readable bit -n = Value at POR bit 15 RCON: RESET CONTROL REGISTER(1) R/W-0 IOPUWR U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- R/W-0 VREGS bit 8 R/W-1 POR bit 0 R/W-0 SWR R/W-0 SWDTEN(2) R/W-0 WDTO R/W-0 SLEEP R/W-0 IDLE R/W-1 BOR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown bit 14 bit 13-9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 TRAPR: Trap Reset Flag bit 1 = A Trap Conflict Reset has occurred 0 = A Trap Conflict Reset has not occurred IOPUWR: Illegal Opcode or Uninitialized W Access Reset Flag bit 1 = An illegal opcode detection, an illegal address mode or uninitialized W register used as an Address Pointer caused a Reset 0 = An illegal opcode or uninitialized W Reset has not occurred Unimplemented: Read as `0' VREGS: Voltage Regulator Standby During Sleep bit 1 = Voltage regulator is active during Sleep 0 = Voltage regulator goes into Standby mode during Sleep EXTR: External Reset Pin (MCLR) bit 1 = A Master Clear (pin) Reset has occurred 0 = A Master Clear (pin) Reset has not occurred SWR: Software Reset Flag (Instruction) bit 1 = A RESET instruction has been executed 0 = A RESET instruction has not been executed SWDTEN: Software Enable/Disable of WDT bit(2) 1 = WDT is enabled 0 = WDT is disabled WDTO: Watchdog Timer Time-out Flag bit 1 = WDT time-out has occurred 0 = WDT time-out has not occurred SLEEP: Wake-up from Sleep Flag bit 1 = Device has been in Sleep mode 0 = Device has not been in Sleep mode IDLE: Wake-up from Idle Flag bit 1 = Device was in Idle mode 0 = Device was not in Idle mode BOR: Brown-out Reset Flag bit 1 = A Brown-out Reset has occurred 0 = A Brown-out Reset has not occurred POR: Power-on Reset Flag bit 1 = A Power-up Reset has occurred 0 = A Power-up Reset has not occurred All of the Reset status bits can be set or cleared in software. Setting one of these bits in software does not cause a device Reset. If the FWDTEN Configuration bit is `1' (unprogrammed), the WDT is always enabled, regardless of the SWDTEN bit setting. Note 1: 2: DS70591B-page 116 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 6.1 System Reset 2. BOR Reset: The on-chip voltage regulator has a BOR circuit that keeps the device in Reset until VDD crosses the VBOR threshold and the delay, TBOR, has elapsed. The delay, TBOR, ensures that the voltage regulator output becomes stable. PWRT Timer: The programmable power-up timer continues to hold the processor in Reset for a specific period of time (TPWRT) after a BOR. The delay TPWRT ensures that the system power supplies have stabilized at the appropriate level for full-speed operation. After the delay, TPWRT, has elapsed, the SYSRST becomes inactive, which in turn enables the selected oscillator to start generating clock cycles. Oscillator Delay: The total delay for the clock to be ready for various clock source selections is given in Table 6-1. Refer to Section 9.0 "Oscillator Configuration" for more information. When the oscillator clock is ready, the processor begins execution from location 0x000000. The user application programs a GOTO instruction at the Reset address, which redirects program execution to the appropriate start-up routine. The Fail-Safe Clock Monitor (FSCM), if enabled, begins to monitor the system clock when the system clock is ready and the delay, TFSCM, elapsed. The dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 families of devices have two types of Reset: * Cold Reset * Warm Reset A cold Reset is the result of a Power-on Reset (POR) or a Brown-out Reset (BOR). On a cold Reset, the FNOSC Configuration bits in the FOSC Configuration register select the device clock source. A warm Reset is the result of all the other Reset sources, including the RESET instruction. On warm Reset, the device will continue to operate from the current clock source as indicated by the Current Oscillator Selection (COSC<2:0>) bits in the Oscillator Control (OSCCON<14:12>) register. The device is kept in a Reset state until the system power supplies have stabilized at appropriate levels and the oscillator clock is ready. The sequence in which this occurs is detailed below and is shown in Figure 6-2. 1. POR Reset: A POR circuit holds the device in Reset when the power supply is turned on. The POR circuit is active until VDD crosses the VPOR threshold and the delay, TPOR, has elapsed. 3. 4. 5. 6. TABLE 6-1: OSCILLATOR DELAY Oscillator Start-up Delay TOSCD(1) TOSCD(1) TOSCD(1) TOSCD(1) -- TOSCD(1) TOSCD(1) -- TOSCD(1) Oscillator Start-up Timer -- -- TOST(2) TOST(2) -- TOST(2) TOST(2) -- -- PLL Lock Time -- TLOCK(3) -- -- -- TLOCK(3) TLOCK(3) TLOCK(3) -- Total Delay TOSCD(1) TOSCD + TLOCK(1,3) TOSCD + TOST(1,2) TOSCD + TOST(1,2) -- TOSCD + TOST + TLOCK(1,2,3) TOSCD + TOST + TLOCK(1,2,3) TLOCK(3) TOSCD(1) Oscillator Mode FRC, FRCDIV16, FRCDIVN FRCPLL XT HS EC XTPLL HSPLL ECPLL LPRC Note 1: 2: 3: TOSCD = Oscillator start-up delay (1.1 s max for FRC, 70 s max for LPRC). Crystal oscillator start-up times vary with crystal characteristics, load capacitance, etc. TOST = Oscillator start-up timer delay (1024 oscillator clock period). For example, TOST = 102.4 s for a 10 MHz crystal and TOST = 32 ms for a 32 kHz crystal. TLOCK = PLL lock time (1.5 ms nominal) if PLL is enabled. 2009 Microchip Technology Inc. Preliminary DS70591B-page 117 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 FIGURE 6-2: SYSTEM RESET TIMING VBOR VPOR VDD TPOR POR Reset 1 TBOR 2 BOR Reset 3 TPWRT SYSRST 4 Oscillator Clock TOSCD TOST TLOCK 6 FSCM 5 Device Status Reset Run TFSCM Time Note 1: 2: POR Reset: A POR circuit holds the device in Reset when the power supply is turned on. The POR circuit is active until VDD crosses the VPOR threshold and the delay, TPOR, has elapsed. BOR Reset: The on-chip voltage regulator has a BOR circuit that keeps the device in Reset until VDD crosses the VBOR threshold and the delay, TBOR, has elapsed. The delay, TBOR, ensures the voltage regulator output becomes stable. PWRT Timer: The programmable power-up timer continues to hold the processor in Reset for a specific period of time (TPWRT) after a BOR. The delay, TPWRT, ensures that the system power supplies have stabilized at the appropriate level for full-speed operation. After the delay, TPWRT has elapsed and the SYSRST becomes inactive, which in turn, enables the selected oscillator to start generating clock cycles. Oscillator Delay: The total delay for the clock to be ready for various clock source selections is given in Table 6-1. Refer to Section 9.0 "Oscillator Configuration" for more information. When the oscillator clock is ready, the processor begins execution from location 0x000000. The user application programs a GOTO instruction at the Reset address, which redirects program execution to the appropriate start-up routine. If the Fail-Safe Clock Monitor (FSCM) is enabled, it begins to monitor the system clock when the system clock is ready and the delay, TFSCM, has elapsed. 3: 4: 5: 6: Note: When the device exits the Reset condition (begins normal operation), the device operating parameters (voltage, frequency, temperature, etc.) must be within their operating ranges; otherwise, the device may not function correctly. The user application must ensure that the delay between the time power is first applied, and the time SYSRST becomes inactive, is long enough to get all operating parameters within specification. DS70591B-page 118 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 6.2 Power-on Reset (POR) VBOR threshold and the delay, TBOR, has elapsed. The delay, TBOR, ensures the voltage regulator output becomes stable. The BOR Status (BOR) bit in the Reset Control (RCON<1>) register is set to indicate the Brown-out Reset. The device will not run at full speed after a BOR as the VDD should rise to acceptable levels for full-speed operation. The PWRT provides power-up time delay (TPWRT) to ensure that the system power supplies have stabilized at the appropriate levels for full-speed operation before the SYSRST is released. The power-up timer delay (TPWRT) is programmed by the Power-on Reset Timer Value Select (FPWRT<2:0>) bits in the POR Configuration (FPOR<2:0>) register, which provides eight settings (from 0 ms to 128 ms). Refer to Section 24.0 "Special Features" for further details. Figure 6-3 shows the typical brown-out scenarios. The reset delay (TBOR + TPWRT) is initiated each time VDD rises above the VBOR trip point A Power-on Reset (POR) circuit ensures the device is reset from power-on. The POR circuit is active until VDD crosses the VPOR threshold and the delay, TPOR, has elapsed. The delay, TPOR, ensures the internal device bias circuits become stable. The device supply voltage characteristics must meet the specified starting voltage and rise rate requirements to generate the POR. Refer to Section 27.0 "Electrical Characteristics" for details. The POR Status (POR) bit in the Reset Control (RCON<0>) register is set to indicate the Power-on Reset. 6.3 Brown-out Reset (BOR) and Power-up Timer (PWRT) The on-chip regulator has a Brown-out Reset (BOR) circuit that resets the device when the VDD is too low (VDD < VBOR) for proper device operation. The BOR circuit keeps the device in Reset until VDD crosses the FIGURE 6-3: VDD BROWN-OUT SITUATIONS VBOR TBOR + TPWRT SYSRST VDD VBOR TBOR + TPWRT SYSRST VDD dips before PWRT expires VDD VBOR TBOR + TPWRT SYSRST 2009 Microchip Technology Inc. Preliminary DS70591B-page 119 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 6.4 External Reset (EXTR) ority level 13 through level 15, inclusive. The address error (level 13) and oscillator error (level 14) traps fall into this category. The Trap Reset (TRAPR) flag in the Reset Control (RCON<15>) register is set to indicate the Trap Conflict Reset. Refer to Section 7.0 "Interrupt Controller" for more information on Trap Conflict Resets. The external Reset is generated by driving the MCLR pin low. The MCLR pin is a Schmitt Trigger input with an additional glitch filter. Reset pulses that are longer than the minimum pulse width will generate a Reset. Refer to Section 27.0 "Electrical Characteristics" for minimum pulse width specifications. The external Reset (MCLR) pin (EXTR) bit in the Reset Control (RCON) register is set to indicate the MCLR Reset. 6.8 Illegal Condition Device Reset 6.4.0.1 EXTERNAL SUPERVISORY CIRCUIT An illegal condition device Reset occurs due to the following sources: * Illegal Opcode Reset * Uninitialized W Register Reset * Security Reset The Illegal Opcode or Uninitialized W Access Reset (IOPUWR) flag in the Reset Control (RCON<14>) register is set to indicate the illegal condition device Reset. Many systems have external supervisory circuits that generate Reset signals to reset multiple devices in the system. This external Reset signal can be directly connected to the MCLR pin to reset the device when the rest of system is reset. 6.4.0.2 INTERNAL SUPERVISORY CIRCUIT When using the internal power supervisory circuit to reset the device, the external Reset pin (MCLR) should be tied directly or resistively to VDD. In this case, the MCLR pin will not be used to generate a Reset. The external Reset pin (MCLR) does not have an internal pull-up and must not be left unconnected. 6.8.1 ILLEGAL OPCODE RESET A device Reset is generated if the device attempts to execute an illegal opcode value that is fetched from program memory. The Illegal Opcode Reset function can prevent the device from executing program memory sections that are used to store constant data. To take advantage of the Illegal Opcode Reset, use only the lower 16 bits of each program memory section to store the data values. The upper 8 bits should be programmed with 3Fh, which is an illegal opcode value. 6.5 Software RESET Instruction (SWR) Whenever the RESET instruction is executed, the device will assert SYSRST, placing the device in a special Reset state. This Reset state will not re-initialize the clock. The clock source in effect prior to the RESET instruction will remain. SYSRST is released at the next instruction cycle and the Reset vector fetch will commence. The Software Reset (SWR) flag (instruction) in the Reset Control (RCON<6>) register is set to indicate the software Reset. 6.8.2 UNINITIALIZED W REGISTER RESET Any attempt to use the uninitialized W register as an Address Pointer will Reset the device. The W register array (with the exception of W15) is cleared during all Resets and is considered uninitialized until written to. 6.6 Watchdog Time-out Reset (WDTO) 6.8.3 SECURITY RESET Whenever a Watchdog time-out occurs, the device will asynchronously assert SYSRST. The clock source will remain unchanged. A WDT time-out during Sleep or Idle mode will wake-up the processor, but will not reset the processor. The Watchdog Timer Time-out (WDTO) flag in the Reset Control (RCON<4>) register is set to indicate the Watchdog Reset. Refer to Section 24.4 "Watchdog Timer (WDT)" for more information on Watchdog Reset. If a Program Flow Change (PFC) or Vector Flow Change (VFC) targets a restricted location in a protected segment (boot and secure segment), that operation will cause a Security Reset. The PFC occurs when the program counter is reloaded as a result of a call, jump, computed jump, return, return from subroutine or other form of branch instruction. The VFC occurs when the program counter is reloaded with an interrupt or trap vector. Refer to Section 24.8 "Code Protection and CodeGuardTM Security" for more information on Security Reset. 6.7 Trap Conflict Reset If a lower priority hard trap occurs while a higher priority trap is being processed, a hard Trap Conflict Reset occurs. The hard traps include exceptions of pri- DS70591B-page 120 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 6.9 Using the RCON Status Bits Table 6-2 provides a summary of the Reset flag bit operation. The user application can read the Reset Control (RCON) register after any device Reset to determine the cause of the Reset. Note: The status bits in the RCON register should be cleared after they are read so that the next RCON register value after a device Reset will be meaningful. TABLE 6-2: Flag Bit RESET FLAG BIT OPERATION Set by: Trap conflict event Illegal opcode or uninitialized W register access or Security Reset MCLR Reset RESET instruction WDT time-out PWRSAV #SLEEP instruction PWRSAV #IDLE instruction POR, BOR POR POR,BOR POR,BOR POR POR,BOR PWRSAV instruction, CLRWDT instruction, POR,BOR POR,BOR POR,BOR Cleared by: TRAPR (RCON<15>) IOPWR (RCON<14>) EXTR (RCON<7>) SWR (RCON<6>) WDTO (RCON<4>) SLEEP (RCON<3>) IDLE (RCON<2>) BOR (RCON<1>) POR (RCON<0>) Note: All Reset flag bits can be set or cleared by user software. 2009 Microchip Technology Inc. Preliminary DS70591B-page 121 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 NOTES: DS70591B-page 122 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 7.0 INTERRUPT CONTROLLER Interrupt vectors are prioritized in terms of their natural priority. This priority is linked to their position in the vector table. Lower addresses generally have a higher natural priority. For example, the interrupt associated with vector 0 will take priority over interrupts at any other vector address. The dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 devices implement up to 71 unique interrupts and five non-maskable traps. These are summarized in Table 7-1. Note 1: This data sheet summarizes the features of the dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 47. "Interrupts (Part V)" (DS70597) in the "dsPIC33F/ PIC24H Family Reference Manual", which is available from the Microchip web site (www.microchip.com). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 "Memory Organization" in this data sheet for device-specific register and bit information. The dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 interrupt controller reduces the numerous peripheral interrupt request signals to a single interrupt request signal to the dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 CPU. It has the following features: * Up to eight processor exceptions and software traps * Seven user-selectable priority levels * Interrupt Vector Table (IVT) with up to 118 vectors * A unique vector for each interrupt or exception source * Fixed priority within a specified user priority level * Alternate Interrupt Vector Table (AIVT) for debug support * Fixed interrupt entry and return latencies 7.1.1 ALTERNATE INTERRUPT VECTOR TABLE The Alternate Interrupt Vector Table (AIVT) is located after the IVT, as shown in Figure 7-1. Access to the AIVT is provided by the ALTIVT control bit (INTCON2<15>). If the ALTIVT bit is set, all interrupt and exception processes use the alternate vectors instead of the default vectors. The alternate vectors are organized in the same manner as the default vectors. The AIVT supports debugging by providing a means to switch between an application and a support environment without requiring the interrupt vectors to be reprogrammed. This feature also enables switching between applications for evaluation of different software algorithms at run time. If the AIVT is not needed, the AIVT should be programmed with the same addresses used in the IVT. 7.2 Reset Sequence 7.1 Interrupt Vector Table A device Reset is not a true exception because the interrupt controller is not involved in the Reset process. The dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 device clears its registers in response to a Reset, which forces the PC to zero. The digital signal controller then begins program execution at location 0x000000. A GOTO instruction at the Reset address can redirect program execution to the appropriate start-up routine. Note: Any unimplemented or unused vector locations in the IVT and AIVT should be programmed with the address of a default interrupt handler routine that contains a RESET instruction. The Interrupt Vector Table (IVT) is shown in Figure 7-1. The IVT resides in program memory, starting at location 000004h. The IVT contains 126 vectors, consisting of eight nonmaskable trap vectors, plus up to 118 sources of interrupt. In general, each interrupt source has its own vector. Each interrupt vector contains a 24-bit-wide address. The value programmed into each interrupt vector location is the starting address of the associated Interrupt Service Routine (ISR). 2009 Microchip Technology Inc. Preliminary DS70591B-page 123 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 FIGURE 7-1: dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 INTERRUPT VECTOR TABLE Reset - GOTO Instruction Reset - GOTO Address Reserved Oscillator Fail Trap Vector Address Error Trap Vector Stack Error Trap Vector Math Error Trap Vector DMA Error Trap Vector Reserved Reserved Interrupt Vector 0 Interrupt Vector 1 ~ ~ ~ Interrupt Vector 52 Interrupt Vector 53 Interrupt Vector 54 ~ ~ ~ Interrupt Vector 116 Interrupt Vector 117 Reserved Reserved Reserved Oscillator Fail Trap Vector Address Error Trap Vector Stack Error Trap Vector Math Error Trap Vector DMA Error Trap Vector Reserved Reserved Interrupt Vector 0 Interrupt Vector 1 ~ ~ ~ Interrupt Vector 52 Interrupt Vector 53 Interrupt Vector 54 ~ ~ ~ Interrupt Vector 116 Interrupt Vector 117 Start of Code 0x000000 0x000002 0x000004 0x000014 Decreasing Natural Order Priority 0x00007C 0x00007E 0x000080 Interrupt Vector Table (IVT)(1) 0x0000FC 0x0000FE 0x000100 0x000102 0x000114 Alternate Interrupt Vector Table (AIVT)(1) 0x00017C 0x00017E 0x000180 0x0001FE 0x000200 Note 1: See Table 7-1 for the list of implemented interrupt vectors. DS70591B-page 124 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 TABLE 7-1: Vector Number INTERRUPT VECTORS Interrupt Request (IQR) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21-23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39-48 49 50 51-52 53 54 IVT Address AIVT Address Interrupt Source 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29-31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47-56 57 58 59-60 61 62 Highest Natural Order Priority 0x000014 0x000114 INT0 - External Interrupt 0 0x000016 0x000116 IC1 - Input Capture 1 0x000018 0x000118 OC1 - Output Compare 1 0x00001A 0x00011A T1 - Timer1 0x00001C 0x00011C DMA0 - DMA Channel 0 0x00001E 0x00011E IC2 - Input Capture 2 0x000020 0x000120 OC2 - Output Compare 2 0x000022 0x000122 T2 - Timer2 0x000024 0x000124 T3 - Timer3 0x000026 0x000126 SPI1E - SPI1 Fault 0x000028 0x000128 SPI1 - SPI1 Transfer Done 0x00002A 0x00012A U1RX - UART1 Receiver 0x00002C 0x00012C U1TX - UART1 Transmitter 0x00002E 0x00012E ADC - ADC Group Convert Done 0x000030 0x000130 DMA1 - DMA Channel 1 0x000032 0x000132 Reserved 0x000034 0x000134 SI2C1 - I2C1 Slave Event 0x000036 0x000136 MI2C1 - I2C1 Master Event 0x000038 0x000138 CMP1 - Analog Comparator 1 Interrupt 0x00003A 0x00013A CN - Input Change Notification Interrupt 0x00003C 0x00013C INT1 - External Interrupt 1 0x00003E0x00013EReserved 0x000042 0x000142 0x000044 0x000144 DMA2 - DMA Channel 2 0x000046 0x000146 OC3 - Output Compare 3 0x000048 0x000148 OC4 - Output Compare 4 0x00004A 0x00014A T4 - Timer4 0x00004C 0x00014C T5 - Timer5 0x00004E 0x00014E INT2 - External Interrupt 2 0x000050 0x000150 U2RX - UART2 Receiver 0x000052 0x000152 U2TX - UART2 Transmitter 0x000054 0x000154 SPI2E - SPI2 Error 0x000056 0x000156 SPI2 - SPI2 Transfer Done 0x000058 0x000158 C1RX - ECAN1 Receive Data Ready 0x00005A 0x00015A C1 - ECAN1 Event 0x00005C 0x00015C DMA3 - DMA Channel 3 0x00005E 0x00015E IC3 - Input Capture 3 0x000060 0x000160 IC4 - Input Capture 4 0x0000620x000162Reserved 0x000074 0x000174 0x000076 0x000176 SI2C2 - I2C2 Slave Events 0x000078 0x000178 MI2C2 - I2C2 Master Events 0x00007A0x00017AReserved 0x00007C 0x00017C 0x00007E 0x00017E INT3 - External Interrupt 3 0x000080 0x000180 INT4 - External Interrupt 4 2009 Microchip Technology Inc. Preliminary DS70591B-page 125 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 TABLE 7-1: Vector Number 63-64 65 66 67-72 73 74 75-77 78 79 80 81 82 83 84-88 89 90 91 92 93 94-101 102 103 104 105 106 107 108 109 110 111 112 113 114-117 118 119 120 121 122 123 124 125 INTERRUPT VECTORS (CONTINUED) Interrupt Request (IQR) 55-56 57 58 59-64 65 66 67-69 70 71 72 73 74 75 76-80 81 82 83 84 85 86-93 94 95 96 97 98 99 100 101 102 103 104 105 106-109 110 111 112 113 114 115 116 117 IVT Address 0x0000820x000084 0x000086 0x000088 0x00008A0x000094 0x000096 0x000098 0x00009A0x00009E 0x0000A0 0x0000A2 0x0000A4 0x0000A6 0x0000A8 0x0000AA 0x0000AC0x0000B4 0x0000B6 0x0000B8 0x0000BA 0x0000BC 0x0000BE 0x0000C00x0000CE 0x0000D0 0x0000D2 0x0000D4 0x0000D6 0x0000D8 0x0000DA 0x0000DC 0x0000DE 0x0000E0 0x0000E2 AIVT Address 0x0001820x000184 0x000186 0x000188 0x00018A0x000194 0x000196 0x000198 0x00019A0x00019E 0x0001A0 0x0001A2 0x0001A4 0x0001A6 0x0001A8 0x0001AA 0x0001AC0x0001B4 0x0001B6 0x0001B8 0x0001BA 0x0001BC 0x0001BE 0x0001C00x0001CE 0x0001D0 0x0001D2 0x0001D4 0x0001D6 0x0001D8 0x0001DA 0x0001DC 0x0001DE 0x0001E0 0x00001E2 Reserved PWM PSEM Special Event Match QEI1 - Position Counter Compare Reserved U1E - UART1 Error Interrupt U2E - UART2 Error Interrupt Reserved C1TX - ECAN1 Transmit Data Request Reserved Reserved PWM Secondary Special Event Match Reserved QEI2 - Position Counter Compare Reserved ADC Pair 8 Conversion Done ADC Pair 9 Conversion Done ADC Pair 10 Conversion Done ADC Pair 11 Conversion Done ADC Pair 12 Conversion Done Reserved PWM1 - PWM1 Interrupt PWM2 - PWM2 Interrupt PWM3 - PWM3 Interrupt PWM4 - PWM4 Interrupt PWM5 - PWM5 Interrupt PWM6 - PWM6 Interrupt PWM7- PWM7 Interrupt PWM8 - PWM8 Interrupt PWM9 - PWM9 Interrupt CMP2 - Analog Comparator 2 Interrupt Source 0x0000E4 0x0001E4 CMP3 - Analog Comparator 3 0x0000E6 0x0001E6 CMP4 - Analog Comparator 4 0x0000E80x0001E8Reserved 0x0000EE 0x0001EE 0x0000F0 0x0001F0 ADC Pair 0 Convert Done 0x0000F2 0x0001F2 ADC Pair 1 Convert Done 0x0000F4 0x0001F4 ADC Pair 2 Convert Done 0x0000F6 0x0001F6 ADC Pair 3 Convert Done 0x0000F8 0x0001F8 ADC Pair 4 Convert Done 0x0000FA 0x0001FA ADC Pair 5 Convert Done 0x0000FC 0x0001FC ADC Pair 6 Convert Done 0x0000FE 0x0001FE ADC Pair 7 Convert Done Lowest Natural Order Priority DS70591B-page 126 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 7.3 Interrupt Control and Status Registers 7.3.5 INTTREG The dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 devices implement 27 registers for the interrupt controller: * * * * * * INTCON1 INTCON2 IFSx IECx IPCx INTTREG The INTTREG register contains the associated interrupt vector number and the new CPU Interrupt priority Level, which are latched into the Vector Number (VECNUM<6:0>) and Interrupt Level (ILR<3:0>) bit fields in the INTTREG register. The new Interrupt Priority Level is the priority of the pending interrupt. The interrupt sources are assigned to the IFSx, IECx and IPCx registers in the same sequence that they are listed in Table 7-1. For example, the INT0 (External Interrupt 0) is shown as having vector number 8 and a natural order priority of 0. Thus, the INT0IF bit is found in IFS0<0>, the INT0IE bit is found in IEC0<0> and the INT0IP bits are found in the first position of IPC0 (IPC0<2:0>). 7.3.1 INTCON1 AND INTCON2 Global interrupt control functions are controlled from INTCON1 and INTCON2. INTCON1 contains the Interrupt Nesting Disable (NSTDIS) bit as well as the control and status flags for the processor trap sources. The INTCON2 register controls the external interrupt request signal behavior and the use of the Alternate Interrupt Vector Table. 7.3.6 STATUS/CONTROL REGISTERS Although they are not specifically part of the interrupt control hardware, two of the CPU Control registers contain bits that control interrupt functionality. * The CPU STATUS register, SR, contains the IPL<2:0> bits (SR<7:5>). These bits indicate the current CPU interrupt Priority Level. The user can change the current CPU priority level by writing to the IPL bits. * The CORCON register contains the IPL3 bit, which together with IPL<2:0>, indicates the current CPU priority level. IPL3 is a read-only bit so that trap events cannot be masked by the user software. All Interrupt registers are described in Register 7-1 through Register 7-46 in the following pages. 7.3.2 IFSx The IFSx registers maintain all of the interrupt request flags. Each source of interrupt has a status bit, which is set by the respective peripherals or external signal and is cleared via software. 7.3.3 IECx The IECx registers maintain all of the interrupt enable bits. These control bits are used to individually enable interrupts from the peripherals or external signals. 7.3.4 IPCx The IPCx registers are used to set the Interrupt Priority Level for each source of interrupt. Each user interrupt source can be assigned to one of eight priority levels. 2009 Microchip Technology Inc. Preliminary DS70591B-page 127 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 REGISTER 7-1: R-0 OA bit 15 R/W-0(3) IPL2 bit 7 Legend: C = Clearable bit S = Settable bit `1' = Bit is set bit 7-5 R = Readable bit W = Writable bit `0' = Bit is cleared U = Unimplemented bit, read as `0' -n = Value at POR x = Bit is unknown (2) SR: CPU STATUS REGISTER(1) R-0 OB R/C-0 SA R/C-0 SB R-0 OAB R/C-0 SAB R -0 DA R/W-0 DC bit 8 R/W-0(3) IPL1 (2) R/W-0(3) IPL0 (2) R-0 RA R/W-0 N R/W-0 OV R/W-0 Z R/W-0 C bit 0 IPL<2:0>: CPU Interrupt Priority Level Status bits(2) 111 = CPU Interrupt Priority Level is 7 (15), user interrupts disabled 110 = CPU Interrupt Priority Level is 6 (14) 101 = CPU Interrupt Priority Level is 5 (13) 100 = CPU Interrupt Priority Level is 4 (12) 011 = CPU Interrupt Priority Level is 3 (11) 010 = CPU Interrupt Priority Level is 2 (10) 001 = CPU Interrupt Priority Level is 1 (9) 000 = CPU Interrupt Priority Level is 0 (8) For complete register details, see Register 3-1. The IPL<2:0> bits are concatenated with the IPL<3> bit (CORCON<3>) to form the CPU Interrupt Priority Level. The value in parentheses indicates the IPL if IPL<3> = 1. User interrupts are disabled when IPL<3> = 1. The IPL<2:0> Status bits are read-only when NSTDIS (INTCON1<15>) = 1. Note 1: 2: 3: REGISTER 7-2: U-0 -- bit 15 R/W-0 SATA bit 7 Legend: R = Readable bit 0' = Bit is cleared bit 3 CORCON: CORE CONTROL REGISTER(1) U-0 -- U-0 -- U-0 US R/W-0 EDT R-0 R-0 DL<2:0> R-0 bit 8 R/W-0 SATB R/W-1 SATDW R/W-0 ACCSAT R/C-0 IPL3(2) R/W-0 PSV R/W-0 RND R/W-0 IF bit 0 C = Clearable bit W = Writable bit `x = Bit is unknown -n = Value at POR `1' = Bit is set U = Unimplemented bit, read as `0' IPL3: CPU Interrupt Priority Level Status bit 3(2) 1 = CPU Interrupt Priority Level is greater than 7 0 = CPU Interrupt Priority Level is 7 or less For complete register details, see Register 3-2. The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU Interrupt Priority Level. Note 1: 2: DS70591B-page 128 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 REGISTER 7-3: R/W-0 NSTDIS bit 15 R/W-0 SFTACERR bit 7 Legend: R = Readable bit -n = Value at POR bit 15 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 DIV0ERR R/W-0 DMACERR R/W-0 MATHERR R/W-0 ADDRERR R/W-0 STKERR R/W-0 OSCFAIL U-0 -- bit 0 INTCON1: INTERRUPT CONTROL REGISTER 1 R/W-0 OVAERR R/W-0 OVBERR R/W-0 COVAERR R/W-0 COVBERR R/W-0 OVATE R/W-0 OVBTE R/W-0 COVTE bit 8 NSTDIS: Interrupt Nesting Disable bit 1 = Interrupt nesting is disabled 0 = Interrupt nesting is enabled OVAERR: Accumulator A Overflow Trap Flag bit 1 = Trap was caused by overflow of Accumulator A 0 = Trap was not caused by overflow of Accumulator A OVBERR: Accumulator B Overflow Trap Flag bit 1 = Trap was caused by overflow of Accumulator B 0 = Trap was not caused by overflow of Accumulator B COVAERR: Accumulator A Catastrophic Overflow Trap Flag bit 1 = Trap was caused by catastrophic overflow of Accumulator A 0 = Trap was not caused by catastrophic overflow of Accumulator A COVBERR: Accumulator B Catastrophic Overflow Trap Flag bit 1 = Trap was caused by catastrophic overflow of Accumulator B 0 = Trap was not caused by catastrophic overflow of Accumulator B OVATE: Accumulator A Overflow Trap Enable bit 1 = Trap overflow of Accumulator A 0 = Trap disabled OVBTE: Accumulator B Overflow Trap Enable bit 1 = Trap overflow of Accumulator B 0 = Trap disabled COVTE: Catastrophic Overflow Trap Enable bit 1 = Trap on catastrophic overflow of Accumulator A or B enabled 0 = Trap disabled SFTACERR: Shift Accumulator Error Status bit 1 = Math error trap was caused by an invalid accumulator shift 0 = Math error trap was not caused by an invalid accumulator shift DIV0ERR: Arithmetic Error Status bit 1 = Math error trap was caused by a divide by zero 0 = Math error trap was not caused by a divide by zero DMACERR: DMA Controller Error Status bit 1 = DMA controller error trap has occurred 0 = DMA controller error trap has not occurred MATHERR: Arithmetic Error Status bit 1 = Math error trap has occurred 0 = Math error trap has not occurred bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 2009 Microchip Technology Inc. Preliminary DS70591B-page 129 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 REGISTER 7-3: bit 3 INTCON1: INTERRUPT CONTROL REGISTER 1 (CONTINUED) ADDRERR: Address Error Trap Status bit 1 = Address error trap has occurred 0 = Address error trap has not occurred STKERR: Stack Error Trap Status bit 1 = Stack error trap has occurred 0 = Stack error trap has not occurred OSCFAIL: Oscillator Failure Trap Status bit 1 = Oscillator failure trap has occurred 0 = Oscillator failure trap has not occurred Unimplemented: Read as `0' bit 2 bit 1 bit 0 DS70591B-page 130 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 REGISTER 7-4: R/W-0 ALTIVT bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- U-0 -- R/W-0 INT4EP R/W-0 INT3EP R/W-0 INT2EP R/W-0 INT1EP INTCON2: INTERRUPT CONTROL REGISTER 2 R-0 DISI U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 R/W-0 INT0EP bit 0 ALTIVT: Enable Alternate Interrupt Vector Table bit 1 = Use alternate vector table 0 = Use standard (default) vector table DISI: DISI Instruction Status bit 1 = DISI instruction is active 0 = DISI instruction is not active Unimplemented: Read as `0' INT4EP: External Interrupt 4 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge INT3EP: External Interrupt 3 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge INT2EP: External Interrupt 2 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge INT1EP: External Interrupt 1 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge INT0EP: External Interrupt 0 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge bit 14 bit 13-5 bit 4 bit 3 bit 2 bit 1 bit 0 2009 Microchip Technology Inc. Preliminary DS70591B-page 131 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 REGISTER 7-5: U-0 -- bit 15 R/W-0 T2IF bit 7 Legend: R = Readable bit -n = Value at POR bit 15 bit 14 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 OC2IF R/W-0 IC2IF R/W-0 DMA0IF R/W-0 T1IF R/W-0 OC1IF R/W-0 IC1IF IFS0: INTERRUPT FLAG STATUS REGISTER 0 R/W-0 DMA1IF R/W-0 ADIF R/W-0 U1TXIF R/W-0 U1RXIF R/W-0 SPI1IF R/W-0 SPI1EIF R/W-0 T3IF bit 8 R/W-0 INT0IF bit 0 Unimplemented: Read as `0' DMA1IF: DMA Channel 1 Data Transfer Complete Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred ADIF: ADC Group Conversion Complete Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred U1TXIF: UART1 Transmitter Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred U1RXIF: UART1 Receiver Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred SPI1IF: SPI1 Event Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred SPI1EIF: SPI1 Fault Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred T3IF: Timer3 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred T2IF: Timer2 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred OC2IF: Output Compare Channel 2 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred IC2IF: Input Capture Channel 2 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred DMA0IF: DMA Channel 0 Data Transfer Complete Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred T1IF: Timer1 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 DS70591B-page 132 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 REGISTER 7-5: bit 2 IFS0: INTERRUPT FLAG STATUS REGISTER 0 (CONTINUED) OC1IF: Output Compare Channel 1 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred IC1IF: Input Capture Channel 1 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred INT0IF: External Interrupt 0 Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 1 bit 0 2009 Microchip Technology Inc. Preliminary DS70591B-page 133 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 REGISTER 7-6: R/W-0 U2TXIF bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 12 IFS1: INTERRUPT FLAG STATUS REGISTER 1 R/W-0 U2RXIF R/W-0 INT2IF R/W-0 T5IF R/W-0 T4IF R/W-0 OC4IF R/W-0 OC3IF R/W-0 DMA2IF bit 8 R/W-0 SI2C1IF bit 0 U-0 -- U-0 -- R/W-0 INT1IF R/W-0 CNIF R/W-0 AC1IF R/W-0 MI2C1IF W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown bit 11 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7-5 bit 4 bit 3 bit 2 bit 1 bit 0 U2TXIF: UART2 Transmitter Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred U2RXIF: UART2 Receiver Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred INT2IF: External Interrupt 2 Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred T5IF: Timer5 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred T4IF: Timer4 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred OC4IF: Output Compare Channel 4 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred OC3IF: Output Compare Channel 3 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred DMA2IF: DMA Channel 2 Data Transfer Complete Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred Unimplemented: Read as `0' INT1IF: External Interrupt 1 Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred CNIF: Input Change Notification Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred AC1IF: Analog Comparator 1 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred MI2C1IF: I2C1 Master Events Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred SI2C1IF: I2C1 Slave Events Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred DS70591B-page 134 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 REGISTER 7-7: U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-7 bit 6 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 IC4IF R/W-0 IC3IF R/W-0 DMA3IF R/W-0 C1IF (1) IFS2: INTERRUPT FLAG STATUS REGISTER 2 U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 R/W-0 C1EIF (1) R/W-0 SPI2IF R/W-0 SPI2EIF bit 0 Unimplemented: Read as `0' IC4IF: Input Capture Channel 4 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred IC3IF: Input Capture Channel 3 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred DMA3IF: DMA Channel 3 Data Transfer Complete Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred C1IF: ECAN1 Event Interrupt Flag Status bit(1) 1 = Interrupt request has occurred 0 = Interrupt request has not occurred C1EIF: ECAN1 External Event Interrupt Flag Status bit(1) 1 = Interrupt request has occurred 0 = Interrupt request has not occurred SPI2IF: SPI2 Event Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred SPI2EIF: SPI2 Error Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Note 1: Interrupts disabled on devices without ECANTM modules 2009 Microchip Technology Inc. Preliminary DS70591B-page 135 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 REGISTER 7-8: U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-11 bit 10 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 INT4IF R/W-0 INT3IF U-0 -- U-0 -- R/W-0 MI2C2IF R/W-0 SI2C2IF U-0 -- bit 0 IFS3: INTERRUPT FLAG STATUS REGISTER 3 U-0 -- U-0 -- U-0 -- U-0 -- R/W-0 QEI1IF R/W-0 PSEMIF U-0 -- bit 8 Unimplemented: Read as `0' QEI1IF: QEI1 Event Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred PSEMIF: PWM Special Event Match Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred Unimplemented: Read as `0' INT4IF: External Interrupt 4 Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred INT3IF: External Interrupt 3 Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred Unimplemented: Read as `0' MI2C2IF: I2C2 Master Events Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred SI2C2IF: I2C2 Slave Events Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred Unimplemented: Read as `0' bit 9 bit 8-7 bit 6 bit 5 bit 4-3 bit 2 bit 1 bit 0 DS70591B-page 136 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 REGISTER 7-9: U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-12 bit 11 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 C1TXIF (1) IFS4: INTERRUPT FLAG STATUS REGISTER 4 U-0 -- U-0 -- U-0 -- R/W-0 QEI2IF U-0 -- R/W-0 PSESMIF U-0 -- bit 8 U-0 -- U-0 -- U-0 -- R/W-0 U2EIF R/W-0 U1EIF U-0 -- bit 0 Unimplemented: Read as `0' QEI2IF: QEI2 Event Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred Unimplemented: Read as `0' PSESMIF: PWM Special Event Secondary Match Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred Unimplemented: Read as `0' C1TXIF: ECAN1 Transmit Data Request Interrupt Flag Status bit(1) 1 = Interrupt request has occurred 0 = Interrupt request has not occurred Unimplemented: Read as `0' U2EIF: UART2 Error Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred U1EIF: UART1 Error Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred Unimplemented: Read as `0' bit 10 bit 9 bit 8-7 bit 6 bit 5-3 bit 2 bit 1 bit 0 Note 1: Interrupts disabled on devices without ECANTM modules. 2009 Microchip Technology Inc. Preliminary DS70591B-page 137 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 REGISTER 7-10: R/W-0 PWM2IF bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- U-0 -- R/W-0 ADCP11IF R/W-0 ADCP10IF R/W-0 ADCP9IF R/W-0 ADCP8IF U-0 -- bit 0 IFS5: INTERRUPT FLAG STATUS REGISTER 5 R/W-0 R/W-0 ADCP12IF U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 PWM1IF PWM2IF: PWM2 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred PWM1IF: PWM1 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred ADCP12IF: ADC Pair 12 Conversion Done Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred Unimplemented: Read as `0' ADCP11IF: ADC Pair 11 Conversion Done Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred ADCP10IF: ADC Pair 10 Conversion Done Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred ADCP9IF: ADC Pair 9 Conversion Done Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred ADCP8IF: ADC Pair 8 Conversion Done Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred Unimplemented: Read as `0' bit 14 bit 13 bit 12-5 bit 4 bit 3 bit 2 bit 1 bit 0 DS70591B-page 138 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 REGISTER 7-11: R/W-0 ADCP1IF bit 15 R/W-0 AC2IF bit 7 Legend: R = Readable bit -n = Value at POR bit 15 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 PWM9IF R/W-0 PWM8IF R/W-0 PWM7IF R/W-0 PWM6IF R/W-0 PWM5IF R/W-0 PWM4IF IFS6: INTERRUPT FLAG STATUS REGISTER 6 R/W-0 U-0 -- U-0 -- U-0 -- U-0 -- R/W-0 AC4IF R/W-0 AC3IF bit 8 R/W-0 PWM3IF bit 0 ADCP0IF ADCP1IF: ADC Pair 1 Conversion Done Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred ADCP0IF: ADC Pair 0 Conversion Done Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred Unimplemented: Read as `0' AC4IF: Analog Comparator 4 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred AC3IF: Analog Comparator 3 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred AC2IF: Analog Comparator 2 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred PWM9IF: PWM9 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred PWM8IF: PWM8 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred PWM7IF: PWM7 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred PWM6IF: PWM6 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred PWM5IF: PWM5 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred PWM4IF: PWM4 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred PWM3IF: PWM3 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 14 bit 13-10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 2009 Microchip Technology Inc. Preliminary DS70591B-page 139 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 REGISTER 7-12: U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-6 bit 5 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- R/W-0 ADCP7IF R/W-0 ADCP6IF R/W-0 ADCP5IF R/W-0 ADCP4IF R/W-0 ADCP3IF IFS7: INTERRUPT FLAG STATUS REGISTER 7 U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 R/W-0 ADCP2IF bit 0 Unimplemented: Read as `0' ADCP7IF: ADC Pair 7 Conversion Done Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred ADCP6IF: ADC Pair 6 Conversion Done Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred ADCP5IF: ADC Pair 5 Conversion Done Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred ADCP4IF: ADC Pair 4 Conversion Done Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred ADCP3IF: ADC Pair 3 Conversion Done Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred ADCP2IF: ADC Pair 2 Conversion Done Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 4 bit 3 bit 2 bit 1 bit 0 DS70591B-page 140 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 REGISTER 7-13: U-0 -- bit 15 R/W-0 T2IE bit 7 Legend: R = Readable bit -n = Value at POR bit 15 bit 14 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 OC2IE R/W-0 IC2IE R/W-0 DMA0IE R/W-0 T1IE R/W-0 OC1IE R/W-0 IC1IE IEC0: INTERRUPT ENABLE CONTROL REGISTER 0 R/W-0 R/W-0 ADIE R/W-0 U1TXIE R/W-0 U1RXIE R/W-0 SPI1IE R/W-0 SPI1EIE R/W-0 T3IE bit 8 R/W-0 INT0IE bit 0 DMA1IE Unimplemented: Read as `0' DMA1IE: DMA Channel 1 Data Transfer Complete Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled ADIE: ADC1 Conversion Complete Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled U1TXIE: UART1 Transmitter Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled U1RXIE: UART1 Receiver Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled SPI1IE: SPI1 Event Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled SPI1EIE: SPI1 Event Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled T3IE: Timer3 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled T2IE: Timer2 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled OC2IE: Output Compare Channel 2 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled IC2IE: Input Capture Channel 2 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled DMA0IE: DMA Channel 0 Data Transfer Complete Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled T1IE: Timer1 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 2009 Microchip Technology Inc. Preliminary DS70591B-page 141 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 REGISTER 7-13: bit 2 IEC0: INTERRUPT ENABLE CONTROL REGISTER 0 (CONTINUED) OC1IE: Output Compare Channel 1 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled IC1IE: Input Capture Channel 1 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled INT0IE: External Interrupt 0 Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 1 bit 0 DS70591B-page 142 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 REGISTER 7-14: R/W-0 U2TXIE bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 12 IEC1: INTERRUPT ENABLE CONTROL REGISTER 1 R/W-0 INT2IE R/W-0 T5IE R/W-0 T4IE R/W-0 OC4IE R/W-0 OC3IE R/W-0 DMA2IE bit 8 R/W-0 SI2C1IE bit 0 R/W-0 U2RXIE U-0 -- U-0 -- R/W-0 INT1IE R/W-0 CNIE R/W-0 AC1IE R/W-0 MI2C1IE W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown bit 11 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7-5 bit 4 bit 3 bit 2 bit 1 bit 0 U2TXIE: UART2 Transmitter Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled U2RXIE: UART2 Receiver Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled INT2IE: External Interrupt 2 Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled T5IE: Timer5 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled T4IE: Timer4 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled OC4IE: Output Compare Channel 4 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled OC3IE: Output Compare Channel 3 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled DMA2IE: DMA Channel 2 Data Transfer Complete Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled Unimplemented: Read as `0' INT1IE: External Interrupt 1 Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled CNIE: Input Change Notification Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled AC1IE: Analog Comparator 1 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled MI2C1IE: I2C1 Master Events Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled SI2C1IE: I2C1 Slave Events Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled 2009 Microchip Technology Inc. Preliminary DS70591B-page 143 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 REGISTER 7-15: U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-7 bit 6 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 IC4IE R/W-0 IC3IE R/W-0 DMA3IE R/W-0 C1IE (1) IEC2: INTERRUPT ENABLE CONTROL REGISTER 2 U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 R/W-0 C1RXIE (1) R/W-0 SPI2IE R/W-0 SPI2EIE bit 0 Unimplemented: Read as `0' IC4IE: Input Capture Channel 4 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled IC3IE: Input Capture Channel 3 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled DMA3IE: DMA Channel 3 Data Transfer Complete Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request has enabled C1IE: ECAN1 Event Interrupt Enable bit(1) 1 = Interrupt request enabled 0 = Interrupt request not enabled C1RXIE: ECAN1 Receive Data Ready Interrupt Enable bit(1) 1 = Interrupt request enabled 0 = Interrupt request not enabled SPI2IE: SPI2 Event Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled SPI2EIE: SPI2 Error Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Note 1: Interrupts disabled on devices without ECANTM modules DS70591B-page 144 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 REGISTER 7-16: U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-11 bit 10 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 INT4IE R/W-0 INT3EI U-0 -- U-0 -- R/W-0 MI2C2IE R/W-0 SI2C2IE U-0 -- bit 0 IEC3: INTERRUPT ENABLE CONTROL REGISTER 3 U-0 -- U-0 -- U-0 -- U-0 -- R/W-0 QEI1IE R/W-0 PSEMIE U-0 -- bit 8 Unimplemented: Read as `0' QEI1IE: QEI1 Event Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled PSEMIE: PWM Special Event Match Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled Unimplemented: Read as `0' INT4IE: External Interrupt 4 Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled INT3IE: External Interrupt 3 Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled Unimplemented: Read as `0' MI2C2IE: I2C2 Master Events Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled SI2C2IE: I2C2 Slave Events Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled Unimplemented: Read as `0' bit 9 bit 8-7 bit 6 bit 6 bit 4-3 bit 2 bit 1 bit 0 2009 Microchip Technology Inc. Preliminary DS70591B-page 145 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 REGISTER 7-17: U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-12 bit 11 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 C1TXIE (1) IEC4: INTERRUPT ENABLE CONTROL REGISTER 4 U-0 -- U-0 -- U-0 -- R/W-0 QEI2IE U-0 -- R/W-0 PSESMIE U-0 -- bit 8 U-0 -- U-0 -- U-0 -- R/W-0 U2EIE R/W-0 U1EIE U-0 -- bit 0 Unimplemented: Read as `0' QEI2IE: QEI2 Event Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled Unimplemented: Read as `0' PSESMIE: PWM Special Event Secondary Match Error Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled Unimplemented: Read as `0' C1TXIE: ECAN1 Transmit Data Request Interrupt Enable bit(1) 1 = Interrupt request occurred 0 = Interrupt request not occurred Unimplemented: Read as `0' U2EIE: UART2 Error Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled U1EIE: UART1 Error Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled Unimplemented: Read as `0' bit 10 bit 9 bit 8-7 bit 6 bit 5-3 bit 2 bit 1 bit 0 Note 1: Interrupts disabled on devices without ECANTM modules. DS70591B-page 146 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 REGISTER 7-18: R/W-0 PWM2IE bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- U-0 -- R/W-0 ADCP11IE R/W-0 ADCP10IE R/W-0 ADCP9IE R/W-0 ADCP8IE U-0 -- bit 0 IEC5: INTERRUPT ENABLE CONTROL REGISTER 5 R/W-0 R/W-0 ADCP12IE U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 PWM1IE PWM2IE: PWM2 Interrupt Enable bit(1) 1 = Interrupt request is enabled 0 = Interrupt request is not enabled PWM1IE: PWM1 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled ADCP12IE: ADC Pair 12 Conversion Done Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled Unimplemented: Read as `0' ADCP11IE: ADC Pair 11 Conversion Done Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled ADCP10IE: ADC Pair 10 Conversion Done Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled ADCP9IE: ADC Pair 9 Conversion Done Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled ADCP8IE: ADC Pair 8 Conversion Done Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled Unimplemented: Read as `0' bit 14 bit 13 bit 12-5 bit 4 bit 3 bit 2 bit 1 bit 0 2009 Microchip Technology Inc. Preliminary DS70591B-page 147 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 REGISTER 7-19: R/W-0 ADCP1IE bit 15 R/W-0 AC2IE bit 7 Legend: R = Readable bit -n = Value at POR bit 15 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 PWM9IE R/W-0 PWM8IE R/W-0 PWM7IE R/W-0 PWM6IE R/W-0 PWM5IE R/W-0 PWM4IE IEC6: INTERRUPT ENABLE CONTROL REGISTER 6 R/W-0 U-0 -- U-0 -- U-0 -- U-0 -- R/W-0 AC4IE R/W-0 AC3IE bit 8 R/W-0 PWM3IE bit 0 ADCP0IE ADCP1IE: ADC Pair 1 Conversion Done Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled ADCP0IE: ADC Pair 0 Conversion Done Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled Unimplemented: Read as `0 AC4IE: Analog Comparator 4 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled AC3IE: Analog Comparator 3 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled AC2IE: Analog Comparator 2 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled PWM9IE: PWM9 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled PWM8IE: PWM8 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled PWM7IE: PWM7 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled PWM6IE: PWM6 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled PWM5IE: PWM5 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled PWM4IE: PWM4 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled PWM3IE: PWM3 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 14 bit 13-10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 DS70591B-page 148 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 REGISTER 7-20: U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-6 bit 5 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- R/W-0 ADCP7IE R/W-0 ADCP6IE R/W-0 ADCP5IE R/W-0 ADCP4IE R/W-0 ADCP3IE IEC7: INTERRUPT ENABLE CONTROL REGISTER 7 U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 R/W-0 ADCP2IE bit 0 Unimplemented: Read as `0' ADCP7IE: ADC Pair 7 Conversion Done Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled ADCP6IE: ADC Pair 6 Conversion Done Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled ADCP5IE: ADC Pair 5 Conversion Done Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled ADCP4IE: ADC Pair 4 Conversion Done Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled ADCP3IE: ADC Pair 3 Conversion Done Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled ADCP2IE: ADC Pair 2 Conversion Done Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 4 bit bit bit bit 2009 Microchip Technology Inc. Preliminary DS70591B-page 149 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 REGISTER 7-21: U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15 bit 14-12 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-1 R/W-0 IC1IP<2:0> R/W-0 U-0 -- R/W-1 R/W-0 INT0IP<2:0> bit 0 IPC0: INTERRUPT PRIORITY CONTROL REGISTER 0 R/W-1 R/W-0 T1IP<2:0> R/W-0 U-0 -- R/W-1 R/W-0 OC1IP<2:0> bit 8 R/W-0 R/W-0 Unimplemented: Read as `0' T1IP<2:0>: Timer1 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' OC1IP<2:0>: Output Compare Channel 1 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' IC1IP<2:0>: Input Capture Channel 1 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' INT0IP<2:0>: External Interrupt 0 Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 11 bit 10-8 bit 7 bit 6-4 bit 3 bit 2-0 DS70591B-page 150 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 REGISTER 7-22: U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15 bit 14-12 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-1 R/W-0 IC2IP<2:0> R/W-0 U-0 -- R/W-1 R/W-0 DMA0IP<2:0> bit 0 IPC1: INTERRUPT PRIORITY CONTROL REGISTER 1 R/W-1 R/W-0 T2IP<2:0> R/W-0 U-0 -- R/W-1 R/W-0 OC2IP<2:0> bit 8 R/W-0 R/W-0 Unimplemented: Read as `0' T2IP<2:0>: Timer2 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' OC2IP<2:0>: Output Compare Channel 2 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' IC2IP<2:0>: Input Capture Channel 2 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled DMA0IP<2:0>: DMA Channel 0 Data Transfer Complete Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 11 bit 10-8 bit 7 bit 6-4 bit 3-0 2009 Microchip Technology Inc. Preliminary DS70591B-page 151 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 REGISTER 7-23: U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15 bit 14-12 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-1 R/W-0 SPI1EIP<2:0> R/W-0 U-0 -- R/W-1 R/W-0 T3IP<2:0> bit 0 IPC2: INTERRUPT PRIORITY CONTROL REGISTER 2 R/W-1 R/W-0 U1RXIP<2:0> R/W-0 U-0 -- R/W-1 R/W-0 SPI1IP<2:0> bit 8 R/W-0 R/W-0 Unimplemented: Read as `0' U1RXIP<2:0>: UART1 Receiver Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' SPI1IP<2:0>: SPI1 Event Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' SPI1EIP<2:0>: SPI1 Error Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' T3IP<2:0>: Timer3 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 11 bit 10-8 bit 7 bit 6-4 bit 3 bit 2-0 DS70591B-page 152 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 REGISTER 7-24: U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-11 bit 10-8 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-1 R/W-0 ADIP<2:0> R/W-0 U-0 -- R/W-1 R/W-0 U1TXIP<2:0> bit 0 IPC3: INTERRUPT PRIORITY CONTROL REGISTER 3 U-0 -- U-0 -- U-0 -- U-0 -- R/W-1 R/W-0 DMA1IP<2:0> bit 8 R/W-0 R/W-0 Unimplemented: Read as `0' DMA1IP<2:0>: DMA Channel 1 Data Transfer Complete Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' ADIP<2:0>: ADC1 Conversion Complete Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' U1TXIP<2:0>: UART1 Transmitter Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 7 bit 6-4 bit 3 bit 2-0 2009 Microchip Technology Inc. Preliminary DS70591B-page 153 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 REGISTER 7-25: U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15 bit 14-12 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-1 R/W-0 MI2C1IP<2:0> R/W-0 U-0 -- R/W-1 R/W-0 SI2C1IP<2:0> bit 0 IPC4: INTERRUPT PRIORITY CONTROL REGISTER 4 R/W-1 R/W-0 CNIP<2:0> R/W-0 U-0 -- R/W-1 R/W-0 AC1IP<2:0> bit 8 R/W-0 R/W-0 Unimplemented: Read as `0' CNIP<2:0>: Change Notification Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' AC1IP<2:0>: Analog Comparator 1 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' MI2C1IP<2:0>: I2C1 Master Events Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' SI2C1IP<2:0>: I2C1 Slave Events Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 11 bit 10-8 bit 7 bit 6-4 bit 3 bit 2-0 DS70591B-page 154 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 REGISTER 7-26: U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-3 bit 2-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- U-0 -- U-0 -- U-0 -- R/W-1 R/W-0 INT1IP<2:0> bit 0 IPC5: INTERRUPT PRIORITY CONTROL REGISTER 5 U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 R/W-0 Unimplemented: Read as `0' INT1IP<2:0>: External Interrupt 1 Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled 2009 Microchip Technology Inc. Preliminary DS70591B-page 155 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 REGISTER 7-27: U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15 bit 14-12 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-1 R/W-0 OC3IP<2:0> R/W-0 U-0 -- R/W-1 R/W-0 DMA2IP<2:0> bit 0 IPC6: INTERRUPT PRIORITY CONTROL REGISTER 6 R/W-1 R/W-0 T4IP<2:0> R/W-0 U-0 -- R/W-1 R/W-0 OC4IP<2:0> bit 8 R/W-0 R/W-0 Unimplemented: Read as `0' T4IP<2:0>: Timer4 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' OC4IP<2:0>: Output Compare Channel 4 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' OC3IP<2:0>: Output Compare Channel 3 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' DMA2IP<2:0>: DMA Channel 2 Data Transfer Complete Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 11 bit 10-8 bit 7 bit 6-4 bit 3 bit 2-0 DS70591B-page 156 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 REGISTER 7-28: U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15 bit 14-12 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-1 R/W-0 INT2IP<2:0> R/W-0 U-0 -- R/W-1 R/W-0 T5IP<2:0> bit 0 IPC7: INTERRUPT PRIORITY CONTROL REGISTER 7 R/W-1 R/W-0 U2TXIP<2:0> R/W-0 U-0 -- R/W-1 R/W-0 U2RXIP<2:0> bit 8 R/W-0 R/W-0 Unimplemented: Read as `0' U2TXIP<2:0>: UART2 Transmitter Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' U2RXIP<2:0>: UART2 Receiver Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' INT2IP<2:0>: External Interrupt 2 Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' T5IP<2:0>: Timer5 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 11 bit 10-8 bit 7 bit 6-4 bit 3 bit 2-0 2009 Microchip Technology Inc. Preliminary DS70591B-page 157 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 REGISTER 7-29: U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15 bit 14-12 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-1 R/W-0 SPI2IP<2:0> R/W-0 U-0 -- R/W-1 R/W-0 SPI2EIP<2:0> bit 0 IPC8: INTERRUPT PRIORITY CONTROL REGISTER 8 R/W-1 R/W-0 C1IP<2:0> (1) R/W-0 U-0 -- R/W-1 R/W-0 C1RXIP<2:0> (1) R/W-0 bit 8 R/W-0 Unimplemented: Read as `0' C1IP<2:0>: ECAN1 Event Interrupt Priority bits(1) 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' C1RXIP<2:0>: ECAN1 Receive Data Ready Interrupt Priority bits(1) 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' SPI2IP<2:0>: SPI2 Event Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' SPI2EIP<2:0>: SPI2 Error Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 11 bit 10-8 bit 7 bit 6-4 bit 3 bit 2-0 Note 1: Interrupts disabled on devices without ECANTM modules DS70591B-page 158 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 REGISTER 7-30: U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-11 bit 10-8 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-1 R/W-0 IC3IP<2:0> R/W-0 U-0 -- R/W-1 R/W-0 DMA3IP<2:0> bit 0 IPC9: INTERRUPT PRIORITY CONTROL REGISTER 9 U-0 -- U-0 -- U-0 -- U-0 -- R/W-1 R/W-0 IC4IP<2:0> bit 8 R/W-0 R/W-0 Unimplemented: Read as `0' IC4IP<2:0>: Input Capture Channel 4 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' IC3IP<2:0>: Input Capture Channel 3 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' DMA3IP<2:0>: DMA Channel 3 Data Transfer Complete Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 7 bit 6-4 bit 3 bit 2-0 2009 Microchip Technology Inc. Preliminary DS70591B-page 159 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 REGISTER 7-31: U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-11 bit 10-8 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-1 R/W-0 SI2C2IP<2:0> R/W-0 U-0 -- U-0 -- U-0 -- U-0 -- bit 0 IPC12: INTERRUPT PRIORITY CONTROL REGISTER 12 U-0 -- U-0 -- U-0 -- U-0 -- R/W-1 R/W-0 MI2C2IP<2:0> bit 8 R/W-0 Unimplemented: Read as `0' MI2C2IP<2:0>: I2C2 Master Events Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' SI2C2IP<2:0>: I2C2 Slave Events Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' bit 7 bit 6-4 bit 3-0 DS70591B-page 160 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 REGISTER 7-32: U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-11 bit 10-8 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-1 R/W-0 INT3IP<2:0> R/W-0 U-0 -- U-0 -- U-0 -- U-0 -- bit 0 IPC13: INTERRUPT PRIORITY CONTROL REGISTER 13 U-0 -- U-0 -- U-0 -- U-0 -- R/W-1 R/W-0 INT4IP<2:0> bit 8 R/W-0 Unimplemented: Read as `0' INT4IP<2:0>: External Interrupt 4 Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' INT3IP<2:0>: External Interrupt 3 Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' bit 7 bit 6-4 bit 3-0 2009 Microchip Technology Inc. Preliminary DS70591B-page 161 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 REGISTER 7-33: U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-11 bit 10-8 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-1 R/W-0 PSEMIP<2:0> R/W-0 U-0 -- U-0 -- U-0 -- U-0 -- bit 0 IPC14: INTERRUPT PRIORITY CONTROL REGISTER 14 U-0 -- U-0 -- U-0 -- U-0 -- R/W-1 R/W-0 QEI1IP<2:0> bit 8 R/W-0 Unimplemented: Read as `0' QEI1IP<2:0>: QEI1 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' PSEMIP<2:0>: PWM Special Event Match Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' bit 7 bit 6-4 bit 3-0 DS70591B-page 162 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 REGISTER 7-34: U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-11 bit 10-8 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-1 R/W-0 U1EIP<2:0> R/W-0 U-0 -- U-0 -- U-0 -- U-0 -- bit 0 IPC16: INTERRUPT PRIORITY CONTROL REGISTER 16 U-0 -- U-0 -- U-0 -- U-0 -- R/W-1 R/W-0 U2EIP<2:0> bit 8 R/W-0 Unimplemented: Read as `0' U2EIP<2:0>: UART2 Error Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' U1EIP<2:0>: UART1 Error Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' bit 7 bit 6-4 bit 3-0 2009 Microchip Technology Inc. Preliminary DS70591B-page 163 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 REGISTER 7-35: U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-11 bit 10-8 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 0 IPC17: INTERRUPT PRIORITY CONTROL REGISTER 17 U-0 -- U-0 -- U-0 -- U-0 -- R/W-1 R/W-0 C1TXIP<2:0>(1) bit 8 R/W-0 Unimplemented: Read as `0' C1TXIP<2:0>: ECAN1 Transmit Data Request Interrupt Priority bits(1) 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' bit 7-0 Note 1: Interrupts disabled on devices without ECANTM modules DS70591B-page 164 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 REGISTER 7-36: U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15 bit 14-12 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-1 R/W-0 PSESMIP<2:0> R/W-0 U-0 -- U-0 -- U-0 -- U-0 -- bit 0 IPC18: INTERRUPT PRIORITY CONTROL REGISTER 18 R/W-1 R/W-0 QEI2IP<2:0> R/W-0 U-0 -- U-0 -- U-0 -- U-0 -- bit 8 Unimplemented: Read as `0' QEI2IP<2:0>: QEI2 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' PSESMIP<2:0>: PWM Special Event Secondary Match Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' bit 11-7 bit 6-4 bit 3-0 2009 Microchip Technology Inc. Preliminary DS70591B-page 165 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 REGISTER 7-37: U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15 bit 14-12 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-1 R/W-0 ADCP8IP<2:0> R/W-0 U-0 -- U-0 -- U-0 -- U-0 -- bit 0 IPC20: INTERRUPT PRIORITY CONTROL REGISTER 20 R/W-1 R/W-0 ADCP10IP<2:0> R/W-0 U-0 -- R/W-1 R/W-0 ADCP9IP<2:0> bit 8 R/W-0 Unimplemented: Read as `0' ADCP10IP<2:0>: ADC Pair 10 Conversion Done Interrupt 1 Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' ADCP9IP<2:0>: ADC Pair 9 Conversion Done Interrupt 1 Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' ADCP8IP<2:0>: ADC Pair 8 Conversion Done Interrupt 1 Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' bit 11 bit 10-8 bit 7 bit 6-4 bit 3-0 DS70591B-page 166 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 REGISTER 7-38: U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-7 bit 6-4 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-1 R/W-0 ADCP12IP<2:0> R/W-0 U-0 -- R/W-1 R/W-0 ADCP11IP<2:0> bit 0 IPC21: INTERRUPT PRIORITY CONTROL REGISTER 21 U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 R/W-0 Unimplemented: Read as `0' ADCP12IP<2:0>: ADC Pair 12 Conversion Done Interrupt 1 Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' ADCP11IP<2:0>: ADC Pair 11 Conversion Done Interrupt 1 Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3 bit 2-0 2009 Microchip Technology Inc. Preliminary DS70591B-page 167 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 REGISTER 7-39: U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15 bit 14-12 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 0 IPC23: INTERRUPT PRIORITY CONTROL REGISTER 23 R/W-1 R/W-0 PWM2IP<2:0> R/W-0 U-0 -- R/W-1 R/W-0 PWM1IP<2:0> bit 8 R/W-0 Unimplemented: Read as `0' PWM2IP<2:0>: PWM2 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' PWM1IP<2:0>: PWM1 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' bit 11 bit 10-8 bit 7-0 DS70591B-page 168 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 REGISTER 7-40: U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15 bit 14-12 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-1 R/W-0 PWM4IP<2:0> R/W-0 U-0 -- R/W-1 R/W-0 PWM3IP<2:0> bit 0 IPC24: INTERRUPT PRIORITY CONTROL REGISTER 24 R/W-1 R/W-0 PWM6IP<2:0> R/W-0 U-0 -- R/W-1 R/W-0 PWM5IP<2:0> bit 8 R/W-0 R/W-0 Unimplemented: Read as `0' PWM6IP<2:0>: PWM6 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' PWM5IP<2:0>: PWM5 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' PWM4IP<2:0>: PWM4 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' PWM3IP<2:0>: PWM3 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 11 bit 10-8 bit 7 bit 6-4 bit 3 bit 2-0 2009 Microchip Technology Inc. Preliminary DS70591B-page 169 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 REGISTER 7-41: U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15 bit 14-12 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-1 R/W-0 PWM8IP<2:0> R/W-0 U-0 -- R/W-1 R/W-0 PWM7IP<2:0> bit 0 IPC25: INTERRUPT PRIORITY CONTROL REGISTER 25 R/W-1 R/W-0 AC2IP<2:0> R/W-0 U-0 -- R/W-1 R/W-0 PWM9IP<2:0> bit 8 R/W-0 R/W-0 Unimplemented: Read as `0' AC2IP<2:0>: Analog Comparator 2 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' PWM9IP<2:0>: PWM9 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' PWM8IP<2:0>: PWM8 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' PWM7IP<2:0>: PWM7 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 11 bit 10-8 bit 7 bit 6-4 bit 3 bit 2-0 DS70591B-page 170 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 REGISTER 7-42: U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-7 bit 6-4 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-1 R/W-0 AC4IP<2:0> R/W-0 U-0 -- R/W-1 R/W-0 AC3IP<2:0> bit 0 IPC26: INTERRUPT PRIORITY CONTROL REGISTER 26 U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 R/W-0 Unimplemented: Read as `0' AC4IP<2:0>: Analog Comparator 4 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' AC3IP<2:0>: Analog Comparator 3 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3 bit 2-0 2009 Microchip Technology Inc. Preliminary DS70591B-page 171 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 REGISTER 7-43: U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15 bit 14-12 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 0 IPC27: INTERRUPT PRIORITY CONTROL REGISTER 27 R/W-1 R/W-0 ADCP1IP<2:0> R/W-0 U-0 -- R/W-1 R/W-0 ADCP0IP<2:0> bit 8 R/W-0 Unimplemented: Read as `0' ADCP1IP<2:0>: ADC Pair 1 Conversion Done Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' ADCP0IP<2:0>: ADC Pair 0 Conversion Done Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' bit 11 bit 10-8 bit 7-0 DS70591B-page 172 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 REGISTER 7-44: U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15 bit 14-12 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-1 R/W-0 ADCP3IP<2:0> R/W-0 U-0 -- R/W-1 R/W-0 ADCP2IP<2:0> bit 0 IPC28: INTERRUPT PRIORITY CONTROL REGISTER 28 R/W-1 R/W-0 ADCP5IP<2:0> R/W-0 U-0 -- R/W-1 R/W-0 ADCP4IP<2:0> bit 8 R/W-0 R/W-0 Unimplemented: Read as `0' ADCP5IP<2:0>: ADC Pair 5 Conversion Done Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' ADCP4IP<2:0>: ADC Pair 4 Conversion Done Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' ADCP3IP<2:0>: ADC Pair 3 Conversion Done Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' ADCP2IP<2:0>: ADC Pair 2 Conversion Done Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 11 bit 10-8 bit 7 bit 6-4 bit 3 bit 2-0 2009 Microchip Technology Inc. Preliminary DS70591B-page 173 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 REGISTER 7-45: U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-7 bit 6-4 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-1 R/W-0 ADCP7IP<2:0> R/W-0 U-0 -- R/W-1 R/W-0 ADCP6IP<2:0> bit 0 IPC29: INTERRUPT PRIORITY CONTROL REGISTER 29 U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 R/W-0 Unimplemented: Read as `0' ADCP7IP<2:0>: ADC Pair 7 Conversion Done Interrupt 1 Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Unimplemented: Read as `0' ADCP6IP<2:0>: ADC Pair 6 Conversion Done Interrupt 1 Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3 bit 2-0 DS70591B-page 174 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 REGISTER 7-46: U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-12 bit 11-8 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R-0 R-0 R-0 R-0 VECNUM<6:0> bit 0 R-0 R-0 R-0 INTTREG: INTERRUPT CONTROL AND STATUS REGISTER U-0 -- U-0 -- U-0 -- R-0 R-0 ILR<3:0> bit 8 R-0 R-0 Unimplemented: Read as `0' ILR<3:0>: New CPU Interrupt Priority Level bits 1111 = CPU Interrupt Priority Level is 15 * * * 0001 = CPU Interrupt Priority Level is 1 0000 = CPU Interrupt Priority Level is 0 Unimplemented: Read as `0' VECNUM<6:0>: Vector Number of Pending Interrupt bits 0111111 = Interrupt vector pending is number 135 * * * 0000001 = Interrupt vector pending is number 9 0000000 = Interrupt vector pending is number 8 bit 7 bit 6-0 2009 Microchip Technology Inc. Preliminary DS70591B-page 175 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 7.4 7.4.1 Interrupt Setup Procedures INITIALIZATION 7.4.3 TRAP SERVICE ROUTINE Complete the following steps to configure an interrupt source at initialization: 1. 2. Set the NSTDIS bit (INTCON1<15>) if nested interrupts are not desired. Select the user-assigned priority level for the interrupt source by writing the control bits in the appropriate IPCx register. The priority level will depend on the specific application and type of interrupt source. If multiple priority levels are not desired, the IPCx register control bits for all enabled interrupt sources can be programmed to the same non-zero value. Note: At a device Reset, the IPCx registers are initialized such that all user interrupt sources are assigned to priority level 4. A Trap Service Routine (TSR) is coded like an ISR, except that the appropriate trap status flag in the INTCON1 register must be cleared to avoid re-entry into the TSR. 7.4.4 INTERRUPT DISABLE The following steps outline the procedure to disable all user interrupts: 1. 2. Push the current SR value onto the software stack using the PUSH instruction. Force the CPU to priority level 7 by inclusive ORing the value EOh with SRL. To enable user interrupts, the POP instruction can be used to restore the previous SR value. Note: Only user interrupts with a priority level of 7 or lower can be disabled. Trap sources (level 8-level 15) cannot be disabled. 3. 4. Clear the interrupt flag status bit associated with the peripheral in the associated IFSx register. Enable the interrupt source by setting the interrupt enable control bit associated with the source in the appropriate IECx register. The DISI instruction provides a convenient way to disable interrupts of priority levels 1-6 for a fixed period of time. Level 7 interrupt sources are not disabled by the DISI instruction. 7.4.2 INTERRUPT SERVICE ROUTINE the the the the The method used to declare an ISR and initialize IVT with the correct vector address depends on programming language (C or assembler) and language development toolsuite used to develop application. In general, the user application must clear the interrupt flag in the appropriate IFSx register for the source of interrupt that the ISR handles. Otherwise, program will re-enter the ISR immediately after exiting the routine. If the ISR is coded in assembly language, it must be terminated using a RETFIE instruction to unstack the saved PC value, SRL value and old CPU priority level. DS70591B-page 176 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 8.0 DIRECT MEMORY ACCESS (DMA) Direct Memory Access (DMA) is a very efficient mechanism of copying data between peripheral SFRs (e.g., the UART Receive register and Input Capture 1 buffer) and buffers or variables stored in RAM, with minimal CPU intervention. The DMA controller can automatically copy entire blocks of data without requiring the user software to read or write the peripheral Special Function Registers (SFRs) every time a peripheral interrupt occurs. The DMA controller uses a dedicated bus for data transfers and, therefore, does not steal cycles from the code execution flow of the CPU. To exploit the DMA capability, the corresponding user buffers or variables must be located in DMA RAM. Note: The DMA module is not available on dsIPC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406 devices. Note 1: This data sheet summarizes the features of the dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 family of devices. However, it is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 22. "Direct Memory Access (DMA)" (DS70182) in the "dsPIC33F/PIC24H Family Reference Manual", which is available from the Microchip web site (www.microchip.com). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 "Memory Organization" in this data sheet for device-specific register and bit information. The peripherals that can utilize DMA are listed in Table 8-1 along with their associated Interrupt Request (IRQ) numbers. TABLE 8-1: DMA CHANNEL TO PERIPHERAL ASSOCIATIONS DMAxREQ Register IRQSEL<6:0> Bits 0000000 0000001 0000101 0100101 0100110 0000010 0000010 0000110 0000110 0011001 0011001 0011010 0011010 0000111 0001000 0011011 0011100 0001010 0100001 0001011 0001100 0011110 0011111 0100010 1000110 DMAxPAD Register Values to Read From Peripheral -- 0x0140 (IC1BUF) 0x0144 (IC2BUF) 0x0148 (IC3BUF) 0x0148C (IC4BUF) -- -- -- -- -- -- -- -- -- -- -- -- 0x0248 (SPI1BUF) 0x0268 (SPI2BUF) 0x0226 (U1RXREG) -- 0x0236 (U2RXREG) -- 0x0440 (C1RXD) -- DMAxPAD Register Values to Write to Peripheral -- -- -- -- -- 0x0182 (OC1R) 0x0180 (OC1RS) 0x0188 (OC2R) 0x0186 (OC2RS) 0x018E (OC3R) 0x018C (OC3RS) 0x0194 (OC4R) 0x0192 (OC4RS) -- -- -- -- 0x0248 (SPI1BUF) 0x0268 (SPI2BUF) -- 0x0224 (U1TXREG) -- 0x0234 (U2TXREG) -- 0x0442 (C1TXD) Peripheral to DMA Association INT0 - External Interrupt 0 IC1 - Input Capture 1 IC2 - Input Capture 2 IC3 - Input Capture 3 IC4 - Input Capture 4 OC1 - Output Compare 1 Data OC1 - Output Compare 1 Secondary Data OC2 - Output Compare 2 Data OC2 - Output Compare 2 Secondary Data OC3 - Output Compare 3 Data OC3 - Output Compare 3 Secondary Data OC4 - Output Compare 4 Data OC4 - Output Compare 4 Secondary Data TMR2 - Timer2 TMR3 - Timer3 TMR4 - Timer4 TMR5 - Timer5 SPI1 - Transfer Done SPI2 - Transfer Done UART1RX - UART1 Receiver UART1TX - UART1 Transmitter UART2RX - UART2 Receiver UART2TX - UART2 Transmitter ECAN1 - RX Data Ready ECAN1 - TX Data Request 2009 Microchip Technology Inc. Preliminary DS70591B-page 177 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 The DMA controller features four identical data transfer channels. Each channel has its own set of control and STATUS registers. Each DMA channel can be configured to copy data either from buffers stored in dual port DMA RAM to peripheral SFRs or from peripheral SFRs to buffers in DMA RAM. The DMA controller supports the following features: * Word or byte sized data transfers. * Transfers from peripheral to DMA RAM or DMA RAM to peripheral. * Indirect Addressing of DMA RAM locations with or without automatic post-increment. * Peripheral Indirect Addressing - In some peripherals, the DMA RAM read/write addresses may be partially derived from the peripheral. * One-Shot Block Transfers - Terminating DMA transfer after one block transfer. * Continuous Block Transfers - Reloading DMA RAM buffer start address after every block transfer is complete. * Ping-Pong Mode - Switching between two DMA RAM start addresses between successive block transfers, thereby filling two buffers alternately. * Automatic or manual initiation of block transfers. For each DMA channel, a DMA interrupt request is generated when a block transfer is complete. Alternatively, an interrupt can be generated when half of the block has been filled. 8.1 DMAC Registers Each DMAC Channel x (x = 0, 1, 2, or 3) contains the following registers: * A 16-bit DMA Channel Control register (DMAxCON) * A 16-bit DMA Channel IRQ Select register (DMAxREQ) * A 16-bit DMA RAM Primary Start Address Offset register (DMAxSTA) * A 16-bit DMA RAM Secondary Start Address Offset register (DMAxSTB) * A 16-bit DMA Peripheral Address register (DMAxPAD) * A 10-bit DMA Transfer Count register (DMAxCNT) An additional pair of STATUS registers, DMACS0 and DMACS1, are common to all DMAC channels. FIGURE 8-1: TOP LEVEL SYSTEM ARCHITECTURE USING A DEDICATED TRANSACTION BUS Peripheral Indirect Address DMA Controller DMA Control DMA Channels 1 2 SRAM DMA RAM PORT 1 PORT 2 DMA Ready Peripheral 3 3 CPU DMA 0 SRAM X-Bus DMA DS Bus CPU Peripheral DS Bus CPU Non-DMA Ready Peripheral CPU DMA CPU DMA DMA Ready Peripheral 1 DMA Ready Peripheral 2 Note: For clarity, CPU and DMA address buses are not shown. DS70591B-page 178 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 REGISTER 8-1: R/W-0 CHEN bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- R/W-0 R/W-0 U-0 -- U-0 -- R/W-0 DMAxCON: DMA CHANNEL x CONTROL REGISTER R/W-0 SIZE R/W-0 DIR R/W-0 HALF R/W-0 NULLW U-0 -- U-0 -- U-0 -- bit 8 R/W-0 bit 0 AMODE<1:0> MODE<1:0> CHEN: Channel Enable bit 1 = Channel enabled 0 = Channel disabled SIZE: Data Transfer Size bit 1 = Byte 0 = Word DIR: Transfer Direction bit (source/destination bus select) 1 = Read from DMA RAM address; write to peripheral address 0 = Read from peripheral address; write to DMA RAM address HALF: Early Block Transfer Complete Interrupt Select bit 1 = Initiate block transfer complete interrupt when half of the data has been moved 0 = Initiate block transfer complete interrupt when all of the data has been moved NULLW: Null Data Peripheral Write Mode Select bit 1 = Null data write to peripheral in addition to DMA RAM write (DIR bit must also be clear) 0 = Normal operation Unimplemented: Read as `0' AMODE<1:0>: DMA Channel Operating Mode Select bits 11 = Reserved 10 = Peripheral Indirect Addressing mode 01 = Register Indirect without Post-Increment mode 00 = Register Indirect with Post-Increment mode Unimplemented: Read as `0' MODE<1:0>: DMA Channel Operating Mode Select bits 11 = One-Shot, Ping-Pong modes enabled (one block transfer from/to each DMA RAM buffer) 10 = Continuous, Ping-Pong modes enabled 01 = One-Shot, Ping-Pong modes disabled 00 = Continuous, Ping-Pong modes disabled bit 14 bit 13 bit 12 bit 11 bit 10-6 bit 5-4 bit 3-2 bit 1-0 2009 Microchip Technology Inc. Preliminary DS70591B-page 179 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 REGISTER 8-2: R/W-0 FORCE(1) bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-1 R/W-1 R/W-1 R/W-1 IRQSEL<6:0>(2) bit 0 R/W-1 R/W-1 DMAxREQ: DMA CHANNEL x IRQ SELECT REGISTER U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 R/W-1 FORCE: Force DMA Transfer bit(1) 1 = Force a single DMA transfer (Manual mode) 0 = Automatic DMA transfer initiation by DMA request Unimplemented: Read as `0' IRQSEL<6:0>: DMA Peripheral IRQ Number Select bits(2) 0000000-1111111 = DMAIRQ0-DMAIRQ127 selected to be Channel DMAREQ bit 14-7 bit 6-0 Note 1: The FORCE bit cannot be cleared by the user. The FORCE bit is cleared by hardware when the forced DMA transfer is complete. 2: See Table 8-1 for a complete listing of IRQ numbers for all interrupt sources. DS70591B-page 180 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 REGISTER 8-3: R/W-0 bit 15 R/W-0 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DMAxSTA: DMA CHANNEL x RAM START ADDRESS OFFSET REGISTER A R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 bit 8 R/W-0 bit 0 STA<15:8> STA<7:0> STA<15:0>: Primary DMA RAM Start Address bits (source or destination) REGISTER 8-4: R/W-0 bit 15 R/W-0 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-0 DMAxSTB: DMA CHANNEL x RAM START ADDRESS OFFSET REGISTER B R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 bit 0 STB<15:8> STB<7:0> W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown STB<15:0>: Secondary DMA RAM Start Address bits (source or destination) 2009 Microchip Technology Inc. Preliminary DS70591B-page 181 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 REGISTER 8-5: R/W-0 bit 15 R/W-0 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DMAxPAD: DMA CHANNEL x PERIPHERAL ADDRESS REGISTER(1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 bit 8 R/W-0 bit 0 PAD<15:8> PAD<7:0> PAD<15:0>: Peripheral Address Register bits Note 1: If the channel is enabled (i.e., active), writes to this register may result in unpredictable behavior of the DMA channel and should be avoided. 2: See Table 8-1 for a complete list of peripheral addresses. REGISTER 8-6: U-0 -- bit 15 R/W-0 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-10 bit 9-0 DMAxCNT: DMA CHANNEL x TRANSFER COUNT REGISTER(1) U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- R/W-0 R/W-0 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 bit 0 CNT<9:8>(2) CNT<7:0> W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown Unimplemented: Read as `0' CNT<9:0>: DMA Transfer Count Register bits(2) Note 1: If the channel is enabled (i.e., active), writes to this register may result in unpredictable behavior of the DMA channel and should be avoided. 2: Number of DMA transfers = CNT<9:0> + 1. DS70591B-page 182 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 REGISTER 8-7: U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-12 bit 11 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- U-0 -- U-0 -- R/C-0 XWCOL3 R/C-0 XWCOL2 R/C-0 XWCOL1 DMACS0: DMA CONTROLLER STATUS REGISTER 0 U-0 -- U-0 -- U-0 -- R/C-0 PWCOL3 R/C-0 PWCOL2 R/C-0 PWCOL1 R/C-0 PWCOL0 bit 8 R/C-0 XWCOL0 bit 0 Unimplemented: Read as `0' PWCOL3: Channel 3 Peripheral Write Collision Flag bit 1 = Write collision detected 0 = No write collision detected PWCOL2: Channel 2 Peripheral Write Collision Flag bit 1 = Write collision detected 0 = No write collision detected PWCOL1: Channel 1 Peripheral Write Collision Flag bit 1 = Write collision detected 0 = No write collision detected PWCOL0: Channel 0 Peripheral Write Collision Flag bit 1 = Write collision detected 0 = No write collision detected Unimplemented: Read as `0' XWCOL3: Channel 3 DMA RAM Write Collision Flag bit 1 = Write collision detected 0 = No write collision detected XWCOL2: Channel 2 DMA RAM Write Collision Flag bit 1 = Write collision detected 0 = No write collision detected XWCOL1: Channel 1 DMA RAM Write Collision Flag bit 1 = Write collision detected 0 = No write collision detected XWCOL0: Channel 0 DMA RAM Write Collision Flag bit 1 = Write collision detected 0 = No write collision detected bit 10 bit 9 bit 8 bit 7-4 bit 3 bit 2 bit 1 bit 0 2009 Microchip Technology Inc. Preliminary DS70591B-page 183 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 REGISTER 8-8: U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-12 bit 11-8 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- U-0 -- U-0 -- R-0 PPST3 R-0 PPST2 R-0 PPST1 R-0 PPST0 bit 0 DMACS1: DMA CONTROLLER STATUS REGISTER 1 U-0 -- U-0 -- U-0 -- R-1 R-1 R-1 R-1 bit 8 LSTCH<3:0> Unimplemented: Read as `0' LSTCH<3:0>: Last DMA Channel Active bits 1111 = No DMA transfer has occurred since system Reset 1110-0100 = Reserved 0011 = Last data transfer was by DMA Channel 3 0010 = Last data transfer was by DMA Channel 2 0001 = Last data transfer was by DMA Channel 1 0000 = Last data transfer was by DMA Channel 0 Unimplemented: Read as `0' PPST3: Channel 3 Ping-Pong Mode Status Flag bit 1 = DMA3STB register selected 0 = DMA3STA register selected PPST2: Channel 2 Ping-Pong Mode Status Flag bit 1 = DMA2STB register selected 0 = DMA2STA register selected PPST1: Channel 1 Ping-Pong Mode Status Flag bit 1 = DMA1STB register selected 0 = DMA1STA register selected PPST0: Channel 0 Ping-Pong Mode Status Flag bit 1 = DMA0STB register selected 0 = DMA0STA register selected bit 7-4 bit 3 bit 2 bit 1 bit 0 DS70591B-page 184 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 REGISTER 8-9: R-0 bit 15 R-0 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R-0 R-0 R-0 R-0 R-0 R-0 R-0 bit 0 DSADR: MOST RECENT DMA RAM ADDRESS R-0 R-0 R-0 R-0 R-0 R-0 R-0 bit 8 DSADR<15:8> DSADR<7:0> DSADR<15:0>: Most Recent DMA RAM Address Accessed by DMA Controller bits 2009 Microchip Technology Inc. Preliminary DS70591B-page 185 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 NOTES: DS70591B-page 186 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 9.0 OSCILLATOR CONFIGURATION The dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 oscillator system provides: * External and internal oscillator options as clock sources * An on-chip Phase-Locked Loop (PLL) to scale the internal operating frequency to the required system clock frequency * An internal FRC oscillator that can also be used with the PLL, thereby allowing full-speed operation without any external clock generation hardware * Clock switching between various clock sources * Programmable clock postscaler for system power savings * A Fail-Safe Clock Monitor (FSCM) that detects clock failure and takes fail-safe measures * A Clock Control register (OSCCON) * Nonvolatile Configuration bits for main oscillator selection. * Auxiliary PLL for ADC and PWM A simplified diagram of the oscillator system is shown in Figure 9-1. Note 1: This data sheet summarizes the features of the dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 42. "Oscillator (Part IV)" (DS70307) in the "dsPIC33F Family Reference Manual", which is available from the Microchip web site (www.microchip.com). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 "Memory Organization" in this data sheet for device-specific register and bit information. 2009 Microchip Technology Inc. Preliminary DS70591B-page 187 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 FIGURE 9-1: OSC1 R(2) OSC2 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 OSCILLATOR SYSTEM DIAGRAM Primary Oscillator (POSC) POSCCLK XT, HS, EC XTPLL, HSPLL, ECPLL, FRCPLL PLL(1) FVCO(1) To ADC and Auxiliary Clock Generator FRCDIV FRCDIVN /2 S7 FOSC S1/S3 DOZE<2:0> S2 DOZE FCY S3 S1 POSCMD<1:0> FP FRC Oscillator TUN<5:0> / 16 FRCDIV<2:0> FRCDIV16 FRC LPRC S6 S0 LPRC Oscillator Secondary Oscillator (SOSC) SOSCO LPOSCEN SOSCI S5 SOSC S4 Clock Fail S7 Clock Switch Reset NOSC<2:0> FNOSC<2:0> Reference Clock Generation POSCCLK FOSC /N WDT, PWRT, FSCM Timer 1 REFCLKO(3) ROSEL Auxiliary Clock Generation POSCCLK FRCCLK RODIV<3:0> APLL x16 FVCO(1) ACLK /N To PWM/ADC ASRCSEL Note 1: 2: 3: FRCSEL ENAPLL SELACLK APSTSCLR<2:0> See Figure 9-2 for PLL details. If the Oscillator is used with XT or HS modes, an external parallel resistor with the value of 1 M must be connected. REFCLKO functionality is not available if the Primary Oscillator is used. DS70591B-page 188 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 9.1 CPU Clocking System The clock signals generated by the FRC and primary oscillators can be optionally applied to an on-chip Phase-Locked Loop (PLL) to provide a wide range of output frequencies for device operation. PLL configuration is described in Section 9.1.3 "PLL Configuration". The FRC frequency depends on the FRC accuracy (see Table 27-20) and the value of the FRC Oscillator Tuning register (see Register 9-4). The dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 devices provide six system clock options: * * * * * * * Fast RC (FRC) Oscillator FRC Oscillator with PLL Primary (XT, HS, or EC) Oscillator Primary Oscillator with PLL Low-Power RC (LPRC) Oscillator FRC Oscillator with Postscaler Secondary (LP) Oscillator 9.1.2 SYSTEM CLOCK SELECTION 9.1.1 SYSTEM CLOCK SOURCES The Fast RC (FRC) internal oscillator runs at a nominal frequency of 7.37 MHz. User software can tune the FRC frequency. User software can optionally specify a factor (ranging from 1:2 to 1:256) by which the FRC clock frequency is divided. This factor is selected using the FRCDIV<2:0> (CLKDIV<10:8>) bits. The primary oscillator can use one of the following as its clock source: * XT (Crystal): Crystals and ceramic resonators in the range of 3 MHz to 10 MHz. The crystal is connected to the OSC1 and OSC2 pins. * HS (High-Speed Crystal): Crystals in the range of 10 MHz to 40 MHz. The crystal is connected to the OSC1 and OSC2 pins. * EC (External Clock): The external clock signal is directly applied to the OSC1 pin. The secondary (LP) oscillator is designed for low power and uses a 32.768 kHz crystal or ceramic resonator. The LP oscillator uses the SOSCI and SOSCO pins. The LPRC internal oscIllator runs at a nominal frequency of 32.768 kHz. It is also used as a reference clock by the Watchdog Timer (WDT) and Fail-Safe Clock Monitor (FSCM). The oscillator source used at a device Power-on Reset event is selected using Configuration bit settings. The oscillator Configuration bit settings are located in the Configuration registers in the program memory. (Refer to Section 24.1 "Configuration Bits" for further details.) The Initial Oscillator Selection Configuration bits, FNOSC<2:0> (FOSCSEL<2:0>), and the Primary Oscillator Mode Select Configuration bits, POSCMD<1:0> (FOSC<1:0>), select the oscillator source that is used at a Power-on Reset. The FRC primary oscillator is the default (unprogrammed) selection. The Configuration bits allow users to choose among 12 different clock modes, shown in Table 9-1. The output of the oscillator (or the output of the PLL if a PLL mode has been selected), FOSC, is divided by 2 to generate the device instruction clock (FCY) and the peripheral clock time base (FP). FCY defines the operating speed of the device and speeds up to 40 MHz are supported by the dsPIC33FJ32GS406/606/ 608/610 and DSPIC33FJ64GS406/606/608/610 architecture. Instruction execution speed or device operating frequency, FCY, is given by Equation 9-1. EQUATION 9-1: DEVICE OPERATING FREQUENCY FCY = FOSC/2 2009 Microchip Technology Inc. Preliminary DS70591B-page 189 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 TABLE 9-1: CONFIGURATION BIT VALUES FOR CLOCK SELECTION Oscillator Mode Fast RC Oscillator with Divide-by-N (FRCDIVN) Fast RC Oscillator with Divide-by-16 (FRCDIV16) Low-Power RC Oscillator (LPRC) Secondary Oscillator (SOSC) Primary Oscillator (HS) with PLL (HSPLL) Primary Oscillator (XT) with PLL (XTPLL) Primary Oscillator (EC) with PLL (ECPLL) Primary Oscillator (HS) Primary Oscillator (XT) Primary Oscillator (EC) Fast RC Oscillator with PLL (FRCPLL) Fast RC Oscillator (FRC) Note 1: 2: Oscillator Source POSCMD<1:0> Internal Internal Internal Secondary Primary Primary Primary Primary Primary Primary Internal Internal xx xx xx xx 10 01 00 10 01 00 xx xx FNOSC<2:0> 111 110 101 100 011 011 011 010 010 010 001 000 Note 1, 2 1 1 -- -- -- 1 -- -- 1 1 1 OSC2 pin function is determined by the OSCIOFNC Configuration bit. This is the default oscillator mode for an unprogrammed (erased) device. 9.1.3 PLL CONFIGURATION The primary oscillator and internal FRC oscillator can optionally use an on-chip PLL to obtain higher speeds of operation. The PLL provides significant flexibility in selecting the device operating speed. A block diagram of the PLL is shown in Figure 9-2. The output of the primary oscillator or FRC, denoted as `FIN', is divided down by a prescale factor (N1) of 2, 3, ... or 33 before being provided to the PLL's Voltage Controlled Oscillator (VCO). The input to the VCO must be selected in the range of 0.8 MHz to 8 MHz. The prescale factor `N1' is selected using the PLLPRE<4:0> bits (CLKDIV<4:0>). The PLL Feedback Divisor, selected using the PLLDIV<8:0> bits (PLLFBD<8:0>), provides a factor, `M', by which the input to the VCO is multiplied. This factor must be selected such that the resulting VCO output frequency is in the range of 100 MHz to 200 MHz. The VCO output is further divided by a postscale factor, `N2'. This factor is selected using the PLLPOST<1:0> bits (CLKDIV<7:6>). `N2' can be either 2, 4 or 8, and must be selected such that the PLL output frequency (FOSC) is in the range of 12.5 MHz to 80 MHz, which generates device operating speeds of 6.25-40 MIPS. For a primary oscillator or FRC oscillator, output `FIN', the PLL output `FOSC' is given by Equation 9-2. EQUATION 9-2: FOSC CALCULATION M ( N1*N2) FOSC = FIN * For example, suppose a 10 MHz crystal is being used with the selected oscillator mode of XT with PLL (see Equation 9-3). * If PLLPRE<4:0> = 0, then N1 = 2. This yields a VCO input of 10/2 = 5 MHz, which is within the acceptable range of 0.8-8 MHz. * If PLLDIV<8:0> = 0x1E, then M = 32. This yields a VCO output of 5 x 32 = 160 MHz, which is within the 100-200 MHz ranged needed. * If PLLPOST<1:0> = 0, then N2 = 2. This provides a FOSC of 160/2 = 80 MHz. The resultant device operating speed is 80/2 = 40 MIPS. EQUATION 9-3: FCY = FOSC 2 = 1 2 XT WITH PLL MODE EXAMPLE ( 10000000 * 32 ) = 40 MIPS 2*2 DS70591B-page 190 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 FIGURE 9-2: dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 PLL BLOCK DIAGRAM 0.8-8.0 MHz Here(1) Source (Crystal, External Clock or Internal RC) FVCO 100-200 MHz Here(1) VCO PLLDIV N1 Divide by 2-33 N2 Divide by 2, 4, 8 PLLPOST 12.5-80 MHz Here(1) FOSC PLLPRE X M Divide by 2-513 Note 1: This frequency range must be satisfied at all times. 9.2 Auxiliary Clock Generation The auxiliary clock generation is used for a peripherals that need to operate at a frequency unrelated to the system clock such as a PWM or ADC. Note: To achieve 1.04 ns PWM resolution, the auxiliary clock must be set up for 120 MHz. The primary oscillator and internal FRC oscillator sources can be used with an auxiliary PLL to obtain the auxiliary clock. The auxiliary PLL has a fixed 16x multiplication factor. Note: If the primary PLL is used as a source for the auxiliary clock, then the primary PLL should be configured up to a maximum operation of 30 MIPS or less. 9.3 Reference Clock Generation The reference clock output logic provides the user with the ability to output a clock signal based on the system clock or the crystal oscillator on a device pin. The user application can specify a wide range of clock scaling prior to outputting the reference clock. 2009 Microchip Technology Inc. Preliminary DS70591B-page 191 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 REGISTER 9-1: U-0 -- bit 15 R/W-0 CLKLOCK bit 7 Legend: R = Readable bit -n = Value at POR bit 15 bit 14-12 OSCCON: OSCILLATOR CONTROL REGISTER(1) R-y R-y COSC<2:0> R-y U-0 -- R/W-y R/W-y NOSC<2:0>(2) R/W-y bit 8 U-0 -- R-0 LOCK U-0 -- R/C-0 CF U-0 -- U-0 -- R/W-0 OSWEN bit 0 y = Value set from Configuration bits on POR W = Writable bit U = Unimplemented bit, read as `0' `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 11 bit 10-8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2-1 bit 0 Unimplemented: Read as `0' COSC<2:0>: Current Oscillator Selection bits (read-only) 000 = Fast RC oscillator (FRC) 001 = Fast RC oscillator (FRC) with PLL 010 = Primary oscillator (XT, HS, EC) 011 = Primary oscillator (XT, HS, EC) with PLL 100 = Secondary oscillator (SOSC) 101 = Low-Power RC oscillator (LPRC) 110 = Fast RC oscillator (FRC) with divide-by-16 111 = Fast RC oscillator (FRC) with divide-by-n Unimplemented: Read as `0' NOSC<2:0>: New Oscillator Selection bits(2) 000 = Fast RC oscillator (FRC) 001 = Fast RC oscillator (FRC) with PLL 010 = Primary oscillator (XT, HS, EC) 011 = Primary oscillator (XT, HS, EC) with PLL 100 = Secondary oscillator (SOSC) 101 = Low-Power RC oscillator (LPRC) 110 = Fast RC oscillator (FRC) with divide-by-16 111 = Fast RC oscillator (FRC) with divide-by-n CLKLOCK: Clock Lock Enable bit If clock switching is enabled and FSCM is disabled, (FOSC Note 1: Writes to this register require an unlock sequence. Refer to Section 42. "Oscillator (Part IV)" (DS70307) in the "dsPIC33F Family Reference Manual" (available from the Microchip web site) for details. 2: Direct clock switches between any primary oscillator mode with PLL and FRCPLL mode are not permitted. This applies to clock switches in either direction. In these instances, the application must switch to FRC mode as a transition clock source between the two PLL modes. DS70591B-page 192 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 REGISTER 9-2: R/W-0 ROI bit 15 R/W-0 bit 7 Legend: R = Readable bit -n = Value at POR bit 15 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-1 U-0 -- R/W-0 R/W-0 R/W-0 PLLPRE<4:0> bit 0 R/W-0 CLKDIV: CLOCK DIVISOR REGISTER R/W-0 R/W-1 DOZE<2:0> R/W-1 R/W-0 DOZEN (1) R/W-0 R/W-0 FRCDIV<2:0> R/W-0 bit 8 R/W-0 PLLPOST<1:0> ROI: Recover on Interrupt bit 1 = Interrupts will clear the DOZEN bit and the processor clock/peripheral clock ratio is set to 1:1 0 = Interrupts have no effect on the DOZEN bit DOZE<2:0>: Processor Clock Reduction Select bits 000 = FCY/1 001 = FCY/2 010 = FCY/4 011 = FCY/8 (default) 100 = FCY/16 101 = FCY/32 110 = FCY/64 111 = FCY/128 DOZEN: Doze Mode Enable bit(1) 1 = DOZE<2:0> field specifies the ratio between the peripheral clocks and the processor clocks 0 = Processor clock/peripheral clock ratio forced to 1:1 FRCDIV<2:0>: Internal Fast RC Oscillator Postscaler bits 000 = FRC divide by 1 (default) 001 = FRC divide by 2 010 = FRC divide by 4 011 = FRC divide by 8 100 = FRC divide by 16 101 = FRC divide by 32 110 = FRC divide by 64 111 = FRC divide by 256 PLLPOST<1:0>: PLL VCO Output Divider Select bits (also denoted as `N2', PLL postscaler) 00 = Output/2 01 = Output/4 (default) 10 = Reserved 11 = Output/8 Unimplemented: Read as `0' PLLPRE<4:0>: PLL Phase Detector Input Divider bits (also denoted as `N1', PLL prescaler) 00000 = Input/2 (default) 00001 = Input/3 * * * 11111 = Input/33 bit 14-12 bit 11 bit 10-8 bit 7-6 bit 5 bit 4-0 Note 1: This bit is cleared when the ROI bit is set and an interrupt occurs. 2009 Microchip Technology Inc. Preliminary DS70591B-page 193 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 REGISTER 9-3: U-0 -- bit 15 R/W-0 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-9 bit 8-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 R/W-1 R/W-1 R/W-0 R/W-0 R/W-0 PLLFBD: PLL FEEDBACK DIVISOR REGISTER U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- R/W-0 PLLDIV<8> bit 8 R/W-0 bit 0 PLLDIV<7:0> Unimplemented: Read as `0' PLLDIV<8:0>: PLL Feedback Divisor bits (also denoted as `M', PLL multiplier) 000000000 = 2 000000001 = 3 000000010 = 4 * * * 000110000 = 50 (default) * * * 111111111 = 513 DS70591B-page 194 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 REGISTER 9-4: U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-6 bit 5-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 OSCTUN: OSCILLATOR TUNING REGISTER U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 R/W-0 bit 0 TUN<5:0>(1) Unimplemented: Read as `0' TUN<5:0>: FRC Oscillator Tuning bits(1) 011111 = Center frequency + 11.625% (8.23 MHz) 011110 = Center frequency + 11.25% (8.20 MHz) * * * 000001 = Center frequency + 0.375% (7.40 MHz) 000000 = Center frequency (7.37 MHz nominal) 111111 = Center frequency -0.375% (7.345 MHz) * * * 100001 = Center frequency -11.625% (6.52 MHz) 100000 = Center frequency -12% (6.49 MHz) Note 1: OSCTUN functionality has been provided to help customers compensate for temperature effects on the FRC frequency over a wide range of temperatures. The tuning step size is an approximation and is neither characterized nor tested. 2009 Microchip Technology Inc. Preliminary DS70591B-page 195 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 REGISTER 9-5: R/W-0 ENAPLL bit 15 R/W-0 ASRCSEL bit 7 Legend: R = Readable bit -n = Value at POR bit 15 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 FRCSEL U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- ACLKCON: AUXILIARY CLOCK DIVISOR CONTROL REGISTER R-0 APLLCK R/W-1 SELACLK U-0 -- U-0 -- R/W-1 R/W-1 APSTSCLR<2:0> bit 0 U-0 -- R/W-1 ENAPLL: Auxiliary PLL Enable bit 1 = APLL is enabled 0 = APLL is disabled APLLCK: APLL Locked Status bit (read-only) 1 = Indicates that auxiliary PLL is in lock 0 = Indicates that auxiliary PLL is not in lock SELACLK: Select Auxiliary Clock Source for Auxiliary Clock Divider bit 1 = Auxiliary Oscillators provides the source clock for auxiliary clock divider 0 = Primary PLL (FVCO) provides the source clock for auxiliary clock divider Unimplemented: Read as `0' APSTSCLR<2:0>: Auxiliary Clock Output Divider bits 111 = Divided by 1 110 = Divided by 2 101 = Divided by 4 100 = Divided by 8 011 = Divided by 16 010 = Divided by 32 001 = Divided by 64 000 = Divided by 256 ASRCSEL: Select Reference Clock Source for Auxiliary Clock bit 1 = Primary oscillator is the clock source 0 = No clock input is selected FRCSEL: Select Reference Clock Source for Auxiliary PLL bit 1 = Select FRC clock for auxiliary PLL 0 = Input clock source is determined by ASRCSEL bit setting Unimplemented: Read as `0' bit 14 bit 13 bit 12-11 bit 10-8 bit 7 bit 6 bit 5-0 DS70591B-page 196 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 REGISTER 9-6: R/W-0 ROON bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- REFOCON: REFERENCE OSCILLATOR CONTROL REGISTER U-0 -- R/W-0 ROSSLP R/W-0 ROSEL R/W-0 R/W-0 R/W-0 R/W-0 bit 8 U-0 -- bit 0 RODIV<3:0>(1) ROON: Reference Oscillator Output Enable bit 1 = Reference oscillator output enabled on REFCLK0 pin 0 = Reference oscillator output disabled Unimplemented: Read as `0' ROSSLP: Reference Oscillator Run in Sleep bit 1 = Reference oscillator output continues to run in Sleep 0 = Reference oscillator output is disabled in Sleep ROSEL: Reference Oscillator Source Select bit 1 = Oscillator crystal used as the reference clock 0 = System clock used as the reference clock RODIV<3:0>: Reference Oscillator Divider bits(1) 1111 = Reference clock divided by 32,768 1110 = Reference clock divided by 16,384 1101 = Reference clock divided by 8,192 1100 = Reference clock divided by 4,096 1011 = Reference clock divided by 2,048 1010 = Reference clock divided by 1,024 1001 = Reference clock divided by 512 1000 = Reference clock divided by 256 0111 = Reference clock divided by 128 0110 = Reference clock divided by 64 0101 = Reference clock divided by 32 0100 = Reference clock divided by 16 0011 = Reference clock divided by 8 0010 = Reference clock divided by 4 0001 = Reference clock divided by 2 0000 = Reference clock Unimplemented: Read as `0' bit 14 bit 13 bit 12 bit 11-8 bit 7-0 Note 1: The reference oscillator output must be disabled (ROON = 0) before writing to these bits. 2009 Microchip Technology Inc. Preliminary DS70591B-page 197 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 9.4 Clock Switching Operation 2. and the clock switch is aborted. If a valid clock switch has been initiated, the LOCK (OSCCON<5>) and the CF (OSCCON<3>) Status bits are cleared. The new oscillator is turned on by the hardware if it is not currently running. If a crystal oscillator must be turned on, the hardware waits until the Oscillator Start-up Timer (OST) expires. If the new source is using the PLL, the hardware waits until a PLL lock is detected (LOCK = 1). The hardware waits for 10 clock cycles from the new clock source and then performs the clock switch. The hardware clears the OSWEN bit to indicate a successful clock transition. In addition, the NOSC bit values are transferred to the COSC Status bits. The old clock source is turned off at this time, with the exception of LPRC (if WDT or FSCM are enabled) or LP (if LPOSCEN remains set). Note 1: The processor continues to execute code throughout the clock switching sequence. Timing-sensitive code should not be executed during this time. 2: Direct clock switches between any primary oscillator mode with PLL and FRCPLL mode are not permitted. This applies to clock switches in either direction. In these instances, the application must switch to FRC mode as a transition clock source between the two PLL modes. 3: Refer to Section 42. "Oscillator (Part IV)" (DS70307) in the "dsPIC33F Family Reference Manual" for details. Applications are free to switch among any of the four clock sources (primary, LP, FRC and LPRC) under software control at any time. To limit the possible side effects of this flexibility, dsPIC33FJ32GS406/606/608/ 610 and DSPIC33FJ64GS406/606/608/610 devices have a safeguard lock built into the switch process. Note: Primary oscillator mode has three different submodes (XT, HS and EC), which are determined by the POSCMD<1:0> Configuration bits. While an application can switch to and from primary oscillator mode in software, it cannot switch among the different primary submodes without reprogramming the device. 3. 4. 5. 9.4.1 ENABLING CLOCK SWITCHING 6. To enable clock switching, the FCKSM1 Configuration bit in the Configuration register must be programmed to `0'. (Refer to Section 24.1 "Configuration Bits" for further details.) If the FCKSM1 Configuration bit is unprogrammed (`1'), the clock switching function and Fail-Safe Clock Monitor function are disabled. This is the default setting. The NOSC control bits (OSCCON<10:8>) do not control the clock selection when clock switching is disabled. However, the COSC bits (OSCCON<14:12>) reflect the clock source selected by the FNOSC Configuration bits. The OSWEN control bit (OSCCON<0>) has no effect when clock switching is disabled. It is held at `0' at all times. 9.4.2 OSCILLATOR SWITCHING SEQUENCE To perform a clock switch, the following basic sequence is required: 1. If desired, read the COSC bits (OSCCON<14:12>) to determine the current oscillator source. Perform the unlock sequence to allow a write to the OSCCON register high byte. Write the appropriate value to the NOSC control bits (OSCCON<10:8>) for the new oscillator source. Perform the unlock sequence to allow a write to the OSCCON register low byte. Set the OSWEN bit (OSCCON<0>) to initiate the oscillator switch. 9.5 Fail-Safe Clock Monitor (FSCM) 2. 3. The Fail-Safe Clock Monitor (FSCM) allows the device to continue to operate even in the event of an oscillator failure. The FSCM function is enabled by programming. If the FSCM function is enabled, the LPRC internal oscillator runs at all times (except during Sleep mode) and is not subject to control by the Watchdog Timer. In the event of an oscillator failure, the FSCM generates a clock failure trap event and switches the system clock over to the FRC oscillator. Then, the application program can either attempt to restart the oscillator or execute a controlled shutdown. The trap can be treated as a warm Reset by simply loading the Reset address into the oscillator fail trap vector. If the PLL multiplier is used to scale the system clock, the internal FRC is also multiplied by the same factor on clock failure. Essentially, the device switches to FRC with PLL on a clock failure. 4. 5. Once the basic sequence is completed, the system clock hardware responds automatically as follows: 1. The clock switching hardware compares the COSC Status bits with the new value of the NOSC control bits. If they are the same, the clock switch is a redundant operation. In this case, the OSWEN bit is cleared automatically DS70591B-page 198 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 10.0 POWER-SAVING FEATURES 10.2 Instruction-Based Power-Saving Modes Note 1: This data sheet summarizes the features of the dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 9. "Watchdog Timer and Power-Saving Modes" (DS70196) in the "dsPIC33F/PIC24H Family Reference Manual", which is available from the Microchip web site (www.microchip.com). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 "Memory Organization" in this data sheet for device-specific register and bit information. The dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 devices provide the ability to manage power consumption by selectively managing clocking to the CPU and the peripherals. In general, a lower clock frequency and a reduction in the number of circuits being clocked constitutes lower consumed power. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 devices can manage power consumption in four different ways: * * * * Clock Frequency Instruction-Based Sleep and Idle modes Software-Controlled Doze mode Selective Peripheral Control in Software The dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 devices have two special power-saving modes that are entered through the execution of a special PWRSAV instruction. Sleep mode stops clock operation and halts all code execution. Idle mode halts the CPU and code execution, but allows peripheral modules to continue operation. The assembler syntax of the PWRSAV instruction is shown in Example 10-1. Note: SLEEP_MODE and IDLE_MODE are constants defined in the assembler include file for the selected device. Sleep and Idle modes can be exited as a result of an enabled interrupt, WDT time-out or a device Reset. When the device exits these modes, it is said to wake-up. 10.2.1 SLEEP MODE The following occur in Sleep mode: * The system clock source is shut down. If an on-chip oscillator is used, it is turned off. * The device current consumption is reduced to a minimum, provided that no I/O pin is sourcing current. * The Fail-Safe Clock Monitor does not operate, since the system clock source is disabled. * The LPRC clock continues to run in Sleep mode if the WDT is enabled. * The WDT, if enabled, is automatically cleared prior to entering Sleep mode. * Some device features or peripherals may continue to operate. This includes the items such as the input change notification on the I/O ports or peripherals that use an external clock input. * Any peripheral that requires the system clock source for its operation is disabled. The device will wake-up from Sleep mode on any of these events: * Any interrupt source that is individually enabled * Any form of device Reset * A WDT time-out On wake-up from Sleep mode, the processor restarts with the same clock source that was active when Sleep mode was entered. Combinations of these methods can be used to selectively tailor an application's power consumption while still maintaining critical application features, such as timing-sensitive communications. 10.1 Clock Frequency and Clock Switching The dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 devices allow a wide range of clock frequencies to be selected under application control. If the system clock configuration is not locked, users can choose low-power or highprecision oscillators by simply changing the NOSC bits (OSCCON<10:8>). The process of changing a system clock during operation, as well as limitations to the process, are discussed in more detail in Section 9.0 "Oscillator Configuration". EXAMPLE 10-1: PWRSAV INSTRUCTION SYNTAX ; Put the device into SLEEP mode ; Put the device into IDLE mode PWRSAV #SLEEP_MODE PWRSAV #IDLE_MODE 2009 Microchip Technology Inc. Preliminary DS70591B-page 199 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 10.2.2 IDLE MODE Doze mode is enabled by setting the DOZEN bit (CLKDIV<11>). The ratio between peripheral and core clock speed is determined by the DOZE<2:0> bits (CLKDIV<14:12>). There are eight possible configurations, from 1:1 to 1:128, with 1:1 being the default setting. Programs can use Doze mode to selectively reduce power consumption in event-driven applications. This allows clock-sensitive functions, such as synchronous communications, to continue without interruption while the CPU idles, waiting for something to invoke an interrupt routine. An automatic return to full-speed CPU operation on interrupts can be enabled by setting the ROI bit (CLKDIV<15>). By default, interrupt events have no effect on Doze mode operation. For example, suppose the device is operating at 20 MIPS and the CAN module has been configured for 500 kbps based on this device operating speed. If the device is placed in Doze mode with a clock frequency ratio of 1:4, the CAN module continues to communicate at the required bit rate of 500 kbps, but the CPU now starts executing instructions at a frequency of 5 MIPS. The following occur in Idle mode: * The CPU stops executing instructions. * The WDT is automatically cleared. * The system clock source remains active. By default, all peripheral modules continue to operate normally from the system clock source, but can also be selectively disabled (see Section 10.5 "Peripheral Module Disable"). * If the WDT or FSCM is enabled, the LPRC also remains active. The device will wake-up from Idle mode on any of these events: * Any interrupt that is individually enabled * Any device Reset * A WDT time-out On wake-up from Idle mode, the clock is reapplied to the CPU and instruction execution will begin (2-4 clock cycles later), starting with the instruction following the PWRSAV instruction, or the first instruction in the ISR. 10.2.3 INTERRUPTS COINCIDENT WITH POWER SAVE INSTRUCTIONS 10.4 PWM Power-Saving Features Any interrupt that coincides with the execution of a PWRSAV instruction is held off until entry into Sleep or Idle mode has completed. The device then wakes up from Sleep or Idle mode. 10.3 Doze Mode Typically, many applications need either a high resolution duty cycle or phase offset (for fixed frequency operation) or a high resolution PWM period for variable frequency modes of operation (such as Resonant mode). Very few applications require both high resolution modes simultaneously. The HRPDIS and the HRDDIS bits in the AUXCONx registers permit the user to disable the circuitry associated with the high resolution duty cycle and PWM period to reduce the operating current of the device. If the HRDDIS bit is set, the circuitry associated with the high resolution duty cycle, phase offset, and dead time for the respective PWM generator is disabled. If the HRPDIS bit is set, the circuitry associated with the high resolution PWM period for the respective PWM generator is disabled. When the HRPDIS bit is set, the smallest unit of measure for the PWM period is 8.32 ns. If the HRDDIS bit is set, the smallest unit of measure for the PWM duty cycle, phase offset and dead time is 8.32 ns. The preferred strategies for reducing power consumption are changing clock speed and invoking one of the power-saving modes. In some circumstances, this may not be practical. For example, it may be necessary for an application to maintain uninterrupted synchronous communication, even while it is doing nothing else. Reducing system clock speed can introduce communication errors, while using a power-saving mode can stop communications completely. Doze mode is a simple and effective alternative method to reduce power consumption while the device is still executing code. In this mode, the system clock continues to operate from the same source and at the same speed. Peripheral modules continue to be clocked at the same speed, while the CPU clock speed is reduced. Synchronization between the two clock domains is maintained, allowing the peripherals to access the SFRs while the CPU executes code at a slower rate. DS70591B-page 200 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 10.5 Peripheral Module Disable The Peripheral Module Disable (PMD) registers provide a method to disable a peripheral module by stopping all clock sources supplied to that module. When a peripheral is disabled using the appropriate PMD control bit, the peripheral is in a minimum power consumption state. The control and STATUS registers associated with the peripheral are also disabled, so writes to those registers will have no effect and read values will be invalid. A peripheral module is enabled only if both the associated bit in the PMD register is cleared and the peripheral is supported by the specific dsPIC(R) DSC variant. If the peripheral is present in the device, it is enabled in the PMD register by default. Note: If a PMD bit is set, the corresponding module is disabled after a delay of one instruction cycle. Similarly, if a PMD bit is cleared, the corresponding module is enabled after a delay of one instruction cycle (assuming the module control registers are already configured to enable module operation). 2009 Microchip Technology Inc. Preliminary DS70591B-page 201 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 REGISTER 10-1: R/W-0 T5MD bit 15 R/W-0 I2C1MD bit 7 Legend: R = Readable bit -n = Value at POR bit 15 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 U2MD R/W-0 U1MD R/W-0 SPI2MD R/W-0 SPI1MD U-0 -- R/W-0 C1MD PMD1: PERIPHERAL MODULE DISABLE CONTROL REGISTER 1 R/W-0 T3MD R/W-0 T2MD R/W-0 T1MD R/W-0 QEI1MD R/W-0 PWMMD(1) U-0 -- bit 8 R/W-0 ADCMD bit 0 R/W-0 T4MD T5MD: Timer5 Module Disable bit 1 = Timer5 module is disabled 0 = Timer5 module is enabled T4MD: Timer4 Module Disable bit 1 = Timer4 module is disabled 0 = Timer4 module is enabled T3MD: Timer3 Module Disable bit 1 = Timer3 module is disabled 0 = Timer3 module is enabled T2MD: Timer2 Module Disable bit 1 = Timer2 module is disabled 0 = Timer2 module is enabled T1MD: Timer1 Module Disable bit 1 = Timer1 module is disabled 0 = Timer1 module is enabled QEI1MD: QEI1 Module Disable bit 1 = QEI1 module is disabled 0 = QEI1 module is enabled PWMMD: PWM Module Disable bit(1) 1 = PWM module is disabled 0 = PWM module is enabled Unimplemented: Read as `0' I2C1MD: I2C1 Module Disable bit 1 = I2C1 module is disabled 0 = I2C1 module is enabled U2MD: UART2 Module Disable bit 1 = UART2 module is disabled 0 = UART2 module is enabled U1MD: UART1 Module Disable bit 1 = UART1 module is disabled 0 = UART1 module is enabled SPI2MD: SPI2 Module Disable bit 1 = SPI2 module is disabled 0 = SPI2 module is enabled bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 Note 1: Once the PWM module is re-enabled (PWMMD is set to `1' and then set to `0'), all PWM registers must be reinitialized. DS70591B-page 202 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 REGISTER 10-1: bit 3 PMD1: PERIPHERAL MODULE DISABLE CONTROL REGISTER 1 (CONTINUED) SPI1MD: SPI1 Module Disable bit 1 = SPI1 module is disabled 0 = SPI1 module is enabled Unimplemented: Read as `0' C1MD: ECAN1 Module Disable bit 1 = ECAN1 module is disabled 0 = ECAN1 module is enabled ADCMD: ADC Module Disable bit 1 = ADC module is disabled 0 = ADC module is enabled bit 2 bit 1 bit 0 Note 1: Once the PWM module is re-enabled (PWMMD is set to `1' and then set to `0'), all PWM registers must be reinitialized. 2009 Microchip Technology Inc. Preliminary DS70591B-page 203 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 REGISTER 10-2: U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-12 bit 11 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- U-0 -- U-0 -- R/W-0 OC4MD R/W-0 OC3MD R/W-0 OC2MD PMD2: PERIPHERAL MODULE DISABLE CONTROL REGISTER 2 U-0 -- U-0 -- U-0 -- R/W-0 IC4MD R/W-0 IC3MD R/W-0 IC2MD R/W-0 IC1MD bit 8 R/W-0 OC1MD bit 0 Unimplemented: Read as `0' IC4MD: Input Capture 4 Module Disable bit 1 = Input Capture 4 module is disabled 0 = Input Capture 4 module is enabled IC3MD: Input Capture 3 Module Disable bit 1 = Input Capture 3 module is disabled 0 = Input Capture 3 module is enabled IC2MD: Input Capture 2 Module Disable bit 1 = Input Capture 2 module is disabled 0 = Input Capture 2 module is enabled IC1MD: Input Capture 1 Module Disable bit 1 = Input Capture 1 module is disabled 0 = Input Capture 1 module is enabled Unimplemented: Read as `0' OC4MD: Output Compare 4 Module Disable bit 1 = Output Compare 4 module is disabled 0 = Output Compare 4 module is enabled OC3MD: Output Compare 3 Module Disable bit 1 = Output Compare 3 module is disabled 0 = Output Compare 3 module is enabled OC2MD: Output Compare 2 Module Disable bit 1 = Output Compare 2 module is disabled 0 = Output Compare 2 module is enabled OC1MD: Output Compare 1 Module Disable bit 1 = Output Compare 1 module is disabled 0 = Output Compare 1 module is enabled bit 19 bit 9 bit 8 bit 7-4 bit 3 bit 2 bit 1 bit 0 DS70591B-page 204 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 REGISTER 10-3: U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-11 bit 10 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- R/W-0 QEI2MD U-0 -- U-0 -- U-0 -- R/W-0 I2C2MD U-0 -- bit 0 PMD3: PERIPHERAL MODULE DISABLE CONTROL REGISTER 3 U-0 -- U-0 -- U-0 -- U-0 -- R/W-0 CMPMD U-0 -- U-0 -- bit 8 Unimplemented: Read as `0' CMPMD: Analog Comparator Module Disable bit 1 = Analog Comparator module is disabled 0 = Analog Comparator module is enabled Unimplemented: Read as `0' QEI2MD: QEI2 Module Disable bit 1 = QEI2 module is disabled 0 = QEI2 module is enabled Unimplemented: Read as `0' I2C2MD: I2C2 Module Disable bit 1 = I2C2 module is disabled 0 = I2C2 module is enabled Unimplemented: Read as `0' bit 9-6 bit 5 bit 4-2 bit 1 bit 0 REGISTER 10-4: U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-4 bit 3 PMD4: PERIPHERAL MODULE DISABLE CONTROL REGISTER 4 U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 U-0 -- U-0 -- U-0 -- R/W-0 REFOMD U-0 -- U-0 -- U-0 -- bit 0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown Unimplemented: Read as `0' REFOMD: Reference Clock Generator Module Disable bit 1 = Reference clock generator module is disabled 0 = Reference clock generator module is enabled Unimplemented: Read as `0' bit 2-0 2009 Microchip Technology Inc. Preliminary DS70591B-page 205 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 REGISTER 10-5: R/W-0 PWM8MD bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 0 PMD6: PERIPHERAL MODULE DISABLE CONTROL REGISTER 6 R/W-0 PWM6MD R/W-0 PWM5MD R/W-0 PWM4MD R/W-0 PWM3MD R/W-0 PWM2MD R/W-0 PWM1MD bit 8 R/W-0 PWM7MD PWM8MD: PWM Generator 8 Module Disable bit 1 = PWM Generator 8 module is disabled 0 = PWM Generator 8 module is enabled PWM7MD: PWM Generator 7 Module Disable bit 1 = PWM Generator 7 module is disabled 0 = PWM Generator 7 module is enabled PWM6MD: PWM Generator 6 Module Disable bit 1 = PWM Generator 6 module is disabled 0 = PWM Generator 6 module is enabled PWM5MD: PWM Generator 5 Module Disable bit 1 = PWM Generator 5 module is disabled 0 = PWM Generator 5 module is enabled PWM4MD: PWM Generator 4 Module Disable bit 1 = PWM Generator 4 module is disabled 0 = PWM Generator 4 module is enabled PWM3MD: PWM Generator 3 Module Disable bit 1 = PWM Generator 3 module is disabled 0 = PWM Generator 3 module is enabled PWM2MD: PWM Generator 2 Module Disable bit 1 = PWM Generator 2 module is disabled 0 = PWM Generator 2 module is enabled PWM1MD: PWM Generator 1 Module Disable bit 1 = PWM Generator 1 module is disabled 0 = PWM Generator 1 module is enabled Unimplemented: Read as `0' bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7-0 DS70591B-page 206 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 REGISTER 10-6: U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-12 bit 11 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- PMD7: PERIPHERAL MODULE DISABLE CONTROL REGISTER 7 U-0 -- U-0 -- U-0 -- R/W-0 CMP4MD R/W-0 CMP3MD R/W-0 CMP2MD R/W-0 CMP1MD bit 8 R/W-0 PWM9MD bit 0 Unimplemented: Read as `0' CMP4MD: Analog Comparator 4 Module Disable bit 1 = Analog Comparator 4 module is disabled 0 = Analog Comparator 4 module is enabled CMP3MD: Analog Comparator 3 Module Disable bit 1 = Analog Comparator 3 module is disabled 0 = Analog Comparator 3 module is enabled CMP2MD: Analog Comparator 2 Module Disable bit 1 = Analog Comparator 2 module is disabled 0 = Analog Comparator 2 module is enabled CMP1MD: Analog Comparator 1 Module Disable bit 1 = Analog Comparator 1 module is disabled 0 = Analog Comparator 1 module is enabled Unimplemented: Read as `0' PWM9MD: PWM Generator 9 Module Disable bit 1 = PWM Generator 9 module is disabled 0 = PWM Generator 9 module is enabled bit 10 bit 9 bit 8 bit 7-1 bit 0 2009 Microchip Technology Inc. Preliminary DS70591B-page 207 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 NOTES: DS70591B-page 208 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 11.0 I/O PORTS has ownership of the output data and control signals of the I/O pin. The logic also prevents "loop through", in which a port's digital output can drive the input of a peripheral that shares the same pin. Figure 11-1 shows how ports are shared with other peripherals and the associated I/O pin to which they are connected. When a peripheral is enabled and the peripheral is actively driving an associated pin, the use of the pin as a general purpose output pin is disabled. The I/O pin can be read, but the output driver for the parallel port bit is disabled. If a peripheral is enabled, but the peripheral is not actively driving a pin, that pin can be driven by a port. All port pins have three registers directly associated with their operation as digital I/O. The data direction register (TRISx) determines whether the pin is an input or an output. If the data direction bit is `1', then the pin is an input. All port pins are defined as inputs after a Reset. Reads from the latch (LATx) read the latch. Writes to the latch write the latch. Reads from the port (PORTx) read the port pins, while writes to the port pins write the latch. Any bit and its associated data and control registers that are not valid for a particular device will be disabled. That means the corresponding LATx and TRISx registers and the port pin will read as zeros. When a pin is shared with another peripheral or function that is defined as an input only, it is nevertheless regarded as a dedicated port because there is no other competing source of outputs. Note 1: This data sheet summarizes the features of the dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 10. "I/O Ports" (DS70193) in the "dsPIC33F/PIC24H Family Reference Manual", which is available from the Microchip web site (www.microchip.com). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 "Memory Organization" in this data sheet for device-specific register and bit information. All of the device pins (except VDD, VSS, MCLR and OSC1/CLKI) are shared among the peripherals and the parallel I/O ports. All I/O input ports feature Schmitt Trigger inputs for improved noise immunity. 11.1 Parallel I/O (PIO) Ports Generally a parallel I/O port that shares a pin with a peripheral is subservient to the peripheral. The peripheral's output buffer data and control signals are provided to a pair of multiplexers. The multiplexers select whether the peripheral or the associated port FIGURE 11-1: BLOCK DIAGRAM OF A TYPICAL SHARED PORT STRUCTURE Peripheral Module Peripheral Input Data Peripheral Module Enable Peripheral Output Enable Peripheral Output Data 1 0 1 0 Output Enable Output Multiplexers I/O PIO Module Read TRIS Output Data Data Bus WR TRIS D CK Q I/O Pin TRIS Latch D WR LAT + WR PORT CK Data Latch Q Read LAT Input Data Read PORT 2009 Microchip Technology Inc. Preliminary DS70591B-page 209 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 11.2 Open-Drain Configuration 11.4 I/O Port Write/Read Timing In addition to the PORT, LAT and TRIS registers for data control, some digital-only port pins can also be individually configured for either digital or open-drain output. This is controlled by the Open-Drain Control register, ODCx, associated with each port. Setting any of the bits configures the corresponding pin to act as an open-drain output. The open-drain feature allows the generation of outputs higher than VDD (for example, 5V) on any desired 5V tolerant pins by using external pull-up resistors. The maximum open-drain voltage allowed is the same as the maximum VIH specification. Refer to "Pin Diagrams" for the available pins and their functionality. One instruction cycle is required between a port direction change or port write operation and a read operation of the same port. Typically, this instruction would be a NOP. An example is shown in Example 11-1. 11.5 Input Change Notification 11.3 Configuring Analog Port Pins The input change notification function of the I/O ports allows the dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 devices to generate interrupt requests to the processor in response to a Change-Of-State (COS) on selected input pins. This feature can detect input Change-Of-States even in Sleep mode, when the clocks are disabled. Depending on the device pin count, up to 30 external signals (CNx pin) can be selected (enabled) for generating an interrupt request on a Change-Of-State. Four control registers are associated with the CN module. The CNEN1 and CNEN2 registers contain the interrupt enable control bits for each of the CN input pins. Setting any of these bits enables a CN interrupt for the corresponding pins. Each CN pin also has a weak pull-up connected to it. The pull-ups act as a current source connected to the pin, and eliminate the need for external resistors when the push button or keypad devices are connected. The pull-ups are enabled separately using the CNPU1 and CNPU2 registers, which contain the control bits for each of the CN pins. Setting any of the control bits enables the weak pull-ups for the corresponding pins. Note: Pull-ups on change notification pins should always be disabled when the port pin is configured as a digital output. The ADPCFG and TRIS registers control the operation of the Analog-to-Digital (A/D) port pins. The port pins that are to function as analog inputs must have their corresponding TRIS bit set (input). If the TRIS bit is cleared (output), the digital output level (VOH or VOL) will be converted. The ADPCFG and ADPCFG2 registers have a default value of 0x000; therefore, all pins that share ANx functions are analog (not digital) by default. When the PORT register is read, all pins configured as analog input channels will read as cleared (a low level). Pins configured as digital inputs will not convert an analog input. Analog levels on any pin defined as a digital input (including the ANx pins) can cause the input buffer to consume current that exceeds the device specifications. EQUATION 11-1: MOV MOV NOP BTSS 0xFF00, W0 W0, TRISBB PORTB, #13 PORT WRITE/READ EXAMPLE ; ; ; ; Configure PORTB<15:8> as inputs and PORTB<7:0> as outputs Delay 1 cycle Next Instruction DS70591B-page 210 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 12.0 TIMER1 The unique features of Timer1 allow it to be used for Real-Time Clock (RTC) applications. A block diagram of Timer1 is shown in Figure 12-1. The Timer1 module can operate in one of the following modes: * * * * Timer mode Gated Timer mode Synchronous Counter mode Asynchronous Counter mode Note 1: This data sheet summarizes the features of the dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 11. "Timers" (DS70205) in the "dsPIC33F/PIC24H Family Reference Manual", which is available from the Microchip web site (www.microchip.com). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 "Memory Organization" in this data sheet for device-specific register and bit information. The Timer1 module is a 16-bit timer, which can serve as a time counter for the Real-Time Clock (RTC), or operate as a free-running interval timer/counter. The Timer1 module has the following unique features over other timers: * Can be operated from the low-power 32.767 kHz crystal oscillator available on the device * Can be operated in Asynchronous Counter mode from an external clock source. * The external clock input (T1CK) can optionally be synchronized to the internal device clock and the clock synchronization is performed after the prescaler. In Timer and Gated Timer modes, the input clock is derived from the internal instruction cycle clock (FCY). In Synchronous and Asynchronous Counter modes, the input clock is derived from the external clock input at the T1CK pin. The Timer modes are determined by the following bits: * Timer Clock Source Control bit (TCS): T1CON<1> * Timer Synchronization Control bit (TSYNC): T1CON<2> * Timer Gate Control bit (TGATE): T1CON<6> The timer control bit settings for different operating modes are given in the Table 12-1. TABLE 12-1: Mode Timer Gated Timer Synchronous Counter Asynchronous Counter TIMER MODE SETTINGS TCS 0 0 1 1 TGATE 0 1 x x TSYNC x x 1 0 FIGURE 12-1: 16-BIT TIMER1 MODULE BLOCK DIAGRAM Falling Edge Detect Gate Sync 1 Set T1IF Flag 0 FCY Prescaler (/n) 10 Reset TGATE TCKPS<1:0> 1 T1CK 00 TMR1 x1 Prescaler (/n) Sync 0 TGATE TCS PR1 Comparator Equal TSYNC TCKPS<1:0> 2009 Microchip Technology Inc. Preliminary DS70591B-page 211 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 REGISTER 12-1: R/W-0 TON bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 TGATE R/W-0 R/W-0 U-0 -- R/W-0 TSYNC R/W-0 TCS U-0 -- bit 0 T1CON: TIMER1 CONTROL REGISTER U-0 -- R/W-0 TSIDL U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 TCKPS<1:0> TON: Timer1 On bit 1 = Starts 16-bit Timer1 0 = Stops 16-bit Timer1 Unimplemented: Read as `0' TSIDL: Stop in Idle Mode bit 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode Unimplemented: Read as `0' TGATE: Timer1 Gated Time Accumulation Enable bit When T1CS = 1: This bit is ignored. When T1CS = 0: 1 = Gated time accumulation enabled 0 = Gated time accumulation disabled TCKPS<1:0> Timer1 Input Clock Prescale Select bits 11 = 1:256 10 = 1:64 01 = 1:8 00 = 1:1 Unimplemented: Read as `0' TSYNC: Timer1 External Clock Input Synchronization Select bit When TCS = 1: 1 = Synchronize external clock input 0 = Do not synchronize external clock input When TCS = 0: This bit is ignored. TCS: Timer1 Clock Source Select bit 1 = External clock from T1CK pin (on the rising edge) 0 = Internal clock (FCY) Unimplemented: Read as `0' bit 14 bit 13 bit 12-7 bit 6 bit 5-4 bit 3 bit 2 bit 1 bit 0 DS70591B-page 212 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 13.0 TIMER2/3/4/5 FEATURES * A Type B timer can be concatenated with a Type C timer to form a 32-bit timer * External clock input (TxCK) is always synchronized to the internal device clock and the clock synchronization is performed after the prescaler. Figure 13-1 shows a block diagram of the Type B timer. Timer3 and Timer5 are Type C timers that offer the following major features: * A Type C timer can be concatenated with a Type B timer to form a 32-bit timer * At least one Type C timer has the ability to trigger an A/D conversion. * The external clock input (TxCK) is always synchronized to the internal device clock and the clock synchronization is performed before the prescaler A block diagram of the Type C timer is shown in Figure 13-2. Note: Timer3 is not available on all devices. Note 1: This data sheet summarizes the features of the dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 11. "Timers" (DS70205) in the "dsPIC33F/PIC24H Family Reference Manual", which is available from the Microchip web site (www.microchip.com). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 "Memory Organization" in this data sheet for device-specific register and bit information. Timer2 and Timer4 are Type B timers that offer the following major features: FIGURE 13-1: TYPE B TIMER BLOCK DIAGRAM (x = 2, 4) Gate Sync FCY Falling Edge Detect 1 Set TxIF Flag Prescaler (/n) TCKPS<1:0> 10 Reset 0 00 TMRx TGATE Prescaler (/n) TxCK TCKPS<1:0> Sync x1 Comparator TGATE TCS PRx Equal FIGURE 13-2: TYPE C TIMER BLOCK DIAGRAM (x = 3, 5) Gate Sync Falling Edge Detect 1 Set TxIF Flag FCY Prescaler (/n) 10 TMRx Reset 0 TCKPS<1:0> Sync TxCK TCKPS<1:0> TGATE TCS Prescaler (/n) 00 TGATE x1 Comparator Equal ADC SOC Trigger PRx 2009 Microchip Technology Inc. Preliminary DS70591B-page 213 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 The Timer2/3/4/5 modules can operate in one of the following modes: * Timer mode * Gated Timer mode * Synchronous Counter mode In Timer and Gated Timer modes, the input clock is derived from the internal instruction cycle clock (FCY). In Synchronous Counter mode, the input clock is derived from the external clock input at the TxCK pin. The timer modes are determined by the following bits: * TCS (TxCON<1>): Timer Clock Source Control bit * TGATE (TxCON<6>): Timer Gate Control bit Timer control bit settings for different operating modes are given in the Table 13-1. When configured for 32-bit operation, only the Type B Timer Control (TxCON) register bits are required for setup and control while the Type C Timer Control register bits are ignored (except the TSIDL bit). For interrupt control, the combined 32-bit timer uses the interrupt enable, interrupt flag and interrupt priority control bits of the Type C timer. The interrupt control and status bits for the Type B timer are ignored during 32-bit timer operation. The timers that can be combined to form a 32-bit timer are listed in Table 13-2. TABLE 13-2: Timer2 32-BIT TIMER Type C Timer (msw) Timer3 Timer5 Type B Timer (lsw) TImer4 TABLE 13-1: Mode Timer Gated Timer TIMER MODE SETTINGS TCS 0 0 1 TGATE 0 1 x Synchronous Counter 13.1 16-Bit Operation A block diagram representation of the 32-bit timer module is shown in Figure 13-3. The 32-timer module can operate in one of the following modes: * Timer mode * Gated Timer mode * Synchronous Counter mode To configure the timer features for 32-bit operation: 1. 2. 3. 4. Set the T32 control bit. Select the prescaler ratio for Timer2 using the TCKPS<1:0> bits. Set the Clock and Gating modes using the corresponding TCS and TGATE bits. Load the timer period value. PR3 contains the most significant word of the value, while PR2 contains the least significant word. If interrupts are required, set the interrupt enable bit, T3IE. Use the priority bits, T3IP<2:0>, to set the interrupt priority. While Timer2 controls the timer, the interrupt appears as a Timer3 interrupt. Set the corresponding TON bit. To configure any of the timers for individual 16-bit operation: 1. 2. 3. 4. 5. Clear the T32 bit corresponding to that timer. Select the timer prescaler ratio using the TCKPS<1:0> bits. Set the Clock and Gating modes using the TCS and TGATE bits. Load the timer period value into the PRx register. If interrupts are required, set the interrupt enable bit, TxIE. Use the priority bits, TxIP<2:0>, to set the interrupt priority. Set the TON bit. 5. 6. 6. 13.2 32-Bit Operation A 32-bit timer module can be formed by combining a Type B and a Type C 16-bit timer module. For 32-bit timer operation, the T32 control bit in the Type B Timer Control (TxCON<3>) register must be set. The Type C timer holds the most significant word (msw) and the Type B timer holds the least significant word (lsw) for 32-bit operation. DS70591B-page 214 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 FIGURE 13-3: 32-BIT TIMER BLOCK DIAGRAM Gate Sync Falling Edge Detect PRx PRy 0 1 Set TyIF Flag Comparator FCY Prescaler (/n) 10 lsw 00 TMRx(1) msw TMRy(2) Equal TGATE Reset TCKPS<1:0> Prescaler (/n) Sync x1 TxCK TCKPS<1:0> TGATE TCS TMRyHLD Data Bus <15:0> Note 1: 2: Timerx is a Type B Timer (x = 2, 4). Timery is a Type C Timer (y = 3, 5). 2009 Microchip Technology Inc. Preliminary DS70591B-page 215 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 REGISTER 13-1: R/W-0 TON bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 TGATE R/W-0 R/W-0 R/W-0 T32 U-0 -- R/W-0 TCS U-0 -- bit 0 TxCON: TIMER CONTROL REGISTER (x = 2, 4) U-0 -- R/W-0 TSIDL U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 TCKPS<1:0> TON: Timerx On bit When T32 = 1 (in 32-Bit Timer mode): 1 = Starts 32-bit TMRx:TMRy timer pair 0 = Stops 32-bit TMRx:TMRy timer pair When T32 = 0 (in 16-Bit Timer mode): 1 = Starts 16-bit timer 0 = Stops 16-bit timer Unimplemented: Read as `0' TSIDL: Stop in Idle Mode bit 1 = Discontinue timer operation when device enters Idle mode 0 = Continue timer operation in Idle mode Unimplemented: Read as `0' TGATE: Timerx Gated Time Accumulation Enable bit When TCS = 1: This bit is ignored. When TCS = 0: 1 = Gated time accumulation enabled 0 = Gated time accumulation disabled TCKPS<1:0>: Timerx Input Clock Prescale Select bits 11 = 1:256 prescale value 10 = 1:64 prescale value 01 = 1:8 prescale value 00 = 1:1 prescale value T32: 32-Bit Timerx Mode Select bit 1 = TMRx and TMRy form a 32-bit timer 0 = TMRx and TMRy form separate 16-bit timer Unimplemented: Read as `0' TCS: Timerx Clock Source Select bit 1 = External clock from TxCK pin 0 = Internal clock (FOSC/2) Unimplemented: Read as `0' bit 14 bit 13 bit 12-7 bit 6 bit 5-4 bit 3 bit 2 bit 1 bit 0 DS70591B-page 216 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 REGISTER 13-2: R/W-0 TON(2) bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 TGATE(2) R/W-0 R/W-0 U-0 -- U-0 -- R/W-0 TCS(2) U-0 -- bit 0 TyCON: TIMER CONTROL REGISTER (y = 3, 5) U-0 -- R/W-0 TSIDL(1) U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 TCKPS<1:0>(2) TON: Timery On bit(2) 1 = Starts 16-bit Timery 0 = Stops 16-bit Timery Unimplemented: Read as `0' TSIDL: Stop in Idle Mode bit(1) 1 = Discontinue timer operation when device enters Idle mode 0 = Continue timer operation in Idle mode Unimplemented: Read as `0' TGATE: Timery Gated Time Accumulation Enable bit(2) When TCS = 1: This bit is ignored. When TCS = 0: 1 = Gated time accumulation enabled 0 = Gated time accumulation disabled TCKPS<1:0>: Timery Input Clock Prescale Select bits(2) 11 = 1:256 prescale value 10 = 1:64 prescale value 01 = 1:8 prescale value 00 = 1:1 prescale value Unimplemented: Read as `0' TCS: Timery Clock Source Select bit(2) 1 = External clock from TxCK pin 0 = Internal clock (FOSC/2) Unimplemented: Read as `0' When 32-bit timer operation is enabled (T32 = 1) in the Timer Control register (TxCON<3>), the TSIDL bit must be cleared to operate the 32-bit timer in Idle mode. When the 32-bit timer operation is enabled (T32 = 1) in the Timer Control (TxCON<3>) register, these bits have no effect. bit 14 bit 13 bit 12-7 bit 6 bit 5-4 bit 3-2 bit 1 bit 0 Note 1: 2: 2009 Microchip Technology Inc. Preliminary DS70591B-page 217 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 NOTES: DS70591B-page 218 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 14.0 INPUT CAPTURE * Simple Capture Event modes: - Capture timer value on every falling edge of input at ICx pin - Capture timer value on every rising edge of input at ICx pin * Capture timer value on every edge (rising and falling) * Prescaler Capture Event modes: - Capture timer value on every 4th rising edge of input at ICx pin - Capture timer value on every 16th rising edge of input at ICx pin Each input capture channel can select one of the two 16-bit timers (Timer2 or Timer3) for the time base. The selected timer can use either an internal or external clock. Other operational features include: * Device wake-up from capture pin during CPU Sleep and Idle modes * Interrupt on input capture event * 4-word FIFO buffer for capture values - Interrupt optionally generated after 1, 2, 3 or 4 buffer locations are filled * Use of input capture to provide additional sources of external interrupts Note 1: This data sheet summarizes the features of the dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 12. "Input Capture" (DS70198) in the "dsPIC33F/ PIC24H Family Reference Manual", which is available from the Microchip web site (www.microchip.com). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 "Memory Organization" in this data sheet for device-specific register and bit information. The input capture module is useful in applications requiring frequency (period) and pulse measurement. The dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 devices support up to two input capture channels. The input capture module captures the 16-bit value of the selected Time Base register when an event occurs at the ICx pin. The events that cause a capture event are listed below in three categories: FIGURE 14-1: INPUT CAPTURE BLOCK DIAGRAM From 16-Bit Timers TMR2 TMR3 16 16 ICTMR (ICxCON<7>) 1 Prescaler Counter (1, 4, 16) ICx Pin 3 Edge Detection Logic and Clock Synchronizer ICM<2:0> (ICxCON<2:0>) Mode Select ICOV, ICBNE (ICxCON<4:3>) FIFO R/W Logic 0 ICxBUF ICxI<1:0> ICxCON Interrupt Logic System Bus Set Flag ICxIF (in IFSx Register) Note 1: An `x' in a signal, register or bit name denotes the number of the capture channel. 2009 Microchip Technology Inc. Preliminary DS70591B-page 219 FIFO dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 14.1 Input Capture Registers ICxCON: INPUT CAPTURE x CONTROL REGISTER (x = 1, 2) U-0 -- R/W-0 ICSIDL U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 R/W-0 R/W-0 ICI<1:0> R-0, HC ICOV R-0, HC ICBNE R/W-0 R/W-0 ICM<2:0> bit 0 HC = Hardware Clearable bit W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 REGISTER 14-1: U-0 -- bit 15 R/W-0 ICTMR bit 7 Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13 Unimplemented: Read as `0' ICSIDL: Input Capture Module Stop in Idle Control bit 1 = Input capture module halts in CPU Idle mode 0 = Input capture module continues to operate in CPU Idle mode Unimplemented: Read as `0' ICTMR: Input Capture Timer Select bits 1 = TMR2 contents are captured on capture event 0 = TMR3 contents are captured on capture event ICI<1:0>: Select Number of Captures per Interrupt bits 11 = Interrupt on every fourth capture event 10 = Interrupt on every third capture event 01 = Interrupt on every second capture event 00 = Interrupt on every capture event ICOV: Input Capture Overflow Status Flag bit (read-only) 1 = Input capture overflow occurred 0 = No input capture overflow occurred ICBNE: Input Capture Buffer Empty Status bit (read-only) 1 = Input capture buffer is not empty, at least one more capture value can be read 0 = Input capture buffer is empty ICM<2:0>: Input Capture Mode Select bits 111 = Input capture functions as interrupt pin only when device is in Sleep or Idle mode. Rising edge detect-only, all other control bits are not applicable. 110 = Unused (module disabled) 101 = Capture mode, every 16th rising edge 100 = Capture mode, every 4th rising edge 011 = Capture mode, every rising edge 010 = Capture mode, every falling edge 001 = Capture mode, every edge (rising and falling). ICI<1:0> bits do not control interrupt generation for this mode. 000 = Input capture module turned off bit 12-8 bit 7 bit 6-5 bit 4 bit 3 bit 2-0 DS70591B-page 220 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 15.0 OUTPUT COMPARE The output compare module can select either Timer2 or Timer3 for its time base. The module compares the value of the timer with the value of one or two Compare registers depending on the operating mode selected. The state of the output pin changes when the timer value matches the Compare register value. The output compare module generates either a single output pulse, or a sequence of output pulses, by changing the state of the output pin on the compare match events. The output compare module can also generate interrupts on compare match events. The output compare module has multiple operating modes: * * * * * * * Active-Low One-Shot mode Active-High One-Shot mode Toggle mode Delayed One-Shot mode Continuous Pulse mode PWM mode without Fault Protection PWM mode with Fault Protection Note 1: This data sheet summarizes the features of the dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 13. "Output Compare" (DS70209) in the "dsPIC33F/ PIC24H Family Reference Manual", which is available from the Microchip web site (www.microchip.com). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 "Memory Organization" in this data sheet for device-specific register and bit information. FIGURE 15-1: OUTPUT COMPARE MODULE BLOCK DIAGRAM Set Flag bit OCxIF OCxRS OCxR Output Logic 3 SQ R Output Enable OCx Comparator 0 16 1 16 OCTSEL 0 1 OCM<2:0> Mode Select OCFA TMR2 TMR3 TMR2 Rollover TMR3 Rollover Note: An `x' in a signal, register or bit name denotes the number of the output compare channels. 2009 Microchip Technology Inc. Preliminary DS70591B-page 221 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 15.1 Output Compare Modes application must disable the associated timer when writing to the Output Compare Control registers to avoid malfunctions. Note: See Section 13. "Output Compare" in the "dsPIC33F/PIC24H Family Reference Manual" (DS7029) for OCxR and OCxRS register restrictions. Configure the Output Compare modes by setting the appropriate Output Compare Mode (OCM<2:0>) bits in the Output Compare Control (OCxCON<2:0>) register. Table 15-1 lists the different bit settings for the Output Compare modes. Figure 15-2 illustrates the output compare operation for various modes. The user TABLE 15-1: OCM<2:0> 000 001 010 011 100 101 110 111 OUTPUT COMPARE MODES Mode Module Disabled Active-Low One-Shot Active-High One-Shot Toggle Delayed One-Shot Continuous Pulse PWM without Fault Protection PWM with Fault Protection OCx Pin Initial State Controlled by GPIO register 0 1 Current output is maintained 0 0 `0', if OCxR is zero `1', if OCxR is non-zero `0', if OCxR is zero `1', if OCxR is non-zero OCx rising edge OCx falling edge OCx rising and falling edge OCx falling edge OCx falling edge No interrupt OCFA falling edge for OC1 to OC4 OCx Interrupt Generation -- FIGURE 15-2: OUTPUT COMPARE OPERATION Output Compare Mode Enabled Timer is Reset on Period Match OCxRS TMRy OCxR Active-Low One-Shot (OCM = 001) Active-High One-Shot (OCM = 010) Toggle (OCM = 011) Delayed One-Shot (OCM = 100) Continuous Pulse (OCM = 101) PWM (OCM = 110 or 111) DS70591B-page 222 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 REGISTER 15-1: U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13 HC = Hardware Clearable bit W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- U-0 -- R-0, HC OCFLT R/W-0 OCTSEL R/W-0 R/W-0 OCM<2:0> bit 0 OCxCON: OUTPUT COMPARE x CONTROL REGISTER (x = 1, 2) U-0 -- R/W-0 OCSIDL U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 R/W-0 Unimplemented: Read as `0' OCSIDL: Stop Output Compare in Idle Mode Control bit 1 = Output Compare x halts in CPU Idle mode 0 = Output Compare x continues to operate in CPU Idle mode Unimplemented: Read as `0' OCFLT: PWM Fault Condition Status bit 1 = PWM Fault condition has occurred (cleared in hardware only) 0 = No PWM Fault condition has occurred (this bit is only used when OCM<2:0> = 111) OCTSEL: Output Compare Timer Select bit 1 = Timer3 is the clock source for Compare x 0 = Timer2 is the clock source for Compare x OCM<2:0>: Output Compare Mode Select bits 111 = PWM mode on OCx, Fault pin enabled 110 = PWM mode on OCx, Fault pin disabled 101 = Initialize OCx pin low, generate continuous output pulses on OCx pin 100 = Initialize OCx pin low, generate single output pulse on OCx pin 011 = Compare event toggles OCx pin 010 = Initialize OCx pin high, compare event forces OCx pin low 001 = Initialize OCx pin low, compare event forces OCx pin high 000 = Output compare channel is disabled bit 12-5 bit 4 bit 3 bit 2-0 2009 Microchip Technology Inc. Preliminary DS70591B-page 223 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 NOTES: DS70591B-page 224 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 16.0 HIGH-SPEED PWM * Independent PWM frequency, duty cycle, and phase shift changes * Current compensation * Enhanced Leading-Edge Blanking (LEB) functionality * PWM Capture functionality Note: Duty cycle, dead-time, phase shift and frequency resolution is 8.32 ns in Center-Aligned PWM mode. Note 1: This data sheet summarizes the features of the dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 50. "High-Speed PWM" (DS70579) in the "dsPIC33F/ PIC24H Family Reference Manual", which is available from the Microchip web site (www.microchip.com). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 "Memory Organization" in this data sheet for device-specific register and bit information. The High-Speed PWM module on the dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 devices supports a wide variety of PWM modes and output formats. This PWM module is ideal for power conversion applications, such as: * * * * * * * AC/DC Converters DC/DC Converters Power Factor Correction Uninterruptible Power Supply (UPS) Inverters Battery Chargers Digital Lighting Figure 16-1 conceptualizes the PWM module in a simplified block diagram. Figure 16-2 illustrates how the module hardware is partitioned for each PWM output pair for the Complementary PWM mode. The PWM module contains nine PWM generators. The module has up to 18 PWM output pins: PWM1H, PWM1L, PWM2H, PWM2L, PWM3H, PWM3L, PWM4H, PWM4L, PWM5H, PWM5L, PWM6H, PWM6L, PWM7H, PWM7L, PWM8H, PWM8L, PWM9H, and PWM9L. For complementary outputs, these 18 I/O pins are grouped into H/L pairs. 16.2 Feature Description The PWM module is designed for applications that require: * High-resolution at high PWM frequencies * The ability to drive Standard, Edge-Aligned, Center-Aligned Complementary mode, and Push-Pull mode outputs * The ability to create multiphase PWM outputs For Center-Aligned mode, the duty cycle, period phase and dead-time resolutions will be 8.32 ns. Two common, medium power converter topologies are push-pull and half-bridge. These designs require the PWM output signal to be switched between alternate pins, as provided by the Push-Pull PWM mode. Phase-shifted PWM describes the situation where each PWM generator provides outputs, but the phase relationship between the generator outputs is specifiable and changeable. Multiphase PWM is often used to improve DC/DC converter load transient response, and reduce the size of output filter capacitors and inductors. Multiple DC/DC converters are often operated in parallel, but phase-shifted in time. A single PWM output operating at 250 kHz has a period of 4 s, but an array of four PWM channels, staggered by 1 s each, yields an effective switching frequency of 1 MHz. Multiphase PWM applications typically use a fixed-phase relationship. Variable phase PWM is useful in Zero Voltage Transition (ZVT) power converters. Here, the PWM duty cycle is always 50%, and the power flow is controlled by varying the relative phase shift between the two PWM generators. 16.1 Features Overview The High-Speed PWM module incorporates the following features: * * * * * * * * * * * * * * * Two master time base modules Up to nine PWM generators with up to 18 outputs Two PWM outputs per PWM generator Individual time base and duty cycle for each PWM output Duty cycle, dead time, phase shift, and frequency resolution of 1.04 ns at 40 MIPS Independent fault and current-limit inputs for eight PWM Outputs Redundant output True Independent output Center-Aligned PWM mode Output override control Chop mode (also known as Gated mode) Special Event Trigger Prescaler for input clock Dual trigger from PWM to Analog-to-Digital Converter (ADC) per PWM period PWMxL and PWMxH output pin swapping 2009 Microchip Technology Inc. Preliminary DS70591B-page 225 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 FIGURE 16-1: HIGH-SPEED PWM MODULE ARCHITECTURAL DIAGRAM SYNCIx Data Bus Primary and Secondary Master Time Base Synchronization Signal PWM1 Interrupt SYNCOx PWM1H PWM Generator 1 PWM1L Fault, Current-Limit and Dead Time Compensation Synchronization Signal PWM2 Interrupt PWM2H PWM Generator 2 PWM2L Fault, Current-Limit and Dead Time Compensation CPU PWM3 through PWM7 Synchronization Signal PWM8 Interrupt PWM8H PWM Generator 8 PWM8L Fault, Current-Limit and Dead Time Compensation Synchronization Signal PWM9 Interrupt PWM9H PWM Generator 9 PWM9L Primary Trigger ADC Module Secondary Trigger Special Event Trigger Fault and Current-Limit DS70591B-page 226 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 FIGURE 16-2: HIGH-SPEED PWM MODULE REGISTER INTERCONNECTION DIAGRAM PTCON, PTCON2 STCON, STCON2 Module Control and Timing SYNCI1 *** SYNCI4 PTPER SEVTCMP Special Event Compare Trigger SYNCO1 Comparator Comparator Special Event Postscaler Special Event Trigger Master Time Base Counter PMTMR Clock Prescaler Primary Master Time Base STPER SEVTCMP Special Event Compare Trigger SYNCO2 Comparator Comparator Special Event Postscaler Special Event Trigger Master Time Base Counter SMTMR Clock Prescaler Secondary Master Time Base MDC Synchronization Master Duty Cycle Register Master Duty Cycle PDCx MUX Master Period Comparator PWMCAPx PWM Generator 1 PWM Output Mode Control Logic User Override Logic Current-Limit Override Logic Fault Override Logic Dead Time Logic Pin Control Logic ADC Trigger PTMRx Comparator PHASEx SDCx MUX Comparator Interrupt Logic ADC Trigger TRIGx Secondary PWM 16-bit Data Bus PWM1H PWM1L Fault and Current-Limit Logic FLTn(1) Synchronization STMRx SPHASEx Master Duty Cycle Master Period PWMCONx Comparator STRIGx TRGCONx FLTCONx IOCONx ALTDTRx DTRx LEBCONx PWMxH PWM Generator 2 - PWM Generator 9 PWMxL FLTn(1) DTCMPx Note 1: n = 1 through 23. 2009 Microchip Technology Inc. Preliminary DS70591B-page 227 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 16.3 Control Registers The following registers control the operation of the High-Speed PWM module. * * * * * * * * * * * * * * * * * * * * * * * * * * PTCON: PWM Time Base Control Register PTCON2: PWM Clock Divider Select Register PTPER: Primary Master Time Base Period Register SEVTCMP: PWM Special Event Compare Register STCON: PWM Secondary Master Time Base Control Register STCON2: PWM Secondary Clock Divider Select Register STPER: Secondary Master Time Base Period Register SSEVTCMP: PWM Secondary Special Event Compare Register CHOP: PWM Chop Clock Generator Register MDC: PWM Master Duty Cycle Register PWMCONx: PWM Control Register PDCx: PWM Generator Duty Cycle Register PHASEx: PWM Primary Phase Shift Register DTRx: PWM Dead Time Register ALTDTRx: PWM Alternate Dead Time Register SDCx: PWM Secondary Duty Cycle Register SPHASEx: PWM Secondary Phase Shift Register TRGCONx: PWM Trigger Control Register IOCONx: PWM I/O Control Register FCLCONx: PWM Fault Current-Limit Control Register TRIGx: PWM Primary Trigger Compare Value Register STRIGx: PWM Secondary Trigger Compare Value Register LEBCONx: Leading-Edge Blanking Control Register LEBDLYx: Leading-Edge Blanking Delay Register AUXCONx: PWM Auxiliary Control Register PWMCAPx: Primary PWM Time Base Capture Register DS70591B-page 228 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 REGISTER 16-1: R/W-0 PTEN bit 15 R/W-0 SYNCEN bit 7 Legend: R = Readable bit -n = Value at POR bit 15 HC = Cleared in Hardware HS = Set in Hardware W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown (1) PTCON: PWM TIME BASE CONTROL REGISTER U-0 -- R/W-0 PTSIDL HS/HC-0 SESTAT R/W-0 SEIEN R/W-0 EIPU (1) R/W-0 SYNCPOL (1) R/W-0 SYNCOEN(1) bit 8 R/W-0 R/W-0 SYNCSRC<2:0> (1) R/W-0 R/W-0 R/W-0 R/W-0 (1) R/W-0 bit 0 SEVTPS<3:0> PTEN: PWM Module Enable bit 1 = PWM module is enabled 0 = PWM module is disabled Unimplemented: Read as `0' PTSIDL: PWM Time Base Stop in Idle Mode bit 1 = PWM time base halts in CPU Idle mode 0 = PWM time base runs in CPU Idle mode SESTAT: Special Event Interrupt Status bit 1 = Special Event Interrupt is pending 0 = Special Event Interrupt is not pending SEIEN: Special Event Interrupt Enable bit 1 = Special Event Interrupt is enabled 0 = Special Event Interrupt is disabled EIPU: Enable Immediate Period Updates bit(1) 1 = Active Period register is updated immediately 0 = Active Period register updates occur on PWM cycle boundaries SYNCPOL: Synchronize Input and Output Polarity bit(1) 1 = SYNCIx/SYNCO1 polarity is inverted (active-low) 0 = SYNCIx/SYNCO1 is active-high SYNCOEN: Primary Time Base Sync Enable bit(1) 1 = SYNCO1 output is enabled 0 = SYNCO1 output is disabled SYNCEN: External Time Base Synchronization Enable bit(1) 1 = External synchronization of primary time base is enabled 0 = External synchronization of primary time base is disabled SYNCSRC<2:0>: Synchronous Source Selection bits(1) 000 = SYNCI1 001 = SYNCI2 010 = SYNCI3 011 = SYNCI4 100 = Reserved 101 = Reserved 111 = Reserved bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6-4 Note 1: These bits should be changed only when PTEN = 0. In addition, when using the SYNCIx feature, the user application must program the period register with a value that is slightly larger than the expected period of the external synchronization input signal. 2009 Microchip Technology Inc. Preliminary DS70591B-page 229 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 REGISTER 16-1: bit 3-0 PTCON: PWM TIME BASE CONTROL REGISTER (CONTINUED) SEVTPS<3:0>: PWM Special Event Trigger Output Postscaler Select bits(1) 1111 = 1:16 Postscaler generates Special Event Trigger on every sixteenth compare match event * * * 0001 = 1:2 Postscaler generates Special Event Trigger on every second compare match event 0000 = 1:1 Postscaler generates Special Event Trigger on every compare match event Note 1: These bits should be changed only when PTEN = 0. In addition, when using the SYNCIx feature, the user application must program the period register with a value that is slightly larger than the expected period of the external synchronization input signal. DS70591B-page 230 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 REGISTER 16-2: U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-3 bit 2-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- U-0 -- U-0 -- U-0 -- R/W-0 R/W-0 PCLKDIV<2:0> (1) PTCON2: PWM CLOCK DIVIDER SELECT REGISTER U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 R/W-0 bit 0 Unimplemented: Read as `0' PCLKDIV<2:0>: PWM Input Clock Prescaler (Divider) Select bits(1) 111 = Reserved 110 = Divide by 64, maximum PWM timing resolution 101 = Divide by 32, maximum PWM timing resolution 100 = Divide by 16, maximum PWM timing resolution 011 = Divide by 8, maximum PWM timing resolution 010 = Divide by 4, maximum PWM timing resolution 001 = Divide by 2, maximum PWM timing resolution 000 = Divide by 1, maximum PWM timing resolution (power-on default) Note 1: These bits should be changed only when PTEN = 0. Changing the clock selection during operation will yield unpredictable results. REGISTER 16-3: R/W-1 bit 15 R/W-1 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-0 PTPER: PRIMARY MASTER TIME BASE PERIOD REGISTER R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 bit 8 R/W-1 R/W-1 R/W-1 R/W-1 R/W-0 R/W-0 R/W-0 bit 0 PTPER<15:8> PTPER<7:0> W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown PTPER<15:0>: Primary Master Time Base (PMTMR) Period Value bits Note: The PWM time base has a minimum value of 0x0010, and a maximum value of 0xFFF8. 2009 Microchip Technology Inc. Preliminary DS70591B-page 231 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 REGISTER 16-4: R/W-0 bit 15 R/W-0 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-3 bit 2-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 R/W-0 SEVTCMP<7:3> R/W-0 R/W-0 U-0 -- U-0 -- U-0 -- bit 0 SEVTCMP: PWM SPECIAL EVENT COMPARE REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 bit 8 SEVTCMP<15:8> SEVTCMP<15:3>: Special Event Compare Count Value bits Unimplemented: Read as `0' DS70591B-page 232 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 REGISTER 16-5: U-0 -- bit 15 R/W-0 SYNCEN bit 7 Legend: R = Readable bit -n = Value at POR bit 15-13 bit 12 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 R/W-0 SYNCSRC<2:0> R/W-0 R/W-0 R/W-0 R/W-0 STCON: PWM SECONDARY MASTER TIME BASE CONTROL REGISTER U-0 -- U-0 -- HS/HC-0 SESTAT R/W-0 SEIEN R/W-0 EIPU (1) R/W-0 SYNCPOL R/W-0 SYNCOEN bit 8 R/W-0 bit 0 SEVTPS<3:0> Unimplemented: Read as `0' SESTAT: Special Event Interrupt Status bit 1 = Secondary Special Event Interrupt is pending 0 = Secondary Special Event Interrupt is not pending SEIEN: Special Event Interrupt Enable bit 1 = Secondary Special Event Interrupt is enabled 0 = Secondary Special Event Interrupt is disabled EIPU: Enable Immediate Period Updates bit(1) 1 = Active Secondary Period register is updated immediately 0 = Active Secondary Period register updates occur on PWM cycle boundries SYNCPOL: Synchronize Input and Output Polarity bit 1 = SYNCIx/SYNCO2 polarity is inverted (active-low) 0 = SYNCIx/SYNCO2 polarity is active-high SYNCOEN: Secondary Master Time Base Sync Enable bit 1 = SYNCO2 output is enabled. 0 = SYNCO2 output is disabled SYNCEN: External Secondary Master Time Base Synchronization Enable bit 1 = External synchronization of secondary time base is enabled 0 = External synchronization of secondary time base is disabled SYNCSRC<2:0>: Secondary Time Base Sync Source Selection bits 000 = SYNCI1 001 = SYNCI2 010 = SYNCI3 011 = SYNCI4 100 = Reserved 101 = Reserved 111 = Reserved SEVTPS<3:0>: PWM Secondary Special Event Trigger Output Postscaler Select bits 1111 = 1:16 Postcale 0001 = 1:2 Postcale * * * 0000 = 1:1 Postscale bit 11 bit 10 bit 9 bit 8 bit 7 bit 6-4 bit 3-0 Note 1: This bit only applies to the secondary master time base period. 2009 Microchip Technology Inc. Preliminary DS70591B-page 233 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 REGISTER 16-6: U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-3 bit 2-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- U-0 -- U-0 -- U-0 -- R/W-0 R/W-0 PCLKDIV<2:0>(1) bit 0 STCON2: PWM SECONDARY CLOCK DIVIDER SELECT REGISTER U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 R/W-0 Unimplemented: Read as `0' PCLKDIV<2:0>: PWM Input Clock Prescaler (Divider) Select bits(1) 111 = Reserved 110 = Divide by 64, maximum PWM timing resolution 101 = Divide by 32, maximum PWM timing resolution 100 = Divide by 16, maximum PWM timing resolution 011 = Divide by 8, maximum PWM timing resolution 010 = Divide by 4, maximum PWM timing resolution 001 = Divide by 2, maximum PWM timing resolution 000 = Divide by 1, maximum PWM timing resolution (power-on default) Note 1: These bits should be changed only when PTEN = 0. Changing the clock selection during operation will yield unpredictable results. REGISTER 16-7: R/W-1 bit 15 R/W-1 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-0 STPER: SECONDARY MASTER TIME BASE PERIOD REGISTER R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 bit 8 R/W-1 R/W-1 R/W-1 R/W-1 R/W-0 R/W-0 R/W-0 bit 0 STPER<15:8> STPER<7:0> W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown STPER<15:0>: Secondary Master Time Base (SMTMR) Period Value bits DS70591B-page 234 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 REGISTER 16-8: R/W-0 bit 15 R/W-0 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-3 bit 2-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 R/W-0 SSEVTCMP<7:3> R/W-0 R/W-0 U-0 -- U-0 -- U-0 -- bit 0 SSEVTCMP: PWM SECONDARY SPECIAL EVENT COMPARE REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 bit 8 SSEVTCMP<15:8> SSEVTCMP<15:3>: Special Event Compare Count Value bits Unimplemented: Read as `0' REGISTER 16-9: R/W-0 CHPCLKEN bit 15 R/W-0 bit 7 Legend: R = Readable bit -n = Value at POR bit 15 CHOP: PWM CHOP CLOCK GENERATOR REGISTER U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- R/W-0 R/W-0 bit 8 R/W-0 R/W-0 CHOP<7:3> R/W-0 R/W-0 U-0 -- U-0 -- U-0 -- bit 0 CHOP<9:8> W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown CHPCLKEN: Enable Chop Clock Generator bit 1 = Chop clock generator is enabled 0 = Chop clock generator is disabled Unimplemented: Read as `0' CHOP<9:3>: Chop Clock Divider bits Value in 8.32 ns increments. The frequency of the chop clock signal is given by the following expression: Chop Frequency = 1/(16.64 * (CHOP<7:3> + 1) * Primary Master PWM Input Clock Period) bit 14-10 bit 9-3 Note: The chop clock generator operates with the primary PWM clock prescaler (PCLKDIVL<2:0>) in the PTCON2 register. 2009 Microchip Technology Inc. Preliminary DS70591B-page 235 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 REGISTER 16-10: MDC: PWM MASTER DUTY CYCLE REGISTER R/W-0 bit 15 R/W-0 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 bit 8 R/W-0 bit 0 MDC<15:8> MDC<7:0> MDC<15:0>: Master PWM Duty Cycle Value bits Note 1: The smallest pulse width that can be generated on the PWM output corresponds to a value of 0x0009, while the maximum pulse width generated corresponds to a value of Period - 0x0008. 2: As the Duty Cycle gets closer to 0% or 100% of the PWM Period (0 to 40 ns, depending on the mode of operation), PWM Duty Cycle resolution will increase from 1 to 3 LSBs. DS70591B-page 236 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 REGISTER 16-11: PWMCONx: PWM CONTROL REGISTER HS/HC-0 FLTSTAT bit 15 R/W-0 bit 7 Legend: R = Readable bit -n = Value at POR bit 15 HC = Cleared in Hardware HS = Set in Hardware W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 R/W-0 DTCP (4) (1) HS/HC-0 CLSTAT (1) HS/HC-0 TRGSTAT R/W-0 FLTIEN R/W-0 CLIEN R/W-0 TRGIEN R/W-0 ITB (3) R/W-0 MDCS(3) bit 8 U-0 -- R/W-0 MTBS R/W-0 CAM (2,3) R/W-0 XPRES (5) R/W-0 IUE bit 0 DTC<1:0> FLTSTAT: Fault Interrupt Status bit(1) 1 = Fault interrupt is pending 0 = No Fault interrupt is pending This bit is cleared by setting FLTIEN = 0. CLSTAT: Current-Limit Interrupt Status bit(1) 1 = Current-limit interrupt is pending 0 = No current-limit interrupt is pending This bit is cleared by setting CLIEN = 0. TRGSTAT: Trigger Interrupt Status bit 1 = Trigger interrupt is pending 0 = No trigger interrupt is pending This bit is cleared by setting TRGIEN = 0. FLTIEN: Fault Interrupt Enable bit 1 = Fault interrupt is enabled 0 = Fault interrupt is disabled and FLTSTAT bit is cleared CLIEN: Current-Limit Interrupt Enable bit 1 = Current-limit interrupt enabled 0 = Current-limit interrupt disabled and CLSTAT bit is cleared TRGIEN: Trigger Interrupt Enable bit 1 = A trigger event generates an interrupt request 0 = Trigger event interrupts are disabled and TRGSTAT bit is cleared ITB: Independent Time Base Mode bit(3) 1 = PHASEx/SPHASEx registers provide time base period for this PWM generator 0 = PTPER register provides timing for this PWM generator MDCS: Master Duty Cycle Register Select bit(3) 1 = MDC register provides duty cycle information for this PWM generator 0 = PDCx and SDCx registers provide duty cycle information for this PWM generator bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 Note 1: Software must clear the interrupt status here, and in the corresponding IFS bit in the Interrupt Controller. 2: The Independent Time Base mode (ITB = 1) must be enabled to use Center-Aligned mode. If ITB = 0, the CAM bit is ignored. 3: These bits should not be changed after the PWM is enabled (PTEN = 1). 4: For DTCP to be effective, DTC<1:0> must be set to `11'; otherwise, DTCP is ignored. 5: To operate in External Period Reset mode, configure FCLCONx 2009 Microchip Technology Inc. Preliminary DS70591B-page 237 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 REGISTER 16-11: PWMCONx: PWM CONTROL REGISTER (CONTINUED) bit 7-6 DTC<1:0>: Dead Time Control bits 11 = Dead Time Compensation mode 10 = Dead time function is disabled 01 = Negative dead time actively applied for Complementary Output mode 00 = Positive dead time actively applied for all output modes DTCP: Dead Time Compensation Polarity bit(4) 1 = If DTCMPx = 0, PWMxL is shortened, and PWMxH is lengthened If DTCMPx = 1, PWMxH is shortened, and PWMxL is lengthened 0 = If DTCMPx = 0, PWMxH is shortened, and PWMLx is lengthened If DTCMPx = 1, PWMxL is shortened, and PWMxH is lengthened Unimplemented: Read as `0' MTBS: Master Time Base Select bit 1 = PWM generator uses the secondary master time base for synchronization and the clock source for the PWM generation logic (if secondary time base is available) 0 = PWM generator uses the primary master time base for synchronization and the clock source for the PWM generation logic CAM: Center-Aligned Mode Enable bit(2,3) 1 = Center-Aligned mode is enabled 0 = Edge-Aligned mode is enabled XPRES: External PWM Reset Control bit(5) 1 = Current-limit source resets the time base for this PWM generator if it is in Independent Time Base mode 0 = External pins do not affect PWM time base IUE: Immediate Update Enable bit 1 = Updates to the active MDC/PDCx/SDCx registers are immediate 0 = Updates to the active PDCx registers are synchronized to the PWM time base bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Note 1: Software must clear the interrupt status here, and in the corresponding IFS bit in the Interrupt Controller. 2: The Independent Time Base mode (ITB = 1) must be enabled to use Center-Aligned mode. If ITB = 0, the CAM bit is ignored. 3: These bits should not be changed after the PWM is enabled (PTEN = 1). 4: For DTCP to be effective, DTC<1:0> must be set to `11'; otherwise, DTCP is ignored. 5: To operate in External Period Reset mode, configure FCLCONx DS70591B-page 238 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 REGISTER 16-12: PDCx: PWM GENERATOR DUTY CYCLE REGISTER R/W-0 bit 15 R/W-0 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 bit 8 R/W-0 bit 0 PDCx<15:8> PDCx<7:0> PDCx<15:0>: PWM Generator # Duty Cycle Value bits Note 1: In Independent PWM mode, the PDCx register controls the PWMxH duty cycle only. In the Complementary, Redundant and Push-Pull PWM modes, the PDCx register controls the duty cycle of both the PWMxH and PWMxL. 2: The smallest pulse width that can be generated on the PWM output corresponds to a value of 0x0009, while the maximum pulse width generated corresponds to a value of Period - 0x0008. 3: As the Duty Cycle gets closer to 0% or 100% of the PWM Period (0 to 40 ns, depending on the mode of operation), PWM Duty Cycle resolution will increase from 1 to 3 LSBs. REGISTER 16-13: SDCx: PWM SECONDARY DUTY CYCLE REGISTER R/W-0 bit 15 R/W-0 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 bit 8 R/W-0 bit 0 SDCx<15:8> SDCx<7:0> SDCx<15:0>: Secondary Duty Cycle bits for PWMxL Output Pin Note 1: The SDCx register is used in Independent PWM mode only. When used in Independent PWM mode, the SDCx register controls the PWMxL duty cycle. 2: The smallest pulse width that can be generated on the PWM output corresponds to a value of 0x0009, while the maximum pulse width generated corresponds to a value of Period - 0x0008. 3: As the Duty Cycle gets closer to 0% or 100% of the PWM Period (0 to 40 ns, depending on the mode of operation), PWM Duty Cycle resolution will increase from 1 to 3 LSBs. 2009 Microchip Technology Inc. Preliminary DS70591B-page 239 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 REGISTER 16-14: PHASEx: PWM PRIMARY PHASE SHIFT REGISTER R/W-0 bit 15 R/W-0 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 bit 8 R/W-0 bit 0 PHASEx<15:8> PHASEx<7:0> PHASEx<15:0>: PWM Phase Shift Value or Independent Time Base Period bits for the PWM Generator Note 1: If PWMCONx DS70591B-page 240 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 REGISTER 16-15: SPHASEx: PWM SECONDARY PHASE SHIFT REGISTER R/W-0 bit 15 R/W-0 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 bit 8 R/W-0 bit 0 SPHASEx<15:8> SPHASEx<7:0> SPHASEx<15:0>: Secondary Phase Offset bits for PWMxL Output Pin (used in Independent PWM mode only) Note 1: If PWMCONx 2009 Microchip Technology Inc. Preliminary DS70591B-page 241 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 REGISTER 16-16: DTRx: PWM DEAD TIME REGISTER U-0 -- bit 15 R/W-0 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 -- R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 bit 8 R/W-0 bit 0 DTRx<13:8> DTRx<7:0> Unimplemented: Read as `0' DTRx<13:0>: Unsigned 14-bit Dead Time Value bits for PWMx Dead Time Unit REGISTER 16-17: ALTDTRx: PWM ALTERNATE DEAD TIME REGISTER U-0 -- bit 15 R/W-0 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 -- R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 bit 8 R/W-0 bit 0 ALTDTRx<13:8> ALTDTRx<7:0> Unimplemented: Read as `0' ALTDTRx<13:0>: Unsigned 14-bit Dead Time Value bits for PWMx Dead Time Unit DS70591B-page 242 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 REGISTER 16-18: TRGCONx: PWM TRIGGER CONTROL REGISTER R/W-0 bit 15 R/W-0 DTM bit 7 Legend: R = Readable bit -n = Value at POR bit 15-12 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown (1) R/W-0 R/W-0 R/W-0 U-0 -- U-0 -- U-0 -- U-0 -- bit 8 TRGDIV<3:0> U-0 -- R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 bit 0 TRGSTRT<5:0> TRGDIV<3:0>: Trigger # Output Divider bits 1111 = Trigger output for every 16th trigger event 1110 = Trigger output for every 15th trigger event 1101 = Trigger output for every 14th trigger event 1100 = Trigger output for every 13th trigger event 1011 = Trigger output for every 12th trigger event 1010 = Trigger output for every 11th trigger event 1001 = Trigger output for every 10th trigger event 1000 = Trigger output for every 9th trigger event 0111 = Trigger output for every 8th trigger event 0110 = Trigger output for every 7th trigger event 0101 = Trigger output for every 6th trigger event 0100 = Trigger output for every 5th trigger event 0011 = Trigger output for every 4th trigger event 0010 = Trigger output for every 3rd trigger event 0001 = Trigger output for every 2nd trigger event 0000 = Trigger output for every trigger event Unimplemented: Read as `0' DTM: Dual Trigger Mode bit(1) 1 = Secondary trigger event is combined with the primary trigger event to create PWM trigger 0 = Secondary trigger event is not combined with the primary trigger event to create PWM trigger. Two separate PWM triggers are generated. Unimplemented: Read as `0' TRGSTRT<5:0>: Trigger Postscaler Start Enable Select bits 111111 = Wait 63 PWM cycles before generating the first trigger event after the module is enabled * * * 000010 = Wait 2 PWM cycles before generating the first trigger event after the module is enabled 000001 = Wait 1 PWM cycles before generating the first trigger event after the module is enabled 000000 = Wait 0 PWM cycles before generating the first trigger event after the module is enabled The secondary PWM generator cannot generate PWM trigger interrupts. bit 11-8 bit 7 bit 6 bit 5-0 Note 1: 2009 Microchip Technology Inc. Preliminary DS70591B-page 243 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 REGISTER 16-19: IOCONx: PWM I/O CONTROL REGISTER R/W-0 PENH bit 15 R/W-0 bit 7 Legend: R = Readable bit -n = Value at POR bit 15 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SWAP R/W-0 PENL R/W-0 POLH R/W-0 POLL R/W-0 R/W-0 R/W-0 OVRENH R/W-0 OVRENL bit 8 R/W-0 OSYNC bit 0 PMOD<1:0>(1) OVRDAT<1:0> FLTDAT<1:0> CLDAT<1:0> PENH: PWMxH Output Pin Ownership bit 1 = PWM module controls PWMxH pin 0 = GPIO module controls PWMxH pin PENL: PWMxL Output Pin Ownership bit 1 = PWM module controls PWMxL pin 0 = GPIO module controls PWMxL pin POLH: PWMxH Output Pin Polarity bit 1 = PWMxH pin is active-low 0 = PWMxH pin is active-high POLL: PWMxL Output Pin Polarity bit 1 = PWMxL pin is active-low 0 = PWMxL pin is active-high PMOD<1:0>: PWM # I/O Pin Mode bits(1) 11 = PWM I/O pin pair is in the True Independent Output mode 10 = PWM I/O pin pair is in the Push-Pull Output mode 01 = PWM I/O pin pair is in the Redundant Output mode 00 = PWM I/O pin pair is in the Complementary Output mode OVRENH: Override Enable for PWMxH Pin bit 1 = OVRDAT<1> provides data for output on PWMxH pin 0 = PWM generator provides data for PWMxH pin OVRENL: Override Enable for PWMxL Pin bit 1 = OVRDAT<0> provides data for output on PWMxL pin 0 = PWM generator provides data for PWMxL pin OVRDAT<1:0>: Data for PWMxH, PWMxL Pins if Override is Enabled bits If OVERENH = 1, OVRDAT<1> provides data for PWMxH If OVERENL = 1, OVRDAT<0> provides data for PWMxL FLTDAT<1:0>: State(2) for PWMxH and PWMxL Pins if FLTMOD is Enabled bits FCLCONx bit 14 bit 13 bit 12 bit 11-10 bit 9 bit 8 bit 7-6 bit 5-4 Note 1: These bits should not be changed after the PWM module is enabled (PTEN = 1). 2: State represents the active/inactive state of the PWM depending on the POLH and POLL bit settings. DS70591B-page 244 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 REGISTER 16-19: IOCONx: PWM I/O CONTROL REGISTER (CONTINUED) bit 3-2 CLDAT<1:0>: State(2) for PWMxH and PWMxL Pins if CLMOD is Enabled bits FCLCONx bit 0 Note 1: These bits should not be changed after the PWM module is enabled (PTEN = 1). 2: State represents the active/inactive state of the PWM depending on the POLH and POLL bit settings. 2009 Microchip Technology Inc. Preliminary DS70591B-page 245 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 REGISTER 16-20: TRIGx: PWM PRIMARY TRIGGER COMPARE VALUE REGISTER R/W-0 bit 15 R/W-0 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-3 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 R/W-0 TRGCMP<7:3> R/W-0 R/W-0 U-0 -- U-0 -- U-0 -- bit 0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 bit 8 TRGCMP<15:8> TRGCMP<15:3>: Trigger Compare Value bits When the primary PWM functions in local time base, this register contains the compare values that can trigger the ADC module. Unimplemented: Read as `0' bit 2-0 DS70591B-page 246 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 REGISTER 16-21: FCLCONx: PWM FAULT CURRENT-LIMIT CONTROL REGISTER R/W-0 IFLTMOD bit 15 R/W-0 bit 7 Legend: R = Readable bit -n = Value at POR bit 15 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 R/W-0 FLTSRC<4:0>(2,3) R/W-0 R/W-0 R/W-0 FLTPOL(1) R/W-0 R/W-0 R/W-0 R/W-0 CLSRC<4:0>(2,3) R/W-0 R/W-0 R/W-0 CLPOL(1) R/W-0 CLMOD bit 8 R/W-0 bit 0 FLTMOD<1:0> IFLTMOD: Independent Fault Mode Enable bit 1 = Independent Fault mode: Current-limit input maps FLTDAT<1> to PWMxH output, and Fault input maps FLTDAT<0> to PWMxL output. The CLDAT<1:0> bits are not used for override functions. 0 = Normal Fault mode: Current-Limit mode maps CLDAT<1:0> bits to the PWMxH and PWMxL outputs. The PWM Fault mode maps FLTDAT<1:0> to the PWMxH and PWMxL outputs. Note 1: These bits should be changed only when PTEN = 0. Changing the clock selection during operation will yield unpredictable results. 2: When Independent Fault mode is enabled (IFLTMOD = 1), and Fault 1 is used for Current-Limit mode (CLSRC<4:0> = b0000), the Fault Control Source Select bits (FLTSRC<4:0>) should be set to an unused Fault source to prevent Fault 1 from disabling both the PWMxL and PWMxH outputs. 3: When Independent Fault mode is enabled (IFLTMOD = 1) and Fault 1 is used for Fault mode (FLTSRC<4:0> = b0000), the Current-Limit Control Source Select bits (CLSRC<4:0>) should be set to an unused current-limit source to prevent the current-limit source from disabling both the PWMxH and PWMxL outputs. 2009 Microchip Technology Inc. Preliminary DS70591B-page 247 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 REGISTER 16-21: FCLCONx: PWM FAULT CURRENT-LIMIT CONTROL REGISTER (CONTINUED) bit 14-10 CLSRC<4:0>: Current-Limit Control Signal Source Select bits for PWM Generator #(2,4). These bits also specify the source for the dead time compensation input signal, DTCMPx. 11111 = Reserved 11110 = Fault 23 11101 = Fault 22 11100 = Fault 21 11011 = Fault 20 11010 = Fault 19 11001 = Fault 18 11000 = Fault 17 10111 = Fault 16 10110 = Fault 15 10101 = Fault 14 10100 = Fault 13 10011 = Fault 12 10010 = Fault 11 10001 = Fault 10 10000 = Fault 9 01111 = Fault 8 01110 = Fault 7 01101 = Fault 6 01100 = Fault 5 01011 = Fault 4 01010 = Fault 3 01001 = Fault 2 01000 = Fault 1 00111 = Reserved 00110 = Reserved 00101 = Reserved 00100 = Reserved 00011 = Analog Comparator 4 00010 = Analog Comparator 3 00001 = Analog Comparator 2 00000 = Analog Comparator 1 CLPOL: Current-Limit Polarity bit for PWM Generator #(1) 1 = The selected current-limit source is active-low 0 = The selected current-limit source is active-high CLMOD: Current-Limit Mode Enable bit for PWM Generator # 1 = Current-Limit mode is enabled 0 = Current-Limit mode is disabled bit 9 bit 8 Note 1: These bits should be changed only when PTEN = 0. Changing the clock selection during operation will yield unpredictable results. 2: When Independent Fault mode is enabled (IFLTMOD = 1), and Fault 1 is used for Current-Limit mode (CLSRC<4:0> = b0000), the Fault Control Source Select bits (FLTSRC<4:0>) should be set to an unused Fault source to prevent Fault 1 from disabling both the PWMxL and PWMxH outputs. 3: When Independent Fault mode is enabled (IFLTMOD = 1) and Fault 1 is used for Fault mode (FLTSRC<4:0> = b0000), the Current-Limit Control Source Select bits (CLSRC<4:0>) should be set to an unused current-limit source to prevent the current-limit source from disabling both the PWMxH and PWMxL outputs. DS70591B-page 248 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 REGISTER 16-21: FCLCONx: PWM FAULT CURRENT-LIMIT CONTROL REGISTER (CONTINUED) bit 7-3 FLTSRC<4:0>: Fault Control Signal Source Select bits for PWM Generator #(2,4) 11111 = Reserved 11110 = Fault 23 11101 = Fault 22 11100 = Fault 21 11011 = Fault 20 11010 = Fault 19 11001 = Fault 18 11000 = Fault 17 10111 = Fault 16 10110 = Fault 15 10101 = Fault 14 10100 = Fault 13 10011 = Fault 12 10010 = Fault 11 10001 = Fault 10 10000 = Fault 9 01111 = Fault 8 01110 = Fault 7 01101 = Fault 6 01100 = Fault 5 01011 = Fault 4 01010 = Fault 3 01001 = Fault 2 01000 = Fault 1 00111 = Reserved 00110 = Reserved 00101 = Reserved 00100 = Reserved 00011 = Analog Comparator 4 00010 = Analog Comparator 3 00001 = Analog Comparator 2 00000 = Analog Comparator 1 FLTPOL: Fault Polarity bit for PWM Generator #(1) 1 = The selected Fault source is active-low 0 = The selected Fault source is active-high FLTMOD<1:0>: Fault Mode bits for PWM Generator # 11 = Fault input is disabled 10 = Reserved 01 = The selected Fault source forces PWMxH, PWMxL pins to FLTDAT values (cycle) 00 = The selected Fault source forces PWMxH, PWMxL pins to FLTDAT values (latched condition) bit 2 bit 1-0 Note 1: These bits should be changed only when PTEN = 0. Changing the clock selection during operation will yield unpredictable results. 2: When Independent Fault mode is enabled (IFLTMOD = 1), and Fault 1 is used for Current-Limit mode (CLSRC<4:0> = b0000), the Fault Control Source Select bits (FLTSRC<4:0>) should be set to an unused Fault source to prevent Fault 1 from disabling both the PWMxL and PWMxH outputs. 3: When Independent Fault mode is enabled (IFLTMOD = 1) and Fault 1 is used for Fault mode (FLTSRC<4:0> = b0000), the Current-Limit Control Source Select bits (CLSRC<4:0>) should be set to an unused current-limit source to prevent the current-limit source from disabling both the PWMxH and PWMxL outputs. 2009 Microchip Technology Inc. Preliminary DS70591B-page 249 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 REGISTER 16-22: STRIGx: PWM SECONDARY TRIGGER COMPARE VALUE REGISTER R/W-0 bit 15 R/W-0 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-3 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 R/W-0 STRGCMP<7:3> R/W-0 R/W-0 U-0 -- U-0 -- U-0 -- bit 0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 bit 8 STRGCMP<15:8> STRGCMP<15:3>: Secondary Trigger Compare Value bits When the secondary PWM functions in local time base, this register contains the compare values that can trigger the ADC module. Unimplemented: Read as `0' bit 2-0 DS70591B-page 250 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 REGISTER 16-23: LEBCONx: LEADING-EDGE BLANKING CONTROL REGISTER R/W-0 PHR bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- R/W-0 BCH R/W-0 BCL R/W-0 BPHH R/W-0 BPHL R/W-0 BPLH R/W-0 PHF R/W-0 PLR R/W-0 PLF R/W-0 FLTLEBEN R/W-0 CLLEBEN U-0 -- U-0 -- bit 8 R/W-0 BPLL bit 0 PHR: PWMxH Rising Edge Trigger Enable bit 1 = Rising edge of PWMxH will trigger Leading-Edge Blanking counter 0 = Leading-Edge Blanking ignores rising edge of PWMxH PHF: PWMxH Falling Edge Trigger Enable bit 1 = Falling edge of PWMxH will trigger Leading-Edge Blanking counter 0 = Leading-Edge Blanking ignores falling edge of PWMxH PLR: PWMxL Rising Edge Trigger Enable bit 1 = Rising edge of PWMxL will trigger Leading-Edge Blanking counter 0 = Leading-Edge Blanking ignores rising edge of PWMxL PLF: PWMxL Falling Edge Trigger Enable bit 1 = Falling edge of PWMxL will trigger Leading-Edge Blanking counter 0 = Leading-Edge Blanking ignores falling edge of PWMxL FLTLEBEN: Fault Input Leading-Edge Blanking Enable bit 1 = Leading-Edge Blanking is applied to selected fault input 0 = Leading-Edge Blanking is not applied to selected fault input CLLEBEN: Current-Limit Leading-Edge Blanking Enable bit 1 = Leading-Edge Blanking is applied to selected current-limit input 0 = Leading-Edge Blanking is not applied to selected current-limit input Unimplemented: Read as `0' BCH: Blanking in Selected-Blanking Signal High Enable bit(1) 1 = State blanking (of current-limit and/or fault input signals) when selected blanking signal is high 0 = No blanking when selected blanking signal is high BCL: Blanking in Selected-Blanking Signal Low Enable bit(1) 1 = State blanking (of current-limit and/or fault input signals) when selected blanking signal is low 0 = No blanking when selected blanking signal is low BPHH: Blanking in PWMxH High Enable bit 1 = State blanking (of current-limit and/or fault input signals) when PWMxH output is high 0 = No blanking when PWMxH output is high BPHL: Blanking in PWMxH Low Enable bit 1 = State blanking (of current-limit and/or fault input signals) when PWMxH output is low 0 = No blanking when PWMxH output is low BPLH: Blanking in PWMxL High Enable bit 1 = State blanking (of current-limit and/or fault input signals) when PWMxL output is high 0 = No blanking when PWMxL output is high BPLL: Blanking in PWMxL Low Enable bit 1 = State blanking (of current-limit and/or fault input signals) when PWMxL output is low 0 = No blanking when PWMxL output is low bit 14 bit 13 bit 12 bit 11 bit 10 bit 9-6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Note 1: The blanking signal is selected via the BLANKSEL bits in the AUXCONx register. 2009 Microchip Technology Inc. Preliminary DS70591B-page 251 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 REGISTER 16-24: LEBDLYx: LEADING-EDGE BLANKING DELAY REGISTER U-0 -- bit 15 R/W-0 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-12 bit 11-3 bit 2-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 R/W-0 LEB<7:3> R/W-0 R/W-0 U-0 -- U-0 -- U-0 -- bit 0 U-0 -- U-0 -- U-0 -- R/W-0 R/W-0 R/W-0 R/W-0 bit 8 LEB<11:8> Unimplemented: Read as `0' LEB<11:3>: Leading-Edge Blanking Delay bits for Current-Limit and Fault Inputs Value in 8.4 ns increments Unimplemented: Read as `0' DS70591B-page 252 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 REGISTER 16-25: AUXCONx: PWM AUXILIARY CONTROL REGISTER R/W-0 HRPDIS bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CHOPHEN R/W-0 HRDDIS U-0 -- U-0 -- R/W-0 R/W-0 R/W-0 R/W-0 bit 8 R/W-0 CHOPLEN bit 0 BLANKSEL<3:0> CHOPSEL<3:0> HRPDIS: High Resolution PWM Period Disable bit(1) 1 = High resolution PWM period is disabled to reduce power consumption 0 = High resolution PWM period is enabled HRDDIS: High Resolution PWM Duty Cycle Disable bit(1) 1 = High resolution PWM duty cycle is disabled to reduce power consumption 0 = High resolution PWM duty cycle is enabled Unimplemented: Read as `0' BLANKSEL<3:0>: PWM State Blank Source Select bits The selected state blank signal will block the current limit and/or fault input signals (if enabled via the BCH and BCL bits in the LEBCONx register) 1001 = PWM9H selected as state blank source 1000 = PWM8H selected as state blank source 0111 = PWM7H selected as state blank source 0110 = PWM6H selected as state blank source 0101 = PWM5H selected as state blank source 0100 = PWM4H selected as state blank source 0011 = PWM3H selected as state blank source 0010 = PWM2H selected as state blank source 0001 = PWM1H selected as state blank source 0000 = 1'b0 (no state blanking) Unimplemented: Read as `0' CHOPSEL<3:0>: PWM Chop Clock Source Select bits The selected signal will enable and disable (CHOP) the selected PWM outputs 1001 = PWM9H selected as CHOP clock source 1000 = PWM8H selected as CHOP clock source 0111 = PWM7H selected as CHOP clock source 0110 = PWM6H selected as CHOP clock source 0101 = PWM5H selected as CHOP clock source 0100 = PWM4H selected as CHOP clock source 0011 = PWM3H selected as CHOP clock source 0010 = PWM2H selected as CHOP clock source 0001 = PWM1H selected as CHOP clock source 0000 = Chop Clock generator selected as CHOP clock source CHOPHEN: PWMxH Output Chopping Enable bit 1 = PWMxH chopping function is enabled 0 = PWMxH chopping function is disabled CHOPLEN: PWMxL Output Chopping Enable bit 1 = PWMxL chopping function is enabled 0 = PWMxL chopping function is disabled bit 14 bit 13-12 bit 11-8 bit 7-6 bit 5-2 bit 1 bit 0 2009 Microchip Technology Inc. Preliminary DS70591B-page 253 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 REGISTER 16-26: PWMCAPx: PRIMARY PWM TIME BASE CAPTURE REGISTER R-0 bit 15 R-0 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-3 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R-0 R-0 PWMCAP<7:3> R-0 R-0 U-0 -- U-0 -- U-0 -- bit 0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 bit 8 PWMCAP<15:8> PWMCAP<15:3>: Captured PWM Time Base Value bits(1,2) The value in this register represents the captured PWM time base value when a leading edge is detected on the current-limit input. Unimplemented: Read as `0' bit 2-0 Note 1: The capture feature is only available on primary output (PWMxH). 2: This feature is active only after LEB processing on the current-limit input signal is complete. DS70591B-page 254 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 17.0 QUADRATURE ENCODER INTERFACE (QEI) MODULE This chapter describes the Quadrature Encoder Interface (QEI) module and associated operational modes. The QEI module provides the interface to incremental encoders for obtaining mechanical position data. The operational features of the QEI include: * Three input channels for two phase signals and index pulse * 16-bit up/down position counter * Count direction status * Position Measurement (x2 and x4) mode * Programmable digital noise filters on inputs * Alternate 16-bit Timer/Counter mode * Quadrature Encoder Interface interrupts These operating modes are determined by setting the appropriate bits, QEIM<2:0> in (QEIxCON<10:8>). Figure 17-1 depicts the Quadrature Encoder Interface block diagram. Note: An `x' used in the names of pins, control/ status bits and registers denotes a particular Quadrature Encoder Interface (QEI) module number (x = 1 or 2). Note 1: This data sheet summarizes the features of the dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 15. "Quadrature Encoder Interface (QEI)" (DS70208) in the "dsPIC33F/PIC24H Family Reference Manual", which is available from the Microchip web site (www.microchip.com). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 "Memory Organization" in this data sheet for device-specific register and bit information. FIGURE 17-1: Sleep Input QUADRATURE ENCODER INTERFACE BLOCK DIAGRAM (x = 1 OR 2) TQCKPS<1:0> TQCS TCY 0 1 QEIM<2:0> 1 0 D CK Q Q QExIF Event Flag 2 Prescaler 1, 8, 64, 256 Synchronize Det TQGATE QEAx(1) Programmable Digital Filter UPDN_SRC 0 1 Programmable Digital Filter Programmable Digital Filter PCDOUT 0 3 QEIxCON<11> 2 Quadrature Encoder Interface Logic 16-bit Up/Down Counter (POSxCNT) Reset Comparator/ Zero Detect Equal 3 QEIM<2:0> Mode Select Max Count Register (MAXxCNT) QEBx(1) INDXx(1) Note 1: Existing Pin Logic Up/Down UPDNx 1 The QEI1 module can be connected to the QEA1/QEB1/INDX1 or AQEA1/AQEB1/AINDX1 pins, which are controlled by clearing or setting the ALTQIO bit in the FPOR Configuration register. See Section 24.0 "Special Features" for more information. 2009 Microchip Technology Inc. Preliminary DS70591B-page 255 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 REGISTER 17-1: R/W-0 CNTERR bit 15 R/W-0 SWPAB bit 7 Legend: R = Readable bit -n = Value at POR bit 15 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 PCDOUT R/W-0 TQGATE R/W-0 R/W-0 R/W-0 POSRES R/W-0 TQCS QEIxCON: QEIx CONTROL REGISTER (x = 1 or 2) U-0 -- R/W-0 QEISIDL R-0 INDEX R/W-0 UPDN R/W-0 R/W-0 QEIM<2:0> bit 8 R/W-0 UPDN_SRC bit 0 R/W-0 TQCKPS<1:0> CNTERR: Count Error Status Flag bit(1) 1 = Position count error has occurred 0 = No position count error has occurred Unimplemented: Read as `0' QEISIDL: Stop in Idle Mode bit 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode INDEX: Index Pin State Status bit (Read-Only) 1 = Index pin is High 0 = Index pin is Low UPDN: Position Counter Direction Status bit(2) 1 = Position Counter Direction is positive (+) 0 = Position Counter Direction is negative (-) QEIM<2:0>: Quadrature Encoder Interface Mode Select bits 111 = Quadrature Encoder Interface enabled (x4 mode) with position counter reset by match (MAXxCNT) 110 = Quadrature Encoder Interface enabled (x4 mode) with Index Pulse reset of position counter 101 = Quadrature Encoder Interface enabled (x2 mode) with position counter reset by match (MAXxCNT) 100 = Quadrature Encoder Interface enabled (x2 mode) with Index Pulse reset of position counter 011 = Unused (Module disabled) 010 = Unused (Module disabled) 001 = Starts 16-bit Timer 000 = Quadrature Encoder Interface/Timer off SWPAB: Phase A and Phase B Input Swap Select bit 1 = Phase A and Phase B inputs swapped 0 = Phase A and Phase B inputs not swapped PCDOUT: Position Counter Direction State Output Enable bit 1 = Position Counter Direction Status Output Enable (QEI logic controls state of I/O pin) 0 = Position Counter Direction Status Output Disabled (Normal I/O pin operation) bit 14 bit 13 bit 12 bit 11 bit 10-8 bit 7 bit 6 Note 1: CNTERR flag only applies when QEIM<2:0> = `110' or `100'. 2: Read-only bit when QEIM<2:0> = `1XX'. Read/write bit when QEIM<2:0> = `001'. 3: Prescaler utilized for 16-bit Timer mode only. 4: This bit applies only when QEIM<2:0> = 100 or 110. 5: When configured for QEI mode, this control bit is a `don't care'. DS70591B-page 256 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 REGISTER 17-1: bit 5 QEIxCON: QEIx CONTROL REGISTER (x = 1 or 2) (CONTINUED) TQGATE: Timer Gated Time Accumulation Enable bit 1 = Timer gated time accumulation enabled 0 = Timer gated time accumulation disabled TQCKPS<1:0>: Timer Input Clock Prescale Select bits(3) 11 = 1:256 prescale value 10 = 1:64 prescale value 01 = 1:8 prescale value 00 = 1:1 prescale value POSRES: Position Counter Reset Enable bit(4) 1 = Index Pulse resets Position Counter 0 = Index Pulse does not reset Position Counter TQCS: Timer Clock Source Select bit 1 = External clock from pin QEAx (on the rising edge) 0 = Internal clock (TCY) UPDN_SRC: Position Counter Direction Selection Control bit(5) 1 = QEBx pin state defines position counter direction 0 = Control/Status bit, UPDN (QEIxCON<11>), defines timer counter (POSxCNT) direction bit 4-3 bit 2 bit 1 bit 0 Note 1: CNTERR flag only applies when QEIM<2:0> = `110' or `100'. 2: Read-only bit when QEIM<2:0> = `1XX'. Read/write bit when QEIM<2:0> = `001'. 3: Prescaler utilized for 16-bit Timer mode only. 4: This bit applies only when QEIM<2:0> = 100 or 110. 5: When configured for QEI mode, this control bit is a `don't care'. 2009 Microchip Technology Inc. Preliminary DS70591B-page 257 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 REGISTER 17-2: U-0 -- bit 15 R/W-0 QEOUT bit 7 Legend: R = Readable bit -n = Value at POR bit 15-11 bit 10-9 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 QECK<2:0> U-0 -- U-0 -- U-0 -- U-0 -- bit 0 DFLTxCON: DIGITAL FILTER CONTROL REGISTER U-0 -- U-0 -- U-0 -- U-0 -- R/W-0 R/W-0 R/W-0 CEID bit 8 IMV<2:0> Unimplemented: Read as `0' IMV<1:0>: Index Match Value bits - These bits allow the user application to specify the state of the QEAx and QEBx input pins during an Index pulse when the POSxCNT register is to be reset. In x4 Quadrature Count Mode: IMV1 = Required State of Phase B input signal for match on index pulse IMV0 = Required State of Phase A input signal for match on index pulse In x4 Quadrature Count Mode: IMV1 = Selects Phase input signal for Index state match (0 = Phase A, 1 = Phase B) IMV0 = Required state of the selected Phase input signal for match on index pulse CEID: Count Error Interrupt Disable bit 1 = Interrupts due to count errors are disabled 0 = Interrupts due to count errors are enabled QEOUT: QEAx/QEBx/INDXx Pin Digital Filter Output Enable bit 1 = Digital filter outputs enabled 0 = Digital filter outputs disabled (normal pin operation) QECK<2:0>: QEAx/QEBx/INDXx Digital Filter Clock Divide Select Bits 111 = 1:256 Clock Divide 110 = 1:128 Clock Divide 101 = 1:64 Clock Divide 100 = 1:32 Clock Divide 011 = 1:16 Clock Divide 010 = 1:4 Clock Divide 001 = 1:2 Clock Divide 000 = 1:1 Clock Divide Unimplemented: Read as `0' bit 8 bit 7 bit 6-4 bit 3-0 DS70591B-page 258 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 18.0 SERIAL PERIPHERAL INTERFACE (SPI) The Serial Peripheral Interface (SPI) module is a synchronous serial interface useful for communicating with other peripheral or microcontroller devices. These peripheral devices can be serial EEPROMs, shift registers, display drivers, analog-to-digital converters and so on. The SPI module is compatible with SPI and SIOP from Motorola(R). The SPI module consists of a 16-bit shift register, SPIxSR (where x = 1), used for shifting data in and out, and a buffer register, SPIxBUF. A control register, SPIxCON, configures the module. Additionally, a STATUS register, SPIxSTAT, indicates status conditions. The serial interface consists of 4 pins: * * * * SDIx (Serial Data Input) SDOx (Serial Data Output) SCKx (Shift Clock Input Or Output) SSx (Active-Low Slave Select). Note 1: This data sheet summarizes the features of the dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 18. "Serial Peripheral Interface (SPI)" (DS70206) in the "dsPIC33F/PIC24H Family Reference Manual", which is available from the Microchip web site (www.microchip.com). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 "Memory Organization" in this data sheet for device-specific register and bit information. In Master mode operation, SCK is a clock output; in Slave mode, it is a clock input. FIGURE 18-1: SCKx SPI MODULE BLOCK DIAGRAM 1:1 to 1:8 Secondary Prescaler Sync Control Control Clock Shift Control Select Edge 1:1/4/16/64 Primary Prescaler FCY SSx(1) SPIxCON1<1:0> SPIxCON1<4:2> Enable Master Clock SDOx SDIx bit 0 SPIxSR Transfer Transfer SPIxRXB SPIxTXB SPIxBUF Read SPIxBUF Write SPIxBUF 16 Internal Data Bus Note 1: The SPI1 module can be connected to the SS1 or ASS1 pins, which are controlled by clearing or setting the ALTSS1 bit in the FPOR Configuration register. See Section 24.0 "Special Features" for more information. 2009 Microchip Technology Inc. Preliminary DS70591B-page 259 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 REGISTER 18-1: R/W-0 SPIEN bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15 C = Clearable bit W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/C-0 SPIROV U-0 -- U-0 -- U-0 -- U-0 -- R-0 SPITBF R-0 SPIRBF bit 0 SPIxSTAT: SPIx STATUS AND CONTROL REGISTER U-0 -- R/W-0 SPISIDL U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 SPIEN: SPIx Enable bit 1 = Enables module and configures SCKx, SDOx, SDIx and SSx as serial port pins 0 = Disables module Unimplemented: Read as `0' SPISIDL: Stop in Idle Mode bit 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode Unimplemented: Read as `0' SPIROV: Receive Overflow Flag bit 1 = A new byte/word is completely received and discarded. The user software has not read the previous data in the SPIxBUF register. 0 = No overflow has occurred Unimplemented: Read as `0' SPITBF: SPIx Transmit Buffer Full Status bit 1 = Transmit not yet started, SPIxTXB is full 0 = Transmit started, SPIxTXB is empty. Automatically set in hardware when CPU writes SPIxBUF location, loading SPIxTXB. Automatically cleared in hardware when SPIx module transfers data from SPIxTXB to SPIxSR. SPIRBF: SPIx Receive Buffer Full Status bit 1 = Receive complete, SPIxRXB is full 0 = Receive is not complete, SPIxRXB is empty. Automatically set in hardware when SPIx transfers data from SPIxSR to SPIxRXB. Automatically cleared in hardware when core reads SPIxBUF location, reading SPIxRXB. bit 14 bit 13 bit 12-7 bit 6 bit 5-2 bit 1 bit 0 DS70591B-page 260 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 REGISTER 18-2: U-0 -- bit 15 R/W-0 SSEN(3) bit 7 Legend: R = Readable bit -n = Value at POR bit 15-13 bit 12 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 CKP R/W-0 MSTEN R/W-0 R/W-0 SPRE<2:0>(2) R/W-0 R/W-0 SPIXCON1: SPIx CONTROL REGISTER 1 U-0 -- U-0 -- R/W-0 DISSCK R/W-0 DISSDO R/W-0 MODE16 R/W-0 SMP R/W-0 CKE(1) bit 8 R/W-0 bit 0 PPRE<1:0>(2) Unimplemented: Read as `0' DISSCK: Disable SCKx pin bit (SPI Master modes only) 1 = Internal SPI clock is disabled; pin functions as I/O 0 = Internal SPI clock is enabled DISSDO: Disable SDOx pin bit 1 = SDOx pin is not used by module; pin functions as I/O 0 = SDOx pin is controlled by the module MODE16: Word/Byte Communication Select bit 1 = Communication is word-wide (16 bits) 0 = Communication is byte-wide (8 bits) SMP: SPIx Data Input Sample Phase bit Master mode: 1 = Input data sampled at end of data output time 0 = Input data sampled at middle of data output time Slave mode: SMP must be cleared when SPIx is used in Slave mode. CKE: SPIx Clock Edge Select bit(1) 1 = Serial output data changes on transition from active clock state to Idle clock state (see bit 6) 0 = Serial output data changes on transition from Idle clock state to active clock state (see bit 6) SSEN: Slave Select Enable bit (Slave mode)(3) 1 = SSx pin used for Slave mode 0 = SSx pin not used by module; pin controlled by port function CKP: Clock Polarity Select bit 1 = Idle state for clock is a high level; active state is a low level 0 = Idle state for clock is a low level; active state is a high level MSTEN: Master Mode Enable bit 1 = Master mode 0 = Slave mode The CKE bit is not used in the Framed SPI modes. Program this bit to `0' for the Framed SPI modes (FRMEN = 1). Do not set both primary and secondary prescalers to a value of 1:1. This bit must be cleared when FRMEN = 1. bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 Note 1: 2: 3: 2009 Microchip Technology Inc. Preliminary DS70591B-page 261 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 REGISTER 18-2: bit 4-2 SPIXCON1: SPIx CONTROL REGISTER 1 (CONTINUED) SPRE<2:0>: Secondary Prescale bits (Master mode)(2) 111 = Secondary prescale 1:1 110 = Secondary prescale 2:1 . . . 000 = Secondary prescale 8:1 PPRE<1:0>: Primary Prescale bits (Master mode)(2) 11 = Primary prescale 1:1 10 = Primary prescale 4:1 01 = Primary prescale 16:1 00 = Primary prescale 64:1 The CKE bit is not used in the Framed SPI modes. Program this bit to `0' for the Framed SPI modes (FRMEN = 1). Do not set both primary and secondary prescalers to a value of 1:1. This bit must be cleared when FRMEN = 1. bit 1-0 Note 1: 2: 3: DS70591B-page 262 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 REGISTER 18-3: R/W-0 FRMEN bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- R/W-0 FRMDLY U-0 -- bit 0 SPIxCON2: SPIx CONTROL REGISTER 2 R/W-0 R/W-0 FRMPOL U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 SPIFSD FRMEN: Framed SPIx Support bit 1 = Framed SPIx support enabled (SSx pin used as frame sync pulse input/output) 0 = Framed SPIx support disabled SPIFSD: Frame Sync Pulse Direction Control bit 1 = Frame sync pulse input (slave) 0 = Frame sync pulse output (master) FRMPOL: Frame Sync Pulse Polarity bit 1 = Frame sync pulse is active-high 0 = Frame sync pulse is active-low Unimplemented: Read as `0' FRMDLY: Frame Sync Pulse Edge Select bit 1 = Frame sync pulse coincides with first bit clock 0 = Frame sync pulse precedes first bit clock Unimplemented: This bit must not be set to `1' by the user application bit 14 bit 13 bit 12-2 bit 1 bit 0 2009 Microchip Technology Inc. Preliminary DS70591B-page 263 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 NOTES: DS70591B-page 264 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 19.0 INTER-INTEGRATED CIRCUIT (I2CTM) 19.1 Operating Modes Note 1: This data sheet summarizes the features of the dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 19. "Inter-Integrated Circuit (I2CTM)" (DS70195) in the "dsPIC33F/PIC24H Family Reference Manual", which is available from the Microchip web site (www.microchip.com). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 "Memory Organization" in this data sheet for device-specific register and bit information. The Inter-Integrated Circuit (I2C) module provides complete hardware support for both Slave and Multi-Master modes of the I2C serial communication standard with a 16-bit interface. The I2C module has a 2-pin interface: * The SCLx pin is clock. * The SDAx pin is data. The I2C module offers the following key features: * I2C interface supporting both Master and Slave modes of operation. * I2C Slave mode supports 7-bit and 10-bit addressing. * I2C Master mode supports 7-bit and 10-bit addressing. * I2C port allows bidirectional transfers between master and slaves. * Serial clock synchronization for I2C port can be used as a handshake mechanism to suspend and resume serial transfer (SCLREL control). * I2C supports multi-master operation, detects bus collision and arbitrates accordingly. The hardware fully implements all the master and slave functions of the I2C Standard and Fast mode specifications, as well as 7-bit and 10-bit addressing. The I2C module can operate either as a slave or a master on an I2C bus. The following types of I2C operation are supported: * * * I2C slave operation with 7-bit addressing I2C slave operation with 10-bit addressing I2C master operation with 7-bit or 10-bit addressing For details about the communication sequence in each of these modes, refer to the "dsPIC33F/PIC24H Family Reference Manual". Please see the Microchip web site (www.microchip.com) for the latest "dsPIC33F/PIC24H Family Reference Manual" chapters. 19.2 I2C Registers I2CxCON and I2CxSTAT are control and STATUS registers, respectively. The I2CxCON register is readable and writable. The lower six bits of I2CxSTAT are read-only. The remaining bits of the I2CSTAT are read/write: * I2CxRSR is the shift register used for shifting data internal to the module and the user application has no access to it. * I2CxRCV is the receive buffer and the register to which data bytes are written, or from which data bytes are read. * I2CxTRN is the transmit register to which bytes are written during a transmit operation. * The I2CxADD register holds the slave address. * A Status bit, ADD10, indicates 10-Bit Address mode. * The I2CxBRG acts as the Baud Rate Generator (BRG) reload value. In receive operations, I2CxRSR and I2CxRCV together form a double-buffered receiver. When I2CxRSR receives a complete byte, it is transferred to I2CxRCV, and an interrupt pulse is generated. 2009 Microchip Technology Inc. Preliminary DS70591B-page 265 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 FIGURE 19-1: I2CTM BLOCK DIAGRAM (X = 1) Internal Data Bus I2CxRCV Shift Clock I2CxRSR LSb SDAx Address Match Read SCLx Match Detect Write I2CxMSK Write Read I2CxADD Read Start and Stop Bit Detect Start and Stop Bit Generation Control Logic Write I2CxSTAT Read Write I2CxCON Read Collision Detect Acknowledge Generation Clock Stretching Write I2CxTRN LSb Shift Clock Reload Control Read Write I2CxBRG Read BRG Down Counter TCY/2 DS70591B-page 266 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 REGISTER 19-1: R/W-0 I2CEN bit 15 R/W-0 GCEN bit 7 Legend: R = Readable bit -n = Value at POR bit 15 U = Unimplemented bit, read as `0' W = Writable bit `1' = Bit is set HS = Hardware Settable bit `0' = Bit is cleared HC = Hardware Clearable bit x = Bit is unknown R/W-0 STREN R/W-0 ACKDT R/W-0, HC ACKEN R/W-0, HC RCEN R/W-0, HC PEN R/W-0, HC RSEN I2CxCON: I2Cx CONTROL REGISTER U-0 -- R/W-0 I2CSIDL R/W-1, HC SCLREL R/W-0 IPMIEN R/W-0 A10M R/W-0 DISSLW R/W-0 SMEN bit 8 R/W-0, HC SEN bit 0 I2CEN: I2Cx Enable bit 1 = Enables the I2Cx module and configures the SDAx and SCLx pins as serial port pins 0 = Disables the I2Cx module. All I2C pins are controlled by port functions. Unimplemented: Read as `0' I2CSIDL: Stop in Idle Mode bit 1 = Discontinue module operation when device enters an Idle mode 0 = Continue module operation in Idle mode SCLREL: SCLx Release Control bit (when operating as I2C slave) 1 = Release SCLx clock 0 = Hold SCLx clock low (clock stretch) If STREN = 1: Bit is R/W (i.e., software can write `0' to initiate stretch and write `1' to release clock). Hardware clear at beginning of slave transmission. Hardware clear at end of slave reception. If STREN = 0: Bit is R/S (i.e., software can only write `1' to release clock). Hardware clear at beginning of slave transmission. IPMIEN: Intelligent Peripheral Management Interface (IPMI) Enable bit 1 = IPMI mode is enabled; all addresses Acknowledged 0 = IPMI mode disabled A10M: 10-Bit Slave Address bit 1 = I2CxADD is a 10-bit slave address 0 = I2CxADD is a 7-bit slave address DISSLW: Disable Slew Rate Control bit 1 = Slew rate control disabled 0 = Slew rate control enabled SMEN: SMBus Input Levels bit 1 = Enable I/O pin thresholds compliant with SMBus specification 0 = Disable SMBus input thresholds GCEN: General Call Enable bit (when operating as I2C slave) 1 = Enable interrupt when a general call address is received in the I2CxRSR (module is enabled for reception) 0 = General call address disabled STREN: SCLx Clock Stretch Enable bit (when operating as I2C slave) Used in conjunction with SCLREL bit. 1 = Enable software or receive clock stretching 0 = Disable software or receive clock stretching bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 2009 Microchip Technology Inc. Preliminary DS70591B-page 267 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 REGISTER 19-1: bit 5 I2CxCON: I2Cx CONTROL REGISTER (CONTINUED) ACKDT: Acknowledge Data bit (when operating as I2C master, applicable during master receive) Value that is transmitted when the software initiates an Acknowledge sequence. 1 = Send NACK during Acknowledge 0 = Send ACK during Acknowledge ACKEN: Acknowledge Sequence Enable bit (when operating as I2C master, applicable during master receive) 1 = Initiate Acknowledge sequence on SDAx and SCLx pins and transmit ACKDT data bit. Hardware clear at end of master Acknowledge sequence. 0 = Acknowledge sequence not in progress RCEN: Receive Enable bit (when operating as I2C master) 1 = Enables Receive mode for I2C. Hardware clear at end of eighth bit of master receive data byte. 0 = Receive sequence not in progress PEN: Stop Condition Enable bit (when operating as I2C master) 1 = Initiate Stop condition on SDAx and SCLx pins. Hardware clear at end of master Stop sequence. 0 = Stop condition not in progress RSEN: Repeated Start Condition Enable bit (when operating as I2C master) 1 = Initiate Repeated Start condition on SDAx and SCLx pins. Hardware clear at end of master Repeated Start sequence. 0 = Repeated Start condition not in progress SEN: Start Condition Enable bit (when operating as I2C master) 1 = Initiate Start condition on SDAx and SCLx pins. Hardware clear at end of master Start sequence. 0 = Start condition not in progress bit 4 bit 3 bit 2 bit 1 bit 0 DS70591B-page 268 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 REGISTER 19-2: R-0, HSC ACKSTAT bit 15 R/C-0, HS IWCOL bit 7 Legend: R = Readable bit -n = Value at POR bit 15 U = Unimplemented bit, read as `0' W = Writable bit `1' = Bit is set HS = Hardware Settable bit `0' = Bit is cleared HSC = Hardware Settable/Clearable x = Bit is unknown R/C-0, HS I2COV R-0, HSC D_A R/C-0, HSC R/C-0, HSC P S R-0, HSC R_W R-0, HSC RBF I2CxSTAT: I2Cx STATUS REGISTER U-0 -- U-0 -- U-0 -- R/C-0, HSC BCL R-0, HSC GCSTAT R-0, HSC ADD10 bit 8 R-0, HSC TBF bit 0 R-0, HSC TRSTAT ACKSTAT: Acknowledge Status bit (when operating as I2C master, applicable to master transmit operation) 1 = NACK received from slave 0 = ACK received from slave Hardware set or clear at end of slave Acknowledge. TRSTAT: Transmit Status bit (when operating as I2C master, applicable to master transmit operation) 1 = Master transmit is in progress (8 bits + ACK) 0 = Master transmit is not in progress Hardware set at beginning of master transmission. Hardware clear at end of slave Acknowledge. Unimplemented: Read as `0' BCL: Master Bus Collision Detect bit 1 = A bus collision has been detected during a master operation 0 = No collision Hardware set at detection of bus collision. GCSTAT: General Call Status bit 1 = General call address was received 0 = General call address was not received Hardware set when address matches general call address. Hardware clear at Stop detection. ADD10: 10-Bit Address Status bit 1 = 10-bit address was matched 0 = 10-bit address was not matched Hardware set at match of 2nd byte of matched 10-bit address. Hardware clear at Stop detection. IWCOL: Write Collision Detect bit 1 = An attempt to write the I2CxTRN register failed because the I2C module is busy 0 = No collision Hardware set at occurrence of write to I2CxTRN while busy (cleared by software). I2COV: Receive Overflow Flag bit 1 = A byte was received while the I2CxRCV register is still holding the previous byte 0 = No overflow Hardware set at attempt to transfer I2CxRSR to I2CxRCV (cleared by software). D_A: Data/Address bit (when operating as I2C slave) 1 = Indicates that the last byte received was data 0 = Indicates that the last byte received was device address Hardware clear at device address match. Hardware set by reception of slave byte. P: Stop bit 1 = Indicates that a Stop bit has been detected last 0 = Stop bit was not detected last Hardware set or clear when Start, Repeated Start or Stop detected. bit 14 bit 13-11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 2009 Microchip Technology Inc. Preliminary DS70591B-page 269 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 REGISTER 19-2: bit 3 I2CxSTAT: I2Cx STATUS REGISTER (CONTINUED) S: Start bit 1 = Indicates that a Start (or Repeated Start) bit has been detected last 0 = Start bit was not detected last Hardware set or clear when Start, Repeated Start or Stop detected. R_W: Read/Write Information bit (when operating as I2C slave) 1 = Read - indicates data transfer is output from slave 0 = Write - indicates data transfer is input to slave Hardware set or clear after reception of I 2C device address byte. RBF: Receive Buffer Full Status bit 1 = Receive complete, I2CxRCV is full 0 = Receive not complete, I2CxRCV is empty Hardware set when I2CxRCV is written with received byte. Hardware clear when software reads I2CxRCV. TBF: Transmit Buffer Full Status bit 1 = Transmit in progress, I2CxTRN is full 0 = Transmit complete, I2CxTRN is empty Hardware set when software writes I2CxTRN. Hardware clear at completion of data transmission. bit 2 bit 1 bit 0 DS70591B-page 270 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 REGISTER 19-3: U-0 -- bit 15 R/W-0 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-10 bit 9-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 I2CxMSK: I2Cx SLAVE MODE ADDRESS MASK REGISTER U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- R/W-0 R/W-0 bit 8 R/W-0 bit 0 AMSK<9:8> AMSK<7:0> Unimplemented: Read as `0' AMSK<9:0>: Mask for Address bit x Select bits 1 = Enable masking for bit x of incoming message address; bit match not required in this position 0 = Disable masking for bit x; bit match required in this position 2009 Microchip Technology Inc. Preliminary DS70591B-page 271 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 NOTES: DS70591B-page 272 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 20.0 UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER (UART) The primary features of the UART module are: * Full-Duplex, 8-Bit or 9-Bit Data Transmission through the UxTX and UxRX pins * Even, Odd or No Parity Options (for 8-bit data) * One or Two Stop bits * Hardware Flow Control Option with UxCTS and UxRTS Pins * Fully Integrated Baud Rate Generator with 16-Bit Prescaler * Baud Rates Ranging from 10 Mbps to 38 bps at 40 MIPS * 4-Deep First-In First-Out (FIFO) Transmit Data Buffer * 4-Deep FIFO Receive Data Buffer * Parity, Framing and Buffer Overrun Error Detection * Support for 9-bit mode with Address Detect (9th bit = 1) * Transmit and Receive Interrupts * A Separate Interrupt for all UART Error Conditions * Loopback mode for Diagnostic Support * Support for Sync and Break Characters * Support for Automatic Baud Rate Detection * IrDA Encoder and Decoder Logic * 16x Baud Clock Output for IrDA Support * Support for DMA A simplified block diagram of the UART module is shown in Figure 20-1. The UART module consists of these key hardware elements: * Baud Rate Generator * Asynchronous Transmitter * Asynchronous Receiver Note 1: This data sheet summarizes the features of the dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 17. "UART" (DS70188) in the "dsPIC33F/PIC24H Family Reference Manual", which is available from the Microchip web site (www.microchip.com). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 "Memory Organization" in this data sheet for device-specific register and bit information. The Universal Asynchronous Receiver Transmitter (UART) module is one of the serial I/O modules available in the dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 device families. The UART is a full-duplex, asynchronous system that can communicate with peripheral devices, such as personal computers, LIN, RS-232 and RS-485 interfaces. The module also supports a hardware flow control option with the UxCTS and UxRTS pins and also includes an IrDA encoder and decoder. FIGURE 20-1: UART SIMPLIFIED BLOCK DIAGRAM Baud Rate Generator IrDA(R) Hardware Flow Control UxRTS UxCTS UART Receiver UxRX UART Transmitter UxTX 2009 Microchip Technology Inc. Preliminary DS70591B-page 273 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 REGISTER 20-1: R/W-0 UARTEN bit 15 R/W-0 HC WAKE bit 7 Legend: R = Readable bit -n = Value at POR bit 15 HC = Hardware Clearable W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 LPBACK R/W-0, HC ABAUD R/W-0 URXINV R/W-0 BRGH R/W-0 R/W-0 (1) UxMODE: UARTx MODE REGISTER U-0 -- R/W-0 USIDL R/W-0 IREN (2) R/W-0 RTSMD U-0 -- R/W-0 R/W-0 bit 8 R/W-0 STSEL bit 0 UEN<1:0> PDSEL<1:0> UARTEN: UARTx Enable bit(1) 1 = UARTx is enabled; all UARTx pins are controlled by UARTx as defined by UEN<1:0> 0 = UARTx is disabled; all UARTx pins are controlled by PORT latches; UARTx power consumption minimal Unimplemented: Read as `0' USIDL: Stop in Idle Mode bit 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode IREN: IrDA(R) Encoder and Decoder Enable bit(2) 1 = IrDA encoder and decoder enabled 0 = IrDA encoder and decoder disabled RTSMD: Mode Selection for UxRTS Pin bit 1 = UxRTS pin in Simplex mode 0 = UxRTS pin in Flow Control mode Unimplemented: Read as `0' UEN<1:0>: UARTx Enable bits 11 = UxTX, UxRX and BCLK pins are enabled and used; UxCTS pin controlled by PORT latches 10 = UxTX, UxRX, UxCTS and UxRTS pins are enabled and used 01 = UxTX, UxRX and UxRTS pins are enabled and used; UxCTS pin controlled by PORT latches 00 = UxTX and UxRX pins are enabled and used; UxCTS and UxRTS/BCLK pins controlled by PORT latches WAKE: Wake-up on Start bit Detect During Sleep Mode Enable bit 1 = UARTx will continue to sample the UxRX pin; interrupt generated on falling edge; bit cleared in hardware on following rising edge 0 = No wake-up enabled LPBACK: UARTx Loopback Mode Select bit 1 = Enable Loopback mode 0 = Loopback mode is disabled ABAUD: Auto-Baud Enable bit 1 = Enable baud rate measurement on the next character - requires reception of a Sync field (55h) before other data; cleared in hardware upon completion 0 = Baud rate measurement disabled or completed bit 14 bit 13 bit 12 bit 11 bit 10 bit 9-8 bit 7 bit 6 bit 5 Note 1: Refer to Section 17. "UART" (DS70188) in the "dsPIC33F/PIC24H Family Reference Manual" for information on enabling the UART module for receive or transmit operation. 2: This feature is only available for the 16x BRG mode (BRGH = 0). DS70591B-page 274 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 REGISTER 20-1: bit 4 UxMODE: UARTx MODE REGISTER (CONTINUED) URXINV: Receive Polarity Inversion bit 1 = UxRX Idle state is `0' 0 = UxRX Idle state is `1' BRGH: High Baud Rate Enable bit 1 = BRG generates 4 clocks per bit period (4x baud clock, High-Speed mode) 0 = BRG generates 16 clocks per bit period (16x baud clock, Standard mode) PDSEL<1:0>: Parity and Data Selection bits 11 = 9-bit data, no parity 10 = 8-bit data, odd parity 01 = 8-bit data, even parity 00 = 8-bit data, no parity STSEL: Stop Bit Selection bit 1 = Two Stop bits 0 = One Stop bit bit 3 bit 2-1 bit 0 Note 1: Refer to Section 17. "UART" (DS70188) in the "dsPIC33F/PIC24H Family Reference Manual" for information on enabling the UART module for receive or transmit operation. 2: This feature is only available for the 16x BRG mode (BRGH = 0). 2009 Microchip Technology Inc. Preliminary DS70591B-page 275 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 REGISTER 20-2: R/W-0 UTXISEL1 bit 15 R/W-0 bit 7 Legend: R = Readable bit -n = Value at POR bit 15,13 UxSTA: UARTx STATUS AND CONTROL REGISTER R/W-0 R/W-0 UTXISEL0 U-0 -- R/W-0, HC UTXBRK R/W-0 UTXEN (1) R-0 UTXBF R-1 TRMT bit 8 UTXINV R/W-0 R/W-0 ADDEN R-1 RIDLE R-0 PERR R-0 FERR R/C-0 OERR R-0 URXDA bit 0 URXISEL<1:0> HC = Hardware Clearable bit W = Writable bit `1' = Bit is set C = Clearable bit U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown UTXISEL<1:0>: Transmission Interrupt Mode Selection bits 11 = Reserved; do not use 10 = Interrupt when a character is transferred to the Transmit Shift register, and as a result, the transmit buffer becomes empty 01 = Interrupt when the last character is shifted out of the Transmit Shift register; all transmit operations are completed 00 = Interrupt when a character is transferred to the Transmit Shift register (this implies there is at least one character open in the transmit buffer) UTXINV: Transmit Polarity Inversion bit If IREN = 0: 1 = UxTX Idle state is `0' 0 = UxTX Idle state is `1' If IREN = 1: 1 = IrDA(R) encoded UxTX Idle state is `1' 0 = IrDA encoded UxTX Idle state is `0' bit 14 bit 12 bit 11 Unimplemented: Read as `0' UTXBRK: Transmit Break bit 1 = Send Sync Break on next transmission - Start bit, followed by twelve `0' bits, followed by Stop bit; cleared by hardware upon completion 0 = Sync Break transmission disabled or completed UTXEN: Transmit Enable bit(1) 1 = Transmit enabled, UxTX pin controlled by UARTx 0 = Transmit disabled, any pending transmission is aborted and buffer is reset; UxTX pin controlled by port UTXBF: Transmit Buffer Full Status bit (read-only) 1 = Transmit buffer is full 0 = Transmit buffer is not full; at least one more character can be written TRMT: Transmit Shift Register Empty bit (read-only) 1 = Transmit Shift register is empty and transmit buffer is empty (the last transmission has completed) 0 = Transmit Shift register is not empty, a transmission is in progress or queued URXISEL<1:0>: Receive Interrupt Mode Selection bits 11 = Interrupt is set on UxRSR transfer making the receive buffer full (i.e., has 4 data characters) 10 = Interrupt is set on UxRSR transfer making the receive buffer 3/4 full (i.e., has 3 data characters) 0x = Interrupt is set when any character is received and transferred from the UxRSR to the receive buffer; receive buffer has one or more characters bit 10 bit 9 bit 8 bit 7-6 Note 1: Refer to Section 17. "UART" (DS70188) in the "dsPIC33F/PIC24H Family Reference Manual" for information on enabling the UART module for transmit operation. DS70591B-page 276 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 REGISTER 20-2: bit 5 UxSTA: UARTx STATUS AND CONTROL REGISTER (CONTINUED) ADDEN: Address Character Detect bit (bit 8 of received data = 1) 1 = Address Detect mode enabled. If 9-bit mode is not selected, this does not take effect. 0 = Address Detect mode disabled RIDLE: Receiver Idle bit (read-only) 1 = Receiver is Idle 0 = Receiver is active PERR: Parity Error Status bit (read-only) 1 = Parity error has been detected for the current character (character at the top of the receive FIFO) 0 = Parity error has not been detected FERR: Framing Error Status bit (read-only) 1 = Framing error has been detected for the current character (character at the top of the receive FIFO) 0 = Framing error has not been detected OERR: Receive Buffer Overrun Error Status bit (clear/read-only) 1 = Receive buffer has overflowed 0 = Receive buffer has not overflowed. Clearing a previously set OERR bit (1 0 transition) will reset the receiver buffer and the UxRSR to the empty state. URXDA: Receive Buffer Data Available bit (read-only) 1 = Receive buffer has data, at least one more character can be read 0 = Receive buffer is empty bit 4 bit 3 bit 2 bit 1 bit 0 Note 1: Refer to Section 17. "UART" (DS70188) in the "dsPIC33F/PIC24H Family Reference Manual" for information on enabling the UART module for transmit operation. 2009 Microchip Technology Inc. Preliminary DS70591B-page 277 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 NOTES: DS70591B-page 278 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 21.0 ENHANCED CAN (ECANTM) MODULE * Programmable Loopback mode supports self-test operation * Signaling via interrupt capabilities for all CAN receiver and transmitter error states * Programmable clock source * Programmable link to input capture module (IC2 for CAN1) for time-stamping and network synchronization * Low-power Sleep and Idle mode The CAN bus module consists of a protocol engine and message buffering/control. The CAN protocol engine handles all functions for receiving and transmitting messages on the CAN bus. Messages are transmitted by first loading the appropriate data registers. Status and errors can be checked by reading the appropriate registers. Any message detected on the CAN bus is checked for errors and then matched against filters to see if it should be received and stored in one of the receive registers. Note 1: This data sheet summarizes the features of the dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 21. "Enhanced Controller Area Network (ECANTM)" (DS70185) in the dsPIC33F/PIC24H Family Reference Manual, which is available from the Microchip web site (www.microchip.com). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 "Memory Organization" in this data sheet for device-specific register and bit information. 21.2 Frame Types 21.1 Overview The Enhanced Controller Area Network (ECAN) module is a serial interface, useful for communicating with other CAN modules or microcontroller devices. This interface/protocol was designed to allow communications within noisy environments. The dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 devices contain up to two ECAN modules. The ECAN module is a communication controller implementing the CAN 2.0 A/B protocol, as defined in the BOSCH CAN specification. The module supports CAN 1.2, CAN 2.0A, CAN 2.0B Passive and CAN 2.0B Active versions of the protocol. The module implementation is a full CAN system. The CAN specification is not covered within this data sheet. The reader can refer to the BOSCH CAN specification for further details. The module features are as follows: * Implementation of the CAN protocol, CAN 1.2, CAN 2.0A and CAN 2.0B * Standard and extended data frames * 0-8 bytes data length * Programmable bit rate up to 1 Mbit/sec * Automatic response to remote transmission requests * Up to eight transmit buffers with application specified prioritization and abort capability (each buffer can contain up to 8 bytes of data) * Up to 32 receive buffers (each buffer can contain up to 8 bytes of data) * Up to 16 full (standard/extended identifier) acceptance filters * Three full acceptance filter masks * DeviceNetTM addressing support * Programmable wake-up functionality with integrated low-pass filter The ECAN module transmits various types of frames which include data messages, or remote transmission requests initiated by the user, as other frames that are automatically generated for control purposes. The following frame types are supported: * Standard Data Frame: A standard data frame is generated by a node when the node wishes to transmit data. It includes an 11-bit Standard Identifier (SID), but not an 18-bit Extended Identifier (EID). * Extended Data Frame: An extended data frame is similar to a standard data frame, but includes an extended identifier as well. * Remote Frame: It is possible for a destination node to request the data from the source. For this purpose, the destination node sends a remote frame with an identifier that matches the identifier of the required data frame. The appropriate data source node sends a data frame as a response to this remote request. * Error Frame: An error frame is generated by any node that detects a bus error. An error frame consists of two fields: an error flag field and an error delimiter field. * Overload Frame: An overload frame can be generated by a node as a result of two conditions. First, the node detects a dominant bit during interframe space which is an illegal condition. Second, due to internal conditions, the node is not yet able to start reception of the next message. A node can generate a maximum of 2 sequential overload frames to delay the start of the next message. * Interframe Space: Interframe space separates a proceeding frame (of whatever type) from a following data or remote frame. 2009 Microchip Technology Inc. Preliminary DS70591B-page 279 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 FIGURE 21-1: ECANTM MODULE BLOCK DIAGRAM RxF15 Filter RxF14 Filter RxF13 Filter RxF12 Filter DMA Controller RxF11 Filter RxF10 Filter RxF9 Filter RxF8 Filter TRB7 Tx/Rx Buffer Control Register TRB6 Tx/Rx Buffer Control Register TRB5 Tx/Rx Buffer Control Register TRB4 Tx/Rx Buffer Control Register TRB3 Tx/Rx Buffer Control Register TRB2 Tx/Rx Buffer Control Register TRB1 Tx/Rx Buffer Control Register TRB0 Tx/Rx Buffer Control Register RxF7 Filter RxF6 Filter RxF5 Filter RxF4 Filter RxF3 Filter RxF2 Filter RxF1 Filter RxF0 Filter RxM2 Mask RxM1 Mask RxM0 Mask Transmit Byte Sequencer Message Assembly Buffer CAN Protocol Engine Control Configuration Logic CPU Bus Interrupts C1Tx C1Rx DS70591B-page 280 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 21.3 Modes of Operation The module can be programmed to apply a low-pass filter function to the CiRX input line while the module or the CPU is in Sleep mode. The WAKFIL bit (CiCFG2<14>) enables or disables the filter. Note: Typically, if the ECAN module is allowed to transmit in a particular mode of operation and a transmission is requested immediately after the ECAN module has been placed in that mode of operation, the module waits for 11 consecutive recessive bits on the bus before starting transmission. If the user switches to Disable mode within this 11-bit period, then this transmission is aborted and the corresponding TXABT bit is set and TXREQ bit is cleared. The ECAN module can operate in one of several operation modes selected by the user. These modes include: * * * * * * Initialization mode Disable mode Normal Operation mode Listen Only mode Listen All Messages mode Loopback mode Modes are requested by setting the REQOP<2:0> bits (CiCTRL1<10:8>). Entry into a mode is Acknowledged by monitoring the OPMODE<2:0> bits (CiCTRL1<7:5>). The module does not change the mode and the OPMODE bits until a change in mode is acceptable, generally during bus Idle time, which is defined as at least 11 consecutive recessive bits. 21.3.3 NORMAL OPERATION MODE 21.3.1 INITIALIZATION MODE In the Initialization mode, the module does not transmit or receive. The error counters are cleared and the interrupt flags remain unchanged. The user application has access to Configuration registers that are access restricted in other modes. The module protects the user from accidentally violating the CAN protocol through programming errors. All registers which control the configuration of the module can not be modified while the module is on-line. The ECAN module is not allowed to enter the Configuration mode while a transmission is taking place. The Configuration mode serves as a lock to protect the following registers: * * * * * All Module Control registers Baud Rate and Interrupt Configuration registers Bus Timing registers Identifier Acceptance Filter registers Identifier Acceptance Mask registers Normal Operation mode is selected when REQOP<2:0> = 000. In this mode, the module is activated and the I/O pins assumes the CAN bus functions. The module transmits and receive CAN bus messages via the CiTX and CiRX pins. 21.3.4 LISTEN ONLY MODE If the Listen Only mode is activated, the module on the CAN bus is passive. The transmitter buffers revert to the port I/O function. The receive pins remain inputs. For the receiver, no error flags or Acknowledge signals are sent. The error counters are deactivated in this state. The Listen Only mode can be used for detecting the baud rate on the CAN bus. To use this, it is necessary that there are at least two further nodes that communicate with each other. 21.3.5 LISTEN ALL MESSAGES MODE 21.3.2 DISABLE MODE In Disable mode, the module does not transmit or receive. The module has the ability to set the WAKIF bit due to bus activity, however, any pending interrupts remains and the error counters retains their value. If the REQOP<2:0> bits (CiCTRL1<10:8>) = 001, the module enters the Module Disable mode. If the module is active, the module waits for 11 recessive bits on the CAN bus, detect that condition as an Idle bus, then accept the module disable command. When the OPMODE<2:0> bits (CiCTRL1<7:5>) = 001, that indicates whether the module successfully went into Module Disable mode. The I/O pins reverts to normal I/O function when the module is in the Module Disable mode. The module can be set to ignore all errors and receive any message. The Listen All Messages mode is activated by setting REQOP<2:0> = `111'. In this mode, the data which is in the message assembly buffer, until the time an error occurred, is copied in the receive buffer and can be read via the CPU interface. 21.3.6 LOOPBACK MODE If the Loopback mode is activated, the module connects the internal transmit signal to the internal receive signal at the module boundary. The transmit and receive pins revert to their port I/O function. 2009 Microchip Technology Inc. Preliminary DS70591B-page 281 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 REGISTER 21-1: U-0 -- bit 15 R-1 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13 CiCTRL1: ECANTM CONTROL REGISTER 1 U-0 -- R/W-0 CSIDL R/W-0 ABAT r-0 -- R/W-1 R/W-0 REQOP<2:0> R/W-0 bit 8 R-0 OPMODE<2:0> R-0 U-0 -- R/W-0 CANCAP U-0 -- U-0 -- R/W-0 WIN bit 0 C = Writable bit, but only `0' can be written to clear the bit r = Bit is Reserved W = Writable bit U = Unimplemented bit, read as `0' `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 12 bit 11 bit 10-8 bit 7-5 bit 4 bit 3 bit 2-1 bit 0 Unimplemented: Read as `0' CSIDL: Stop in Idle Mode bit 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode ABAT: Abort All Pending Transmissions bit 1 = Signal all transmit buffers to abort transmission 0 = Module will clear this bit when all transmissions are aborted Reserved: Do not use REQOP<2:0>: Request Operation Mode bits 000 = Set Normal Operation mode 001 = Set Disable mode 010 = Set Loopback mode 011 = Set Listen Only Mode 100 = Set Configuration mode 101 = Reserved 110 = Reserved 111 = Set Listen All Messages mode OPMODE<2:0>: Operation Mode bits 000 = Module is in Normal Operation mode 001 = Module is in Disable mode 010 = Module is in Loopback mode 011 = Module is in Listen Only mode 100 = Module is in Configuration mode 101 = Reserved 110 = Reserved 111 = Module is in Listen All Messages mode Unimplemented: Read as `0' CANCAP: CAN Message Receive Timer Capture Event Enable bit 1 = Enable input capture based on CAN message receive 0 = Disable CAN capture Unimplemented: Read as `0' WIN: SFR Map Window Select bit 1 = Use filter window 0 = Use buffer window DS70591B-page 282 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 REGISTER 21-2: U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-5 bit 4-0 C = Writeable bit, but only `0' can be written to clear the bit W = Writable bit U = Unimplemented bit, read as `0' `1' = Bit is set `0' = Bit is cleared x = Bit is unknown CiCTRL2: ECANTM CONTROL REGISTER 2 U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 U-0 -- U-0 -- R-0 R-0 R-0 DNCNT<4:0> R-0 R-0 bit 0 Unimplemented: Read as `0' DNCNT<4:0>: DeviceNetTM Filter Bit Number bits 10010-11111 = Invalid selection 10001 = Compare up to data byte 3, bit 6 with EID<17> * * * 00001 = Compare up to data byte 1, bit 7 with EID<0> 00000 = Do not compare data bytes 2009 Microchip Technology Inc. Preliminary DS70591B-page 283 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 REGISTER 21-3: U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-13 bit 12-8 C = Writeable bit, but only `0' can be written to clear the bit W = Writable bit U = Unimplemented bit, read as `0' `1' = Bit is set `0' = Bit is cleared x = Bit is unknown CiVEC: ECANTM INTERRUPT CODE REGISTER U-0 -- U-0 -- R-0 R-0 R-0 FILHIT<4:0> R-0 R-0 bit 8 R-1 R-0 R-0 R-0 ICODE<6:0> R-0 R-0 R-0 bit 0 bit 7 bit 6-0 Unimplemented: Read as `0' FILHIT<4:0>: Filter Hit Number bits 10000-11111 = Reserved 01111 = Filter 15 * * * 00001 = Filter 1 00000 = Filter 0 Unimplemented: Read as `0' ICODE<6:0>: Interrupt Flag Code bits 1000101-1111111 = Reserved 1000100 = FIFO almost full interrupt 1000011 = Receiver overflow interrupt 1000010 = Wake-up interrupt 1000001 = Error interrupt 1000000 = No interrupt * * * 0010000-0111111 = Reserved 0001111 = RB15 buffer Interrupt * * * 0001001 = RB9 buffer interrupt 0001000 = RB8 buffer interrupt 0000111 = TRB7 buffer interrupt 0000110 = TRB6 buffer interrupt 0000101 = TRB5 buffer interrupt 0000100 = TRB4 buffer interrupt 0000011 = TRB3 buffer interrupt 0000010 = TRB2 buffer interrupt 0000001 = TRB1 buffer interrupt 0000000 = TRB0 Buffer interrupt DS70591B-page 284 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 REGISTER 21-4: R/W-0 bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-13 C = Writeable bit, but only `0' can be written to clear the bit W = Writable bit U = Unimplemented bit, read as `0' `1' = Bit is set `0' = Bit is cleared x = Bit is unknown U-0 -- U-0 -- R/W-0 R/W-0 R/W-0 FSA<4:0> R/W-0 CiFCTRL: ECANTM FIFO CONTROL REGISTER R/W-0 U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 R/W-0 bit 0 R/W-0 DMABS<2:0> bit 12-5 bit 4-0 DMABS<2:0>: DMA Buffer Size bits 111 = Reserved 110 = 32 buffers in DMA RAM 101 = 24 buffers in DMA RAM 100 = 16 buffers in DMA RAM 011 = 12 buffers in DMA RAM 010 = 8 buffers in DMA RAM 001 = 6 buffers in DMA RAM 000 = 4 buffers in DMA RAM Unimplemented: Read as `0' FSA<4:0>: FIFO Area Starts with Buffer bits 11111 = Read buffer RB31 11110 = Read buffer RB30 * * * 00001 = Tx/Rx buffer TRB1 00000 = Tx/Rx buffer TRB0 2009 Microchip Technology Inc. Preliminary DS70591B-page 285 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 REGISTER 21-5: U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13-8 C = Writable bit, but only `0' can be written to clear the bit W = Writable bit U = Unimplemented bit, read as `0' `1' = Bit is set `0' = Bit is cleared x = Bit is unknown CiFIFO: ECANTM FIFO STATUS REGISTER U-0 -- R-0 R-0 R-0 R-0 FBP<5:0> R-0 R-0 bit 8 U-0 -- R-0 R-0 R-0 R-0 FNRB<5:0> R-0 R-0 bit 0 bit 7-6 bit 5-0 Unimplemented: Read as `0' FBP<5:0>: FIFO Buffer Pointer bits 011111 = RB31 buffer 011110 = RB30 buffer * * * 000001 = TRB1 buffer 000000 = TRB0 buffer Unimplemented: Read as `0' FNRB<5:0>: FIFO Next Read Buffer Pointer bits 011111 = RB31 buffer 011110 = RB30 buffer * * Legend: 000001 = TRB1 buffer 000000 = TRB0 buffer DS70591B-page 286 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 REGISTER 21-6: U-0 -- bit 15 R/C-0 IVRIF bit 7 Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13 CiINTF: ECANTM INTERRUPT FLAG REGISTER U-0 -- R-0 TXBO R-0 TXBP R-0 RXBP R-0 TXWAR R-0 RXWAR R-0 EWARN bit 8 R/C-0 TBIF bit 0 R/C-0 WAKIF R/C-0 ERRIF U-0 -- R/C-0 FIFOIF R/C-0 RBOVIF R/C-0 RBIF C = Writeable bit, but only `0' can be written to clear the bit W = Writable bit U = Unimplemented bit, read as `0' `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Unimplemented: Read as `0' TXBO: Transmitter in Error State Bus Off bit 1 = Transmitter is in Bus Off state 0 = Transmitter is not in Bus Off state TXBP: Transmitter in Error State Bus Passive bit 1 = Transmitter is in Bus Passive state 0 = Transmitter is not in Bus Passive state RXBP: Receiver in Error State Bus Passive bit 1 = Receiver is in Bus Passive state 0 = Receiver is not in Bus Passive state TXWAR: Transmitter in Error State Warning bit 1 = Transmitter is in Error Warning state 0 = Transmitter is not in Error Warning state RXWAR: Receiver in Error State Warning bit 1 = Receiver is in Error Warning state 0 = Receiver is not in Error Warning state EWARN: Transmitter or Receiver in Error State Warning bit 1 = Transmitter or Receiver is in Error State Warning state 0 = Transmitter or Receiver is not in Error State Warning state IVRIF: Invalid Message Received Interrupt Flag bit 1 = Interrupt Request has occurred 0 = Interrupt Request has not occurred WAKIF: Bus Wake-up Activity Interrupt Flag bit 1 = Interrupt Request has occurred 0 = Interrupt Request has not occurred ERRIF: Error Interrupt Flag bit (multiple sources in CiINTF<13:8> register) 1 = Interrupt Request has occurred 0 = Interrupt Request has not occurred Unimplemented: Read as `0' FIFOIF: FIFO Almost Full Interrupt Flag bit 1 = Interrupt Request has occurred 0 = Interrupt Request has not occurred RBOVIF: RX Buffer Overflow Interrupt Flag bit 1 = Interrupt Request has occurred 0 = Interrupt Request has not occurred RBIF: RX Buffer Interrupt Flag bit 1 = Interrupt Request has occurred 0 = Interrupt Request has not occurred TBIF: TX Buffer Interrupt Flag bit 1 = Interrupt Request has occurred 0 = Interrupt Request has not occurred 2009 Microchip Technology Inc. Preliminary DS70591B-page 287 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 REGISTER 21-7: U-0 -- bit 15 R/W-0 IVRIE bit 7 Legend: R = Readable bit -n = Value at POR bit 15-8 bit 7 CiINTE: ECANTM INTERRUPT ENABLE REGISTER U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 R/W-0 WAKIE R/W-0 ERRIE R/W-0 -- R/W-0 FIFOIE R/W-0 RBOVIE R/W-0 RBIE R/W-0 TBIE bit 0 C = Writeable bit, but only `0' can be written to clear the bit W = Writable bit U = Unimplemented bit, read as `0' `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Unimplemented: Read as `0' IVRIE: Invalid Message Received Interrupt Enable bit 1 = Interrupt Request Enabled 0 = Interrupt Request not enabled WAKIE: Bus Wake-up Activity Interrupt Flag bit 1 = Interrupt Request Enabled 0 = Interrupt Request not enabled ERRIE: Error Interrupt Enable bit 1 = Interrupt Request Enabled 0 = Interrupt Request not enabled Unimplemented: Read as `0' FIFOIE: FIFO Almost Full Interrupt Enable bit 1 = Interrupt Request Enabled 0 = Interrupt Request not enabled RBOVIE: RX Buffer Overflow Interrupt Enable bit 1 = Interrupt Request Enabled 0 = Interrupt Request not enabled RBIE: RX Buffer Interrupt Enable bit 1 = Interrupt Request Enabled 0 = Interrupt Request not enabled TBIE: TX Buffer Interrupt Enable bit 1 = Interrupt Request Enabled 0 = Interrupt Request not enabled DS70591B-page 288 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 REGISTER 21-8: R-0 bit 15 R-0 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-8 bit 7-0 C = Writeable bit, but only `0' can be written to clear the bit W = Writable bit U = Unimplemented bit, read as `0' `1' = Bit is set `0' = Bit is cleared x = Bit is unknown R-0 R-0 R-0 R-0 RERRCNT<7:0> R-0 R-0 R-0 bit 0 CiEC: ECANTM TRANSMIT/RECEIVE ERROR COUNT REGISTER R-0 R-0 R-0 R-0 TERRCNT<7:0> R-0 R-0 R-0 bit 8 TERRCNT<7:0>: Transmit Error Count bits RERRCNT<7:0>: Receive Error Count bits REGISTER 21-9: U-0 -- bit 15 CiCFG1: ECANTM BAUD RATE CONFIGURATION REGISTER 1 U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 R/W-0 R/W-0 R/W-0 R/W-0 BRP<5:0> R/W-0 R/W-0 bit 0 R/W-0 R/W-0 SJW<1:0> bit 7 Legend: R = Readable bit -n = Value at POR bit 15-8 bit 7-6 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown bit 5-0 Unimplemented: Read as `0' SJW<1:0>: Synchronization Jump Width bits 11 = Length is 4 x TQ 10 = Length is 3 x TQ 01 = Length is 2 x TQ 00 = Length is 1 x TQ BRP<5:0>: Baud Rate Prescaler bits 11 1111 = TQ = 2 x 64 x 1/FCAN * * * 00 0010 = TQ = 2 x 3 x 1/FCAN 00 0001 = TQ = 2 x 2 x 1/FCAN 00 0000 = TQ = 2 x 1 x 1/FCAN 2009 Microchip Technology Inc. Preliminary DS70591B-page 289 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 REGISTER 21-10: CiCFG2: ECANTM BAUD RATE CONFIGURATION REGISTER 2 U-0 -- bit 15 R/W-x SEG2PHTS bit 7 Legend: R = Readable bit -n = Value at POR bit 15 bit 14 R/W-x WAKFIL U-0 -- U-0 -- U-0 -- R/W-x R/W-x SEG2PH<2:0> R/W-x bit 8 R/W-x SAM R/W-x R/W-x SEG1PH<2:0> R/W-x R/W-x R/W-x PRSEG<2:0> R/W-x bit 0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown bit 13-11 bit 10-8 bit 7 bit 6 bit 5-3 bit 2-0 Unimplemented: Read as `0' WAKFIL: Select CAN bus Line Filter for Wake-up bit 1 = Use CAN bus line filter for wake-up 0 = CAN bus line filter is not used for wake-up Unimplemented: Read as `0' SEG2PH<2:0>: Phase Segment 2 bits 111 = Length is 8 x TQ * * * 000 = Length is 1 x TQ SEG2PHTS: Phase Segment 2 Time Select bit 1 = Freely programmable 0 = Maximum of SEG1PH bits or Information Processing Time (IPT), whichever is greater SAM: Sample of the CAN bus Line bit 1 = Bus line is sampled three times at the sample point 0 = Bus line is sampled once at the sample point SEG1PH<2:0>: Phase Segment 1 bits 111 = Length is 8 x TQ * * * 000 = Length is 1 x TQ PRSEG<2:0>: Propagation Time Segment bits 111 = Length is 8 x TQ * * * 000 = Length is 1 x TQ DS70591B-page 290 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 REGISTER 21-11: CiFEN1: ECANTM ACCEPTANCE FILTER ENABLE REGISTER R/W-1 FLTEN15 bit 15 R/W-1 FLTEN7 bit 7 R/W-1 FLTEN14 R/W-1 FLTEN13 R/W-1 FLTEN12 R/W-1 FLTEN11 R/W-1 FLTEN10 R/W-1 FLTEN9 R/W-1 FLTEN8 bit 8 R/W-1 FLTEN0 bit 0 R/W-1 FLTEN6 R/W-1 FLTEN5 R/W-1 FLTEN4 R/W-1 FLTEN3 R/W-1 FLTEN2 R/W-1 FLTEN1 Legend: R = Readable bit -n = Value at POR bit 15-0 C = Writeable bit, but only `0' can be written to clear the bit W = Writable bit U = Unimplemented bit, read as `0' `1' = Bit is set `0' = Bit is cleared x = Bit is unknown FLTENn: Enable Filter n to Accept Messages bits 1 = Enable Filter n 0 = Disable Filter n REGISTER 21-12: CiBUFPNT1: ECANTM FILTER 0-3 BUFFER POINTER REGISTER R/W-0 bit 15 R/W-0 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-12 C = Writeable bit, but only `0' can be written to clear the bit W = Writable bit U = Unimplemented bit, read as `0' `1' = Bit is set `0' = Bit is cleared x = Bit is unknown R/W-0 R/W-0 F1BP<3:0> R/W-0 R/W-0 R/W-0 R/W-0 F0BP<3:0> R/W-0 R/W-0 F3BP<3:0> R/W-0 R/W-0 R/W-0 R/W-0 F2BP<3:0> R/W-0 bit 8 R/W-0 bit 0 bit 11-8 bit 7-4 bit 3-0 F3BP<3:0>: RX Buffer Mask for Filter 3 bits 1111 = Filter hits received in RX FIFO buffer 1110 = Filter hits received in RX Buffer 14 * * * 0001 = Filter hits received in RX Buffer 1 0000 = Filter hits received in RX Buffer 0 F2BP<3:0>: RX Buffer Mask for Filter 2 bits (same values as bit 15-12) F1BP<3:0>: RX Buffer Mask for Filter 1 bits (same values as bit 15-12) F0BP<3:0>: RX Buffer Mask for Filter 0 bits (same values as bit 15-12) 2009 Microchip Technology Inc. Preliminary DS70591B-page 291 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 REGISTER 21-13: CiBUFPNT2: ECANTM FILTER 4-7 BUFFER POINTER REGISTER R/W-0 bit 15 R/W-0 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-12 C = Writeable bit, but only `0' can be written to clear the bit W = Writable bit U = Unimplemented bit, read as `0' `1' = Bit is set `0' = Bit is cleared x = Bit is unknown R/W-0 R/W-0 F5BP<3:0> R/W-0 R/W-0 R/W-0 R/W-0 F4BP<3:0> R/W-0 R/W-0 F7BP<3:0> R/W-0 R/W-0 R/W-0 R/W-0 F6BP<3:0> R/W-0 bit 8 R/W-0 bit 0 bit 11-8 bit 7-4 bit 3-0 F7BP<3:0>: RX Buffer Mask for Filter 7 bits 1111 = Filter hits received in RX FIFO buffer 1110 = Filter hits received in RX Buffer 14 * * * 0001 = Filter hits received in RX Buffer 1 0000 = Filter hits received in RX Buffer 0 F6BP<3:0>: RX Buffer Mask for Filter 6 bits (same values as bit 15-12) F5BP<3:0>: RX Buffer Mask for Filter 5 bits (same values as bit 15-12) F4BP<3:0>: RX Buffer Mask for Filter 4 bits (same values as bit 15-12) REGISTER 21-14: CiBUFPNT3: ECANTM FILTER 8-11 BUFFER POINTER REGISTER R/W-0 bit 15 R/W-0 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-12 C = Writeable bit, but only `0' can be written to clear the bit W = Writable bit U = Unimplemented bit, read as `0' `1' = Bit is set `0' = Bit is cleared x = Bit is unknown R/W-0 R/W-0 F9BP<3:0> R/W-0 R/W-0 R/W-0 R/W-0 F8BP<3:0> R/W-0 R/W-0 F11BP<3:0> R/W-0 R/W-0 R/W-0 R/W-0 F10BP<3:0> R/W-0 bit 8 R/W-0 bit 0 bit 11-8 bit 7-4 bit 3-0 F11BP<3:0>: RX Buffer Mask for Filter 11 bits 1111 = Filter hits received in RX FIFO buffer 1110 = Filter hits received in RX Buffer 14 * * * 0001 = Filter hits received in RX Buffer 1 0000 = Filter hits received in RX Buffer 0 F10BP<3:0>: RX Buffer Mask for Filter 10 bits (same values as bit 15-12) F9BP<3:0>: RX Buffer Mask for Filter 9 bits (same values as bit 15-12) F8BP<3:0>: RX Buffer Mask for Filter 8 bits (same values as bit 15-12) DS70591B-page 292 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 REGISTER 21-15: CiBUFPNT4: ECANTM FILTER 12-15 BUFFER POINTER REGISTER R/W-0 bit 15 R/W-0 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-12 C = Writeable bit, but only `0' can be written to clear the bit W = Writable bit U = Unimplemented bit, read as `0' `1' = Bit is set `0' = Bit is cleared x = Bit is unknown R/W-0 R/W-0 F13BP<3:0> R/W-0 R/W-0 R/W-0 R/W-0 F12BP<3:0> R/W-0 R/W-0 F15BP<3:0> R/W-0 R/W-0 R/W-0 R/W-0 F14BP<3:0> R/W-0 bit 8 R/W-0 bit 0 bit 11-8 bit 7-4 bit 3-0 F15BP<3:0>: RX Buffer Mask for Filter 15 bits 1111 = Filter hits received in RX FIFO buffer 1110 = Filter hits received in RX Buffer 14 * * * 0001 = Filter hits received in RX Buffer 1 0000 = Filter hits received in RX Buffer 0 F14BP<3:0>: RX Buffer Mask for Filter 14 bits (same values as bit 15-12) F13BP<3:0>: RX Buffer Mask for Filter 13 bits (same values as bit 15-12) F12BP<3:0>: RX Buffer Mask for Filter 12 bits (same values as bit 15-12) 2009 Microchip Technology Inc. Preliminary DS70591B-page 293 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 REGISTER 21-16: CiRXFnSID: ECANTM ACCEPTANCE FILTER STANDARD IDENTIFIER REGISTER n (n = 0-15) R/W-x SID10 bit 15 R/W-x SID2 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-5 R/W-x SID9 R/W-x SID8 R/W-x SID7 R/W-x SID6 R/W-x SID5 R/W-x SID4 R/W-x SID3 bit 8 R/W-x EID16 bit 0 R/W-x SID1 R/W-x SID0 U-0 -- R/W-x EXIDE U-0 -- R/W-x EID17 C = Writeable bit, but only `0' can be written to clear the bit W = Writable bit U = Unimplemented bit, read as `0' `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 4 bit 3 bit 2 bit 1-0 SID<10:0>: Standard Identifier bits 1 = Message address bit SIDx must be `1' to match filter 0 = Message address bit SIDx must be `0' to match filter Unimplemented: Read as `0' EXIDE: Extended Identifier Enable bit If MIDE = 1 then: 1 = Match only messages with extended identifier addresses 0 = Match only messages with standard identifier addresses If MIDE = 0 then: Ignore EXIDE bit. Unimplemented: Read as `0' EID<17:16>: Extended Identifier bits 1 = Message address bit EIDx must be `1' to match filter 0 = Message address bit EIDx must be `0' to match filter DS70591B-page 294 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 REGISTER 21-17: CiRXFnEID: ECANTM ACCEPTANCE FILTER EXTENDED IDENTIFIER REGISTER n (n = 0-15) R/W-x EID15 bit 15 R/W-x EID7 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-0 R/W-x EID14 R/W-x EID13 R/W-x EID12 R/W-x EID11 R/W-x EID10 R/W-x EID9 R/W-x EID8 bit 8 R/W-x EID0 bit 0 R/W-x EID6 R/W-x EID5 R/W-x EID4 R/W-x EID3 R/W-x EID2 R/W-x EID1 C = Writeable bit, but only `0' can be written to clear the bit W = Writable bit U = Unimplemented bit, read as `0' `1' = Bit is set `0' = Bit is cleared x = Bit is unknown EID<15:0>: Extended Identifier bits 1 = Message address bit EIDx must be `1' to match filter 0 = Message address bit EIDx must be `0' to match filter REGISTER 21-18: CiFMSKSEL1: ECANTM FILTER 7-0 MASK SELECTION REGISTER R/W-0 R/W-0 F7MSK<1:0> bit 15 R/W-0 R/W-0 F3MSK<1:0> bit 7 Legend: R = Readable bit -n = Value at POR bit 15-14 R/W-0 R/W-0 F6MSK<1:0> R/W-0 R/W-0 F5MSK<1:0> R/W-0 R/W-0 F4MSK<1:0> bit 8 R/W-0 R/W-0 F0MSK<1:0> bit 0 R/W-0 R/W-0 F2MSK<1:0> R/W-0 R/W-0 F1MSK<1:0> C = Writeable bit, but only `0' can be written to clear the bit W = Writable bit U = Unimplemented bit, read as `0' `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 13-12 bit 11-10 bit 9-8 bit 7-6 bit 5-4 bit 3-2 bit 1-0 F7MSK<1:0>: Mask Source for Filter 7 bits 11 = Reserved 10 = Acceptance Mask 2 registers contain mask 01 = Acceptance Mask 1 registers contain mask 00 = Acceptance Mask 0 registers contain mask F6MSK<1:0>: Mask Source for Filter 6 bits (same values as bit 15-14) F5MSK<1:0>: Mask Source for Filter 5 bits (same values as bit 15-14) F4MSK<1:0>: Mask Source for Filter 4 bits (same values as bit 15-14) F3MSK<1:0>: Mask Source for Filter 3 bits (same values as bit 15-14) F2MSK<1:0>: Mask Source for Filter 2 bits (same values as bit 15-14) F1MSK<1:0>: Mask Source for Filter 1 bits (same values as bit 15-14) F0MSK<1:0>: Mask Source for Filter 0 bits (same values as bit 15-14) 2009 Microchip Technology Inc. Preliminary DS70591B-page 295 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 REGISTER 21-19: CiFMSKSEL2: ECANTM FILTER 15-8 MASK SELECTION REGISTER R/W-0 R/W-0 F15MSK<1:0> bit 15 R/W-0 R/W-0 F11MSK<1:0> bit 7 Legend: R = Readable bit -n = Value at POR bit 15-14 R/W-0 R/W-0 F14MSK<1:0> R/W-0 R/W-0 F13MSK<1:0> R/W-0 R/W-0 F12MSK<1:0> bit 8 R/W-0 R/W-0 F8MSK<1:0> bit 0 R/W-0 R/W-0 F10MSK<1:0> R/W-0 R/W-0 F9MSK<1:0> C = Writeable bit, but only `0' can be written to clear the bit W = Writable bit U = Unimplemented bit, read as `0' `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 13-12 bit 11-10 bit 9-8 bit 7-6 bit 5-4 bit 3-2 bit 1-0 F15MSK<1:0>: Mask Source for Filter 15 bits 11 = Reserved 10 = Acceptance Mask 2 registers contain mask 01 = Acceptance Mask 1 registers contain mask 00 = Acceptance Mask 0 registers contain mask F14MSK<1:0>: Mask Source for Filter 14 bits (same values as bit 15-14) F13MSK<1:0>: Mask Source for Filter 13 bits (same values as bit 15-14) F12MSK<1:0>: Mask Source for Filter 12 bits (same values as bit 15-14) F11MSK<1:0>: Mask Source for Filter 11 bits (same values as bit 15-14) F10MSK<1:0>: Mask Source for Filter 10 bits (same values as bit 15-14) F9MSK<1:0>: Mask Source for Filter 9 bits (same values as bit 15-14) F8MSK<1:0>: Mask Source for Filter 8 bits (same values as bit 15-14) DS70591B-page 296 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 REGISTER 21-20: CiRXMnSID: ECANTM ACCEPTANCE FILTER MASK STANDARD IDENTIFIER REGISTER n (n = 0-2) R/W-x SID10 bit 15 R/W-x SID2 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-5 R/W-x SID9 R/W-x SID8 R/W-x SID7 R/W-x SID6 R/W-x SID5 R/W-x SID4 R/W-x SID3 bit 8 R/W-x EID16 bit 0 R/W-x SID1 R/W-x SID0 U-0 -- R/W-x MIDE U-0 -- R/W-x EID17 C = Writeable bit, but only `0' can be written to clear the bit W = Writable bit U = Unimplemented bit, read as `0' `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 4 bit 3 bit 2 bit 1-0 SID<10:0>: Standard Identifier bits 1 = Include bit SIDx in filter comparison 0 = Bit SIDx is don't care in filter comparison Unimplemented: Read as `0' MIDE: Identifier Receive Mode bit 1 = Match only message types (standard or extended address) that correspond to EXIDE bit in filter 0 = Match either standard or extended address message if filters match (i.e., if (Filter SID) = (Message SID) or if (Filter SID/EID) = (Message SID/EID)) Unimplemented: Read as `0' EID<17:16>: Extended Identifier bits 1 = Include bit EIDx in filter comparison 0 = Bit EIDx is don't care in filter comparison REGISTER 21-21: CiRXMnEID: ECANTM ACCEPTANCE FILTER MASK EXTENDED IDENTIFIER REGISTER n (n = 0-2) R/W-x EID15 bit 15 R/W-x EID7 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-0 R/W-x EID14 R/W-x EID13 R/W-x EID12 R/W-x EID11 R/W-x EID10 R/W-x EID9 R/W-x EID8 bit 8 R/W-x EID0 bit 0 R/W-x EID6 R/W-x EID5 R/W-x EID4 R/W-x EID3 R/W-x EID2 R/W-x EID1 C = Writeable bit, but only `0' can be written to clear the bit W = Writable bit U = Unimplemented bit, read as `0' `1' = Bit is set `0' = Bit is cleared x = Bit is unknown EID<15:0>: Extended Identifier bits 1 = Include bit EIDx in filter comparison 0 = Bit EIDx is don't care in filter comparison 2009 Microchip Technology Inc. Preliminary DS70591B-page 297 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 REGISTER 21-22: CiRXFUL1: ECANTM RECEIVE BUFFER FULL REGISTER 1 R/C-0 RXFUL15 bit 15 R/C-0 RXFUL7 bit 7 R/C-0 RXFUL14 R/C-0 RXFUL13 R/C-0 RXFUL12 R/C-0 RXFUL11 R/C-0 RXFUL10 R/C-0 RXFUL9 R/C-0 RXFUL8 bit 8 R/C-0 RXFUL0 bit 0 R/C-0 RXFUL6 R/C-0 RXFUL5 R/C-0 RXFUL4 R/C-0 RXFUL3 R/C-0 RXFUL2 R/C-0 RXFUL1 Legend: R = Readable bit -n = Value at POR bit 15-0 C = Writeable bit, but only `0' can be written to clear the bit W = Writable bit U = Unimplemented bit, read as `0' `1' = Bit is set `0' = Bit is cleared x = Bit is unknown RXFUL<15:0>: Receive Buffer n Full bits 1 = Buffer is full (set by module) 0 = Buffer is empty REGISTER 21-23: CiRXFUL2: ECANTM RECEIVE BUFFER FULL REGISTER 2 R/C-0 RXFUL31 bit 15 R/C-0 RXFUL23 bit 7 R/C-0 RXFUL30 R/C-0 RXFUL29 R/C-0 RXFUL28 R/C-0 RXFUL27 R/C-0 RXFUL26 R/C-0 RXFUL25 R/C-0 RXFUL24 bit 8 R/C-0 RXFUL16 bit 0 R/C-0 RXFUL22 R/C-0 RXFUL21 R/C-0 RXFUL20 R/C-0 RXFUL19 R/C-0 RXFUL18 R/C-0 RXFUL17 Legend: R = Readable bit -n = Value at POR bit 15-0 C = Writeable bit, but only `0' can be written to clear the bit W = Writable bit U = Unimplemented bit, read as `0' `1' = Bit is set `0' = Bit is cleared x = Bit is unknown RXFUL<31:16>: Receive Buffer n Full bits 1 = Buffer is full (set by module) 0 = Buffer is empty DS70591B-page 298 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 REGISTER 21-24: CiRXOVF1: ECANTM RECEIVE BUFFER OVERFLOW REGISTER 1 R/C-0 RXOVF15 bit 15 R/C-0 RXOVF7 bit 7 R/C-0 RXOVF14 R/C-0 RXOVF13 R/C-0 RXOVF12 R/C-0 RXOVF11 R/C-0 RXOVF10 R/C-0 RXOVF9 R/C-0 RXOVF8 bit 8 R/C-0 RXOVF0 bit 0 R/C-0 RXOVF6 R/C-0 RXOVF5 R/C-0 RXOVF4 R/C-0 RXOVF3 R/C-0 RXOVF2 R/C-0 RXOVF1 Legend: R = Readable bit -n = Value at POR bit 15-0 C = Writeable bit, but only `0' can be written to clear the bit W = Writable bit U = Unimplemented bit, read as `0' `1' = Bit is set `0' = Bit is cleared x = Bit is unknown RXOVF<15:0>: Receive Buffer n Overflow bits 1 = Module attempted to write to a full buffer (set by module) 0 = No overflow condition REGISTER 21-25: CiRXOVF2: ECANTM RECEIVE BUFFER OVERFLOW REGISTER 2 R/C-0 RXOVF31 bit 15 R/C-0 RXOVF23 bit 7 R/C-0 RXOVF30 R/C-0 RXOVF29 R/C-0 RXOVF28 R/C-0 RXOVF27 R/C-0 RXOVF26 R/C-0 RXOVF25 R/C-0 RXOVF24 bit 8 R/C-0 RXOVF16 bit 0 R/C-0 RXOVF22 R/C-0 RXOVF21 R/C-0 RXOVF20 R/C-0 RXOVF19 R/C-0 RXOVF18 R/C-0 RXOVF17 Legend: R = Readable bit -n = Value at POR bit 15-0 C = Writeable bit, but only `0' can be written to clear the bit W = Writable bit U = Unimplemented bit, read as `0' `1' = Bit is set `0' = Bit is cleared x = Bit is unknown RXOVF<31:16>: Receive Buffer n Overflow bits 1 = Module attempted to write to a full buffer (set by module) 0 = No overflow condition 2009 Microchip Technology Inc. Preliminary DS70591B-page 299 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 REGISTER 21-26: CiTRmnCON: ECANTM Tx/Rx BUFFER m CONTROL REGISTER (m = 0,2,4,6; n = 1,3,5,7) R/W-0 TXENn bit 15 R/W-0 TXENm bit 7 R-0 TXABTn R-0 TXLARBn R-0 TXERRn R/W-0 TXREQn R/W-0 RTRENn R/W-0 R/W-0 TXnPRI<1:0> bit 8 R/W-0 R/W-0 TXmPRI<1:0> bit 0 R-0 TXABTm(1) R-0 R-0 TXLARBm(1) TXERRm(1) R/W-0 TXREQm R/W-0 RTRENm Legend: R = Readable bit -n = Value at POR bit 15-8 bit 7 C = Writeable bit, but only `0' can be written to clear the bit W = Writable bit U = Unimplemented bit, read as `0' `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 6 bit 5 bit 4 bit 3 bit 2 bit 1-0 See Definition for Bits 7-0, Controls Buffer n TXENm: TX/RX Buffer Selection bit 1 = Buffer TRBn is a transmit buffer 0 = Buffer TRBn is a receive buffer TXABTm: Message Aborted bit(1) 1 = Message was aborted 0 = Message completed transmission successfully TXLARBm: Message Lost Arbitration bit(1) 1 = Message lost arbitration while being sent 0 = Message did not lose arbitration while being sent TXERRm: Error Detected During Transmission bit(1) 1 = A bus error occurred while the message was being sent 0 = A bus error did not occur while the message was being sent TXREQm: Message Send Request bit 1 = Requests that a message be sent. The bit automatically clears when the message is successfully sent. 0 = Clearing the bit to `0' while set requests a message abort. RTRENm: Auto-Remote Transmit Enable bit 1 = When a remote transmit is received, TXREQ will be set 0 = When a remote transmit is received, TXREQ will be unaffected TXmPRI<1:0>: Message Transmission Priority bits 11 = Highest message priority 10 = High intermediate message priority 01 = Low intermediate message priority 00 = Lowest message priority Note 1: This bit is cleared when TXREQ is set. Note: The buffers, SID, EID, DLC, Data Field and Receive Status registers are located in DMA RAM. DS70591B-page 300 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 21.4 ECAN Message Buffers ECAN Message Buffers are part of DMA RAM Memory. They are not ECAN Special Function Registers. The user application must directly write into the DMA RAM area that is configured for ECAN Message Buffers. The location and size of the buffer area is defined by the user application. BUFFER 21-1: U-0 -- bit 15 R/W-x SID5 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-13 bit 12-2 bit 1 ECANTM MESSAGE BUFFER WORD 0 U-0 -- U-0 -- R/W-x SID10 R/W-x SID9 R/W-x SID8 R/W-x SID7 R/W-x SID6 bit 8 R/W-x IDE bit 0 R/W-x SID4 R/W-x SID3 R/W-x SID2 R/W-x SID1 R/W-x SID0 R/W-x SRR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown bit 0 Unimplemented: Read as `0' SID<10:0>: Standard Identifier bits SRR: Substitute Remote Request bit 1 = Message will request remote transmission 0 = Normal message IDE: Extended Identifier bit 1 = Message will transmit extended identifier 0 = Message will transmit standard identifier BUFFER 21-2: U-0 -- bit 15 R/W-x EID13 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-12 bit 11-0 ECANTM MESSAGE BUFFER WORD 1 U-0 -- U-0 -- U-0 -- R/W-x EID17 R/W-x EID16 R/W-x EID15 R/W-x EID14 bit 8 R/W-x EID6 bit 0 R/W-x EID12 R/W-x EID11 R/W-x EID10 R/W-x EID9 R/W-x EID8 R/W-x EID7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown Unimplemented: Read as `0' EID<17:6>: Extended Identifier bits 2009 Microchip Technology Inc. Preliminary DS70591B-page 301 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 ( BUFFER 21-3: R/W-x EID5 bit 15 U-x -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-10 bit 9 ECANTM MESSAGE BUFFER WORD 2 R/W-x EID4 R/W-x EID3 R/W-x EID2 R/W-x EID1 R/W-x EID0 R/W-x RTR R/W-x RB1 bit 8 R/W-x DLC0 bit 0 U-x -- U-x -- R/W-x RB0 R/W-x DLC3 R/W-x DLC2 R/W-x DLC1 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown bit 8 bit 7-5 bit 4 bit 3-0 EID<5:0>: Extended Identifier bits RTR: Remote Transmission Request bit 1 = Message will request remote transmission 0 = Normal message RB1: Reserved Bit 1 User must set this bit to `0' per CAN protocol. Unimplemented: Read as `0' RB0: Reserved Bit 0 User must set this bit to `0' per CAN protocol. DLC<3:0>: Data Length Code bits BUFFER 21-4: R/W-x bit 15 R/W-x bit 7 Legend: R = Readable bit -n = Value at POR bit 15-8 bit 7-0 ECANTM MESSAGE BUFFER WORD 3 R/W-x R/W-x R/W-x Byte 1 bit 8 R/W-x R/W-x R/W-x Byte 0 bit 0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x Byte 1<15:8>: ECANTM Message Byte 0 Byte 0<7:0>: ECAN Message Byte 1 DS70591B-page 302 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 BUFFER 21-5: R/W-x bit 15 R/W-x bit 7 Legend: R = Readable bit -n = Value at POR bit 15-8 bit 7-0 R/W-x R/W-x R/W-x Byte 2 bit 0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-x R/W-x R/W-x ECANTM MESSAGE BUFFER WORD 4 R/W-x R/W-x R/W-x Byte 3 bit 8 R/W-x R/W-x R/W-x R/W-x R/W-x Byte 3<15:8>: ECANTM Message Byte 3 Byte 2<7:0>: ECAN Message Byte 2 BUFFER 21-6: R/W-x bit 15 R/W-x bit 7 Legend: R = Readable bit -n = Value at POR bit 15-8 bit 7-0 ECANTM MESSAGE BUFFER WORD 5 R/W-x R/W-x R/W-x Byte 5 bit 8 R/W-x R/W-x R/W-x Byte 4 bit 0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x Byte 5<15:8>: ECANTM Message Byte 5 Byte 4<7:0>: ECAN Message Byte 4 2009 Microchip Technology Inc. Preliminary DS70591B-page 303 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 BUFFER 21-7: R/W-x bit 15 R/W-x bit 7 Legend: R = Readable bit -n = Value at POR bit 15-8 bit 7-0 R/W-x R/W-x R/W-x Byte 6 bit 0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-x R/W-x R/W-x ECANTM MESSAGE BUFFER WORD 6 R/W-x R/W-x R/W-x Byte 7 bit 8 R/W-x R/W-x R/W-x R/W-x R/W-x Byte 7<15:8>: ECANTM Message Byte 7 Byte 6<7:0>: ECAN Message Byte 6 BUFFER 21-8: U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-13 bit 12-8 bit 7-0 ECANTM MESSAGE BUFFER WORD 7 U-0 -- U-0 -- R/W-x R/W-x R/W-x FILHIT<4:0>(1) R/W-x R/W-x bit 8 U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown Unimplemented: Read as `0' FILHIT<4:0>: Filter Hit Code bits(1) Encodes number of filter that resulted in writing this buffer. Unimplemented: Read as `0' Note 1: Only written by module for receive buffers, unused for transmit buffers. DS70591B-page 304 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 22.0 HIGH-SPEED 10-BIT ANALOG-TO-DIGITAL CONVERTER (ADC) 22.2 Module Description Note 1: This data sheet summarizes the features of the dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 44. "High-Speed 10-Bit Analog-to-Digital Converter (ADC)" (DS70321) in the "dsPIC33F/PIC24H Family Reference Manual", which is available from the Microchip web site (www.microchip.com). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 "Memory Organization" in this data sheet for device-specific register and bit information. The dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 devices provide high-speed successive approximation Analog-to-Digital conversions to support applications such as AC/DC and DC/DC power converters. This ADC module is designed for applications that require low latency between the request for conversion and the resultant output data. Typical applications include: * AC/DC power supplies * DC/DC converters * Power Factor Correction (PFC) This ADC works with the high-speed PWM module in power control applications that require high-frequency control loops. This module can sample and convert two analog inputs in a 0.5 microsecond when two SARs are used. This small conversion delay reduces the "phase lag" between measurement and control system response. Up to five inputs may be sampled at a time (four inputs from the dedicated sample and hold circuits and one from the shared sample and hold circuit). If multiple inputs request conversion, the ADC will convert them in a sequential manner, starting with the lowest order input. This ADC design provides each pair of analog inputs (AN1,AN0), (AN3,AN2),..., the ability to specify its own trigger source out of a maximum of sixteen different trigger sources. This capability allows this ADC to sample and convert analog inputs that are associated with PWM generators operating on independent time bases. The user application typically requires synchronization between analog data sampling and PWM output to the application circuit. The very high-speed operation of this ADC module allows "data on demand". In addition, several hardware features have been added to the peripheral interface to improve real-time performance in a typical DSP-based application. Result alignment options Automated sampling External conversion start control Two internal inputs to monitor 1.2V internal reference and EXTREF input signal A block diagram of the ADC module is shown in Figure 22-2. * * * * 22.1 Features Overview The ADC module incorporates the following features: * 10-bit resolution * Unipolar inputs * Up to two Successive Approximation Registers (SARs) * Up to 24 external input channels * Two internal analog inputs * Dedicated result register for each analog input * 1 LSB accuracy at 3.3V * Single supply operation * 4 Msps conversion rate at 3.3V (devices with two SARs) * 2 Msps conversion rate at 3.3V (devices with one SAR) * Low-power CMOS technology 2009 Microchip Technology Inc. Preliminary DS70591B-page 305 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 22.3 Module Functionality The ADC module uses the following control and STATUS registers: * * * * * * * * * * * * ADCON: A/D Control Register ADSTAT: A/D Status Register ADBASE: A/D Base Register ADPCFG: A/D Port Configuration Register ADPCFG2: A/D Port Configuration Register 2 ADCPC0: A/D Convert Pair Control Register 0 ADCPC1: A/D Convert Pair Control Register 1 ADCPC2: A/D Convert Pair Control Register 2 ADCPC3: A/D Convert Pair Control Register 3 ADCPC4: A/D Convert Pair Control Register 4 ADCPC5: A/D Convert Pair Control Register 5 ADCPC6: A/D Convert Pair Control Register 6 The high-speed 10-bit ADC is designed to support power conversion applications when used with the High-Speed PWM module. The ADC may have one or two SAR modules, depending on the device variant. If two SARs are present on a device, two conversions can be processed at a time, yielding 4 Msps conversion rate. If only one SAR is present on a device, only one conversion can be processed at a time, yielding 2 Msps conversion rate. The high-speed 10-bit ADC produces two 10-bit conversion results in a 0.5 microsecond. The ADC module supports up to 24 external analog inputs and two internal analog inputs. To monitor reference voltage, two internal inputs, AN24 and AN25, are connected to the EXTREF and internal band gap voltages (1.2V), respectively. The analog reference voltage is defined as the device supply voltage (AVDD/AVSS). The ADCON register controls the operation of the ADC module. The ADSTAT register displays the status of the conversion processes. The ADPCFG registers configure the port pins as analog inputs or as digital I/O. The ADCPCx registers control the triggering of the ADC conversions. See Register 22-1 through Register 22-12 for detailed bit configurations. Note: A unique feature of the ADC module is its ability to sample inputs in an asynchronous manner. Individual sample and hold circuits can be triggered independently of each other. DS70591B-page 306 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 FIGURE 22-1: ADC BLOCK DIAGRAM FOR dsPIC33FJ32GS406 AND DSPIC33FJ64GS406 DEVICES WITH ONE SAR Even Numbered Inputs with Dedicated Sample and Hold (S&H) Circuits AN0 AN2 Bus Interface SAR Core AN4 Eight 16-Bit Registers AN6 AN1 Shared Sample and Hold AN3 AN5 AN7 AN8 AN9 AN10 AN11 AN12 AN13 AN14 AN15 AN24(1) (EXTREF) AN25(2) (INTREF) Note 1: 2: AN24 (EXTREF) is an internal analog input. To measure the voltage at AN12 (EXTREF), an analog comparator must be enabled and EXTREF must be selected as the comparator reference. AN25 (INTREF) is an internal analog input and is not available on a pin. 2009 Microchip Technology Inc. Preliminary Data Format DS70591B-page 307 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 FIGURE 22-2: ADC BLOCK DIAGRAM FOR dsPIC33FJ32GS606 AND dsPIC33FJ64GS606 DEVICES WITH TWO SARS Even Numbered Inputs with Dedicated Sample and Hold (S&H) Circuits AN0 AN2 Data Format SAR Core AN4 Seven 16-Bit Registers AN6 AN10 AN12 AN14 AN24(1) (EXTREF) AN1 Odd Numbered Inputs with Shared S&H Data Format SAR Core Seven 16-Bit Registers AN3 AN5 AN7 AN9 AN11 AN13 AN15 AN25(2) (INTREF) Note 1: 2: AN24 (EXTREF) is an internal analog input. To measure the voltage at AN12 (EXTREF), an analog comparator must be enabled and EXTREF must be selected as the comparator reference. AN25 (INTREF) is an internal analog input and is not available on a pin. DS70591B-page 308 Preliminary 2009 Microchip Technology Inc. Bus Interface AN8 Even Numbered Inputs with Shared S&H dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 FIGURE 22-3: ADC BLOCK DIAGRAM FOR dsPIC33FJ32GS608 AND dsPIC33FJ64GS608 DEVICES WITH TWO SARS Even Numbered Inputs with Dedicated Sample and Hold (S&H) Circuits AN0 AN2 Data Format SAR Core AN4 Seven 16-Bit Registers AN6 AN8 AN10 AN12 AN14 AN16 AN24(1) (EXTREF) AN1 Odd Numbered Inputs with Shared S&H Data Format SAR Core Seven 16-Bit Registers AN3 AN5 AN7 AN9 AN11 AN13 AN15 AN17 AN25(2) (INTREF) Note 1: 2: AN24 (EXTREF) is an internal analog input. To measure the voltage at AN12 (EXTREF), an analog comparator must be enabled and EXTREF must be selected as the comparator reference. AN25 (INTREF) is an internal analog input and is not available on a pin. 2009 Microchip Technology Inc. Preliminary DS70591B-page 309 Bus Interface Even Numbered Inputs with Shared S&H dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 FIGURE 22-4: ADC BLOCK DIAGRAM FOR dsPIC33FJ32GS610 AND dsPIC33FJ64GS610 DEVICES WITH TWO SARS Even Numbered Inputs with Dedicated Sample and Hold (S&H) Circuits AN0 AN2 Data Format SAR Core AN4 Seven 16-Bit Registers AN6 AN8 AN10 AN12 AN14 AN16 AN18 AN20 AN22 AN24(1) (EXTREF) AN1 Odd Numbered Inputs with Shared S&H Data Format SAR Core Seven 16-Bit Registers AN3 AN5 AN7 AN9 AN11 AN13 AN15 AN17 AN19 AN21 AN23 AN25(2) (INTREF) Note 1: 2: AN24 (EXTREF) is an internal analog input. To measure the voltage at AN12 (EXTREF), an analog comparator must be enabled and EXTREF must be selected as the comparator reference. AN25 (INTREF) is an internal analog input and is not available on a pin. DS70591B-page 310 Preliminary 2009 Microchip Technology Inc. Bus Interface Even Numbered Inputs with Shared S&H dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 REGISTER 22-1: R/W-0 ADON bit 15 R/W-0 EIE(1) bit 7 Legend: R = Readable bit -n = Value at POR bit 15 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 ORDER(1) R/W-0 R/W-0 U-0 -- R/W-0 R/W-1 ADCS<2:0>(1) bit 0 ADCON: A/D CONTROL REGISTER U-0 -- R/W-0 ADSIDL R/W-0 SLOWCLK(1) U-0 -- R/W-0 GSWTRG U-0 -- R/W-0 FORM(1) bit 8 R/W-1 SEQSAMP(1) ASYNCSAMP(1) ADON: A/D Operating Mode bit 1 = A/D converter module is operating 0 = A/D converter is off Unimplemented: Read as `0' ADSIDL: Stop in Idle Mode bit 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode SLOWCLK: Enable The Slow Clock Divider bit(1) 1 = ADC is clocked by the auxiliary PLL (ACLK) 0 = ADC is clock by the primary PLL (FVCO) Unimplemented: Read as `0' GSWTRG: Global Software Trigger bit When this bit is set by the user, it will trigger conversions if selected by the TRGSRC<4:0> bits in the ADCPCx registers. This bit must be cleared by the user prior to initiating another global trigger (i.e., this bit is not auto-clearing). bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 Unimplemented: Read as `0' FORM: Data Output Format bit(1) 1 = Fractional (DOUT = dddd dddd dd00 0000) 0 = Integer (DOUT = 0000 00dd dddd dddd) EIE: Early Interrupt Enable bit(1) 1 = Interrupt is generated after first conversion is completed 0 = Interrupt is generated after second conversion is completed ORDER: Conversion Order bit(1) 1 = Odd numbered analog input is converted first, followed by conversion of even numbered input 0 = Even numbered analog input is converted first, followed by conversion of odd numbered input SEQSAMP: Sequential Sample Enable bit(1) 1 = Shared Sample and Hold (S&H) circuit is sampled at the start of the second conversion if ORDER = 0. If ORDER = 1, then the shared S&H is sampled at the start of the first conversion. 0 = Shared S&H is sampled at the same time the dedicated S&H is sampled if the shared S&H is not currently busy with an existing conversion process. If the shared S&H is busy at the time the dedicated S&H is sampled, then the shared S&H will sample at the start of the new conversion cycle. ASYNCSAMP: Asynchronous Dedicated S&H Sampling Enable bit(1) 1 = The dedicated S&H is constantly sampling and then terminates sampling as soon as the trigger pulse is detected. 0 = The dedicated S&H starts sampling when the trigger event is detected and completes the sampling process in two ADC clock cycles. bit 7 bit 6 bit 5 bit 4 Note 1: This control bit can only be changed while the ADC is disabled (ADON = 0). 2009 Microchip Technology Inc. Preliminary DS70591B-page 311 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 REGISTER 22-1: bit 3 bit 2-0 ADCON: A/D CONTROL REGISTER (CONTINUED) Unimplemented: Read as `0' ADCS<2:0>: A/D Conversion Clock Divider Select bits(1) 111 = FADC/8 110 = FADC/7 101 = FADC/6 100 = FADC/5 011 = FADC/4 (default) 010 = FADC/3 001 = FADC/2 000 = FADC/1 Note 1: This control bit can only be changed while the ADC is disabled (ADON = 0). DS70591B-page 312 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 REGISTER 22-2: U-0 -- bit 15 R/C-0, HS P7RDY bit 7 Legend: R = Readable bit -n = Value at POR C = Clearable bit bit 15-13 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 W = Writable bit `1' = Bit is set HS = Hardware Settable bit U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/C-0, HS P6RDY R/C-0, HS P5RDY R/C-0, HS P4RDY R/C-0, HS P3RDY R/C-0, HS P2RDY R/C-0, HS P1RDY ADSTAT: A/D STATUS REGISTER U-0 -- U-0 -- R/C-0, HS P12RDY R/C-0, HS P11RDY R/C-0, HS P10RDY R/C-0, HS P9RDY R/C-0, HS P8RDY bit 8 R/C-0, HS P0RDY bit 0 Unimplemented: Read as `0' P12RDY: Conversion Data for Pair 12 Ready bit Bit is set when data is ready in buffer, cleared when a `0' is written to this bit. P11RDY: Conversion Data for Pair 11 Ready bit Bit is set when data is ready in buffer, cleared when a `0' is written to this bit. P10RDY: Conversion Data for Pair 10 Ready bit Bit is set when data is ready in buffer, cleared when a `0' is written to this bit. P9RDY: Conversion Data for Pair 9 Ready bit Bit is set when data is ready in buffer, cleared when a `0' is written to this bit. P8RDY: Conversion Data for Pair 8 Ready bit Bit is set when data is ready in buffer, cleared when a `0' is written to this bit. P7RDY: Conversion Data for Pair 7 Ready bit Bit is set when data is ready in buffer, cleared when a `0' is written to this bit. P6RDY: Conversion Data for Pair 6 Ready bit Bit is set when data is ready in buffer, cleared when a `0' is written to this bit. P5RDY: Conversion Data for Pair 5 Ready bit Bit is set when data is ready in buffer, cleared when a `0' is written to this bit. P4RDY: Conversion Data for Pair 4 Ready bit Bit is set when data is ready in buffer, cleared when a `0' is written to this bit. P3RDY: Conversion Data for Pair 3 Ready bit Bit is set when data is ready in buffer, cleared when a `0' is written to this bit. P2RDY: Conversion Data for Pair 2 Ready bit Bit is set when data is ready in buffer, cleared when a `0' is written to this bit. P1RDY: Conversion Data for Pair 1 Ready bit Bit is set when data is ready in buffer, cleared when a `0' is written to this bit. P0RDY: Conversion Data for Pair 0 Ready bit Bit is set when data is ready in buffer, cleared when a `0' is written to this bit. Not all PxRDY bits are available on all devices. See Figure 22-1, Figure 22-2, Figure 22-3, and Figure 22-4 for the available analog inputs. Note: 2009 Microchip Technology Inc. Preliminary DS70591B-page 313 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 REGISTER 22-3: R/W-0 bit 15 R/W-0 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-1 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 R/W-0 R/W-0 ADBASE<7:1> R/W-0 R/W-0 R/W-0 U-0 -- bit 0 ADBASE: A/D BASE REGISTER(1,2) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 bit 8 ADBASE<15:8> ADBASE<15:1>: This register contains the base address of the user's ADC Interrupt Service Routine jump table. This register, when read, contains the sum of the ADBASE register contents and the encoded value of the PxRDY Status bits. The encoder logic provides the bit number of the highest priority PxRDY bits where P0RDY is the highest priority, and P6RDY is the lowest priority. Unimplemented: Read as `0' bit 0 Note 1: The encoding results are shifted left two bits so bits 1-0 of the result are always zero. 2: As an alternative to using the ADBASE Register, the ADCP0-ADCP12 ADC Pair Conversion Complete Interrupts can be used to invoke A to D conversion completion routines for individual ADC input pairs. DS70591B-page 314 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 REGISTER 22-4: R/W-0 PCFG15 bit 15 R/W-0 PCFG7 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 PCFG6 R/W-0 PCFG5 R/W-0 PCFG4 R/W-0 PCFG3 R/W-0 PCFG2 R/W-0 PCFG1 ADPCFG: A/D PORT CONFIGURATION REGISTER R/W-0 R/W-0 PCFG13 R/W-0 PCFG12 R/W-0 PCFG11 R/W-0 PCFG10 R/W-0 PCFG9 R/W-0 PCFG8 bit 8 R/W-0 PCFG0 bit 0 PCFG14 PCFG<15:0>: A/D Port Configuration Control bits 1 = Port pin in Digital mode, port read input enabled, A/D input multiplexor connected to AVSS 0 = Port pin in Analog mode, port read input disabled, A/D samples pin voltage Not all PCFGx bits are available on all devices. See Figure 22-1, Figure 22-2, Figure 22-3, and Figure 22-4 for the available analog inputs (PCFGx = ANx, where x = 0-15). Note: REGISTER 22-5: U-0 -- bit 15 R/W-0 PCFG23 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-8 bit 7-0 ADPCFG2: A/D PORT CONFIGURATION REGISTER U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 R/W-0 R/W-0 PCFG21 R/W-0 PCFG20 R/W-0 PCFG19 R/W-0 PCFG18 R/W-0 PCFG17 R/W-0 PCFG16 bit 0 PCFG22 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown Unimplemented: Read as `0' PCFG<23:16>: A/D Port Configuration Control bits 1 = Port pin in Digital mode, port read input enabled, A/D input multiplexor connected to AVSS 0 = Port pin in Analog mode, port read input disabled, A/D samples pin voltage Not all PCFGx bits are available on all devices. See Figure 22-1, Figure 22-2, Figure 22-3, and Figure 22-4 for the available analog inputs (PCFGx = ANx, where x = 16-23). Note: 2009 Microchip Technology Inc. Preliminary DS70591B-page 315 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 REGISTER 22-6: R/W-0 IRQEN1 bit 15 R/W-0 IRQEN0 bit 7 Legend: R = Readable bit -n = Value at POR bit 15 ADCPC0: A/D CONVERT PAIR CONTROL REGISTER 0 R/W-0 SWTRG1 R/W-0 R/W-0 R/W-0 TRGSRC1<4:0> R/W-0 R/W-0 bit 8 R/W-0 PEND1 R/W-0 PEND0 R/W-0 SWTRG0 R/W-0 R/W-0 R/W-0 TRGSRC0<4:0> R/W-0 R/W-0 bit 0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown bit 14 bit 13 bit 12-8 IRQEN1: Interrupt Request Enable 1 bit 1 = Enable IRQ generation when requested conversion of channels AN3 and AN2 is completed 0 = IRQ is not generated PEND1: Pending Conversion Status 1 bit 1 = Conversion of channels AN3 and AN2 is pending. Set when selected trigger is asserted 0 = Conversion is complete SWTRG1: Software Trigger 1 bit 1 = Start conversion of AN3 and AN2 (if selected in TRGSRC bits)(1) This bit is automatically cleared by hardware when the PEND1 bit is set. 0 = Conversion is not started TRGSRC1<4:0>: Trigger 1 Source Selection bits Selects trigger source for conversion of analog channels AN3 and AN2. 00000 = No conversion enabled 00001 = Individual software trigger selected 00010 = Global software trigger selected 00011 = PWM Special Event Trigger selected 00100 = PWM Generator 1 primary trigger selected 00101 = PWM Generator 2 primary trigger selected 00110 = PWM Generator 3 primary trigger selected 00111 = PWM Generator 4 primary trigger selected 01000 = PWM Generator 5 primary trigger selected 01001 = PWM Generator 6 primary trigger selected 01010 = PWM Generator 7 primary trigger selected 01011 = PWM Generator 8 primary trigger selected 01100 = Timer1 period match 01101 = PWM secondary special event trigger selected 01110 = PWM Generator 1 secondary trigger selected 01111 = PWM Generator 2 secondary trigger selected 10000 = PWM Generator 3 secondary trigger selected 10001 = PWM Generator 4 secondary trigger selected 10010 = PWM Generator 5 secondary trigger selected 10011 = PWM Generator 6 secondary trigger selected 10100 = PWM Generator 7 secondary trigger selected 10101 = PWM Generator 8 secondary trigger selected 10110 = PWM Generator 9 secondary trigger selected 10111 = PWM Generator 1 current-limit ADC trigger 11000 = PWM Generator 2 current-limit ADC trigger 11001 = PWM Generator 3 current-limit ADC trigger 11010 = PWM Generator 4 current-limit ADC trigger 11011 = PWM Generator 5 current-limit ADC trigger 11100 = PWM Generator 6 current-limit ADC trigger 11101 = PWM Generator 7 current-limit ADC trigger 11110 = PWM Generator 8 current-limit ADC trigger 11111 = Timer2 period match Note 1: The trigger source must be set as a global software trigger prior to setting this bit to `1'. If other conversions are in progress, the conversion will be performed when the conversion resources are available. DS70591B-page 316 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 REGISTER 22-6: bit 7 ADCPC0: A/D CONVERT PAIR CONTROL REGISTER 0 (CONTINUED) bit 6 bit 5 bit 4-0 IRQEN0: Interrupt Request Enable 0 bit 1 = Enable IRQ generation when requested conversion of channels AN1 and AN0 is completed 0 = IRQ is not generated PEND0: Pending Conversion Status 0 bit 1 = Conversion of channels AN1 and AN0 is pending; set when selected trigger is asserted 0 = Conversion is complete SWTRG0: Software Trigger 0 bit 1 = Start conversion of AN1 and AN0 (if selected by TRGSRC bits)(1) This bit is automatically cleared by hardware when the PEND0 bit is set. 0 = Conversion is not started. TRGSRC0<4:0>: Trigger 0 Source Selection bits Selects trigger source for conversion of analog channels AN1 and AN0. 00000 = No conversion enabled 00001 = Individual software trigger selected 00010 = Global software trigger selected 00011 = PWM Special Event Trigger selected 00100 = PWM Generator 1 primary trigger selected 00101 = PWM Generator 2 primary trigger selected 00110 = PWM Generator 3 primary trigger selected 00111 = PWM Generator 4 primary trigger selected 01000 = PWM Generator 5 primary trigger selected 01001 = PWM Generator 6 primary trigger selected 01010 = PWM Generator 7 primary trigger selected 01011 = PWM Generator 8 primary trigger selected 01100 = Timer1 period match 01101 = Pwm secondary special event trigger selected 01110 = PWM Generator 1 secondary trigger selected 01111 = PWM Generator 2 secondary trigger selected 10000 = PWM Generator 3 secondary trigger selected 10001 = PWM Generator 4 secondary trigger selected 10010 = PWM Generator 5 secondary trigger selected 10011 = PWM Generator 6 secondary trigger selected 10100 = PWM Generator 7 secondary trigger selected 10101 = PWM Generator 8 secondary trigger selected 10110 = PWM Generator 9 secondary trigger selected 10111 = PWM Generator 1 current-limit ADC trigger 11000 = PWM Generator 2 current-limit ADC trigger 11001 = PWM Generator 3 current-limit ADC trigger 11010 = PWM Generator 4 current-limit ADC trigger 11011 = PWM Generator 5 current-limit ADC trigger 11100 = PWM Generator 6 current-limit ADC trigger 11101 = PWM Generator 7 current-limit ADC trigger 11110 = PWM Generator 8 current-limit ADC trigger 11111 = Timer2 period match Note 1: The trigger source must be set as a global software trigger prior to setting this bit to `1'. If other conversions are in progress, the conversion will be performed when the conversion resources are available. 2009 Microchip Technology Inc. Preliminary DS70591B-page 317 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 REGISTER 22-7: R/W-0 IRQEN3 bit 15 R/W-0 IRQEN2 bit 7 Legend: R = Readable bit -n = Value at POR bit 15 ADCPC1: A/D CONVERT PAIR CONTROL REGISTER 1 R/W-0 SWTRG3 R/W-0 R/W-0 R/W-0 TRGSRC3<4:0> R/W-0 R/W-0 bit 8 R/W-0 PEND3 R/W-0 PEND2 R/W-0 SWTRG2 R/W-0 R/W-0 R/W-0 TRGSRC2<4:0> R/W-0 R/W-0 bit 0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown bit 14 bit 13 bit 12-8 IRQEN3: Interrupt Request Enable 3 bit 1 = Enable IRQ generation when requested conversion of channels AN7 and AN6 is completed 0 = IRQ is not generated PEND3: Pending Conversion Status 3 bit 1 = Conversion of channels AN7 and AN6 is pending. Set when selected trigger is asserted 0 = Conversion is complete SWTRG3: Software Trigger 3 bit 1 = Start conversion of AN7 and AN6 (if selected in TRGSRC bits)(1) This bit is automatically cleared by hardware when the PEND3 bit is set. 0 = Conversion is not started. TRGSRC3<4:0>: Trigger 3 Source Selection bits(1) Selects trigger source for conversion of analog channels AN7 and AN6. 00000 = No conversion enabled 00001 = Individual software trigger selected 00010 = Global software trigger selected 00011 = PWM Special Event Trigger selected 00100 = PWM Generator 1 primary trigger selected 00101 = PWM Generator 2 primary trigger selected 00110 = PWM Generator 3 primary trigger selected 00111 = PWM Generator 4 primary trigger selected 01000 = PWM Generator 5 primary trigger selected 01001 = PWM Generator 6 primary trigger selected 01010 = PWM Generator 7 primary trigger selected 01011 = PWM Generator 8 primary trigger selected 01100 = Timer1 period match 01101 = PWM secondary special event trigger selected 01110 = PWM Generator 1 secondary trigger selected 01111 = PWM Generator 2 secondary trigger selected 10000 = PWM Generator 3 secondary trigger selected 10001 = PWM Generator 4 secondary trigger selected 10010 = PWM Generator 5 secondary trigger selected 10011 = PWM Generator 6 secondary trigger selected 10100 = PWM Generator 7 secondary trigger selected 10101 = PWM Generator 8 secondary trigger selected 10110 = PWM Generator 9 secondary trigger selected 10111 = PWM Generator 1 current-limit ADC trigger 11000 = PWM Generator 2 current-limit ADC trigger 11001 = PWM Generator 3 current-limit ADC trigger 11010 = PWM Generator 4 current-limit ADC trigger 11011 = PWM Generator 5 current-limit ADC trigger 11100 = PWM Generator 6 current-limit ADC trigger 11101 = PWM Generator 7 current-limit ADC trigger 11110 = PWM Generator 8 current-limit ADC trigger 11111 = Timer2 period match Note 1: The trigger source must be set as a global software trigger prior to setting this bit to `1'. If other conversions are in progress, the conversion will be performed when the conversion resources are available. DS70591B-page 318 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 REGISTER 22-7: bit 7 ADCPC1: A/D CONVERT PAIR CONTROL REGISTER 1 (CONTINUED) bit 6 bit 5 bit 4-0 IRQEN2: Interrupt Request Enable 2 bit 1 = Enable IRQ generation when requested conversion of channels AN5 and AN4 is completed 0 = IRQ is not generated PEND2: Pending Conversion Status 2 bit 1 = Conversion of channels AN5 and AN4 is pending; set when selected trigger is asserted. 0 = Conversion is complete SWTRG2: Software Trigger 2 bit 1 = Start conversion of AN5 and AN4 (if selected by TRGSRC bits)(1) This bit is automatically cleared by hardware when the PEND2 bit is set. 0 = Conversion is not started TRGSRC2<4:0>: Trigger 2 Source Selection bits Selects trigger source for conversion of analog channels AN5 and AN4. 00000 = No conversion enabled 00001 = Individual software trigger selected 00010 = Global software trigger selected 00011 = PWM Special Event Trigger selected 00100 = PWM Generator 1 primary trigger selected 00101 = PWM Generator 2 primary trigger selected 00110 = PWM Generator 3 primary trigger selected 00111 = PWM Generator 4 primary trigger selected 01000 = PWM Generator 5 primary trigger selected 01001 = PWM Generator 6 primary trigger selected 01010 = PWM Generator 7 primary trigger selected 01011 = PWM Generator 8 primary trigger selected 01100 = Timer1 period match 01101 = PWM secondary special event trigger selected 01110 = PWM Generator 1 secondary trigger selected 01111 = PWM Generator 2 secondary trigger selected 10000 = PWM Generator 3 secondary trigger selected 10001 = PWM Generator 4 secondary trigger selected 10010 = PWM Generator 5 secondary trigger selected 10011 = PWM Generator 6 secondary trigger selected 10100 = PWM Generator 7 secondary trigger selected 10101 = PWM Generator 8 secondary trigger selected 10110 = PWM Generator 9 secondary trigger selected 10111 = PWM Generator 1 current-limit ADC trigger 11000 = PWM Generator 2 current-limit ADC trigger 11001 = PWM Generator 3 current-limit ADC trigger 11010 = PWM Generator 4 current-limit ADC trigger 11011 = PWM Generator 5 current-limit ADC trigger 11100 = PWM Generator 6 current-limit ADC trigger 11101 = PWM Generator 7 current-limit ADC trigger 11110 = PWM Generator 8 current-limit ADC trigger 11111 = Timer2 period match Note 1: The trigger source must be set as a global software trigger prior to setting this bit to `1'. If other conversions are in progress, the conversion will be performed when the conversion resources are available. 2009 Microchip Technology Inc. Preliminary DS70591B-page 319 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 REGISTER 22-8: R/W-0 IRQEN5 bit 15 R/W-0 IRQEN4 bit 7 Legend: R = Readable bit -n = Value at POR bit 15 ADCPC2: A/D CONVERT PAIR CONTROL REGISTER 2 R/W-0 SWTRG5 R/W-0 R/W-0 R/W-0 TRGSRC5<4:0> R/W-0 R/W-0 bit 8 R/W-0 PEND5 R/W-0 PEND4 R/W-0 SWTRG4 R/W-0 R/W-0 R/W-0 TRGSRC4<4:0> R/W-0 R/W-0 bit 0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown bit 14 bit 13 bit 12-8 IRQEN5: Interrupt Request Enable 5 bit 1 = Enable IRQ generation when requested conversion of channels AN11 and AN10 is completed 0 = IRQ is not generated PEND5: Pending Conversion Status 5 bit 1 = Conversion of channels AN11 and AN10 is pending; set when selected trigger is asserted 0 = Conversion is complete SWTRG5: Software Trigger 5 bit 1 = Start conversion of AN11 and AN10 (if selected in TRGSRC bits)(1) This bit is automatically cleared by hardware when the PEND5 bit is set. 0 = Conversion is not started TRGSRC5<4:0>: Trigger 5 Source Selection bits Selects trigger source for conversion of analog channels AN11 and AN10. 00000 = No conversion enabled 00001 = Individual software trigger selected 00010 = Global software trigger selected 00011 = PWM Special Event Trigger selected 00100 = PWM Generator 1 primary trigger selected 00101 = PWM Generator 2 primary trigger selected 00110 = PWM Generator 3 primary trigger selected 00111 = PWM Generator 4 primary trigger selected 01000 = PWM Generator 5 primary trigger selected 01001 = PWM Generator 6 primary trigger selected 01010 = PWM Generator 7 primary trigger selected 01011 = PWM Generator 8 primary trigger selected 01100 = Timer1 period match 01101 = PWM secondary special event trigger selected 01110 = PWM Generator 1 secondary trigger selected 01111 = PWM Generator 2 secondary trigger selected 10000 = PWM Generator 3 secondary trigger selected 10001 = PWM Generator 4 secondary trigger selected 10010 = PWM Generator 5 secondary trigger selected 10011 = PWM Generator 6 secondary trigger selected 10100 = PWM Generator 7 secondary trigger selected 10101 = PWM Generator 8 secondary trigger selected 10110 = PWM Generator 9 secondary trigger selected 10111 = PWM Generator 1 current-limit ADC trigger 11000 = PWM Generator 2 current-limit ADC trigger 11001 = PWM Generator 3 current-limit ADC trigger 11010 = PWM Generator 4 current-limit ADC trigger 11011 = PWM Generator 5 current-limit ADC trigger 11100 = PWM Generator 6 current-limit ADC trigger 11101 = PWM Generator 7 current-limit ADC trigger 11110 = PWM Generator 8 current-limit ADC trigger 11111 = Timer2 period match Note 1: The trigger source must be set as a global software trigger prior to setting this bit to `1'. If other conversions are in progress, the conversion will be performed when the conversion resources are available. DS70591B-page 320 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 REGISTER 22-8: bit 7 ADCPC2: A/D CONVERT PAIR CONTROL REGISTER 2 (CONTINUED) bit 6 bit 5 bit 4-0 IRQEN4: Interrupt Request Enable 4 bit 1 = Enable IRQ generation when requested conversion of channels AN9 and AN8 is completed 0 = IRQ is not generated PEND4: Pending Conversion Status 4 bit 1 = Conversion of channels AN9 and AN8 is pending; set when selected trigger is asserted 0 = Conversion is complete SWTRG4: Software Trigger4 bit 1 = Start conversion of AN9 and AN8 (if selected by TRGSRC bits)(1) This bit is automatically cleared by hardware when the PEND4 bit is set. 0 = Conversion is not started TRGSRC4<4:0>: Trigger 4 Source Selection bits Selects trigger source for conversion of analog channels AN9 and AN8. 00000 = No conversion enabled 00001 = Individual software trigger selected 00010 = Global software trigger selected 00011 = PWM Special Event Trigger selected 00100 = PWM Generator 1 primary trigger selected 00101 = PWM Generator 2 primary trigger selected 00110 = PWM Generator 3 primary trigger selected 00111 = PWM Generator 4 primary trigger selected 01000 = PWM Generator 5 primary trigger selected 01001 = PWM Generator 6 primary trigger selected 01010 = PWM Generator 7 primary trigger selected 01011 = PWM Generator 8 primary trigger selected 01100 = Timer1 period match 01101 = Secondary special event trigger selected 01110 = PWM Generator 1 secondary trigger selected 01111 = PWM Generator 2 secondary trigger selected 10000 = PWM Generator 3 secondary trigger selected 10001 = PWM Generator 4 secondary trigger selected 10010 = PWM Generator 5 secondary trigger selected 10011 = PWM Generator 6 secondary trigger selected 10100 = PWM Generator 7 secondary trigger selected 10101 = PWM Generator 8 secondary trigger selected 10110 = PWM Generator 9 secondary trigger selected 10111 = PWM Generator 1 current-limit ADC trigger 11000 = PWM Generator 2 current-limit ADC trigger 11001 = PWM Generator 3 current-limit ADC trigger 11010 = PWM Generator 4 current-limit ADC trigger 11011 = PWM Generator 5 current-limit ADC trigger 11100 = PWM Generator 6 current-limit ADC trigger 11101 = PWM Generator 7 current-limit ADC trigger 11110 = PWM Generator 8 current-limit ADC trigger 11111 = Timer2 period match Note 1: The trigger source must be set as a global software trigger prior to setting this bit to `1'. If other conversions are in progress, the conversion will be performed when the conversion resources are available. 2009 Microchip Technology Inc. Preliminary DS70591B-page 321 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 REGISTER 22-9: R/W-0 IRQEN7 bit 15 R/W-0 IRQEN6 bit 7 Legend: R = Readable bit -n = Value at POR bit 15 ADCPC3: A/D CONVERT PAIR CONTROL REGISTER 3 R/W-0 SWTRG7 R/W-0 R/W-0 R/W-0 TRGSRC7<4:0> R/W-0 R/W-0 bit 8 R/W-0 PEND7 R/W-0 PEND6 R/W-0 SWTRG6 R/W-0 R/W-0 R/W-0 TRGSRC6<4:0> R/W-0 R/W-0 bit 0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown bit 14 bit 13 bit 12-8 IRQEN7: Interrupt Request Enable 7 bit 1 = Enable IRQ generation when requested conversion of channels AN15 and AN14 is completed 0 = IRQ is not generated PEND7: Pending Conversion Status 7 bit 1 = Conversion of channels AN15 and AN14 is pending; set when selected trigger is asserted 0 = Conversion is complete SWTRG7: Software Trigger 7 bit 1 = Start conversion of AN15 and AN14 (if selected in TRGSRC bits)(1) This bit is automatically cleared by hardware when the PEND7 bit is set. 0 = Conversion is not started TRGSRC7<4:0>: Trigger 7 Source Selection bits Selects trigger source for conversion of analog channels AN15 and 14. 00000 = No conversion enabled 00001 = Individual software trigger selected 00010 = Global software trigger selected 00011 = PWM Special Event Trigger selected 00100 = PWM Generator 1 primary trigger selected 00101 = PWM Generator 2 primary trigger selected 00110 = PWM Generator 3 primary trigger selected 00111 = PWM Generator 4 primary trigger selected 01000 = PWM Generator 5 primary trigger selected 01001 = PWM Generator 6 primary trigger selected 01010 = PWM Generator 7 primary trigger selected 01011 = PWM Generator 8 primary trigger selected 01100 = Timer1 period match 01101 = Secondary special event trigger selected 01110 = PWM Generator 1 secondary trigger selected 01111 = PWM Generator 2 secondary trigger selected 10000 = PWM Generator 3 secondary trigger selected 10001 = PWM Generator 4 secondary trigger selected 10010 = PWM Generator 5 secondary trigger selected 10011 = PWM Generator 6 secondary trigger selected 10100 = PWM Generator 7 secondary trigger selected 10101 = PWM Generator 8 secondary trigger selected 10110 = PWM Generator 9 secondary trigger selected 10111 = PWM Generator 1 current-limit ADC trigger 11000 = PWM Generator 2 current-limit ADC trigger 11001 = PWM Generator 3 current-limit ADC trigger 11010 = PWM Generator 4 current-limit ADC trigger 11011 = PWM Generator 5 current-limit ADC trigger 11100 = PWM Generator 6 current-limit ADC trigger 11101 = PWM Generator 7 current-limit ADC trigger 11110 = PWM Generator 8 current-limit ADC trigger 11111 = Timer2 period match Note 1: The trigger source must be set as a global software trigger prior to setting this bit to `1'. If other conversions are in progress, the conversion will be performed when the conversion resources are available. DS70591B-page 322 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 REGISTER 22-9: bit 7 ADCPC3: A/D CONVERT PAIR CONTROL REGISTER 3 (CONTINUED) bit 6 bit 5 bit 4-0 IRQEN6: Interrupt Request Enable 6 bit 1 = Enable IRQ generation when requested conversion of channels AN13 and AN12 is completed 0 = IRQ is not generated PEND6: Pending Conversion Status 6 bit 1 = Conversion of channels AN13 and AN12 is pending; set when selected trigger is asserted 0 = Conversion is complete SWTRG6: Software Trigger 6 bit 1 = Start conversion of AN13 and AN12 (if selected by TRGSRC bits)(1) This bit is automatically cleared by hardware when the PEND6 bit is set. 0 = Conversion is not started TRGSRC6<4:0>: Trigger 6 Source Selection bits Selects trigger source for conversion of analog channels AN13 and AN12. 00000 = No conversion enabled 00001 = Individual software trigger selected 00010 = Global software trigger selected 00011 = PWM Special Event Trigger selected 00100 = PWM Generator 1 primary trigger selected 00101 = PWM Generator 2 primary trigger selected 00110 = PWM Generator 3 primary trigger selected 00111 = PWM Generator 4 primary trigger selected 01000 = PWM Generator 5 primary trigger selected 01001 = PWM Generator 6 primary trigger selected 01010 = PWM Generator 7 primary trigger selected 01011 = PWM Generator 8 primary trigger selected 01100 = Timer1 period match 01101 = Secondary special event trigger selected 01110 = PWM Generator 1 secondary trigger selected 01111 = PWM Generator 2 secondary trigger selected 10000 = PWM Generator 3 secondary trigger selected 10001 = PWM Generator 4 secondary trigger selected 10010 = PWM Generator 5 secondary trigger selected 10011 = PWM Generator 6 secondary trigger selected 10100 = PWM Generator 7 secondary trigger selected 10101 = PWM Generator 8 secondary trigger selected 10110 = PWM Generator 9 secondary trigger selected 10111 = PWM Generator 1 current-limit ADC trigger 11000 = PWM Generator 2 current-limit ADC trigger 11001 = PWM Generator 3 current-limit ADC trigger 11010 = PWM Generator 4 current-limit ADC trigger 11011 = PWM Generator 5 current-limit ADC trigger 11100 = PWM Generator 6 current-limit ADC trigger 11101 = PWM Generator 7 current-limit ADC trigger 11110 = PWM Generator 8 current-limit ADC trigger 11111 = Timer2 period match Note 1: The trigger source must be set as a global software trigger prior to setting this bit to `1'. If other conversions are in progress, the conversion will be performed when the conversion resources are available. 2009 Microchip Technology Inc. Preliminary DS70591B-page 323 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 REGISTER 22-10: ADCPC4: A/D CONVERT PAIR CONTROL REGISTER 4 R/W-0 IRQEN9 bit 15 R/W-0 IRQEN8 bit 7 Legend: R = Readable bit -n = Value at POR bit 15 R/W-0 PEND9 R/W-0 SWTRG9 R/W-0 R/W-0 R/W-0 TRGSRC9<4:0> R/W-0 R/W-0 bit 8 R/W-0 PEND8 R/W-0 SWTRG8 R/W-0 R/W-0 R/W-0 TRGSRC8<4:0> R/W-0 R/W-0 bit 0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown bit 14 bit 13 bit 12-8 IRQEN9: Interrupt Request Enable 9 bit 1 = Enable IRQ generation when requested conversion of channels AN19 and AN18 is completed 0 = IRQ is not generated PEND9: Pending Conversion Status 9 bit 1 = Conversion of channels AN19 and AN18 is pending; set when selected trigger is asserted 0 = Conversion is complete SWTRG9: Software Trigger 9 bit 1 = Start conversion of AN19 and AN18 (if selected in TRGSRC bits)(1) This bit is automatically cleared by hardware when the PEND9 bit is set. 0 = Conversion is not started TRGSRC9<4:0>: Trigger 9 Source Selection bits Selects trigger source for conversion of analog channels AN19 and AN18. 00000 = No conversion enabled 00001 = Individual software trigger selected 00010 = Global software trigger selected 00011 = PWM Special Event Trigger selected 00100 = PWM Generator 1 primary trigger selected 00101 = PWM Generator 2 primary trigger selected 00110 = PWM Generator 3 primary trigger selected 00111 = PWM Generator 4 primary trigger selected 01000 = PWM Generator 5 primary trigger selected 01001 = PWM Generator 6 primary trigger selected 01010 = PWM Generator 7 primary trigger selected 01011 = PWM Generator 8 primary trigger selected 01100 = Timer1 period match 01101 = PWM secondary special event trigger selected 01110 = PWM Generator 1 secondary trigger selected 01111 = PWM Generator 2 secondary trigger selected 10000 = PWM Generator 3 secondary trigger selected 10001 = PWM Generator 4 secondary trigger selected 10010 = PWM Generator 5 secondary trigger selected 10011 = PWM Generator 6 secondary trigger selected 10100 = PWM Generator 7 secondary trigger selected 10101 = PWM Generator 8 secondary trigger selected 10110 = PWM Generator 9 secondary trigger selected 10111 = PWM Generator 1 current-limit ADC trigger 11000 = PWM Generator 2 current-limit ADC trigger 11001 = PWM Generator 3 current-limit ADC trigger 11010 = PWM Generator 4 current-limit ADC trigger 11011 = PWM Generator 5 current-limit ADC trigger 11100 = PWM Generator 6 current-limit ADC trigger 11101 = PWM Generator 7 current-limit ADC trigger 11110 = PWM Generator 8 current-limit ADC trigger 11111 = Timer2 period match Note 1: The trigger source must be set as a global software trigger prior to setting this bit to `1'. If other conversions are in progress, the conversion will be performed when the conversion resources are available. DS70591B-page 324 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 REGISTER 22-10: ADCPC4: A/D CONVERT PAIR CONTROL REGISTER 4 (CONTINUED) bit 7 IRQEN8: Interrupt Request Enable 8 bit 1 = Enable IRQ generation when requested conversion of channels AN17 and AN16 is completed 0 = IRQ is not generated PEND8: Pending Conversion Status 8 bit 1 = Conversion of channels AN17 and AN16 is pending; set when selected trigger is asserted 0 = Conversion is complete SWTRG8: Software Trigger 8 bit 1 = Start conversion of AN17 and AN16 (if selected by TRGSRC bits)(1) This bit is automatically cleared by hardware when the PEND8 bit is set. 0 = Conversion is not started TRGSRC8<4:0>: Trigger 8 Source Selection bits Selects trigger source for conversion of analog channels AN17 and AN16. 00000 = No conversion enabled 00001 = Individual software trigger selected 00010 = Global software trigger selected 00011 = PWM Special Event Trigger selected 00100 = PWM Generator 1 primary trigger selected 00101 = PWM Generator 2 primary trigger selected 00110 = PWM Generator 3 primary trigger selected 00111 = PWM Generator 4 primary trigger selected 01000 = PWM Generator 5 primary trigger selected 01001 = PWM Generator 6 primary trigger selected 01010 = PWM Generator 7 primary trigger selected 01011 = PWM Generator 8 primary trigger selected 01100 = Timer1 period match 01101 = PWM secondary special event trigger selected 01110 = PWM Generator 1 secondary trigger selected 01111 = PWM Generator 2 secondary trigger selected 10000 = PWM Generator 3 secondary trigger selected 10001 = PWM Generator 4 secondary trigger selected 10010 = PWM Generator 5 secondary trigger selected 10011 = PWM Generator 6 secondary trigger selected 10100 = PWM Generator 7 secondary trigger selected 10101 = PWM Generator 8 secondary trigger selected 10110 = PWM Generator 9 secondary trigger selected 10111 = PWM Generator 1 current-limit ADC trigger 11000 = PWM Generator 2 current-limit ADC trigger 11001 = PWM Generator 3 current-limit ADC trigger 11010 = PWM Generator 4 current-limit ADC trigger 11011 = PWM Generator 5 current-limit ADC trigger 11100 = PWM Generator 6 current-limit ADC trigger 11101 = PWM Generator 7 current-limit ADC trigger 11110 = PWM Generator 8 current-limit ADC trigger 11111 = Timer2 period match bit 6 bit 5 bit 4-0 Note 1: The trigger source must be set as a global software trigger prior to setting this bit to `1'. If other conversions are in progress, the conversion will be performed when the conversion resources are available. 2009 Microchip Technology Inc. Preliminary DS70591B-page 325 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 REGISTER 22-11: ADCPC5: A/D CONVERT PAIR CONTROL REGISTER 5 R/W-0 IRQEN11 bit 15 R/W-0 IRQEN10 bit 7 R/W-0 PEND11 R/W-0 SWTRG11 R/W-0 R/W-0 R/W-0 TRGSRC11<4:0> R/W-0 R/W-0 bit 8 R/W-0 PEND10 R/W-0 SWTRG10 R/W-0 R/W-0 R/W-0 TRGSRC10<4:0> R/W-0 R/W-0 bit 0 Legend: R = Readable bit -n = Value at POR bit 15 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown bit 14 bit 13 bit 12-8 IRQEN11: Interrupt Request Enable 11 bit 1 = Enable IRQ generation when requested conversion of channels AN23 and AN22 is completed 0 = IRQ is not generated PEND11: Pending Conversion Status 11 bit 1 = Conversion of channels AN23 and AN22 is pending; set when selected trigger is asserted 0 = Conversion is complete SWTRG11: Software Trigger 11 bit 1 = Start conversion of AN23 and AN22 (if selected in TRGSRC bits)(1). This bit is automatically cleared by hardware when the PEND11 bit is set. 0 = Conversion is not started TRGSRC11<4:0>: Trigger 11 Source Selection bits Selects trigger source for conversion of analog channels AN23 and AN22. 00000 = No conversion enabled 00001 = Individual software trigger selected 00010 = Global software trigger selected 00011 = PWM Special Event Trigger selected 00100 = PWM Generator 1 primary trigger selected 00101 = PWM Generator 2 primary trigger selected 00110 = PWM Generator 3 primary trigger selected 00111 = PWM Generator 4 primary trigger selected 01000 = PWM Generator 5 primary trigger selected 01001 = PWM Generator 6 primary trigger selected 01010 = PWM Generator 7 primary trigger selected 01011 = PWM Generator 8 primary trigger selected 01100 = Timer1 period match 01101 = PWM secondary special event trigger selected 01110 = PWM Generator 1 secondary trigger selected 01111 = PWM Generator 2 secondary trigger selected 10000 = PWM Generator 3 secondary trigger selected 10001 = PWM Generator 4 secondary trigger selected 10010 = PWM Generator 5 secondary trigger selected 10011 = PWM Generator 6 secondary trigger selected 10100 = PWM Generator 7 secondary trigger selected 10101 = PWM Generator 8 secondary trigger selected 10110 = PWM Generator 9 secondary trigger selected 10111 = PWM Generator 1 current-limit ADC trigger 11000 = PWM Generator 2 current-limit ADC trigger 11001 = PWM Generator 3 current-limit ADC trigger 11010 = PWM Generator 4 current-limit ADC trigger 11011 = PWM Generator 5 current-limit ADC trigger 11100 = PWM Generator 6 current-limit ADC trigger 11101 = PWM Generator 7 current-limit ADC trigger 11110 = PWM Generator 8 current-limit ADC trigger 11111 = Timer2 period match Note 1: The trigger source must be set as a global software trigger prior to setting this bit to `1'. If other conversions are in progress, the conversion will be performed when the conversion resources are available. DS70591B-page 326 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 REGISTER 22-11: ADCPC5: A/D CONVERT PAIR CONTROL REGISTER 5 (CONTINUED) bit 7 IRQEN10: Interrupt Request Enable 10 bit 1 = Enable IRQ generation when requested conversion of channels AN21 and AN20 is completed 0 = IRQ is not generated PEND10: Pending Conversion Status 10 bit 1 = Conversion of channels AN21 and AN20 is pending; set when selected trigger is asserted 0 = Conversion is complete SWTRG10: Software Trigger 10 bit 1 = Start conversion of AN21 and AN20 (if selected by TRGSRC bits)(1). This bit is automatically cleared by hardware when the PEND10 bit is set. 0 = Conversion is not started TRGSRC10<4:0>: Trigger 10 Source Selection bits Selects trigger source for conversion of analog channels AN21 and AN20. 00000 = No conversion enabled 00001 = Individual software trigger selected 00010 = Global software trigger selected 00011 = PWM Special Event Trigger selected 00100 = PWM Generator 1 primary trigger selected 00101 = PWM Generator 2 primary trigger selected 00110 = PWM Generator 3 primary trigger selected 00111 = PWM Generator 4 primary trigger selected 01000 = PWM Generator 5 primary trigger selected 01001 = PWM Generator 6 primary trigger selected 01010 = PWM Generator 7 primary trigger selected 01011 = PWM Generator 8 primary trigger selected 01100 = Timer1 period match 01101 = PWM secondary special event trigger selected 01110 = PWM Generator 1 secondary trigger selected 01111 = PWM Generator 2 secondary trigger selected 10000 = PWM Generator 3 secondary trigger selected 10001 = PWM Generator 4 secondary trigger selected 10010 = PWM Generator 5 secondary trigger selected 10011 = PWM Generator 6 secondary trigger selected 10100 = PWM Generator 7 secondary trigger selected 10101 = PWM Generator 8 secondary trigger selected 10110 = PWM Generator 9 secondary trigger selected 10111 = PWM Generator 1 current-limit ADC trigger 11000 = PWM Generator 2 current-limit ADC trigger 11001 = PWM Generator 3 current-limit ADC trigger 11010 = PWM Generator 4 current-limit ADC trigger 11011 = PWM Generator 5 current-limit ADC trigger 11100 = PWM Generator 6 current-limit ADC trigger 11101 = PWM Generator 7 current-limit ADC trigger 11110 = PWM Generator 8 current-limit ADC trigger 11111 = Timer2 period match bit 6 bit 5 bit 4-0 Note 1: The trigger source must be set as a global software trigger prior to setting this bit to `1'. If other conversions are in progress, the conversion will be performed when the conversion resources are available. 2009 Microchip Technology Inc. Preliminary DS70591B-page 327 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 REGISTER 22-12: ADCPC6: A/D CONVERT PAIR CONTROL REGISTER 6 U-0 -- bit 15 R/W-0 IRQEN12 bit 7 U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 R/W-0 PEND12 R/W-0 SWTRG12 R/W-0 R/W-0 R/W-0 TRGSRC12<4:0> R/W-0 R/W-0 bit 0 Legend: R = Readable bit -n = Value at POR bit 15-8 bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown bit 6 bit 5 bit 4-0 Unimplemented: Read as `0' IRQEN12: Interrupt Request Enable 12 bit 1 = Enable IRQ generation when requested conversion of channels AN25 and AN24 is completed 0 = IRQ is not generated PEND12: Pending Conversion Status 12 bit 1 = Conversion of channels AN25 and AN24 is pending; set when selected trigger is asserted 0 = Conversion is complete SWTRG12: Software Trigger 12 bit 1 = Start conversion of AN25 (INTREF) and AN24 (EXTREF) if selected by TRGSRC bits(1) This bit is automatically cleared by hardware when the PEND12 bit is set. 0 = Conversion is not started. TRGSRC12<4:0>: Trigger 12 Source Selection bits Selects trigger source for conversion of analog channels AN25 and AN24. 00000 = No conversion enabled 00001 = Individual software trigger selected 00010 = Global software trigger selected 00011 = PWM Special Event Trigger selected 00100 = PWM Generator 1 primary trigger selected 00101 = PWM Generator 2 primary trigger selected 00110 = PWM Generator 3 primary trigger selected 00111 = PWM Generator 4 primary trigger selected 01000 = PWM Generator 5 primary trigger selected 01001 = PWM Generator 6 primary trigger selected 01010 = PWM Generator 7 primary trigger selected 01011 = PWM Generator 8 primary trigger selected 01100 = Timer1 period match 01101 = PWM secondary special event trigger selected 01110 = PWM Generator 1 secondary trigger selected 01111 = PWM Generator 2 secondary trigger selected 10000 = PWM Generator 3 secondary trigger selected 10001 = PWM Generator 4 secondary trigger selected 10010 = PWM Generator 5 secondary trigger selected 10011 = PWM Generator 6 secondary trigger selected 10100 = PWM Generator 7 secondary trigger selected 10101 = PWM Generator 8 secondary trigger selected 10110 = PWM Generator 9 secondary trigger selected 10111 = PWM Generator 1 current-limit ADC trigger 11000 = PWM Generator 2 current-limit ADC trigger 11001 = PWM Generator 3 current-limit ADC trigger 11010 = PWM Generator 4 current-limit ADC trigger 11011 = PWM Generator 5 current-limit ADC trigger 11100 = PWM Generator 6 current-limit ADC trigger 11101 = PWM Generator 7 current-limit ADC trigger 11110 = PWM Generator 8 current-limit ADC trigger 11111 = Timer2 period match Note 1: The trigger source must be set as a global software trigger prior to setting this bit to `1'. If other conversions are in progress, the conversion will be performed when the conversion resources are available. DS70591B-page 328 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 23.0 HIGH-SPEED ANALOG COMPARATOR * Interrupt generation capability * DACOUT pin to provide DAC output * DAC has three ranges of operation: - AVDD/2 - Internal Reference 1.2V, 1% - External Reference < (AVDD - 1.6V) * ADC sample and convert trigger capability * Disable capability reduces power consumption * Functional support for PWM module: - PWM duty cycle control - PWM period control - PWM Fault detect Note 1: This data sheet summarizes the features of the dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 45. "High-Speed Analog Comparator" (DS70296) in the "dsPIC33F/PIC24H Family Reference Manual", which is available from the Microchip web site (www.microchip.com). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 "Memory Organization" in this data sheet for device-specific register and bit information. The dsPIC33F SMPS Comparator module monitors current and/or voltage transients that may be too fast for the CPU and ADC to capture. 23.2 Module Description 23.1 Features Overview Figure 23-1 shows a functional block diagram of one analog comparator from the SMPS comparator module. The analog comparator provides high-speed operation with a typical delay of 20 ns. The comparator has a typical offset voltage of 5 mV. The negative input of the comparator is always connected to the DAC circuit. The positive input of the comparator is connected to an analog multiplexer that selects the desired source pin. The analog comparator input pins are typically shared with pins used by the Analog-to-Digital Converter (ADC) module. Both the comparator and the ADC can use the same pins at the same time. This capability enables a user to measure an input voltage with the ADC and detect voltage transients with the comparator. The SMPS comparator module offers the following major features: * * * * 16 selectable comparator inputs Up to four analog comparators 10-bit DAC for each analog comparator Programmable output polarity FIGURE 23-1: CMPxA* CMPxB* CMPxC* CMPxD* *x = 1, 2, 3, and 4 COMPARATOR MODULE BLOCK DIAGRAM INSEL<1:0> M U X CMPx* 0 1 RANGE CMPPOL Trigger to PWM Status Glitch Filter Pulse Generator AVDD/2 INTREF M U X DAC AVSS 10 DACOE DACOUT Interrupt Request CMREF EXTREF 2009 Microchip Technology Inc. Preliminary DS70591B-page 329 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 23.3 Module Applications 23.5 Interaction with I/O Buffers This module provides a means for the SMPS dsPIC DSC devices to monitor voltage and currents in a power conversion application. The ability to detect transient conditions and stimulate the dsPIC DSC processor and/or peripherals, without requiring the processor and ADC to constantly monitor voltages or currents, frees the dsPIC DSC to perform other tasks. The comparator module has a high-speed comparator and an associated 10-bit DAC that provides a programmable reference voltage to the inverting input of the comparator. The polarity of the comparator output is user-programmable. The output of the module can be used in the following modes: * * * * * Generate an Interrupt Trigger an ADC Sample and Convert Process Truncate the PWM Signal (current limit) Truncate the PWM Period (current minimum) Disable the PWM Outputs (Fault latch) If the comparator module is enabled and a pin has been selected as the source for the comparator, then the chosen I/O pad must disable the digital input buffer associated with the pad to prevent excessive currents in the digital buffer due to analog input voltages. 23.6 Digital Logic The CMPCONx register (see Register 23-1) provides the control logic that configures the comparator module. The digital logic provides a glitch filter for the comparator output to mask transient signals in less than two instruction cycles. In Sleep or Idle mode, the glitch filter is bypassed to enable an asynchronous path from the comparator to the interrupt controller. This asynchronous path can be used to wake-up the processor from Sleep or Idle mode. The comparator can be disabled while in Idle mode if the CMPSIDL bit is set. If a device has multiple comparators, if any CMPSIDL bit is set, then the entire group of comparators will be disabled while in Idle mode. This behavior reduces complexity in the design of the clock control logic for this module. The digital logic also provides a one TCY width pulse generator for triggering the ADC and generating interrupt requests. The CMPDACx (see Register 23-2) register provides the digital input value to the reference DAC. If the module is disabled, the DAC and comparator are disabled to reduce power consumption. The output of the comparator module may be used in multiple modes at the same time, such as: (1) generate an interrupt, (2) have the ADC take a sample and convert it, and (3) truncate the PWM output in response to a voltage being detected beyond its expected value. The comparator module can also be used to wake-up the system from Sleep or Idle mode when the analog input voltage exceeds the programmed threshold voltage. 23.4 DAC The range of the DAC is controlled via an analog multiplexer that selects either AVDD/2, internal 1.2V, 1% reference, or an external reference source, EXTREF. The full range of the DAC (AVDD/2) will typically be used when the chosen input source pin is shared with the ADC. The reduced range option (INTREF) will likely be used when monitoring current levels using a current sense resistor. Usually, the measured voltages in such applications are small (<1.25V); therefore the option of using a reduced reference range for the comparator extends the available DAC resolution in these applications. The use of an external reference enables the user to connect to a reference that better suits their application. DACOUT, shown in Figure 23-1, can only be associated with a single comparator at a given time. Note: It should be ensured in software that multiple DACOE bits are not set. The output on the DACOUT pin will be indeterminate if multiple comparators enable the DAC output. 23.7 Comparator Input Range The comparator has a limitation for the input Common Mode Range (CMR) of (AVDD - 1.5V), typical. This means that both inputs should not exceed this range. As long as one of the inputs is within the Common Mode Range, the comparator output will be correct. However, any input exceeding the CMR limitation will cause the comparator input to be saturated. If both inputs exceed the CMR, the comparator output will be indeterminate. 23.8 DAC Output Range The DAC has a limitation for the maximum reference voltage input of (AVDD - 1.6) volts. An external reference voltage input should not exceed this value or the reference DAC output will become indeterminate. 23.9 Comparator Registers The comparator module is controlled by the following registers: * CMPCONx: Comparator Control Register * CMPDACx: Comparator DAC Control Register DS70591B-page 330 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 REGISTER 23-1: R/W-0 CMPON bit 15 R/W-0 bit 7 Legend: R = Readable bit -n = Value at POR bit 15 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 R/W-0 EXTREF U-0 -- R/W-0 CMPSTAT U-0 -- R/W-0 CMPPOL CMPCONx: COMPARATOR CONTROL REGISTER U-0 -- R/W-0 CMPSIDL U-0 -- U-0 -- U-0 -- U-0 -- R/W-0 DACOE bit 8 R/W-0 RANGE bit 0 INSEL<1:0> CMPON: Comparator Operating Mode bit 1 = Comparator module is enabled 0 = Comparator module is disabled (reduces power consumption) Unimplemented: Read as `0' CMPSIDL: Stop in Idle Mode bit 1 = Discontinue module operation when device enters Idle mode. 0 = Continue module operation in Idle mode If a device has multiple comparators, any CMPSIDL bit set to `1' disables ALL comparators while in Idle mode. Reserved: Read as `0' DACOE: DAC Output Enable 1 = DAC analog voltage is output to DACOUT pin(1) 0 = DAC analog voltage is not connected to DACOUT pin INSEL<1:0>: Input Source Select for Comparator bits 00 = Select CMPxA input pin 01 = Select CMPxB input pin 10 = Select CMPxC input pin 11 = Select CMPxD input pin EXTREF: Enable External Reference bit 1 = External source provides reference to DAC (maximum DAC voltage determined by external voltage source) 0 = Internal reference sources provide reference to DAC (maximum DAC voltage determined by RANGE bit setting) Reserved: Read as `0' CMPSTAT: Current State of Comparator Output Including CMPPOL Selection bit Reserved: Read as `0' CMPPOL: Comparator Output Polarity Control bit 1 = Output is inverted 0 = Output is non-inverted RANGE: Selects DAC Output Voltage Range bit 1 = High Range: Max DAC Value = AVDD/2, 1.65V at 3.3V AVDD 0 = Low Range: Max DAC Value = INTREF, 1.2V, 1% DACOUT can be associated only with a single comparator at any given time. The software must ensure that multiple comparators do not enable the DAC output by setting their respective DACOE bit. bit 14 bit 13 bit 12-9 bit 8 bit 7-6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Note 1: 2009 Microchip Technology Inc. Preliminary DS70591B-page 331 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 REGISTER 23-2: U-0 -- bit 15 R/W-0 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-10 bit 9-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CMPDACx: COMPARATOR DAC CONTROL REGISTER U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- R/W-0 R/W-0 bit 8 R/W-0 bit 0 CMREF<9:8> CMREF<7:0> Reserved: Read as `0' CMREF<9:0>: Comparator Reference Voltage Select bits 1111111111 = (CMREF * INTREF/1024) or (CMREF * (AVDD/2)/1024) volts depending on RANGE bit or (CMREF * EXTREF/1024) if EXTREF is set * * * 0000000000 = 0.0 volts DS70591B-page 332 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 24.0 SPECIAL FEATURES * * * * * * * Flexible Configuration Watchdog Timer (WDT) Code Protection and CodeGuardTM Security JTAG Boundary Scan Interface In-Circuit Serial ProgrammingTM (ICSPTM) In-Circuit Emulation Brown-out Reset (BOR) Note 1: This data sheet summarizes the features of the dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the "dsPIC33F/PIC24H Family Reference Manual". Please see the Microchip web site (www.microchip.com) for the latest "dsPIC33F/PIC24H Family Reference Manual" sections. 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 "Memory Organization" in this data sheet for device-specific register and bit information. The dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 devices include several features intended to maximize application flexibility and reliability, and minimize cost through elimination of external components. These are: 24.1 Configuration Bits The Configuration bits can be programmed (read as `0'), or left unprogrammed (read as `1'), to select various device configurations. These bits are mapped starting at program memory location 0xF80000. The individual Configuration bit descriptions for the Configuration registers are shown in Table 24-2. Note that address, 0xF80000, is beyond the user program memory space. It belongs to the configuration memory space (0x800000-0xFFFFFF), which can only be accessed using table reads and table writes. The device Configuration register map is shown in Table 24-1. TABLE 24-1: Address 0xF80000 FBS DEVICE CONFIGURATION REGISTER MAP Name Bit 7 -- -- -- IESO FWDTEN -- Reserved -- (1) Bit 6 -- -- -- -- WINDIS ALTQIO Reserved(1) -- Bit 5 -- -- -- -- -- -- ALTSS1 JTAGEN CMPPOL1(2) Bit 4 -- -- -- -- -- WDTPRE -- -- Bit 3 -- -- -- -- -- Bit 2 BSS<2:0> -- Bit 1 -- Bit 0 BWRP -- GWRP 0xF80002 RESERVED 0xF80004 FGS 0xF80006 FOSCSEL 0xF80008 FOSC 0xF8000A FWDT 0xF8000C FPOR 0xF8000E FICD 0xF80010 FCMP GSS<1:0> FNOSC<2:0> FCKSM<1:0> OSCIOFNC POSCMD<1:0> WDTPOST<3:0> FPWRT<2:0> -- CMPPOL0(2) ICS<1:0> HYST0<1:0>(2) HYST1<1:0>(2) Legend: -- = unimplemented bit, read as `0'. Note 1: These bits are reserved for use by development tools and must be programmed as `1'. 2: These bits are reserved on dsPIC33FJXXXGS406 devices and always read as `1'. 2009 Microchip Technology Inc. Preliminary DS70591B-page 333 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 TABLE 24-2: Bit Field BWRP dsPIC33F CONFIGURATION BITS DESCRIPTION Register FBS Description Boot Segment Program Flash Write Protection bit 1 = Boot segment can be written 0 = Boot segment is write-protected Boot Segment Program Flash Code Protection Size bits X11 = No boot program Flash segment Boot space is 256 instruction words (except interrupt vectors) 110 = Standard security; boot program Flash segment ends at 0x0003FE 010 = High security; boot program Flash segment ends at 0x0003FE Boot space is 768 instruction words (except interrupt vectors) 101 = Standard security; boot program Flash segment ends at 0x0007FE 001 = High security; boot program Flash segment ends at 0x0007FE Boot space is 1792 instruction words (except interrupt vectors) 100 = Standard security; boot program Flash segment ends at 0x000FFE 000 = High security; boot program Flash segment ends at 0x000FFE BSS<2:0> FBS GSS<1:0> FGS General Segment Code-Protect bits 11 = User program memory is not code-protected 10 = Standard security 0x = High security General Segment Write-Protect bit 1 = User program memory is not write-protected 0 = User program memory is write-protected Two-speed Oscillator Start-up Enable bit 1 = Start-up device with FRC, then automatically switch to the user-selected oscillator source when ready 0 = Start-up device with user-selected oscillator source Initial Oscillator Source Selection bits 111 = Internal Fast RC (FRC) oscillator with postscaler 110 = Internal Fast RC (FRC) oscillator with divide-by-16 101 = LPRC oscillator 100 = Secondary (LP) oscillator 011 = Primary (XT, HS, EC) oscillator with PLL 010 = Primary (XT, HS, EC) oscillator 001 = Internal Fast RC (FRC) oscillator with PLL 000 = FRC oscillator Clock Switching Mode bits 1x = Clock switching is disabled, Fail-Safe Clock Monitor is disabled 01 = Clock switching is enabled, Fail-Safe Clock Monitor is disabled 00 = Clock switching is enabled, Fail-Safe Clock Monitor is enabled OSC2 Pin Function bit (except in XT and HS modes) 1 = OSC2 is clock output 0 = OSC2 is general purpose digital I/O pin Primary Oscillator Mode Select bits 11 = Primary oscillator disabled 10 = HS Crystal Oscillator mode 01 = XT Crystal Oscillator mode 00 = EC (External Clock) mode GWRP FGS IESO FOSCSEL FNOSC<2:0> FOSCSEL FCKSM<1:0> FOSC OSCIOFNC FOSC POSCMD<1:0> FOSC DS70591B-page 334 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 TABLE 24-2: Bit Field FWDTEN dsPIC33F CONFIGURATION BITS DESCRIPTION (CONTINUED) Register FWDT Description Watchdog Timer Enable bit 1 = Watchdog Timer always enabled (LPRC oscillator cannot be disabled; clearing the SWDTEN bit in the RCON register will have no effect) 0 = Watchdog Timer enabled/disabled by user software (LPRC can be disabled by clearing the SWDTEN bit in the RCON register) Watchdog Timer Window Enable bit 1 = Watchdog Timer in Non-Window mode 0 = Watchdog Timer in Window mode Watchdog Timer Prescaler bit 1 = 1:128 0 = 1:32 Watchdog Timer Postscaler bits 1111 = 1:32,768 1110 = 1:16,384 * * * 0001 = 1:2 0000 = 1:1 Power-on Reset Timer Value Select bits 111 = PWRT = 128 ms 110 = PWRT = 64 ms 101 = PWRT = 32 ms 100 = PWRT = 16 ms 011 = PWRT = 8 ms 010 = PWRT = 4 ms 001 = PWRT = 2 ms 000 = PWRT = Disabled JTAG Enable bit 1 = JTAG is enabled 0 = JTAG is disabled ICD Communication Channel Select Enable bits 11 = Communicate on PGEC1 and PGED1 10 = Communicate on PGEC2 and PGED2 01 = Communicate on PGEC3 and PGED3 00 = Reserved, do not use. Enable Alternate QEI1 pin bit 1 = QEA1, QEB1 and INDX1 are selected as inputs to QEI1 0 = AQEA1, AQEB1 and AINDX1 are selected as inputs to QEI1 Enable Alternate SS1 pin bit 1 = ASS1 is selected as the I/O pin for SPI1 0 = SS1 is selected as the I/O pin for SPI1 Comparator Hysteresis Polarity (for even numbered comparators) 1 = Hysteresis is applied to falling edge 0 = Hysteresis is applied to rising edge Comparator Hysteresis Select 11 = 45 mV Hysteresis 10 = 30 mV Hysteresis 01 = 15 mV Hysteresis 00 = No Hysteresis WINDIS FWDT WDTPRE FWDT WDTPOST<3:0> FWDT FPWRT<2:0> FPOR JTAGEN FICD ICS<1:0> FICD ALTQIO FPOR ALTSS1 FPOR CMPPOL0 FCMP HYST0<1:0> FCMP 2009 Microchip Technology Inc. Preliminary DS70591B-page 335 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 TABLE 24-2: Bit Field CMPPOL1 dsPIC33F CONFIGURATION BITS DESCRIPTION (CONTINUED) Register FCMP Description Comparator Hysteresis Polarity (for odd numbered comparators) 1 = Hysteresis is applied to falling edge 0 = Hysteresis is applied to rising edge Comparator Hysteresis Select 11 = 45 mV Hysteresis 10 = 30 mV Hysteresis 01 = 15 mV Hysteresis 00 = No Hysteresis HYST1<1:0> FCMP 24.2 On-Chip Voltage Regulator FIGURE 24-1: The dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 devices power their core digital logic at a nominal 2.5V. This can create a conflict for designs that are required to operate at a higher typical voltage, such as 3.3V. To simplify system design, all devices in the dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 families incorporate an on-chip regulator that allows the device to run its core logic from VDD. The regulator provides power to the core from the other VDD pins. When the regulator is enabled, a low-ESR (less than 5 ohms) capacitor (such as tantalum or ceramic) must be connected to the VCAP/VDDCORE pin (Figure 24-1). This helps to maintain the stability of the regulator. The recommended value for the filter capacitor is provided in Table 27-13 located in Section 27.1 "DC Characteristics". Note: It is important for the low-ESR capacitor to be placed as close as possible to the VCAP/VDDCORE pin. CONNECTIONS FOR THE ON-CHIP VOLTAGE REGULATOR(1,2) dsPIC33F VDD VCAP/VDDCORE 3.3V CEFC VSS Note 1: 2: These are typical operating voltages. Refer to Table 27-13 located in Section 27.1 "DC Characteristics" for the full operating ranges of VDD and VCAP/VDDCORE. It is important for the low-ESR capacitor to be placed as close as possible to the VCAP/ VDDCORE pin. On a POR, it takes approximately 20 s for the on-chip voltage regulator to generate an output voltage. During this time, designated as TSTARTUP, code execution is disabled. TSTARTUP is applied every time the device resumes operation after any power-down. DS70591B-page 336 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 24.3 BOR: Brown-Out Reset after changing the NOSC bits) or by hardware (i.e., Fail-Safe Clock Monitor) * When a PWRSAV instruction is executed (i.e., Sleep or Idle mode is entered) * When the device exits Sleep or Idle mode to resume normal operation * By a CLRWDT instruction during normal execution Note: The CLRWDT and PWRSAV instructions clear the prescaler and postscaler counts when executed. The Brown-out Reset (BOR) module is based on an internal voltage reference circuit that monitors the regulated supply voltage VCAP/VDDCORE. The main purpose of the BOR module is to generate a device Reset when a brown-out condition occurs. Brown-out conditions are generally caused by glitches on the AC mains (for example, missing portions of the AC cycle waveform due to bad power transmission lines, or voltage sags due to excessive current draw when a large inductive load is turned on). A BOR generates a Reset pulse, which resets the device. The BOR selects the clock source, based on the device Configuration bit values (FNOSC<2:0> and POSCMD<1:0>). If an oscillator mode is selected, the BOR activates the Oscillator Start-up Timer (OST). The system clock is held until OST expires. If the PLL is used, the clock is held until the LOCK bit (OSCCON<5>) is `1'. Concurrently, the PWRT time-out (TPWRT) is applied before the internal Reset is released. If TPWRT = 0 and a crystal oscillator is being used, then a nominal delay of TFSCM = 100 is applied. The total delay in this case is TFSCM. The BOR Status bit (RCON<1>) is set to indicate that a BOR has occurred. The BOR circuit continues to operate while in Sleep or Idle modes and resets the device should VDD fall below the BOR threshold voltage. 24.4.2 SLEEP AND IDLE MODES If the WDT is enabled, it will continue to run during Sleep or Idle modes. When the WDT time-out occurs, the WDT will wake the device and code execution will continue from where the PWRSAV instruction was executed. The corresponding SLEEP or IDLE bits (RCON<3:2>) will need to be cleared in software after the device wakes up. 24.4.3 ENABLING WDT The WDT is enabled or disabled by the FWDTEN Configuration bit in the FWDT Configuration register. When the FWDTEN Configuration bit is set, the WDT is always enabled. The WDT can be optionally controlled in software when the FWDTEN Configuration bit has been programmed to `0'. The WDT is enabled in software by setting the SWDTEN control bit (RCON<5>). The SWDTEN control bit is cleared on any device Reset. The software WDT option allows the user application to enable the WDT for critical code segments and disable the WDT during non-critical segments for maximum power savings. Note: If the WINDIS bit (FWDT<6>) is cleared, the CLRWDT instruction should be executed by the application software only during the last 1/4 of the WDT period. This CLRWDT window can be determined by using a timer. If a CLRWDT instruction is executed before this window, a WDT Reset occurs. 24.4 Watchdog Timer (WDT) For dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 devices, the WDT is driven by the LPRC oscillator. When the WDT is enabled, the clock source is also enabled. 24.4.1 PRESCALER/POSTSCALER The nominal WDT clock source from LPRC is 32.767 kHz. This feeds a prescaler that can be configured for either 5-bit (divide-by-32) or 7-bit (divide-by128) operation. The prescaler is set by the WDTPRE Configuration bit. With a 32.767 kHz input, the prescaler yields a nominal WDT time-out period (TWDT) of 1 ms in 5-bit mode, or 4 ms in 7-bit mode. A variable postscaler divides down the WDT prescaler output and allows for a wide range of time-out periods. The postscaler is controlled by the WDTPOST<3:0> Configuration bits (FWDT<3:0>) which allow the selection of 16 settings, from 1:1 to 1:32,768. Using the prescaler and postscaler, time-out periods ranging from 1 ms to 131 seconds can be achieved. The WDT, prescaler and postscaler are reset: * On any device Reset * On the completion of a clock switch, whether invoked by software (i.e., setting the OSWEN bit The WDT flag bit, WDTO (RCON<4>), is not automatically cleared following a WDT time-out. To detect subsequent WDT events, the flag must be cleared in software. 2009 Microchip Technology Inc. Preliminary DS70591B-page 337 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 FIGURE 24-2: WDT BLOCK DIAGRAM All Device Resets Transition to New Clock Source Exit Sleep or Idle Mode PWRSAV Instruction CLRWDT Instruction Watchdog Timer Sleep/Idle SWDTEN FWDTEN WDTPRE WDTPOST<3:0> WDT Wake-up 1 WDT Reset LPRC Clock RS Prescaler (Divide by N1) RS Postscaler (Divide by N2) 0 WINDIS WDT Window Select CLRWDT Instruction 24.5 JTAG Interface 24.7 In-Circuit Debugger dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 devices implement a JTAG interface, which supports boundary scan device testing, as well as in-circuit programming. Detailed information on this interface will be provided in future revisions of the document. When MPLAB(R) ICD 2 is selected as a debugger, the incircuit debugging functionality is enabled. This function allows simple debugging functions when used with MPLAB IDE. Debugging functionality is controlled through the EMUCx (Emulation/Debug Clock) and EMUDx (Emulation/Debug Data) pin functions. Any of the three pairs of debugging clock/data pins can be used: * PGEC1 and PGED1 * PGEC2 and PGED2 * PGEC3 and PGED3 To use the in-circuit debugger function of the device, the design must implement ICSP connections to MCLR, VDD, VSS, PGC, PGD and the EMUDx/EMUCx pin pair. In addition, when the feature is enabled, some of the resources are not available for general use. These resources include the first 80 bytes of data RAM and two I/O pins. 24.6 In-Circuit Serial Programming dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 family digital signal controllers can be serially programmed while in the end application circuit. This is done with two lines for clock and data and three other lines for power, ground and the programming sequence. Serial programming allows customers to manufacture boards with unprogrammed devices and then program the digital signal controller just before shipping the product. Serial programming also allows the most recent firmware or a custom firmware to be programmed. Refer to the "dsPIC33F/PIC24H Flash Programming Specification" (DS70152) for details about In-Circuit Serial Programming (ICSP). Any of the three pairs of programming clock/data pins can be used: * PGEC1 and PGED1 * PGEC2 and PGED2 * PGEC3 and PGED3 DS70591B-page 338 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 24.8 Code Protection and CodeGuardTM Security When coupled with software encryption libraries, CodeGuardTM Security can be used to securely update Flash even when multiple IPs reside on a single chip. The code protection features are controlled by the Configuration registers: FBS and FGS. Secure segment and RAM protection is not implemented in dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 devices. Note: Refer to the "CodeGuard Security Reference Manual" (DS70180) for further information on usage, configuration and operation of CodeGuard Security. The dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 devices offer the intermediate implementation of CodeGuardTM Security. CodeGuard Security enables multiple parties to securely share resources (memory, interrupts and peripherals) on a single chip. This feature helps protect individual Intellectual Property in collaborative system designs. TABLE 24-3: CODE FLASH SECURITY SEGMENT SIZES FOR 64K BYTE DEVICES BSS<2:0> = x10 1K VS = 256 IW BS = 768 IW 000000h 0001FEh 000200h 0007FEh 000800h BSS<2:0> = x11 0K VS = 256 IW 000000h 0001FEh 000200h BSS<2:0> = x01 4K VS = 256 IW BS = 3840 IW 000000h 0001FEh 000200h 001FFEh 002000h GS = 17920 IW BSS<2:0> = x00 8K VS = 256 IW BS = 7936 IW 000000h 0001FEh 000200h 003FFEh 004000h GS = 13824 IW GS = 21760 IW 00ABFEh GS = 20992 IW 00ABFEh 00ABFEh 00ABFEh TABLE 24-4: CODE FLASH SECURITY SEGMENT SIZES FOR 32K BYTE DEVICES BSS<2:0> = x10 1K VS = 256 IW BS = 768 IW 000000h 0001FEh 000200h 0007FEh 000800h BSS<2:0> = x11 0K VS = 256 IW 000000h 0001FEh 000200h BSS<2:0> = x01 4K VS = 256 IW BS = 3840 IW 000000h 0001FEh 000200h 001FFEh 002000h GS = 7168 IW 0057FEh BSS<2:0> = x00 8K VS = 256 IW BS = 7936 IW 000000h 0001FEh 000200h GS = 11008 IW 0057FEh GS = 10240 IW 0057FEh GS = 3072 IW 003FFEh 004000h 0057FEh 00ABFEh 00ABFEh 00ABFEh 00ABFEh 2009 Microchip Technology Inc. Preliminary DS70591B-page 339 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 NOTES: DS70591B-page 340 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 25.0 Note: INSTRUCTION SET SUMMARY This data sheet summarizes the features of the dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the "dsPIC33F/PIC24H Family Reference Manual". Please see the Microchip web site (www.microchip.com) for the latest "dsPIC33F/PIC24H Family Reference Manual" sections. Most bit-oriented instructions (including rotate/shift instructions) have two operands: simple * The W register (with or without an address modifier) or file register (specified by the value of `Ws' or `f') * The bit in the W register or file register (specified by a literal value or indirectly by the contents of register `Wb') The literal instructions that involve data movement can use some of the following operands: * A literal value to be loaded into a W register or file register (specified by `k') * The W register or file register where the literal value is to be loaded (specified by `Wb' or `f') However, literal instructions that involve arithmetic or logical operations use some of the following operands: * The first source operand, which is a register `Wb' without any address modifier * The second source operand, which is a literal value * The destination of the result (only if not the same as the first source operand), which is typically a register `Wd' with or without an address modifier The MAC class of DSP instructions can use some of the following operands: * The accumulator (A or B) to be used (required operand) * The W registers to be used as the two operands * The X and Y address space prefetch operations * The X and Y address space prefetch destinations * The accumulator write-back destination The other DSP instructions do not involve any multiplication and can include: * The accumulator to be used (required) * The source or destination operand (designated as Wso or Wdo, respectively) with or without an address modifier * The amount of shift specified by a W register, `Wn', or a literal value The control instructions can use some of the following operands: * A program memory address * The mode of the table read and table write instructions The dsPIC33F instruction set is identical to that of the dsPIC30F. Most instructions are a single program memory word (24 bits). Only three instructions require two program memory locations. Each single-word instruction is a 24-bit word, divided into an 8-bit opcode, which specifies the instruction type and one or more operands, which further specify the operation of the instruction. The instruction set is highly orthogonal and is grouped into five basic categories: * * * * * Word or byte-oriented operations Bit-oriented operations Literal operations DSP operations Control operations Table 25-1 shows the general symbols used in describing the instructions. The dsPIC33F instruction set summary in Table 25-2 lists all the instructions, along with the status flags affected by each instruction. Most word or byte-oriented W register instructions (including barrel shift instructions) have three operands: * The first source operand, which is typically a register `Wb' without any address modifier * The second source operand, which is typically a register `Ws' with or without an address modifier * The destination of the result, which is typically a register `Wd' with or without an address modifier However, word or byte-oriented file register instructions have two operands: * The file register specified by the value, `f' * The destination, which could be either the file register, `f', or the W0 register, which is denoted as `WREG' 2009 Microchip Technology Inc. Preliminary DS70591B-page 341 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 Most instructions are a single word. Certain double-word instructions are designed to provide all the required information in these 48 bits. In the second word, the 8 MSbs are `0's. If this second word is executed as an instruction (by itself), it will execute as a NOP. The double-word instructions execute in two instruction cycles. Most single-word instructions are executed in a single instruction cycle, unless a conditional test is true, or the program counter is changed as a result of the instruction. In these cases, the execution takes two instruction cycles with the additional instruction cycle(s) executed as a NOP. Notable exceptions are the BRA (unconditional/computed branch), indirect CALL/GOTO, all table reads and writes and RETURN/RETFIE instructions, which are single-word instructions but take two or three cycles. Certain instructions that involve skipping over the subsequent instruction require either two or three cycles if the skip is performed, depending on whether the instruction being skipped is a single-word or two-word instruction. Moreover, double-word moves require two cycles. Note: For more details on the instruction set, refer to the "16-bit MCU and DSC Programmer's Reference Manual" (DS70157). TABLE 25-1: Field #text (text) [text] {} SYMBOLS USED IN OPCODE DESCRIPTIONS Description Means literal defined by "text" Means "content of text" Means "the location addressed by text" Optional field or operation Register bit field Byte mode selection Double-Word mode selection Shadow register select Word mode selection (default) One of two accumulators {A, B} Accumulator Write-Back Destination Address register {W13, [W13]+ = 2} 4-bit bit selection field (used in word-addressed instructions) {0...15} MCU Status bits: Carry, Digit Carry, Negative, Overflow, Sticky Zero Absolute address, label or expression (resolved by the linker) File register address {0x0000...0x1FFF} 1-bit unsigned literal {0,1} 4-bit unsigned literal {0...15} 5-bit unsigned literal {0...31} 8-bit unsigned literal {0...255} 10-bit unsigned literal {0...255} for Byte mode, {0:1023} for Word mode 14-bit unsigned literal {0...16384} 16-bit unsigned literal {0...65535} 23-bit unsigned literal {0...8388608}; LSb must be `0' Field does not require an entry, can be blank DSP Status bits: ACCA Overflow, ACCB Overflow, ACCA Saturate, ACCB Saturate Program Counter 10-bit signed literal {-512...511} 16-bit signed literal {-32768...32767} 6-bit signed literal {-16...16} Base W register {W0..W15} Destination W register { Wd, [Wd], [Wd++], [Wd--], [++Wd], [--Wd] } Destination W register { Wnd, [Wnd], [Wnd++], [Wnd--], [++Wnd], [--Wnd], [Wnd+Wb] } Dividend, Divisor Working register pair (Direct Addressing) DS70591B-page 342 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 TABLE 25-1: Field Wm*Wm Wm*Wn Wn Wnd Wns WREG Ws Wso Wx SYMBOLS USED IN OPCODE DESCRIPTIONS (CONTINUED) Description Multiplicand and Multiplier Working register pair for Square instructions {W4 * W4,W5 * W5,W6 * W6,W7 * W7} Multiplicand and Multiplier Working register pair for DSP instructions {W4 * W5,W4 * W6,W4 * W7,W5 * W6,W5 * W7,W6 * W7} One of 16 Working registers {W0..W15} One of 16 Destination Working registers {W0...W15} One of 16 Source Working registers {W0...W15} W0 (Working register used in file register instructions) Source W register { Ws, [Ws], [Ws++], [Ws--], [++Ws], [--Ws] } Source W register { Wns, [Wns], [Wns++], [Wns--], [++Wns], [--Wns], [Wns+Wb] } X Data Space Prefetch Address register for DSP instructions {[W8] + = 6, [W8] + = 4, [W8] + = 2, [W8], [W8] - = 6, [W8] - = 4, [W8] - = 2, [W9] + = 6, [W9] + = 4, [W9] + = 2, [W9], [W9] - = 6, [W9] - = 4, [W9] - = 2, [W9 + W12], none} X Data Space Prefetch Destination register for DSP instructions {W4...W7} Y Data Space Prefetch Address register for DSP instructions {[W10] + = 6, [W10] + = 4, [W10] + = 2, [W10], [W10] - = 6, [W10] - = 4, [W10] - = 2, [W11] + = 6, [W11] + = 4, [W11] + = 2, [W11], [W11] - = 6, [W11] - = 4, [W11] - = 2, [W11 + W12], none} Y Data Space Prefetch Destination register for DSP instructions {W4...W7} Wxd Wy Wyd 2009 Microchip Technology Inc. Preliminary DS70591B-page 343 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 TABLE 25-2: Base Instr # 1 Assembly Mnemonic ADD ADD ADD ADD ADD ADD ADD ADD 2 ADDC ADDC ADDC ADDC ADDC ADDC 3 AND AND AND AND AND AND 4 ASR ASR ASR ASR ASR ASR 5 6 BCLR BRA BCLR BCLR BRA BRA BRA BRA BRA BRA BRA BRA BRA BRA BRA BRA BRA BRA BRA BRA BRA BRA BRA BRA BRA BRA 7 8 9 BSET BSW BTG BSET BSET BSW.C BSW.Z BTG BTG INSTRUCTION SET OVERVIEW Assembly Syntax Acc f f,WREG #lit10,Wn Wb,Ws,Wd Wb,#lit5,Wd Wso,#Slit4,Acc f f,WREG #lit10,Wn Wb,Ws,Wd Wb,#lit5,Wd f f,WREG #lit10,Wn Wb,Ws,Wd Wb,#lit5,Wd f f,WREG Ws,Wd Wb,Wns,Wnd Wb,#lit5,Wnd f,#bit4 Ws,#bit4 C,Expr GE,Expr GEU,Expr GT,Expr GTU,Expr LE,Expr LEU,Expr LT,Expr LTU,Expr N,Expr NC,Expr NN,Expr NOV,Expr NZ,Expr OA,Expr OB,Expr OV,Expr SA,Expr SB,Expr Expr Z,Expr Wn f,#bit4 Ws,#bit4 Ws,Wb Ws,Wb f,#bit4 Ws,#bit4 Description Add Accumulators f = f + WREG WREG = f + WREG Wd = lit10 + Wd Wd = Wb + Ws Wd = Wb + lit5 16-Bit Signed Add to Accumulator f = f + WREG + (C) WREG = f + WREG + (C) Wd = lit10 + Wd + (C) Wd = Wb + Ws + (C) Wd = Wb + lit5 + (C) f = f .AND. WREG WREG = f .AND. WREG Wd = lit10 .AND. Wd Wd = Wb .AND. Ws Wd = Wb .AND. lit5 f = Arithmetic Right Shift f WREG = Arithmetic Right Shift f Wd = Arithmetic Right Shift Ws Wnd = Arithmetic Right Shift Wb by Wns Wnd = Arithmetic Right Shift Wb by lit5 Bit Clear f Bit Clear Ws Branch if Carry Branch if Greater Than or Equal Branch if Unsigned Greater Than or Equal Branch if Greater Than Branch if Unsigned Greater Than Branch if Less Than or Equal Branch if Unsigned Less Than or Equal Branch if Less Than Branch if Unsigned Less Than Branch if Negative Branch if Not Carry Branch if Not Negative Branch if Not Overflow Branch if Not Zero Branch if Accumulator A Overflow Branch if Accumulator B Overflow Branch if Overflow Branch if Accumulator A Saturated Branch if Accumulator B Saturated Branch Unconditionally Branch if Zero Computed Branch Bit Set f Bit Set Ws Write C bit to Ws DS70591B-page 344 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 TABLE 25-2: Base Instr # 10 Assembly Mnemonic BTSC BTSC BTSC 11 BTSS BTSS BTSS 12 BTST BTST BTST.C BTST.Z BTST.C BTST.Z 13 BTSTS BTSTS BTSTS.C BTSTS.Z 14 15 CALL CLR CALL CALL CLR CLR CLR CLR 16 17 CLRWDT COM CLRWDT COM COM COM 18 CP CP CP CP 19 20 CP0 CPB CP0 CP0 CPB CPB CPB 21 22 23 24 25 26 CPSEQ CPSGT CPSLT CPSNE DAW DEC CPSEQ CPSGT CPSLT CPSNE DAW DEC DEC DEC 27 DEC2 DEC2 DEC2 DEC2 28 DISI DISI f f,WREG Ws,Wd f Wb,#lit5 Wb,Ws f Ws f Wb,#lit5 Wb,Ws Wb, Wn Wb, Wn Wb, Wn Wb, Wn Wn f f,WREG Ws,Wd f f,WREG Ws,Wd #lit14 INSTRUCTION SET OVERVIEW (CONTINUED) Assembly Syntax f,#bit4 Ws,#bit4 f,#bit4 Ws,#bit4 f,#bit4 Ws,#bit4 Ws,#bit4 Ws,Wb Ws,Wb f,#bit4 Ws,#bit4 Ws,#bit4 lit23 Wn f WREG Ws Acc,Wx,Wxd,Wy,Wyd,AWB Description Bit Test f, Skip if Clear Bit Test Ws, Skip if Clear Bit Test f, Skip if Set Bit Test Ws, Skip if Set Bit Test f Bit Test Ws to C Bit Test Ws to Z Bit Test Ws 2009 Microchip Technology Inc. Preliminary DS70591B-page 345 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 TABLE 25-2: Base Instr # 29 Assembly Mnemonic DIV DIV.S DIV.SD DIV.U DIV.UD 30 31 32 33 34 35 36 37 38 39 DIVF DO ED EDAC EXCH FBCL FF1L FF1R GOTO INC DIVF DO DO ED EDAC EXCH FBCL FF1L FF1R GOTO GOTO INC INC INC 40 INC2 INC2 INC2 INC2 41 IOR IOR IOR IOR IOR IOR 42 43 44 LAC LNK LSR LAC LNK LSR LSR LSR LSR LSR 45 MAC MAC Wn,Expr Wm*Wm,Acc,Wx,Wy,Wxd Wm*Wm,Acc,Wx,Wy,Wxd Wns,Wnd Ws,Wnd Ws,Wnd Ws,Wnd Expr Wn f f,WREG Ws,Wd f f,WREG Ws,Wd f f,WREG #lit10,Wn Wb,Ws,Wd Wb,#lit5,Wd Wso,#Slit4,Acc #lit14 f f,WREG Ws,Wd Wb,Wns,Wnd Wb,#lit5,Wnd Wm*Wn,Acc,Wx,Wxd,Wy,Wyd , AWB Wm*Wm,Acc,Wx,Wxd,Wy,Wyd f,Wn f f,WREG #lit16,Wn #lit8,Wn Wn,f Wso,Wdo WREG,f Wns,Wd Ws,Wnd Acc,Wx,Wxd,Wy,Wyd,AWB INSTRUCTION SET OVERVIEW (CONTINUED) Assembly Syntax Wm,Wn Wm,Wn Wm,Wn Wm,Wn Wm,Wn #lit14,Expr Description Signed 16/16-bit Integer Divide Signed 32/16-bit Integer Divide Unsigned 16/16-bit Integer Divide Unsigned 32/16-bit Integer Divide Signed 16/16-bit Fractional Divide Do code to PC + Expr, lit14 + 1 times Do code to PC + Expr, (Wn) + 1 times Euclidean Distance (no accumulate) Euclidean Distance Swap Wns with Wnd Find Bit Change from Left (MSb) Side Find First One from Left (MSb) Side Find First One from Right (LSb) Side Go to Address Go to Indirect f=f+1 WREG = f + 1 Wd = Ws + 1 f=f+2 WREG = f + 2 Wd = Ws + 2 f = f .IOR. WREG WREG = f .IOR. WREG Wd = lit10 .IOR. Wd Wd = Wb .IOR. Ws Wd = Wb .IOR. lit5 Load Accumulator Link Frame Pointer f = Logical Right Shift f WREG = Logical Right Shift f Wd = Logical Right Shift Ws Wnd = Logical Right Shift Wb by Wns Wnd = Logical Right Shift Wb by lit5 Multiply and Accumulate # of # of Words Cycles 1 1 1 1 1 2 2 1 1 1 1 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 18 18 18 18 18 2 2 1 1 1 1 1 1 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Status Flags Affected N,Z,C,OV N,Z,C,OV N,Z,C,OV N,Z,C,OV N,Z,C,OV None None OA,OB,OAB, SA,SB,SAB OA,OB,OAB, SA,SB,SAB None C C C None None C,DC,N,OV,Z C,DC,N,OV,Z C,DC,N,OV,Z C,DC,N,OV,Z C,DC,N,OV,Z C,DC,N,OV,Z N,Z N,Z N,Z N,Z N,Z OA,OB,OAB, SA,SB,SAB None C,N,OV,Z C,N,OV,Z C,N,OV,Z N,Z N,Z OA,OB,OAB, SA,SB,SAB OA,OB,OAB, SA,SB,SAB None N,Z N,Z None None None None N,Z None None None MAC 46 MOV MOV MOV MOV MOV MOV.b MOV MOV MOV MOV.D MOV.D 47 MOVSAC MOVSAC Square and Accumulate Move f to Wn Move f to f Move f to WREG Move 16-Bit Literal to Wn Move 8-Bit Literal to Wn Move Wn to f Move Ws to Wd Move WREG to f Move Double from W(ns):W(ns + 1) to Wd Move Double from Ws to W(nd + 1):W(nd) Prefetch and Store Accumulator 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 1 DS70591B-page 346 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 TABLE 25-2: Base Instr # 48 Assembly Mnemonic MPY INSTRUCTION SET OVERVIEW (CONTINUED) Assembly Syntax MPY Wm*Wn,Acc,Wx,Wxd,Wy,Wyd MPY Wm*Wm,Acc,Wx,Wxd,Wy,Wyd Description Multiply Wm by Wn to Accumulator Square Wm to Accumulator -(Multiply Wm by Wn) to Accumulator Multiply and Subtract from Accumulator # of # of Words Cycles 1 1 1 1 1 1 1 1 Status Flags Affected OA,OB,OAB, SA,SB,SAB OA,OB,OAB, SA,SB,SAB None OA,OB,OAB, SA,SB,SAB None None None None None None None OA,OB,OAB, SA,SB,SAB C,DC,N,OV,Z C,DC,N,OV,Z C,DC,N,OV,Z None None None None None All None None None None WDTO,Sleep None None None None None None None None C,N,Z C,N,Z C,N,Z N,Z N,Z N,Z C,N,Z C,N,Z C,N,Z 49 50 MPY.N MSC MPY.N Wm*Wn,Acc,Wx,Wxd,Wy,Wyd MSC Wm*Wm,Acc,Wx,Wxd,Wy,Wyd , AWB Wb,Ws,Wnd Wb,Ws,Wnd Wb,Ws,Wnd Wb,Ws,Wnd Wb,#lit5,Wnd Wb,#lit5,Wnd f Acc f f,WREG Ws,Wd 51 MUL MUL.SS MUL.SU MUL.US MUL.UU MUL.SU MUL.UU MUL {Wnd + 1, Wnd} = signed(Wb) * signed(Ws) {Wnd + 1, Wnd} = signed(Wb) * unsigned(Ws) {Wnd + 1, Wnd} = unsigned(Wb) * signed(Ws) {Wnd + 1, Wnd} = unsigned(Wb) * unsigned(Ws) {Wnd + 1, Wnd} = signed(Wb) * unsigned(lit5) {Wnd + 1, Wnd} = unsigned(Wb) * unsigned(lit5) W3:W2 = f * WREG Negate Accumulator f=f+1 WREG = f + 1 Wd = Ws + 1 No Operation No Operation 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 1 1 1 2 1 1 2 2 1 1 1 3 (2) 3 (2) 3 (2) 1 1 1 1 1 1 1 1 1 52 NEG NEG NEG NEG NEG 53 54 NOP POP NOP NOPR POP POP POP.D POP.S f Wdo Wnd Pop f from Top-of-Stack (TOS) Pop from Top-of-Stack (TOS) to Wdo Pop from Top-of-Stack (TOS) to W(nd):W(nd + 1) Pop Shadow Registers Push f to Top-of-Stack (TOS) Push Wso to Top-of-Stack (TOS) Push W(ns):W(ns + 1) to Top-of-Stack (TOS) Push Shadow Registers #lit1 Go into Sleep or Idle mode Relative Call Computed Call Repeat Next Instruction lit14 + 1 times Repeat Next Instruction (Wn) + 1 times Software Device Reset Return from interrupt 55 PUSH PUSH PUSH PUSH.D PUSH.S f Wso Wns 56 57 58 59 60 61 62 63 PWRSAV RCALL REPEAT RESET RETFIE RETLW RETURN RLC PWRSAV RCALL RCALL REPEAT REPEAT RESET RETFIE RETLW RETURN RLC RLC RLC f Wn Expr #lit14 Wn #lit10,Wn Return with Literal in Wn Return from Subroutine f = Rotate Left through Carry f WREG = Rotate Left through Carry f Wd = Rotate Left through Carry Ws f = Rotate Left (No Carry) f WREG = Rotate Left (No Carry) f Wd = Rotate Left (No Carry) Ws f = Rotate Right through Carry f WREG = Rotate Right through Carry f Wd = Rotate Right through Carry Ws f,WREG Ws,Wd f f,WREG Ws,Wd f f,WREG Ws,Wd 64 RLNC RLNC RLNC RLNC 65 RRC RRC RRC RRC 2009 Microchip Technology Inc. Preliminary DS70591B-page 347 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 TABLE 25-2: Base Instr # 66 Assembly Mnemonic RRNC RRNC RRNC RRNC 67 68 69 SAC SE SETM SAC SAC.R SE SETM SETM SETM 70 SFTAC SFTAC SFTAC 71 SL SL SL SL SL SL 72 SUB SUB SUB SUB SUB SUB SUB 73 SUBB SUBB SUBB SUBB SUBB SUBB 74 SUBR SUBR SUBR SUBR SUBR 75 SUBBR SUBBR SUBBR SUBBR SUBBR 76 77 78 79 80 81 82 SWAP TBLRDH TBLRDL TBLWTH TBLWTL ULNK XOR SWAP.b SWAP TBLRDH TBLRDL TBLWTH TBLWTL ULNK XOR XOR XOR XOR XOR 83 ZE ZE f f,WREG #lit10,Wn Wb,Ws,Wd Wb,#lit5,Wd Ws,Wnd INSTRUCTION SET OVERVIEW (CONTINUED) Assembly Syntax f f,WREG Ws,Wd Acc,#Slit4,Wdo Acc,#Slit4,Wdo Ws,Wnd f WREG Ws Acc,Wn Acc,#Slit6 f f,WREG Ws,Wd Wb,Wns,Wnd Wb,#lit5,Wnd Acc f f,WREG #lit10,Wn Wb,Ws,Wd Wb,#lit5,Wd f f,WREG #lit10,Wn Wb,Ws,Wd Wb,#lit5,Wd f f,WREG Wb,Ws,Wd Wb,#lit5,Wd f f,WREG Wb,Ws,Wd Wb,#lit5,Wd Wn Wn Ws,Wd Ws,Wd Ws,Wd Ws,Wd Description f = Rotate Right (No Carry) f WREG = Rotate Right (No Carry) f Wd = Rotate Right (No Carry) Ws Store Accumulator Store Rounded Accumulator Wnd = Sign-Extended Ws f = 0xFFFF WREG = 0xFFFF Ws = 0xFFFF Arithmetic Shift Accumulator by (Wn) Arithmetic Shift Accumulator by Slit6 f = Left Shift f WREG = Left Shift f Wd = Left Shift Ws Wnd = Left Shift Wb by Wns Wnd = Left Shift Wb by lit5 Subtract Accumulators f = f - WREG WREG = f - WREG Wn = Wn - lit10 Wd = Wb - Ws Wd = Wb - lit5 f = f - WREG - (C) WREG = f - WREG - (C) Wn = Wn - lit10 - (C) Wd = Wb - Ws - (C) Wd = Wb - lit5 - (C) f = WREG - f WREG = WREG - f Wd = Ws - Wb Wd = lit5 - Wb f = WREG - f - (C) WREG = WREG - f - (C) Wd = Ws - Wb - (C) Wd = lit5 - Wb - (C) Wn = Nibble Swap Wn Wn = Byte Swap Wn Read Prog<23:16> to Wd<7:0> Read Prog<15:0> to Wd Write Ws<7:0> to Prog<23:16> Write Ws to Prog<15:0> Unlink Frame Pointer f = f .XOR. WREG WREG = f .XOR. WREG Wd = lit10 .XOR. Wd Wd = Wb .XOR. Ws Wd = Wb .XOR. lit5 Wnd = Zero-Extend Ws # of # of Words Cycles 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 1 1 1 1 1 1 1 Status Flags Affected N,Z N,Z N,Z None None C,N,Z None None None OA,OB,OAB, SA,SB,SAB OA,OB,OAB, SA,SB,SAB C,N,OV,Z C,N,OV,Z C,N,OV,Z N,Z N,Z OA,OB,OAB, SA,SB,SAB C,DC,N,OV,Z C,DC,N,OV,Z C,DC,N,OV,Z C,DC,N,OV,Z C,DC,N,OV,Z C,DC,N,OV,Z C,DC,N,OV,Z C,DC,N,OV,Z C,DC,N,OV,Z C,DC,N,OV,Z C,DC,N,OV,Z C,DC,N,OV,Z C,DC,N,OV,Z C,DC,N,OV,Z C,DC,N,OV,Z C,DC,N,OV,Z C,DC,N,OV,Z C,DC,N,OV,Z None None None None None None None N,Z N,Z N,Z N,Z N,Z C,Z,N DS70591B-page 348 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 26.0 DEVELOPMENT SUPPORT 26.1 MPLAB Integrated Development Environment Software The PIC(R) microcontrollers and dsPIC(R) digital signal controllers are supported with a full range of software and hardware development tools: * Integrated Development Environment - MPLAB(R) IDE Software * Compilers/Assemblers/Linkers - MPLAB C Compiler for Various Device Families - HI-TECH C for Various Device Families - MPASMTM Assembler - MPLINKTM Object Linker/ MPLIBTM Object Librarian - MPLAB Assembler/Linker/Librarian for Various Device Families * Simulators - MPLAB SIM Software Simulator * Emulators - MPLAB REAL ICETM In-Circuit Emulator * In-Circuit Debuggers - MPLAB ICD 3 - PICkitTM 3 Debug Express * Device Programmers - PICkitTM 2 Programmer - MPLAB PM3 Device Programmer * Low-Cost Demonstration/Development Boards, Evaluation Kits, and Starter Kits The MPLAB IDE software brings an ease of software development previously unseen in the 8/16/32-bit microcontroller market. The MPLAB IDE is a Windows(R) operating system-based application that contains: * A single graphical interface to all debugging tools - Simulator - Programmer (sold separately) - In-Circuit Emulator (sold separately) - In-Circuit Debugger (sold separately) * A full-featured editor with color-coded context * A multiple project manager * Customizable data windows with direct edit of contents * High-level source code debugging * Mouse over variable inspection * Drag and drop variables from source to watch windows * Extensive on-line help * Integration of select third party tools, such as IAR C Compilers The MPLAB IDE allows you to: * Edit your source files (either C or assembly) * One-touch compile or assemble, and download to emulator and simulator tools (automatically updates all project information) * Debug using: - Source files (C or assembly) - Mixed C and assembly - Machine code MPLAB IDE supports multiple debugging tools in a single development paradigm, from the cost-effective simulators, through low-cost in-circuit debuggers, to full-featured emulators. This eliminates the learning curve when upgrading to tools with increased flexibility and power. 2009 Microchip Technology Inc. Preliminary DS70591B-page 349 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 26.2 MPLAB C Compilers for Various Device Families 26.5 MPLINK Object Linker/ MPLIB Object Librarian The MPLAB C Compiler code development systems are complete ANSI C compilers for Microchip's PIC18, PIC24 and PIC32 families of microcontrollers and the dsPIC30 and dsPIC33 families of digital signal controllers. These compilers provide powerful integration capabilities, superior code optimization and ease of use. For easy source level debugging, the compilers provide symbol information that is optimized to the MPLAB IDE debugger. The MPLINK Object Linker combines relocatable objects created by the MPASM Assembler and the MPLAB C18 C Compiler. It can link relocatable objects from precompiled libraries, using directives from a linker script. The MPLIB Object Librarian manages the creation and modification of library files of precompiled code. When a routine from a library is called from a source file, only the modules that contain that routine will be linked in with the application. This allows large libraries to be used efficiently in many different applications. The object linker/library features include: * Efficient linking of single libraries instead of many smaller files * Enhanced code maintainability by grouping related modules together * Flexible creation of libraries with easy module listing, replacement, deletion and extraction 26.3 HI-TECH C for Various Device Families The HI-TECH C Compiler code development systems are complete ANSI C compilers for Microchip's PIC family of microcontrollers and the dsPIC family of digital signal controllers. These compilers provide powerful integration capabilities, omniscient code generation and ease of use. For easy source level debugging, the compilers provide symbol information that is optimized to the MPLAB IDE debugger. The compilers include a macro assembler, linker, preprocessor, and one-step driver, and can run on multiple platforms. 26.6 MPLAB Assembler, Linker and Librarian for Various Device Families 26.4 MPASM Assembler The MPASM Assembler is a full-featured, universal macro assembler for PIC10/12/16/18 MCUs. The MPASM Assembler generates relocatable object files for the MPLINK Object Linker, Intel(R) standard HEX files, MAP files to detail memory usage and symbol reference, absolute LST files that contain source lines and generated machine code and COFF files for debugging. The MPASM Assembler features include: * Integration into MPLAB IDE projects * User-defined macros to streamline assembly code * Conditional assembly for multi-purpose source files * Directives that allow complete control over the assembly process MPLAB Assembler produces relocatable machine code from symbolic assembly language for PIC24, PIC32 and dsPIC devices. MPLAB C Compiler uses the assembler to produce its object file. The assembler generates relocatable object files that can then be archived or linked with other relocatable object files and archives to create an executable file. Notable features of the assembler include: * * * * * * Support for the entire device instruction set Support for fixed-point and floating-point data Command line interface Rich directive set Flexible macro language MPLAB IDE compatibility DS70591B-page 350 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 26.7 MPLAB SIM Software Simulator 26.9 MPLAB ICD 3 In-Circuit Debugger System The MPLAB SIM Software Simulator allows code development in a PC-hosted environment by simulating the PIC MCUs and dsPIC(R) DSCs on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. Registers can be logged to files for further run-time analysis. The trace buffer and logic analyzer display extend the power of the simulator to record and track program execution, actions on I/O, most peripherals and internal registers. The MPLAB SIM Software Simulator fully supports symbolic debugging using the MPLAB C Compilers, and the MPASM and MPLAB Assemblers. The software simulator offers the flexibility to develop and debug code outside of the hardware laboratory environment, making it an excellent, economical software development tool. MPLAB ICD 3 In-Circuit Debugger System is Microchip's most cost effective high-speed hardware debugger/programmer for Microchip Flash Digital Signal Controller (DSC) and microcontroller (MCU) devices. It debugs and programs PIC(R) Flash microcontrollers and dsPIC(R) DSCs with the powerful, yet easyto-use graphical user interface of MPLAB Integrated Development Environment (IDE). The MPLAB ICD 3 In-Circuit Debugger probe is connected to the design engineer's PC using a high-speed USB 2.0 interface and is connected to the target with a connector compatible with the MPLAB ICD 2 or MPLAB REAL ICE systems (RJ-11). MPLAB ICD 3 supports all MPLAB ICD 2 headers. 26.8 MPLAB REAL ICE In-Circuit Emulator System 26.10 PICkit 3 In-Circuit Debugger/ Programmer and PICkit 3 Debug Express The MPLAB PICkit 3 allows debugging and programming of PIC(R) and dsPIC(R) Flash microcontrollers at a most affordable price point using the powerful graphical user interface of the MPLAB Integrated Development Environment (IDE). The MPLAB PICkit 3 is connected to the design engineer's PC using a full speed USB interface and can be connected to the target via an Microchip debug (RJ-11) connector (compatible with MPLAB ICD 3 and MPLAB REAL ICE). The connector uses two device I/O pins and the reset line to implement in-circuit debugging and In-Circuit Serial ProgrammingTM. The PICkit 3 Debug Express include the PICkit 3, demo board and microcontroller, hookup cables and CDROM with user's guide, lessons, tutorial, compiler and MPLAB IDE software. MPLAB REAL ICE In-Circuit Emulator System is Microchip's next generation high-speed emulator for Microchip Flash DSC and MCU devices. It debugs and programs PIC(R) Flash MCUs and dsPIC(R) Flash DSCs with the easy-to-use, powerful graphical user interface of the MPLAB Integrated Development Environment (IDE), included with each kit. The emulator is connected to the design engineer's PC using a high-speed USB 2.0 interface and is connected to the target with either a connector compatible with incircuit debugger systems (RJ11) or with the new highspeed, noise tolerant, Low-Voltage Differential Signal (LVDS) interconnection (CAT5). The emulator is field upgradable through future firmware downloads in MPLAB IDE. In upcoming releases of MPLAB IDE, new devices will be supported, and new features will be added. MPLAB REAL ICE offers significant advantages over competitive emulators including low-cost, full-speed emulation, run-time variable watches, trace analysis, complex breakpoints, a ruggedized probe interface and long (up to three meters) interconnection cables. 2009 Microchip Technology Inc. Preliminary DS70591B-page 351 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 26.11 PICkit 2 Development Programmer/Debugger and PICkit 2 Debug Express The PICkitTM 2 Development Programmer/Debugger is a low-cost development tool with an easy to use interface for programming and debugging Microchip's Flash families of microcontrollers. The full featured Windows(R) programming interface supports baseline (PIC10F, PIC12F5xx, PIC16F5xx), midrange (PIC12F6xx, PIC16F), PIC18F, PIC24, dsPIC30, dsPIC33, and PIC32 families of 8-bit, 16-bit, and 32-bit microcontrollers, and many Microchip Serial EEPROM products. With Microchip's powerful MPLAB Integrated Development Environment (IDE) the PICkitTM 2 enables in-circuit debugging on most PIC(R) microcontrollers. In-Circuit-Debugging runs, halts and single steps the program while the PIC microcontroller is embedded in the application. When halted at a breakpoint, the file registers can be examined and modified. The PICkit 2 Debug Express include the PICkit 2, demo board and microcontroller, hookup cables and CDROM with user's guide, lessons, tutorial, compiler and MPLAB IDE software. 26.13 Demonstration/Development Boards, Evaluation Kits, and Starter Kits A wide variety of demonstration, development and evaluation boards for various PIC MCUs and dsPIC DSCs allows quick application development on fully functional systems. Most boards include prototyping areas for adding custom circuitry and provide application firmware and source code for examination and modification. The boards support a variety of features, including LEDs, temperature sensors, switches, speakers, RS-232 interfaces, LCD displays, potentiometers and additional EEPROM memory. The demonstration and development boards can be used in teaching environments, for prototyping custom circuits and for learning about various microcontroller applications. In addition to the PICDEMTM and dsPICDEMTM demonstration/development board series of circuits, Microchip has a line of evaluation kits and demonstration software for analog filter design, KEELOQ(R) security ICs, CAN, IrDA(R), PowerSmart battery management, SEEVAL(R) evaluation system, Sigma-Delta ADC, flow rate sensing, plus many more. Also available are starter kits that contain everything needed to experience the specified device. This usually includes a single application and debug capability, all on one board. Check the Microchip web page (www.microchip.com) for the complete list of demonstration, development and evaluation kits. 26.12 MPLAB PM3 Device Programmer The MPLAB PM3 Device Programmer is a universal, CE compliant device programmer with programmable voltage verification at VDDMIN and VDDMAX for maximum reliability. It features a large LCD display (128 x 64) for menus and error messages and a modular, detachable socket assembly to support various package types. The ICSPTM cable assembly is included as a standard item. In Stand-Alone mode, the MPLAB PM3 Device Programmer can read, verify and program PIC devices without a PC connection. It can also set code protection in this mode. The MPLAB PM3 connects to the host PC via an RS-232 or USB cable. The MPLAB PM3 has high-speed communications and optimized algorithms for quick programming of large memory devices and incorporates an MMC card for file storage and data applications. DS70591B-page 352 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 27.0 ELECTRICAL CHARACTERISTICS This section provides an overview of dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 electrical characteristics. Additional information will be provided in future revisions of this document as it becomes available. Absolute maximum ratings for the dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 family are listed below. Exposure to these maximum rating conditions for extended periods may affect device reliability. Functional operation of the device at these or any other conditions above the parameters indicated in the operation listings of this specification is not implied. Absolute Maximum Ratings(1) Ambient temperature under bias.............................................................................................................-40C to +125C Storage temperature .............................................................................................................................. -65C to +150C Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +4.0V Voltage on any pin that is not 5V tolerant, with respect to VSS(4) ................................................... -0.3V to (VDD + 0.3V) Voltage on any 5V tolerant pin with respect to VSS, when Vdd 3.0V(4) ................................................. -0.3V to +5.6V Voltage on any 5V tolerant pin with respect to Vss, when VDD < 3.0V(4) ........................................ -0.3V to (VDD + 0.3V) Voltage on VCAP/VDDCORE with respect to VSS ...................................................................................... 2.25V to 2.75V Maximum current out of VSS pin ...........................................................................................................................300 mA Maximum current into VDD pin(2)...........................................................................................................................250 mA Maximum output current sunk by any I/O pin(3) ........................................................................................................4 mA Maximum output current sourced by any I/O pin(3) ...................................................................................................4 mA Maximum current sunk by all ports .......................................................................................................................200 mA Maximum current sourced by all ports(2) ...............................................................................................................200 mA Maximum output current sunk by non-remappable PWM pins ...............................................................................16 mA Maximum output current sourced by non-remappable PWM pins ..........................................................................16 mA Note 1: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. 2: Maximum allowable current is a function of device maximum power dissipation (see Table 27-2). 3: Exceptions are PWMxL, and PWMxH, which are able to sink/source 16 mA, and digital pins, which are able to sink/source 8 mA. 4: See the "Pin Diagrams" section for 5V tolerant pins. 2009 Microchip Technology Inc. Preliminary DS70591B-page 353 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 27.1 DC Characteristics OPERATING MIPS VS. VOLTAGE VDD Range (in Volts) 3.0-3.6V 3.0-3.6V Temp Range (in C) -40C to +85C -40C to +125C Max MIPS dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 40 40 TABLE 27-1: Characteristic TABLE 27-2: THERMAL OPERATING CONDITIONS Rating Symbol TJ TA TJ TA Min -40 -40 -40 -40 Typ -- -- -- -- Max +125 +85 +140 +125 Unit C C C C Industrial Temperature Devices Operating Junction Temperature Range Operating Ambient Temperature Range Extended Temperature Devices Operating Junction Temperature Range Operating Ambient Temperature Range Power Dissipation: Internal chip power dissipation: PINT = VDD x (IDD - IOH) I/O Pin Power Dissipation: I/O = ({VDD - VOH} x IOH) + (VOL x IOL) Maximum Allowed Power Dissipation PDMAX (TJ - TA)/JA W PD PINT + PI/O W TABLE 27-3: THERMAL PACKAGING CHARACTERISTICS Characteristic Symbol JA JA JA JA JA Typ 28 39 53.1 43 43 Max -- -- -- -- -- Unit C/W C/W C/W C/W C/W Notes 1 1 1 1 1 Package Thermal Resistance, 64-Pin QFN (9x9x0.9 mm) Package Thermal Resistance, 64-Pin TQFP (10x10x1 mm) Package Thermal Resistance, 80-Pin TQFP (12x12x1 mm) Package Thermal Resistance, 100-Pin TQFP (12x12x1 mm) Package Thermal Resistance, 100-Pin TQFP (14x14x1 mm) Note 1: Junction to ambient thermal resistance, Theta-JA (JA) numbers are achieved by package simulations. DS70591B-page 354 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 TABLE 27-4: DC TEMPERATURE AND VOLTAGE SPECIFICATIONS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +125C for Extended Characteristic Min Typ(1) Max Units Conditions DC CHARACTERISTICS Param Symbol No. Operating Voltage Supply Voltage DC10 DC12 DC16 VDD VDR VPOR RAM Data Retention Voltage VDD Start Voltage(4) to Ensure Internal Power-on Reset Signal VDD Rise Rate(3) to Ensure Internal Power-on Reset Signal VDD Core Internal Regulator Voltage (2) 3.0 1.8 -- -- -- -- 3.6 -- VSS V V V Industrial and extended DC17 SVDD 0.03 -- -- V/ms 0-3.0V in 0.1s DC18 VCORE 2.25 -- 2.75 V Voltage is dependent on load, temperature and VDD Note 1: 2: 3: 4: Data in "Typ" column is at 3.3V, +25C unless otherwise stated. This is the limit to which VDD may be lowered without losing RAM data. These parameters are characterized but not tested in manufacturing. VDD voltage must remain at Vss for a minimum of 200 s to ensure POR. 2009 Microchip Technology Inc. Preliminary DS70591B-page 355 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 TABLE 27-5: DC CHARACTERISTICS: OPERATING CURRENT (IDD) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +125C for Extended Max Units Conditions DC CHARACTERISTICS Parameter Typical(1) No. Operating Current (IDD)(2) DC20d 21 30 mA -40C DC20a 21 30 mA +25C 10 MIPS 3.3V See Note 2 DC20b 21 30 mA +85C DC20c 22 30 mA +125C DC21d 28 40 mA -40C DC21a 28 40 mA +25C 16 MIPS 3.3V See Note 2 and Note 3 DC21b 28 40 mA +85C DC21c 29 40 mA +125C DC22d 35 45 mA -40C DC22a 35 45 mA +25C 20 MIPS 3.3V See Note 2 and Note 3 DC22b 35 45 mA +85C DC22c 36 45 mA +125C DC23d 49 60 mA -40C DC23a 49 60 mA +25C 30 MIPS 3.3V See Note 2 and Note 3 DC23b 49 60 mA +85C DC23c 50 60 mA +125C DC24d 66 75 mA -40C DC24a 66 75 mA +25C 40 MIPS 3.3V See Note 2 DC24b 66 75 mA +85C DC24c 67 75 mA +125C DC25d 153 170 mA -40C 40 MIPS DC25a 154 170 mA +25C See Note 2, except PWM is 3.3V operating at maximum speed DC25b 155 170 mA +85C (PTCON2 = 0x0000) DC25c 156 170 mA +125C DC26d 122 135 mA -40C 40 MIPS DC26a 123 135 mA +25C See Note 2, except PWM is 3.3V operating at 1/2 speed DC26b 124 135 mA +85C (PTCON2 = 0x0001) DC26c 125 135 mA +125C DC27d 107 120 mA -40C 40 MIPS DC27a 108 120 mA +25C See Note 2, except PWM is 3.3V operating at 1/4 speed DC27b 109 120 mA +85C (PTCON2 = 0x0002) DC27c 110 120 mA +125C DC28d 88 100 mA -40C 40 MIPS DC28a 89 100 mA +25C See Note 2, except PWM is 3.3V operating at 1/8 speed DC28b 89 100 mA +85C (PTCON2 = 0x0003) DC28c 89 100 mA +125C Note 1: Data in "Typical" column is at 3.3V, +25C unless otherwise stated. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements are as follows: OSC1 driven with external square wave from rail to rail. All I/O pins are configured as inputs and pulled to VSS. MCLR = VDD, WDT and FSCM are disabled. CPU, SRAM, program memory and data memory are operational. No peripheral modules are operating (PMD bits are all set). 3: These parameters are characterized but not tested in manufacturing. DS70591B-page 356 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 TABLE 27-6: DC CHARACTERISTICS: IDLE CURRENT (IIDLE) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +125C for Extended Max Units Conditions DC CHARACTERISTICS Parameter No. DC40d DC40a DC40b DC40c DC41d DC41a DC41b DC41c DC42d DC42a DC42b DC42c DC43d DC43a DC43b DC43c DC44d DC44a DC44b DC44c Note 1: 2: 3: Typical(1) Idle Current (IIDLE): Core Off Clock On Base Current(2) 8 9 9 10 11 11 11 12 14 14 14 15 20 20 21 22 29 29 30 31 15 15 15 15 20 20 20 20 25 25 25 25 30 30 30 30 40 40 40 40 mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA -40C +25C +85C +125C -40C +25C +85C +125C -40C +25C +85C +125C -40C +25C +85C +125C -40C +25C +85C +125C 3.3V 40 MIPS 3.3V 30 MIPS(3) 3.3V 20 MIPS(3) 3.3V 16 MIPS(3) 3.3V 10 MIPS Data in "Typical" column is at 3.3V, +25C unless otherwise stated. Base IIDLE current is measured with core off, clock on and all modules turned off. Peripheral module Disable SFR registers are zeroed. All I/O pins are configured as inputs and pulled to VSS. These parameters are characterized but not tested in manufacturing. 2009 Microchip Technology Inc. Preliminary DS70591B-page 357 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 TABLE 27-7: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +125C for Extended Max Units Conditions DC CHARACTERISTICS Parameter No. DC60d DC60a DC60b DC60c DC61d DC61a DC61b DC61c Note 1: 2: 3: 4: Typical(1) Power-Down Current (IPD)(2,4) 50 50 200 600 8 10 12 13 200 200 500 1000 13 15 20 25 A A A A A A A A -40C +25C +85C +125C -40C +25C +85C +125C 3.3V Watchdog Timer Current: IWDT(3) 3.3V Base Power-Down Current Data in the Typical column is at 3.3V, +25C unless otherwise stated. Base IPD is measured with all peripherals and clocks shut down. All I/Os are configured as inputs and pulled to VSS. WDT, etc., are all switched off, and VREGS (RCON<8>) = 1. The current is the additional current consumed when the WDT module is enabled. This current should be added to the base IPD current. These currents are measured on the device containing the most memory in this family. TABLE 27-8: DC CHARACTERISTICS: DOZE CURRENT (IDOZE) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +125C for Extended Max 120 100 100 120 100 100 120 100 100 120 100 100 Doze Ratio 1:2 1:64 1:128 1:2 1:64 1:128 1:2 1:64 1:128 1:2 1:64 1:128 Units mA mA mA mA mA mA mA mA mA mA mA mA +125C 3.3V 40 MIPS +85C 3.3V 40 MIPS +25C 3.3V 40 MIPS -40C 3.3V 40 MIPS Conditions DC CHARACTERISTICS Parameter No. DC73a DC73f DC73g DC70a DC70f DC70g DC71a DC71f DC71g DC72a DC72f DC72g Note 1: Typical(1) 105 82 82 105 80 79 105 77 77 105 76 76 Data in the Typical column is at 3.3V, +25C unless otherwise stated. DS70591B-page 358 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 TABLE 27-9: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +125C for Extended Characteristic Input Low Voltage I/O Pins MCLR I/O Pins with OSC1 or SOSCI I/O Pins with SDAx, SCLx, U2RX, U2TX I/O Pins with SDAx, SCLx, U2RX, U2TX Input High Voltage I/O Pins Not 5V Tolerant(4) I/O Pins 5V Tolerant(4) CNx Pull-up Current Input Leakage Current(2,3,4) I/O Pins with: 4 mA Source/Sink Capability 8 mA Source/Sink Capability 16 mA Source/Sink Capability DI55 DI56 DI57 ISINK MCLR OSC1 Min Typ(1) Max Units Conditions DC CHARACTERISTICS Param Symbol No. VIL DI10 DI15 DI16 DI18 DI19 VIH DI20 DI21 ICNPU DI30 IIL DI50 VSS VSS VSS VSS VSS -- -- -- -- -- 0.2 VDD 0.2 VDD 0.2 VDD 0.3 VDD 0.2 VDD V V V V V SMBus disabled SMBus enabled 0.7 VDD 0.7 VDD -- -- -- 250 VDD 5.5 -- V V A VDD = 3.3V, VPIN = VSS -- -- -- -- -- -- -- -- -- -- 2 4 8 2 2 A A A A A VSS VPIN VDD, Pin at high-impedance VSS VPIN VDD, Pin at high-impedance VSS VPIN VDD, Pin at high-impedance VSS VPIN VDD VSS VPIN VDD, XT and HS modes Note 1: 2: 3: 4: Sink Current Pins: -- -- 16 mA RA9, RA10, RD3-RD7, RD13, RE0-RE7, RG12, RG13 Pins: -- -- 8 mA RC15 Pins: -- -- 4 mA RA0-RA7, RA14, RA15, RB0RB15, RC1-RC4, RC12-RC14, RD0-RD2, RD8-RD12, RD14, RD15, RE8, RE9, RF0-RF8, RF12, RF13, RG0-RG3, RG6RG9, RG14, RG15 Pins: -- -- 2 mA MCLR Data in "Typ" column is at 3.3V, +25C unless otherwise stated. The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. Negative current is defined as current sourced by the pin. See "Pin Diagrams" for the list of 5V tolerant I/O pins. 2009 Microchip Technology Inc. Preliminary DS70591B-page 359 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 TABLE 27-10: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS DC CHARACTERISTICS Param Symbol No. DO10 VOL Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +125C for Extended Characteristic Output Low Voltage I/O Ports: 4 mA Source/Sink Capability 8 mA Source/Sink Capability 16 mA Source/Sink Capability DO16 DO20 VOH OSC2/CLKO Output High Voltage I/O Ports: 4 mA Source/Sink Capability 8 mA Source/Sink Capability 16 mA Source/Sink Capability DO26 DO27 OSC2/CLKO ISOURCE Source Current Pins: RA9, RA10, RD3-RD7, RD13, RE0-RE7, RG12, RG13 Pins: RC15 Pins: RA0-RA7, RA14, RA15, RB0RB15, RC1-RC4, RC12-RC14, RD0-RD2, RD8-RD12, RD14, RD15, RE8, RE9, RF0-RF8, RF12, RF13, RG0-RG3, RG6RG9, RG14, RG15 Pins: MCLR 2.40 2.40 2.40 2.41 -- -- -- -- -- -- -- -- V V V V IOH = -4 mA, VDD = 3.3V IOH = -8 mA, VDD = 3.3V IOH = -16 mA, VDD = 3.3V IOH = -1.3 mA, VDD = 3.3V -- -- -- -- -- -- -- -- 0.4 0.4 0.4 0.4 V V V V IOL = 4 mA, VDD = 3.3V IOL = 8 mA, VDD = 3.3V IOL = 16 mA, VDD = 3.3V IOL = 2 mA, VDD = 3.3V Min Typ Max Units Conditions -- -- 16 mA -- -- -- -- 8 4 mA mA -- -- 2 mA TABLE 27-11: ELECTRICAL CHARACTERISTICS: BOR DC CHARACTERISTICS Param No. BO10 Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +125C for Extended Characteristic BOR Event on VDD Transition High-to-Low BOR Event is Tied to VDD Core Voltage Decrease Min(1) 2.6 Typ -- Max 2.95 Units V Conditions Symbol VBOR Note 1: Parameters are for design guidance only and are not tested in manufacturing. DS70591B-page 360 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 TABLE 27-12: DC CHARACTERISTICS: PROGRAM MEMORY DC CHARACTERISTICS Param Symbol No. D130 D131 D132B D134 D135 D136a D136b D137a D137b D138a D138b Note 1: 2: EP VPR VPEW TRETD IDDP TRW TRW TPE TPE TWW TWW Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +125C for Extended Characteristic Program Flash Memory Cell Endurance VDD for Read VDD for Self-Timed Write Characteristic Retention Supply Current during Programming Row Write Time Row Write Time Page Erase Time Page Erase Time Word Write Cycle Time Word Write Cycle Time 10,000 VMIN VMIN 20 -- 1.43 1.39 21.8 21.1 45.8 44.5 -- -- -- -- 10 -- -- -- -- -- -- -- 3.6 3.6 -- -- 1.58 1.63 24.1 24.8 50.7 52.3 E/W -40C to +125C V V VMIN = Minimum operating voltage VMIN = Minimum operating voltage Min Typ(1) Max Units Conditions Year Provided no other specifications are violated, -40C to +125C mA ms ms ms ms s s TRW = 11064 FRC cycles, TA = +85C, See Note 2 TRW = 11064 FRC cycles, TA = +125C, See Note 2 TPE = 168517 FRC cycles, TA = +85C, See Note 2 TPE = 168517 FRC cycles, TA = +125C, See Note 2 TWW = 355 FRC cycles, TA = +85C, See Note 2 TWW = 355 FRC cycles, TA = +125C, See Note 2 Data in "Typ" column is at 3.3V, +25C unless otherwise stated. Other conditions: FRC = 7.37 MHz, TUN<5:0> = b'011111 (for Min), TUN<5:0> = b'100000 (for Max). This parameter depends on the FRC accuracy (see Table 27-20) and the value of the FRC Oscillator Tuning register (see Register 9-4). For complete details on calculating the Minimum and Maximum time see Section 5.3 "Programming Operations". TABLE 27-13: INTERNAL VOLTAGE REGULATOR SPECIFICATIONS Operating Conditions: Param No. -40C TA +85C for Industrial -40C TA +125C for Extended Characteristics External Filter Capacitor Value Min 4.7 Typ 10 Max -- Units F Comments Capacitor must be low series resistance (< 5 ohms) Symbol CEFC 2009 Microchip Technology Inc. Preliminary DS70591B-page 361 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 27.2 AC Characteristics and Timing Parameters This section defines dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 AC characteristics and timing parameters. TABLE 27-14: TEMPERATURE AND VOLTAGE SPECIFICATIONS - AC Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +125C for Extended Operating voltage VDD range as described in Section 27.0 "Electrical Characteristics". AC CHARACTERISTICS FIGURE 27-1: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS Load Condition 2 - for OSC2 Load Condition 1 - for all pins except OSC2 VDD/2 RL Pin VSS CL Pin VSS CL RL = 464 CL = 50 pF for all pins except OSC2 15 pF for OSC2 output TABLE 27-15: CAPACITIVE LOADING REQUIREMENTS ON OUTPUT PINS Param Symbol No. DO50 COSCO Characteristic OSC2 Pin Min -- Typ -- Max 15 Units pF Conditions In XT and HS modes when external clock is used to drive OSC1 EC mode In I2CTM mode DO56 DO58 CIO CB All I/O Pins and OSC2 SCLx, SDAx -- -- -- -- 50 400 pF pF DS70591B-page 362 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 FIGURE 27-2: EXTERNAL CLOCK TIMING Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 OS20 OS30 OS25 OS30 OS31 OS31 CLKO OS41 OS40 TABLE 27-16: EXTERNAL CLOCK TIMING REQUIREMENTS AC CHARACTERISTICS Param No. OS10 Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +125C for Extended Characteristic External CLKI Frequency (External clocks allowed only in EC and ECPLL modes) Oscillator Crystal Frequency OS20 OS25 OS30 OS31 OS40 OS41 Note 1: 2: TOSC TCY TosL, TosH TosR, TosF TckR TckF TOSC = 1/FOSC Instruction Cycle Time(2) External Clock in (OSC1) High or Low Time External Clock in (OSC1) Rise or Fall Time CLKO Rise Time(3) CLKO Fall Time(3) Min DC Typ(1) -- Max 40 Units MHz Conditions EC Symb FIN 3.5 10 12.5 25 0.375 x TOSC -- -- -- -- -- -- -- -- -- 5.2 5.2 10 40 DC DC 0.625 x TOSC 20 -- -- MHz MHz ns ns ns ns ns ns XT HS EC EC 3: Data in "Typ" column is at 3.3V, +25C unless otherwise stated. Instruction cycle period (TCY) equals two times the input oscillator time-base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at "min." values with an external clock applied to the OSC1/CLKI pin. When an external clock input is used, the "max." cycle time limit is "DC" (no clock) for all devices. Measurements are taken in EC mode. The CLKO signal is measured on the OSC2 pin. 2009 Microchip Technology Inc. Preliminary DS70591B-page 363 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 TABLE 27-17: PLL CLOCK TIMING SPECIFICATIONS (VDD = 3.0V TO 3.6V) AC CHARACTERISTICS Param No. OS50 Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +125C for Extended Characteristic PLL Voltage Controlled Oscillator (VCO) Input Frequency Range On-Chip VCO System Frequency PLL Start-up Time (Lock Time) CLKO Stability (Jitter) Min 0.8 Typ(1) -- Max 8 Units MHz Conditions ECPLL, XTPLL modes Symbol FPLLI OS51 OS52 OS53 Note 1: FSYS TLOCK DCLK 100 0.9 -3 -- 1.5 0.5 200 3.1 3 MHz mS % Measured over 100 ms period Data in "Typ" column is at 3.3V, +25C unless otherwise stated. Parameters are for design guidance only and are not tested in manufacturing. TABLE 27-18: AUXILIARY PLL CLOCK TIMING SPECIFICATIONS (VDD = 3.0V TO 3.6V) AC CHARACTERISTICS Param No. OS56 OS57 OS58 Note 1: Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +125C for Extended Characteristic 0n-Chip 16x PLL CCO Frequency On-Chip 16x PLL Phase Detector Input Frequency Frequency Generator Lock Time Min 112 7.0 -- Typ(1) 118 7.37 -- Max 120 7.5 10 Units MHz MHz s Conditions Symbol FHPOUT FHPIN TSU Data in "Typ" column is at 3.3V, +25C unless otherwise stated. Parameters are for design guidance only and are not tested in manufacturing. TABLE 27-19: AC CHARACTERISTICS: INTERNAL RC ACCURACY AC CHARACTERISTICS Param No. F20a F20b Note 1: 2: FRC FRC Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for Extended Min Typ Max Units Conditions Characteristic Internal FRC Accuracy @ FRC Frequency = 7.37 MHz(1,2) -1 -2 -- -- +1 +2 % % -40C TA +85C -40C TA +125C VDD = 3.0-3.6V VDD = 3.0-3.6V Frequency calibrated at +25C and 3.3V. The TUN<5:0> bits can be used to compensate for temperature drift. FRC is set to initial frequency of 7.37 MHz (2%) at +25C. DS70591B-page 364 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 TABLE 27-20: INTERNAL RC ACCURACY AC CHARACTERISTICS Param No. F21a F21b LPRC LPRC Characteristic LPRC @ 32.768 kHz(1) -30 -35 -- -- +30 +35 % % -40C TA +85C -40C TA +125C Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +125C for Extended Min Typ Max Units Conditions Note 1: Change of LPRC frequency as VDD changes. FIGURE 27-3: I/O TIMING CHARACTERISTICS I/O Pin (Input) DI35 DI40 I/O Pin (Output) Old Value DO31 DO32 Note: Refer to Figure 27-1 for load conditions. New Value TABLE 27-21: I/O TIMING REQUIREMENTS AC CHARACTERISTICS Param No. DO31 DO32 DI35 DI40 Note 1: Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +125C for Extended Characteristic Port Output Rise Time Port Output Fall Time INTx Pin High or Low Time (output) CNx High or Low Time (input) Min -- -- 20 2 Typ(1) 10 10 -- -- Max 25 25 -- -- Units ns ns ns TCY Conditions Refer to Figure 27-1 for test conditions Refer to Figure 27-1 for test conditions Symbol TIOR TIOF TINP TRBP Data in "Typ" column is at 3.3V, +25C unless otherwise stated. 2009 Microchip Technology Inc. Preliminary DS70591B-page 365 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 FIGURE 27-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING CHARACTERISTICS VDD MCLR Internal POR PWRT Time-out OSC Time-out Internal Reset Watchdog Timer Reset SY12 SY10 SY11 SY30 SY13 I/O Pins SY35 FSCM Delay Note: Refer to Figure 27-1 for load conditions. SY20 SY13 DS70591B-page 366 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 TABLE 27-22: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER TIMING REQUIREMENTS AC CHARACTERISTICS Param Symbol No. SY10 SY11 TMCL TPWRT Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +125C for Extended Characteristic(1) MCLR Pulse Width (low) Power-up Timer Period Min 2 -- Typ(2) -- 2 4 8 16 32 64 128 10 0.72 -- Max -- -- Units s ms Conditions -40C to +85C -40C to +85C User programmable SY12 SY13 SY20 TPOR TIOZ TWDT1 Power-on Reset Delay I/O High-Impedance from MCLR Low or Watchdog Timer Reset Watchdog Timer Time-out Period 3 0.68 -- 30 1.2 -- s s ms -40C to +85C See Section 24.4 "Watchdog Timer (WDT)" and LPRC parameter F21a (Table 27-20). TOSC = OSC1 period SY30 Note 1: 2: TOST Oscillator Start-up Time -- 1024 TOSC -- -- These parameters are characterized but not tested in manufacturing. Data in "Typ" column is at 3.3V, +25C unless otherwise stated. 2009 Microchip Technology Inc. Preliminary DS70591B-page 367 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 FIGURE 27-5: TIMER1, 2 AND 3 EXTERNAL CLOCK TIMING CHARACTERISTICS TxCK Tx10 Tx15 OS60 TMRx Tx11 Tx20 Note: Refer to Figure 27-1 for load conditions. TABLE 27-23: TIMER1 EXTERNAL CLOCK TIMING REQUIREMENTS(1) AC CHARACTERISTICS Param No. TA10 Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +125C for Extended Characteristic TxCK High Time Synchronous, no prescaler Synchronous, with prescaler Asynchronous TA11 TTXL TxCK Low Time Synchronous, no prescaler Synchronous, with prescaler Asynchronous TA15 TTXP TxCK Input Period Synchronous, no prescaler Synchronous, with prescaler Asynchronous OS60 Ft1 T1CK Oscillator Input Frequency Range (oscillator enabled by setting bit, TCS (T1CON<1>)) Min 0.5 TCY + 20 10 10 0.5 TCY + 20 10 10 TCY + 40 Greater of: 20 ns or (TCY + 40)/N 20 DC Typ -- -- -- -- -- -- -- -- Max -- -- -- -- -- -- -- -- Units ns ns ns ns ns ns ns -- N = prescale value (1, 8, 64, 256) Must also meet parameter TA15 Conditions Must also meet parameter TA15 Symbol TTXH -- -- -- 50 ns kHz TA20 Note 1: TCKEXTMRL Delay from External TxCK Clock Edge to Timer Increment Timer1 is a Type A. 0.5 TCY 1.5 TCY -- DS70591B-page 368 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 TABLE 27-24: TIMER2 EXTERNAL CLOCK TIMING REQUIREMENTS AC CHARACTERISTICS Param No. TB10 Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +125C for Extended Characteristic TxCK High Time Synchronous, no prescaler Synchronous, with prescaler TB11 TTXL TxCK Low Time Synchronous, no prescaler Synchronous, with prescaler TB15 TTXP TxCK Input Period Synchronous, no prescaler Synchronous, with prescaler TB20 TCKEXTMRL Delay from External TxCK Clock Edge to Timer Increment Min 0.5 TCY + 20 10 0.5 TCY + 20 10 TCY + 40 Greater of: 20 ns or (TCY + 40)/N 0.5 TCY -- 1.5 TCY -- Typ -- -- -- -- -- Max -- -- -- -- -- Units ns ns ns ns ns N = prescale value (1, 8, 64, 256) Must also meet parameter TB15 Conditions Must also meet parameter TB15 Symbol TTXH TABLE 27-25: TIMER3 EXTERNAL CLOCK TIMING REQUIREMENTS AC CHARACTERISTICS Param No. TC10 TC11 TC15 Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +125C for Extended Characteristic TxCK High Time TxCK Low Time Synchronous Synchronous Min 0.5 TCY + 20 0.5 TCY + 20 TCY + 40 Greater of: 20 ns or (TCY + 40)/N 0.5 TCY -- 1.5 TCY -- Typ -- -- -- Max -- -- -- Units ns ns ns Conditions Must also meet parameter TC15 Must also meet parameter TC15 N = prescale value (1, 8, 64, 256) Symbol TTXH TTXL TTXP TxCK Input Period Synchronous, no prescaler Synchronous, with prescaler TC20 TCKEXTMRL Delay from External TxCK Clock Edge to Timer Increment 2009 Microchip Technology Inc. Preliminary DS70591B-page 369 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 FIGURE 27-6: INPUT CAPTURE (CAPx) TIMING CHARACTERISTICS ICx IC10 IC15 Note: Refer to Figure 27-1 for load conditions. IC11 TABLE 27-26: INPUT CAPTURE TIMING REQUIREMENTS AC CHARACTERISTICS Param No. IC10 IC11 IC15 Note 1: Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +125C for Extended Characteristic(1) ICx Input Low Time ICx Input High Time ICx Input Period No prescaler With prescaler TccH TccP No prescaler With prescaler Min 0.5 TCY + 20 10 0.5 TCY + 20 10 (TCY + 40)/N Max -- -- -- -- -- Units ns ns ns ns ns N = prescale value (1, 4, 16) Conditions Symbol TccL These parameters are characterized but not tested in manufacturing. FIGURE 27-7: OUTPUT COMPARE MODULE (OCx) TIMING CHARACTERISTICS OCx (Output Compare or PWM Mode) OC11 OC10 Note: Refer to Figure 27-1 for load conditions. TABLE 27-27: OUTPUT COMPARE MODULE TIMING REQUIREMENTS AC CHARACTERISTICS Param Symbol No. OC10 OC11 Note 1: TccF TccR Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +125C for Extended Min -- -- Typ -- -- Max -- -- Units ns ns Conditions See parameter D032 See parameter D031 Characteristic(1) OCx Output Fall Time OCx Output Rise Time These parameters are characterized but not tested in manufacturing. DS70591B-page 370 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 FIGURE 27-8: OC/PWM MODULE TIMING CHARACTERISTICS OC20 OCFA OC15 OCx TABLE 27-28: SIMPLE OC/PWM MODE TIMING REQUIREMENTS AC CHARACTERISTICS Param No. OC15 OC20 Note 1: Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +125C for Extended Characteristic(1) Fault Input to PWM I/O Change Fault Input Pulse Width Min -- 50 Typ -- -- Max 50 -- Units ns ns Conditions Symbol TFD TFLT These parameters are characterized but not tested in manufacturing. 2009 Microchip Technology Inc. Preliminary DS70591B-page 371 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 FIGURE 27-9: HIGH-SPEED PWM MODULE FAULT TIMING CHARACTERISTICS MP30 FLTx MP20 PWMx FIGURE 27-10: HIGH-SPEED PWM MODULE TIMING CHARACTERISTICS MP11 MP10 PWMx Note: Refer to Figure 27-1 for load conditions. TABLE 27-29: HIGH-SPEED PWM MODULE TIMING REQUIREMENTS AC CHARACTERISTICS Param No. MP10 MP11 MP20 MP30 MP31 MP32 Note 1: 2: Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +125C for Extended Characteristic(1) PWM Output Fall Time PWM Output Rise Time Fault Input to PWM I/O Change Minimum PWM Fault Pulse Width Tap Delay PWM Input Clock Min -- -- -- 8 1.04 -- Typ 2.5 2.5 -- -- -- -- Max -- -- 15 -- -- 120 Units ns ns ns ns ns MHz ACLK = 120 MHz See Note 2 DTC<10> = 10 Conditions Symbol TFPWM TRPWM TFD TFH TPDLY ACLK These parameters are characterized but not tested in manufacturing. This parameter is a maximum allowed input clock for the PWM module. DS70591B-page 372 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 FIGURE 27-11: SCKx (CKP = 0) SP11 SCKx (CKP = 1) SP35 SP20 MSb SP31 SDIx MSb In SP40 SP41 Bit 14 - - - -1 Bit 14 - - - - - -1 SP30 LSb In SP21 LSb SP10 SP21 SP20 SPIx MODULE MASTER MODE (CKE = 0) TIMING CHARACTERISTICS SDOx Note: Refer to Figure 27-1 for load conditions. TABLE 27-30: SPIx MASTER MODE (CKE = 0) TIMING REQUIREMENTS AC CHARACTERISTICS Param No. SP10 SP11 SP20 SP21 SP30 SP31 SP35 SP40 SP41 Note 1: 2: 3: 4: Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +125C for Extended Characteristic(1) SCKx Output Low Time SCKx Output High Time SCKx Output Fall Time SCKx Output Rise Time SDOx Data Output Fall Time SDOx Data Output Rise Time SDOx Data Output Valid after SCKx Edge Setup Time of SDIx Data Input to SCKx Edge Hold Time of SDIx Data Input to SCKx Edge Min TCY/2 TCY/2 -- -- -- -- -- 23 30 Typ(2) -- -- -- -- -- -- 6 -- -- Max -- -- -- -- -- -- 20 -- -- Units ns ns ns ns ns ns ns ns ns Conditions See Note 3 See Note 3 See parameter D032 and Note 4 See parameter D031 and Note 4 See parameter D032 and Note 4 See parameter D031 and Note 4 Symbol TscL TscH TscF TscR TdoF TdoR TscH2doV, TscL2doV TdiV2scH, TdiV2scL TscH2diL, TscL2diL These parameters are characterized but not tested in manufacturing. Data in "Typ" column is at 3.3V, +25C unless otherwise stated. The minimum clock period for SCKx is 100 ns. Therefore, the clock generated in Master mode must not violate this specification. Assumes 50 pF load on all SPIx pins. 2009 Microchip Technology Inc. Preliminary DS70591B-page 373 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 FIGURE 27-12: SCKX (CKP = 0) SP11 SCKX (CKP = 1) SP10 SP21 SP20 SPIx MODULE MASTER MODE (CKE = 1) TIMING CHARACTERISTICS SP36 SP35 SP20 LSb SP21 SDOX MSb SP40 Bit 14 - - - - - -1 SP30,SP31 Bit 14 - - - -1 SDIX MSb In SP41 LSb In Note: Refer to Figure 27-1 for load conditions. TABLE 27-31: SPIx MODULE MASTER MODE (CKE = 1) TIMING REQUIREMENTS AC CHARACTERISTICS Param No. SP10 SP11 SP20 SP21 SP30 SP31 SP35 SP36 SP40 SP41 Note 1: 2: 3: 4: Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +125C for Extended Characteristic(1) SCKx Output Low Time SCKx Output High Time SCKx Output Fall Time SCKx Output Rise Time SDOx Data Output Fall Time SDOx Data Output Rise Time SDOx Data Output Valid after SCKx Edge SDOx Data Output Setup to First SCKx Edge Setup Time of SDIx Data Input to SCKx Edge Hold Time of SDIx Data Input to SCKx Edge Min TCY/2 TCY/2 -- -- -- -- -- 30 23 30 Typ(2) -- -- -- -- -- -- 6 -- -- -- Max -- -- -- -- -- -- 20 -- -- -- Units ns ns ns ns ns ns ns ns ns ns Conditions See Note 3 See Note 3 See parameter D032 and Note 4 See parameter D031 and Note 4 See parameter D032 and Note 4 See parameter D031 and Note 4 Symbol TscL TscH TscF TscR TdoF TdoR TscH2doV, TscL2doV TdoV2sc, TdoV2scL TdiV2scH, TdiV2scL TscH2diL, TscL2diL These parameters are characterized but not tested in manufacturing. Data in "Typ" column is at 3.3V, +25C unless otherwise stated. The minimum clock period for SCKx is 100 ns. The clock generated in Master mode must not violate this specification. Assumes 50 pF load on all SPIx pins. DS70591B-page 374 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 FIGURE 27-13: SSX SP50 SCKX (CKP = 0) SP71 SCKX (CKP = 1) SP35 SDOX MSb SP72 SP73 SP70 SP73 SP72 SP52 SPIx MODULE SLAVE MODE (CKE = 0) TIMING CHARACTERISTICS Bit 14 - - - - - -1 SP30,SP31 LSb SP51 LSb In SDIX MSb In SP41 Bit 14 - - - -1 SP40 Note: Refer to Figure 27-1 for load conditions. TABLE 27-32: SPIx MODULE SLAVE MODE (CKE = 0) TIMING REQUIREMENTS AC CHARACTERISTICS Param No. SP70 SP71 SP72 SP73 SP30 SP31 SP35 SP40 SP41 SP50 SP51 SP52 Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +125C for Extended Characteristic(1) SCKx Input Low Time SCKx Input High Time SCKx Input Fall Time SCKx Input Rise Time SDOx Data Output Fall Time SDOx Data Output Rise Time SDOx Data Output Valid after SCKx Edge Setup Time of SDIx Data Input to SCKx Edge Hold Time of SDIx Data Input to SCKx Edge SSx to SCKx or SCKx Input SSx to SDOx Output High-Impedance Min 30 30 -- -- -- -- -- 20 20 120 10 Typ(2) -- -- 10 10 -- -- -- -- -- -- -- Max -- -- 25 25 -- -- 30 -- -- -- 50 Units ns ns ns ns ns ns ns ns ns ns ns ns See Note 3 Conditions Symbol TscL TscH TscF TscR TdoF TdoR TscH2doV, TscL2doV TdiV2scH, TdiV2scL TscH2diL, TscL2diL TssL2scH, TssL2scL TssH2doZ See Note 3 See Note 3 See parameter D032 and Note 3 See parameter D031 and Note 3 TscH2ssH SSx after SCKx Edge 1.5 TCY +40 -- -- TscL2ssH Note 1: These parameters are characterized but not tested in manufacturing. 2: Data in "Typ" column is at 3.3V, +25C unless otherwise stated. 3: Assumes 50 pF load on all SPIx pins. 2009 Microchip Technology Inc. Preliminary DS70591B-page 375 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 FIGURE 27-14: SSx SP50 SCKx (CKP = 0) SP71 SCKx (CKP = 1) SP35 SP72 MSb Bit 14 - - - - - -1 SP30,SP31 SDIx SDI MSb In SP41 SP40 Note: Refer to Figure 27-1 for load conditions. Bit 14 - - - -1 LSb In LSb SP51 SP73 SP70 SP73 SP72 SP52 SPIx MODULE SLAVE MODE (CKE = 1) TIMING CHARACTERISTICS SP60 SDOx DS70591B-page 376 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 TABLE 27-33: SPIx MODULE SLAVE MODE (CKE = 1) TIMING REQUIREMENTS AC CHARACTERISTICS Param No. SP70 SP71 SP72 SP73 SP30 SP31 SP35 SP40 SP41 SP50 SP51 SP52 SP60 Note 1: 2: 3: 4: Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +125C for Extended Characteristic(1) SCKx Input Low Time SCKx Input High Time SCKx Input Fall Time SCKx Input Rise Time SDOx Data Output Fall Time SDOx Data Output Rise Time Min 30 30 -- -- -- -- -- 20 20 120 10 1.5 TCY + 40 -- Typ(2) -- -- 10 10 -- -- -- -- -- -- -- -- -- Max -- -- 25 25 -- -- 30 -- -- -- 50 -- 50 Units ns ns ns ns ns ns ns ns ns ns ns ns ns See Note 4 See Note 3 See Note 3 See parameter D032 and Note 3 See parameter D031 and Note 3 Conditions Symbol TscL TscH TscF TscR TdoF TdoR TscH2doV, SDOx Data Output Valid after TscL2doV SCKx Edge TdiV2scH, TdiV2scL TscH2diL, TscL2diL TssL2scH, TssL2scL TssH2doZ TscH2ssH TscL2ssH TssL2doV Setup Time of SDIx Data Input to SCKx Edge Hold Time of SDIx Data Input to SCKx Edge SSx to SCKx or SCKx Input SSx to SDOX Output High-Impedance SSx after SCKx Edge SDOx Data Output Valid after SSx Edge These parameters are characterized but not tested in manufacturing. Data in "Typ" column is at 3.3V, +25C unless otherwise stated. The minimum clock period for SCKx is 100 ns. The clock generated in Master mode must not violate this specification. Assumes 50 pF load on all SPIx pins. 2009 Microchip Technology Inc. Preliminary DS70591B-page 377 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 FIGURE 27-15: I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (MASTER MODE) SCLx IM31 IM30 SDAx IM33 IM34 Start Condition Note: Refer to Figure 27-1 for load conditions. Stop Condition FIGURE 27-16: I2Cx BUS DATA TIMING CHARACTERISTICS (MASTER MODE) IM20 IM11 IM10 IM11 IM26 IM21 SCLx IM10 IM25 IM33 SDAx In IM40 IM40 IM45 SDAx Out Note: Refer to Figure 27-1 for load conditions. DS70591B-page 378 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 TABLE 27-34: I2Cx BUS DATA TIMING REQUIREMENTS (MASTER MODE) AC CHARACTERISTICS Param Symbol No. IM10 Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +125C for Extended Characteristic Min(1) TCY/2 (BRG + 1) TCY/2 (BRG + 1) TCY/2 (BRG + 1) TCY/2 (BRG + 1) TCY/2 (BRG + 1) TCY/2 (BRG + 1) -- 20 + 0.1 CB -- -- 20 + 0.1 CB -- 250 100 40 0 0 0.2 TCY/2 (BRG + 1) TCY/2 (BRG + 1) TCY/2 (BRG + 1) TCY/2 (BRG + 1) TCY/2 (BRG + 1) TCY/2 (BRG + 1) TCY/2 (BRG + 1) TCY/2 (BRG + 1) TCY/2 (BRG + 1) TCY/2 (BRG + 1) TCY/2 (BRG + 1) TCY/2 (BRG + 1) -- -- -- 4.7 1.3 0.5 -- Max -- -- -- -- -- -- 300 300 100 1000 300 300 -- -- -- -- 0.9 -- -- -- -- -- -- -- -- -- -- -- -- -- 3500 1000 400 -- -- -- 400 Units s s s s s s ns ns ns ns ns ns ns ns ns s s s s s s s s s s s s ns ns ns ns ns ns s s s pF Time the bus must be free before a new transmission can start Only relevant for Repeated Start condition After this period the first clock pulse is generated CB is specified to be from 10 to 400 pF CB is specified to be from 10 to 400 pF Conditions TLO:SCL Clock Low Time 100 kHz mode 400 kHz mode 1 MHz mode(2) IM11 THI:SCL Clock High Time 100 kHz mode 400 kHz mode 1 MHz mode(2) SDAx and SCLx 100 kHz mode Fall Time 400 kHz mode 1 MHz mode(2) SDAx and SCLx 100 kHz mode Rise Time 400 kHz mode 1 MHz mode(2) 100 kHz mode 400 kHz mode 1 MHz mode(2) 100 kHz mode 400 kHz mode 1 MHz mode(2) 100 kHz mode 400 kHz mode 1 MHz mode(2) 100 kHz mode 400 kHz mode 1 MHz mode(2) 100 kHz mode 400 kHz mode 1 MHz mode(2) 100 kHz mode 400 kHz mode 1 MHz mode(2) 100 kHz mode 400 kHz mode 1 MHz mode(2) 100 kHz mode 400 kHz mode IM20 TF:SCL IM21 TR:SCL IM25 TSU:DAT Data Input Setup Time THD:DAT Data Input Hold Time TSU:STA Start Condition Setup Time IM26 IM30 IM31 THD:STA Start Condition Hold Time TSU:STO Stop Condition Setup Time THD:STO Stop Condition Hold Time TAA:SCL Output Valid From Clock IM33 IM34 IM40 IM45 TBF:SDA Bus Free Time IM50 CB 1 MHz mode(2) Bus Capacitive Loading Pulse Gobbler Delay 65 390 ns See Note 3 IM51 TPGD 2CTM Baud Rate Generator. Refer to Section 19. "Inter-Integrated Circuit Note 1: BRG is the value of the I (I2CTM)" (DS70195) in the "dsPIC33F/PIC24F Family Reference Manual". 2: Maximum pin capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only). 3: Typical value for this parameter is 130 ns. 2009 Microchip Technology Inc. Preliminary DS70591B-page 379 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 FIGURE 27-17: I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (SLAVE MODE) SCLx IS31 IS30 IS33 IS34 SDAx Start Condition Stop Condition FIGURE 27-18: I2Cx BUS DATA TIMING CHARACTERISTICS (SLAVE MODE) IS20 IS11 IS10 IS30 IS26 IS21 SCLx IS31 IS25 IS33 SDAx In IS40 IS40 IS45 SDAx Out DS70591B-page 380 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 TABLE 27-35: I2Cx BUS DATA TIMING REQUIREMENTS (SLAVE MODE) AC CHARACTERISTICS Param. Symbol IS10 TLO:SCL Characteristic Clock Low Time 100 kHz mode 400 kHz mode 1 MHz mode(1) IS11 THI:SCL Clock High Time 100 kHz mode 400 kHz mode 1 MHz mode(1) IS20 TF:SCL SDAx and SCLx Fall Time SDAx and SCLx Rise Time Data Input Setup Time 100 kHz mode 400 kHz mode 1 MHz mode(1) IS21 TR:SCL 100 kHz mode 400 kHz mode 1 MHz mode(1) IS25 TSU:DAT 100 kHz mode 400 kHz mode 1 MHz mode(1) IS26 THD:DAT Data Input Hold Time TSU:STA Start Condition Setup Time 100 kHz mode 400 kHz mode 1 MHz mode IS30 (1) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +125C for Extended Min 4.7 1.3 0.5 4.0 0.6 0.5 -- 20 + 0.1 CB -- -- 20 + 0.1 CB -- 250 100 100 0 0 0 4.7 0.6 0.25 4.0 0.6 0.25 4.7 0.6 0.6 4000 600 250 0 0 0 4.7 1.3 0.5 -- 3500 1000 350 -- -- -- 400 Max -- -- -- -- -- -- 300 300 100 1000 300 300 -- -- -- -- 0.9 0.3 -- -- -- -- -- -- -- -- -- -- -- Units s s s s s s ns ns ns ns ns ns ns ns ns s s s s s s s s s s s s ns ns ns ns ns ns s s s pF Time the bus must be free before a new transmission can start After this period, the first clock pulse is generated Only relevant for Repeated Start condition CB is specified to be from 10 to 400 pF CB is specified to be from 10 to 400 pF Device must operate at a minimum of 1.5 MHz Device must operate at a minimum of 10 MHz Conditions Device must operate at a minimum of 1.5 MHz Device must operate at a minimum of 10 MHz 100 kHz mode 400 kHz mode 1 MHz mode(1) 100 kHz mode 400 kHz mode 1 MHz mode(1) 100 kHz mode 400 kHz mode 1 MHz mode(1) 100 kHz mode 400 kHz mode 1 MHz mode (1) IS31 THD:STA Start Condition Hold Time TSU:STO Stop Condition Setup Time IS33 IS34 THD:STO Stop Condition Hold Time TAA:SCL Output Valid From Clock IS40 100 kHz mode 400 kHz mode 1 MHz mode(1) 100 kHz mode 400 kHz mode 1 MHz mode(1) IS45 TBF:SDA Bus Free Time IS50 Note 1: CB Bus Capacitive Loading Maximum pin capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only). 2009 Microchip Technology Inc. Preliminary DS70591B-page 381 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 TABLE 27-36: 10-BIT HIGH-SPEED A/D MODULE SPECIFICATIONS AC CHARACTERISTICS Param No. AD01 Standard Operating Conditions: 3.0V and 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +125C for Extended Characteristic Min Typ Max Units Conditions Symbol Device Supply AVDD Module VDD Supply Greater of VDD - 0.3 or 3.0 Vss - 0.3 Analog Input AD10 AD11 AD12 AD13 VINH-VINL Full-Scale Input Span VIN IAD -- Absolute Input Voltage Operating Current Leakage Current VSS AVSS -- -- 8 0.6 VDD AVDD -- -- V V mA A VINL = AVSS = 0V, AVDD = 3.3V Source Impedance = 100 Lesser of VDD + 0.3 or 3.6 VSS + 0.3 V AD02 AVSS Module VSS Supply V AD17 RIN Recommended Impedance Of Analog Voltage Source Resolution Integral Nonlinearity Differential Nonlinearity Gain Error Offset Error Monotonicity(1) Total Harmonic Distortion Signal to Noise and Distortion Spurious Free Dynamic Range Input Signal Bandwidth Effective Number of Bits -- DC Accuracy 100 AD20 Nr 10 data bits > -2 > -1 > -5 > -3 -- -- -- -- -- -- 0.5 0.5 2.0 0.75 -- -73 58 -73 -- 9.4 <2 <1 <5 <3 -- -- -- -- 1 -- bits LSb VINL = AVSS = 0V, AVDD = 3.3V LSb VINL = AVSS = 0V, AVDD = 3.3V LSb VINL = AVSS = 0V, AVDD = 3.3V LSb VINL = AVSS = VSS = 0V, AVDD = VDD = 3.3V -- dB dB dB MHz bits Guaranteed AD21A INL AD22A DNL AD23A GERR AD24A EOFF AD25 AD30 AD31 AD32 AD33 AD34 Note 1: -- THD SINAD SFDR FNYQ ENOB Dynamic Performance The A/D conversion result never decreases with an increase in the input voltage, and has no missing codes. DS70591B-page 382 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 TABLE 27-37: 10-BIT HIGH-SPEED A/D MODULE TIMING REQUIREMENTS AC CHARACTERISTICS Param Symbol No. AD50b TAD AD55b tCONV AD56b FCNV Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +125C for Extended Characteristic Min Typ(1) Max Units Conditions Clock Parameters ADC Clock Period Conversion Time Throughput Rate Devices with Single SAR Devices with Dual SARs AD63b tDPU Note 1: Time to Stabilize Analog Stage from ADC Off to ADC On(1) -- -- 1.0 -- -- -- 2.0 4.0 10 Msps Msps s 35.8 -- -- 14 TAD -- -- ns -- Conversion Rate Timing Parameters These parameters are characterized but not tested in manufacturing. FIGURE 27-19: A/D CONVERSION TIMING PER INPUT Tconv Trigger Pulse TAD A/D Clock A/D Data ADBUFxx CONV 9 Old Data 8 2 1 0 New Data 2009 Microchip Technology Inc. Preliminary DS70591B-page 383 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 TABLE 27-38: COMPARATOR MODULE SPECIFICATIONS AC and DC CHARACTERISTICS Param. Symbol Characteristic No. CM10 CM11 CM12 CM13 CM14 VIOFF VICM VGAIN CMRR TRESP Input Offset Voltage Input Common Mode Voltage Range(1) Open Loop Gain(1) Common Mode Rejection Ratio(1) Large Signal Response 0 90 70 Standard Operating Conditions (unless otherwise stated) Operating temperature: -40C TA +85C for Industrial -40C TA +125C for Extended Min Typ 5 -- -- -- 20 Max 15 AVDD - 1.5 -- -- 30 Units mV V db db ns V+ input step of 100 mv while V- input held at AVDD/2. Delay measured from analog input pin to PWM output pin. Comments Note 1: Parameters are for design guidance only and are not tested in manufacturing. TABLE 27-39: DAC MODULE SPECIFICATIONS AC and DC CHARACTERISTICS Param. Symbol Characteristic No. DA01 DA02 DA03 DA04 DA05 DA06 DA07 CVRSRC External Reference Voltage(1) CVRES INL DNL EOFF EG TSET Resolution Integral Nonlinearity Error Differential Nonlinearity Error Offset Error Gain Error Settling Time(1) -- -- -- -- Standard Operating Conditions (unless otherwise stated) Operating temperature: -40C TA +85C for Industrial -40C TA +125C for Extended Min 0 1.0 0.8 2.0 2.0 Typ Max AVDD - 1.6 10 data bits -- -- -- -- 650 Units V bits -- LSB LSB LSB nsec Measured when range = 1 (high range), and CMREF<9:0> transitions from 0x1FF to 0x300. AVDD = 3.3V, DACREF = (AVDD/2)V Comments Note 1: Parameters are for design guidance only and are not tested in manufacturing. DS70591B-page 384 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 TABLE 27-40: DAC OUTPUT BUFFER SPECIFICATIONS DC CHARACTERISTICS Param. Symbol Characteristic No. DA10 DA11 DA12 DA13 DA14 RLOAD CLOAD IOUT VRANGE Resistive Output Load Impedance Output Load Capacitance Output Current Drive Strength Full Output Drive Strength Voltage Range Standard Operating Conditions (unless otherwise stated) Operating temperature: -40C TA +85C for Industrial -40C TA +125C for Extended Min 3K -- 200 AVSS + 250 mV AVSS + 50 mV Typ -- 20 300 -- -- Max -- 35 400 AVDD - 900 mV AVDD - 500 mV Units pF A V V Sink and source Comments VLRANGE Output Drive Voltage Range at Reduced Current Drive of 50 A IDD Current Consumed when Module is Enabled, High-Power Mode DA15 -- -- 1.3 x IOUT A Module will always consume this current even if no load is connected to the output Closed loop output resistance DA16 ROUTON Output Impedance when Module is Enabled -- -- 10 FIGURE 27-20: QEA/QEB INPUT CHARACTERISTICS TQ36 QEA (input) TQ31 TQ35 TQ30 QEB (input) TQ41 TQ40 TQ31 TQ35 TQ30 QEB Internal 2009 Microchip Technology Inc. Preliminary DS70591B-page 385 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 TABLE 27-41: QUADRATURE DECODER TIMING REQUIREMENTS AC CHARACTERISTICS Param No. TQ30 TQ31 TQ35 TQ36 TQ40 TQ41 Note 1: 2: 3: Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +125C for Extended Characteristic(1) Quadrature Input Low Time Quadrature Input High Time Quadrature Input Period Quadrature Phase Period Filter Time to Recognize Low, with Digital Filter Filter Time to Recognize High, with Digital Filter Typ(2) 6 TCY 6 TCY 12 TCY 3 TCY 3 * N * TCY 3 * N * TCY Max -- -- -- -- -- -- Units ns ns ns ns ns ns Conditions -- -- -- -- N = 1, 2, 4, 16, 32, 64, 128 and 256 (Note 3) N = 1, 2, 4, 16, 32, 64, 128 and 256 (Note 3) Symbol TQUL TQUH TQUIN TQUP TQUFL TQUFH These parameters are characterized but not tested in manufacturing. Data in "Typ" column is at 3.3V, 25C unless otherwise stated. N = Index Channel Digital Filter Clock Divide Select bits. Refer to Section 15. "Quadrature Encoder Interface (QEI)" in the "dsPIC33F/PIC24H Family Reference Manual". FIGURE 27-21: QEA (input) QEI MODULE INDEX PULSE TIMING CHARACTERISTICS QEB (input) Ungated Index TQ51 Index Internal TQ55 Position Counter Reset TQ50 DS70591B-page 386 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 TABLE 27-42: QEI INDEX PULSE TIMING REQUIREMENTS AC CHARACTERISTICS Param No. TQ50 TQ51 TQ55 Note 1: 2: Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +125C for Extended Characteristic(1) Filter Time to Recognize Low, with Digital Filter Filter Time to Recognize High, with Digital Filter Index Pulse Recognized to Position Counter Reset (ungated index) Min 3 * N * TCY 3 * N * TCY 3 TCY Max -- -- -- Units ns ns ns Conditions N = 1, 2, 4, 16, 32, 64, 128 and 256 (Note 2) N = 1, 2, 4, 16, 32, 64, 128 and 256 (Note 2) -- Symbol TqIL TqiH Tqidxr These parameters are characterized but not tested in manufacturing. Alignment of index pulses to QEA and QEB is shown for position counter Reset timing only. Shown for forward direction only (QEA leads QEB). Same timing applies for reverse direction (QEA lags QEB) but index pulse recognition occurs on falling edge. FIGURE 27-22: QEB TIMERQ (QEI MODULE) EXTERNAL CLOCK TIMING CHARACTERISTICS TQ10 TQ15 POSCNT TQ11 TQ20 TABLE 27-43: QEI MODULE EXTERNAL CLOCK TIMING REQUIREMENTS AC CHARACTERISTICS Param No. TQ10 TQ11 TQ15 TQ20 Note 1: Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +125C for Extended Characteristic(1) TQCK High Time TQCK Low Time TQCP Input Period Synchronous, with prescaler Synchronous, with prescaler Min TCY + 20 TCY + 20 Typ -- -- -- -- Max -- -- -- 1.5 TCY Units ns ns ns -- Conditions Must also meet parameter TQ15 Must also meet parameter TQ15 -- -- Symbol TtQH TtQL TtQP Synchronous, 2 * TCY + 40 with prescaler 0.5 TCY TCKEXTMRL Delay from External TxCK Clock Edge to Timer Increment These parameters are characterized but not tested in manufacturing. 2009 Microchip Technology Inc. Preliminary DS70591B-page 387 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 FIGURE 27-23: CAN MODULE I/O TIMING CHARACTERISTICS CiTx Pin (output) CiRx Pin (input) Old Value CA10 CA11 New Value CA20 TABLE 27-44: ECANTM MODULE I/O TIMING REQUIREMENTS AC CHARACTERISTICS Param No. CA10 CA11 CA20 Note 1: Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +125C for Extended Characteristic(1) Port Output Fall Time Port Output Rise Time Pulse Width to Trigger CAN Wake-up Filter Min -- -- 120 Typ -- -- -- Max -- -- -- Units ns ns ns Conditions See parameter D032 See parameter D031 -- Symbol TioF TioR Tcwf These parameters are characterized but not tested in manufacturing. DS70591B-page 388 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 28.0 PACKAGING INFORMATION 64-Lead QFN (9x9x0.9mm) Example XXXXXXXXXX XXXXXXXXXX YYWWNNN 33FJ32FJ32 GS406-I/MR e3 0610017 64-Lead TQFP (10x10x1mm) Example XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN dsPIC33FJ 32GS406 -I/PT e3 0610017 80-Lead TQFP (12x12x1mm) Example XXXXXXXXXXXX XXXXXXXXXXXX YYWWNNN 33FJ32GS608 -I/PT e3 0610017 Legend: XX...X Y YY WW NNN * Note: e3 Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week `01') Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. If the full Microchip part number cannot be marked on one line, it is carried over to the next line, thus limiting the number of available characters for customer-specific information. 2009 Microchip Technology Inc. Preliminary DS70591B-page 389 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 100-Lead TQFP (12x12x1 mm) Example XXXXXXXXXXXX XXXXXXXXXXXX YYWWNNN dsPIC33FJ64 GS608-I/PT e3 0510017 100-Lead TQFP (14x14x1mm) Example XXXXXXXXXXXX XXXXXXXXXXXX YYWWNNN 33FJ32GS610 -I/PF e3 0610017 Legend: XX...X Y YY WW NNN * Note: e3 Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week `01') Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. If the full Microchip part number cannot be marked on one line, it is carried over to the next line, thus limiting the number of available characters for customer-specific information. DS70591B-page 390 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 28.1 Package Details Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2009 Microchip Technology Inc. Preliminary DS70591B-page 391 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS70591B-page 392 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2009 Microchip Technology Inc. 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Preliminary DS70591B-page 401 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 NOTES: DS70591B-page 402 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 APPENDIX A: MIGRATING FROM dsPIC33FJ06GS101/X02 AND dsPIC33FJ16GSX02/X04 TO dsPIC33FJ32GS406/606/608/610 AND DSPIC33FJ64GS406/606/608/610 DEVICES On dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 devices, Fault1 through Fault8 were assigned to Fault and CurrentLimit Controls with the following values: * * * * * * * * 01000 = Fault 1 01001 = Fault 2 01010 = Fault 3 01011 = Fault 4 01100 = Fault 5 01101 = Fault 6 01110 = Fault 7 01111 = Fault 8 This appendix provides an overview of considerations for migrating from the dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 family of devices to the dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 family of devices. The code developed for the dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 devices can be ported to the dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 devices after making the appropriate changes outlined below. A.1 Device Pins and Peripheral Pin Select (PPS) On dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 devices, some peripherals such as the Timer, Input Capture, Output Compare, UART, SPI, External Interrupts, Analog Comparator Output, as well as the PWM4 pin pair, were mapped to physical pins via Peripheral Pin Select (PPS) functionality. On dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 devices, these peripherals are hard-coded to dedicated pins. Because of this, as well as pinout differences between the two devices families, software must be updated to utilize peripherals on the desired pin locations. A.2.2 ANALOG COMPARATORS CONNECTION A.2 A.2.1 High-Speed PWM FAULT AND CURRENT-LIMIT CONTROL SIGNAL SOURCE SELECTION Connection of analog comparators to the PWM Fault and Current-Limit Control Signal Sources on dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/ X04 devices is performed by assigning a comparator to one of the Fault sources via the virtual PPS pins, and then selecting the desired Fault as the source for Fault and Current-Limit Control. On dsPIC33FJ32GS406/ 606/608/610 and DSPIC33FJ64GS406/606/608/610 devices, analog comparators have a direct connection to Fault and Current-Limit Control, and can be selected with the following values for the CLSRC or FLTSRC bits: * * * * 00000 = Analog Comparator 1 00001 = Analog Comparator 2 00010 = Analog Comparator 3 00011 = Analog Comparator 4 Fault and Current-Limit Control Signal Source selection has changed between the two families of devices. On dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 devices, Fault1 through Fault8 were assigned to Fault and Current-Limit Controls with the following values: * * * * * * * * 00000 = Fault 1 00001 = Fault 2 00010 = Fault 3 00011 = Fault 4 00100 = Fault 5 00101 = Fault 6 00110 = Fault 7 00111 = Fault 8 A.2.3 LEADING-EDGE BLANKING (LEB) The Leading-Edge Blanking Delay (LEB) bits have been moved from the LEBCOx register on dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/ X04 devices to the LEBDLYx register on dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 devices. 2009 Microchip Technology Inc. Preliminary DS70591B-page 403 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 APPENDIX B: REVISION HISTORY Revision B (November 2009) The revision includes the following global update: * Added Note 2 to the shaded table that appears at the beginning of each chapter. This new note provides information regarding the availability of registers and their associated bits This revision also includes minor typographical and formatting changes throughout the data sheet text. All other major changes are referenced by their respective section in Table B-1. Revision A (March 2009) This is the initial release of this document. TABLE B-1: MAJOR SECTION UPDATES Section Name Update Description Added "DMA Channels" column and updated the RAM size to 9K for the DSPIC33FJ64GS406 devices in the controller families table (see Table 1). Updated the pin diagrams as follows: * 64-pin TQFP and QFN - Removed FLT8 from pin 51 - Added FLT8 to pin 60 - Added FLT17 to pin 31 - Added FLT18 to pin32 * 80-pin TQFP - Removed FLT8 from pin 63 - Added FLT8 to pin 76 - Added FLT19 to pin 53 - Added FLT20 to pin 52 * 100-pin TQFP - Removed FLT8 from pin 78 - Added FLT8 to pin 93 - Added SYNCO1 to pin 95 "High-Performance, 16-Bit Digital Signal Controllers" Section 4.0 "Memory Organization" Added Data Memory Map for Devices with 8 KB RAM (see Figure 4-4). Removed SFRs IPC25 and IPC26 from the Interrupt Controller Register Map for dsPIC33FJ32GS406 and DSPIC33FJ64GS406 devices (see Table 4-7). The following bits in the Interrupt Controller Register Map for dsPIC33FJ32GS406 and DSPIC33FJ64GS406 devices were changed to unimplemented (see Table 4-7): * * * * * Bit 2 of IFS1 Bits 9-7 of IFS6 Bit 2 of IEC1 Bits 9-7 of IEC6 Bits 10-8 of IPC4 Removed OSCTUN2 and LFSR, updated OSCCON and OSCTUN, renamed bit 13 of the REFOCON SFR in the System Control Register Map from ROSIDL to ROSSLP and changed the All Resets value from `0000' to `2300' for the ACLKCON SFR (see Table 4-56). Updated bit 1 of the PMD Register Map for dsPIC33FJ64GS608 devices from unimplemented to C1MD (see Table 4-60). DS70591B-page 404 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 TABLE B-1: MAJOR SECTION UPDATES (CONTINUED) Section Name Update Description Section 9.0 "Oscillator Configuration" Removed Section 9.2 "FRC Tuning". Removed the PRCDEN, TSEQEN, and LPOSCEN bits from the Oscillator Control Register (see Register 9-1). Updated the Oscillator Tuning Register (see Register 9-4). Removed the Oscillator Tuning Register 2 and the Linear Feedback Shift Register. Updated the default reset values from R/W-0 to R/W-1 for the SELACLK and APSTSCLR<2:0> bits in the ACLKCON register (see Register 9-5). Renamed the ROSIDL bit to ROSSLP in the REFOCON register (see Register 9-6). Section 10.0 "Power-Saving Features" Updated the last paragraph of Section 10.2.2 "Idle Mode" to clarify when instruction execution begins. Added Note 1 to the PMD1 register (see Register 10-1). Section 11.0 "I/O Ports" Section 16.0 "High-Speed PWM" Changed the reference to digital-only pins to 5V tolerant pins in the second paragraph of Section 11.2 "Open-Drain Configuration". Updated the High-Speed PWM Module Register Interconnect Diagram (see Figure 16-2). Updated the SYNCSRC<2:0> = 111, 101, and 100 definitions to Reserved in the PTCON and STCON registers (see Register 16-1 and Register 16-5). Updated the PWM time base maximum value from 0xFFFB to 0xFFF8 in the PTPER register (Register 16-3). Updated the smallest pulse width value from 0x0008 to 0x0009 in Note 1 of the shaded note that follows the MDC register (see Register 16-10). Updated the smallest pulse width value from 0x0008 to 0x0009 in Note 2 of the shaded note that follows the PDCx and SDCx registers (see Register 16-12 and Register 16-13). Added Note 2 and updated the FLTDAT<1:0> and CLDAT<1:0> bits, changing the word `data' to `state' in the IOCONx register (see Register 16-19). Section 20.0 "Universal Asynchronous Receiver Transmitter (UART)" Section 22.0 "High-Speed 10-bit Analog-to-Digital Converter (ADC)" Section 24.0 "Special Features" Updated the two baud rate range features to: 10 Mbps to 38 bps at 40 MIPS. Updated the TRGSRCx<4:0> = 01101 definition from Reserved to PWM secondary special event trigger selected, and updated Note 1 in the ADCP0-ADCP6 registers (see Register 22-6 through Register 22-12). Updated the second paragraph and removed the fourth paragraph in Section 24.1 "Configuration Bits". Updated the Device Configuration Register Map (see Table 24-1). 2009 Microchip Technology Inc. Preliminary DS70591B-page 405 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 TABLE B-1: MAJOR SECTION UPDATES (CONTINUED) Section Name Section 27.0 "Electrical Characteristics" Update Description Updated the Absolute Maximum Ratings for high temperature and added Note 4. Updated all Operating Current (IDD) Typical and Max values in Table 27-5. Updated all Idle Current (IIDLE) Typical and Max values in Table 27-6. Updated all Power-Down Current (IPD) Typical and Max values in Table 27-7. Updated all Doze Current (IDOZE) Typical and Max values in Table 27-8. Updated the Typ and Max values for parameter D150 and removed parameters DI26, DI28, and DI29 from the I/O Pin Input Specifications (see Table 27-9). Updated the Typ and Max values for parameter DO10 and DO27 and the Min and Typ values for parameter DO20 in the I/O Pin Output Specifications (see Table 27-10). Added parameter numbers to the Auxiliary PLL Clock Timing Specifications (see Table 27-18). Added parameters numbers and updated the Internal RC Accuracy Min, Typ, and Max values (see Table 27-19 and Table 27-20). Added parameter numbers, Note 2, updated the Min and Typ parameter values for MP31 and MP32, and removed the conditions for MP10 and MP11 in the High-Speed PWM Module Timing Requirements (see Table 27-29). Updated the SPIx Module Slave Mode (CKE = 1) Timing Characteristics (see Figure 27-14). Added parameter IM51 to the I2Cx Bus Data Timing Requirements (Master Mode) (see Table 27-34). Updated the Max value for parameter AD33 in the 10-bit High-Speed A/D Module Specifications (see Table 27-36). Updated the titles and added parameter numbers to the Comparator and DAC Module Specifications (see Table 27-38 and Table 27-39) and the DAC Output Buffer Specifications (see Table 27-40). DS70591B-page 406 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 INDEX A AC Characteristics ............................................................ 362 Internal RC Accuracy ................................................ 364 Load Conditions ........................................................ 362 Alternate Vector Table (AIVT) ........................................... 123 Arithmetic Logic Unit (ALU)................................................. 41 Assembler MPASM Assembler................................................... 350 CPU Clocking System ...................................................... 189 PLL Configuration..................................................... 190 Selection................................................................... 189 Sources .................................................................... 189 Customer Change Notification Service............................. 413 Customer Notification Service .......................................... 413 Customer Support............................................................. 413 D DAC .................................................................................. 330 Output Range ........................................................... 330 Data Accumulators and Adder/Subtracter .......................... 43 Data Space Write Saturation ...................................... 45 Overflow and Saturation ............................................. 43 Round Logic ............................................................... 44 Write Back .................................................................. 44 Data Address Space........................................................... 49 Alignment.................................................................... 49 Memory Map for dsPIC33FJ32GS406/606/608/610 Devices with 4 KB RAM...................................... 50 Memory Map for DSPIC33FJ64GS406/606/608/610 Devices with 8 KB RAM...................................... 51 Memory Map for DSPIC33FJ64GS406/606/608/610 Devices with 9 KB RAM...................................... 52 Near Data Space ........................................................ 49 Software Stack ......................................................... 100 Width .......................................................................... 49 DC Characteristics............................................................ 354 Doze Current (IDOZE)................................................ 358 I/O Pin Input Specifications ...................................... 359 I/O Pin Output Specifications.................................... 360 Idle Current (IIDLE) .................................................... 357 Operating Current (IDD) ............................................ 356 Power-Down Current (IPD)........................................ 358 Program Memory...................................................... 361 Temperature and Voltage Specifications.................. 355 Demonstration/Development Boards, Evaluation Kits, and Starter Kits ............................... 352 Development Support ....................................................... 349 DMAC Registers ............................................................... 178 DMAxCNT ................................................................ 178 DMAxCON................................................................ 178 DMAxPAD ................................................................ 178 DMAxREQ ................................................................ 178 DMAxSTA ................................................................. 178 DMAxSTB ................................................................. 178 Doze Mode ....................................................................... 200 DSP Engine ........................................................................ 41 Multiplier ..................................................................... 43 B Barrel Shifter ....................................................................... 45 Bit-Reversed Addressing .................................................. 103 Example .................................................................... 104 Implementation ......................................................... 103 Sequence Table (16-Entry)....................................... 104 Block Diagrams 16-bit Timer1 Module ................................................ 211 Comparator ............................................................... 329 Connections for On-Chip Voltage Regulator............. 336 Device Clock ............................................................. 191 DSP Engine ................................................................ 42 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 ...................... 20 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 CPU Core .... 36 ECAN Module ........................................................... 280 I2C............................................................................. 266 Input Capture ............................................................ 219 Oscillator System ...................................................... 188 Output Compare ....................................................... 221 PLL............................................................................ 191 Quadrature Encoder Interface .................................. 255 Reset System............................................................ 115 Shared Port Structure ............................................... 209 Simplified Conceptual High-Speed PWM ................. 226 SPI ............................................................................ 259 Timer2/3 (32-bit) ....................................................... 215 Type B Timer ............................................................ 213 Type C Timer ............................................................ 213 UART ........................................................................ 273 Watchdog Timer (WDT) ............................................ 338 Brown-out Reset (BOR) .................................................... 333 C C Compilers Hi-Tech C.................................................................. 350 MPLAB C .................................................................. 350 Clock Switching................................................................. 198 Enabling .................................................................... 198 Sequence.................................................................. 198 Code Examples Erasing a Program Memory Page............................. 113 Initiating a Programming Sequence.......................... 114 Loading Write Buffers ............................................... 114 Port Write/Read ........................................................ 210 PWRSAV Instruction Syntax..................................... 199 Code Protection ........................................................ 333, 339 CodeGuard Security ......................................................... 333 Configuration Bits.............................................................. 333 Configuration Register Map .............................................. 333 Configuring Analog Port Pins ............................................ 210 CPU Control Registers ........................................................ 38 E ECAN Module CiBUFPNT1 register................................................. 291 CiBUFPNT2 register................................................. 292 CiBUFPNT3 register................................................. 292 CiBUFPNT4 register................................................. 293 CiCFG1 register........................................................ 289 CiCFG2 register........................................................ 290 CiCTRL1 register...................................................... 282 CiCTRL2 register...................................................... 283 CiEC register ............................................................ 289 CiFCTRL register...................................................... 285 CiFEN1 register ........................................................ 291 CiFIFO register ......................................................... 286 2009 Microchip Technology Inc. Preliminary DS70591B-page 407 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 CiFMSKSEL1 register ............................................... 295 CiFMSKSEL2 register ............................................... 296 CiINTE register ......................................................... 288 CiINTF register.......................................................... 287 CiRXFnEID register .................................................. 295 CiRXFnSID register .................................................. 294 CiRXFUL1 register .................................................... 298 CiRXFUL2 register .................................................... 298 CiRXMnEID register.................................................. 297 CiRXMnSID register.................................................. 297 CiRXOVF1 register ................................................... 299 CiRXOVF2 register ................................................... 299 CiTRmnCON register ................................................ 300 CiVEC register .......................................................... 284 Frame Types ............................................................. 279 Modes of Operation .................................................. 281 Overview ................................................................... 279 ECAN Registers Acceptance Filter Enable Register (CiFEN1)............ 291 Acceptance Filter Extended Identifier Register n (CiRXFnEID).................................... 295 Acceptance Filter Mask Extended Identifier Register n (CiRXMnEID)................................... 297 Acceptance Filter Mask Standard Identifier Register n (CiRXMnSID)................................... 297 Acceptance Filter Standard Identifier Register n (CiRXFnSID).................................... 294 Baud Rate Configuration Register 1 (CiCFG1) ......... 289 Baud Rate Configuration Register 2 (CiCFG2) ......... 290 Control Register 1 (CiCTRL1) ................................... 282 Control Register 2 (CiCTRL2) ................................... 283 FIFO Control Register (CiFCTRL) ............................ 285 FIFO Status Register (CiFIFO) ................................. 286 Filter 0-3 Buffer Pointer Register (CiBUFPNT1) ....... 291 Filter 12-15 Buffer Pointer Register (CiBUFPNT4).................................................... 293 Filter 15-8 Mask Selection Register (CiFMSKSEL2) ................................................. 296 Filter 4-7 Buffer Pointer Register (CiBUFPNT2) ....... 292 Filter 7-0 Mask Selection Register (CiFMSKSEL1) ................................................. 295 Filter 8-11 Buffer Pointer Register (CiBUFPNT3).................................................... 292 Interrupt Code Register (CiVEC) .............................. 284 Interrupt Enable Register (CiINTE) ........................... 288 Interrupt Flag Register (CiINTF) ............................... 287 Receive Buffer Full Register 1 (CiRXFUL1).............. 298 Receive Buffer Full Register 2 (CiRXFUL2).............. 298 Receive Buffer Overflow Register 2 (CiRXOVF2)..... 299 Receive Overflow Register (CiRXOVF1) .................. 299 ECAN Transmit/Receive Error Count Register (CiEC) ..... 289 ECAN TX/RX Buffer m Control Register (CiTRmnCON) .......................................................... 300 Electrical Characteristics................................................... 353 AC Characteristics and Timing Parameters .............. 362 BOR .......................................................................... 360 Enhanced CAN Module..................................................... 279 Equations Device Operating Frequency .................................... 189 FOSC Calculation....................................................... 190 XT with PLL Mode Example...................................... 190 Errata .................................................................................. 18 F Fail-Safe Clock Monitor (FSCM)....................................... 198 Flash Program Memory .................................................... 109 Control Registers ...................................................... 110 Operations ................................................................ 110 Programming Algorithm ............................................ 113 RTSP Operation ....................................................... 110 Table Instructions ..................................................... 109 Flexible Configuration ....................................................... 333 H High-Speed Analog Comparator....................................... 329 High-Speed PWM ............................................................. 225 I I/O Ports............................................................................ 209 Parallel I/O (PIO) ...................................................... 209 Write/Read Timing .................................................... 210 I2C Operating Modes ...................................................... 265 Registers .................................................................. 265 In-Circuit Debugger........................................................... 338 In-Circuit Emulation .......................................................... 333 In-Circuit Serial Programming (ICSP)....................... 333, 338 Input Capture .................................................................... 219 Registers .................................................................. 220 Input Change Notification ................................................. 210 Instruction Addressing Modes .......................................... 100 File Register Instructions .......................................... 100 Fundamental Modes Supported ............................... 101 MAC Instructions ...................................................... 101 MCU Instructions ...................................................... 100 Move and Accumulator Instructions.......................... 101 Other Instructions ..................................................... 101 Instruction Set Overview................................................................... 344 Summary .................................................................. 341 Instruction-Based Power-Saving Modes........................... 199 Idle ............................................................................ 200 Sleep ........................................................................ 199 Interfacing Program and Data Memory Spaces................ 105 Internal RC Oscillator Use with WDT........................................................... 337 Internet Address ............................................................... 413 Interrupt Control and Status Registers ............................. 127 IECx .......................................................................... 127 IFSx .......................................................................... 127 INTCON1 .................................................................. 127 INTCON2 .................................................................. 127 INTTREG .................................................................. 127 IPCx .......................................................................... 127 Interrupt Setup Procedures............................................... 176 Initialization ............................................................... 176 Interrupt Disable ....................................................... 176 Interrupt Service Routine .......................................... 176 Trap Service Routine ................................................ 176 Interrupt Vector Table (IVT) .............................................. 123 Interrupts Coincident with Power Save Instructions ......... 200 J JTAG Boundary Scan Interface ........................................ 333 JTAG Interface.................................................................. 338 L Leading-Edge Blanking (LEB) .......................................... 225 DS70591B-page 408 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 M Memory Organization.......................................................... 47 Microchip Internet Web Site .............................................. 413 Migrating from dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 to dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 Devices .............. 403 Migration Analog Comparators Connection.............................. 403 Device Pins and Peripheral Pin Select (PPS)........... 403 Fault and Current-Limit Control Signal Source Selection............................................... 403 Leading-Edge Blanking (LEB)................................... 403 Modes of Operation Disable ...................................................................... 281 Initialization ............................................................... 281 Listen All Messages .................................................. 281 Listen Only ................................................................ 281 Loopback .................................................................. 281 Normal Operation...................................................... 281 Modulo Addressing ........................................................... 102 Applicability ............................................................... 103 Operation Example ................................................... 102 Start and End Address.............................................. 102 W Address Register Selection .................................. 102 MPLAB ASM30 Assembler, Linker, Librarian ................... 350 MPLAB ICD 3 In-Circuit Debugger System ...................... 351 MPLAB Integrated Development Environment Software............................................... 349 MPLAB PM3 Device Programmer .................................... 352 MPLAB REAL ICE In-Circuit Emulator System................. 351 MPLINK Object Linker/MPLIB Object Librarian ................ 350 Memory Map............................................................... 47 Table Read Instructions TBLRDH ........................................................... 107 TBLRDL............................................................ 107 Visibility Operation.................................................... 108 Program Memory Interrupt Vector........................................................... 48 Organization ............................................................... 48 Reset Vector............................................................... 48 Q Quadrature Encoder Interface (QEI)................................. 255 R Reader Response............................................................. 414 Register Maps Analog Comparator .................................................... 92 Change Notification (dsPIC33FJ32GS608/610 and dsPIC33FJ64GS608/601 Devices).............. 56 Change Notification (DSPIC33FJ64GS406/606 Devices) ................... 56 CPU Core ................................................................... 54 DMA............................................................................ 88 ECAN1 (C1CTRL1.WIN = 0 or 1) ............................... 89 ECAN1 (C1CTRL1.WIN = 0) ...................................... 89 ECAN1 (C1CTRL1.WIN = 1) ...................................... 90 High-Speed 10-bit ADC Module (dsPIC33FJ32GS608 and dsPIC33FJ64GS608 Devices)............................ 86 High-Speed 10-bit ADC Module (dsPIC33FJ32GS610 and dsPIC33FJ64GS610 Devices)............................ 84 High-Speed 10-bit ADC Module (for dsPIC33FJ32GS406/606 and DSPIC33FJ64GS406/606 Devices)..................... 87 High-Speed PWM....................................................... 73 High-Speed PWM Generator 1................................... 73 High-Speed PWM Generator 2................................... 74 High-Speed PWM Generator 3................................... 75 High-Speed PWM Generator 4................................... 76 High-Speed PWM Generator 5................................... 77 High-Speed PWM Generator 6................................... 78 High-Speed PWM Generator 7 (All devices except dsPIC33FJ32GS406 and DSPIC33FJ64GS406) ......................................... 79 High-Speed PWM Generator 8 (All devices except dsPIC33FJ32GS406 and DSPIC33FJ64GS406) ......................................... 80 High-Speed PWM Generator 9 (dsPIC33FJ32GS610 and dsPIC33FJ64GS610 Devices)............................ 81 I2C1 ............................................................................ 81 I2C2 ............................................................................ 82 Input Capture.............................................................. 71 Interrupt Controller (dsPIC33FJ32GS406 and DSPIC33FJ64GS406 Devices)............................. 63 Interrupt Controller (dsPIC33FJ32GS606 Devices) ... 69 Interrupt Controller (dsPIC33FJ32GS608 Devices) ... 67 Interrupt Controller (dsPIC33FJ32GS610 Devices) ... 65 Interrupt Controller (dsPIC33FJ64GS606 Devices) ... 61 Interrupt Controller (dsPIC33FJ64GS608 Devices) ... 59 Interrupt Controller (dsPIC33FJ64GS610 Devices) ... 57 NVM............................................................................ 97 Output Compare ......................................................... 72 PMD (dsIPC33FJ64GS606 Devices) ......................... 98 O Open-Drain Configuration ................................................. 210 Oscillator Configuration..................................................... 187 Oscillator Tuning Register (OSCTUN) .............................. 195 Output Compare ............................................................... 221 P Packaging ......................................................................... 389 100-Lead TQFP ........................................................ 398 100-Lead TQFP Land Pattern................................... 399 64-Lead QFN ............................................ 391, 392, 395 64-Lead QFN Land Pattern....................................... 395 64-Lead TQFP .......................................................... 394 64-Lead TQFP Land Pattern..................................... 395 80-Lead TQFP .......................................................... 396 80-Lead TQFP Land Pattern..................................... 397 Marking ..................................................................... 389 Peripheral Module Disable (PMD) .................................... 201 PICkit 2 Development Programmer/Debugger and PICkit 2 Debug Express..................................... 352 PICkit 3 In-Circuit Debugger/Programmer and PICkit 3 Debug Express............................................ 351 Pinout I/O Descriptions (table) ............................................ 21 Power-on Reset (POR) ..................................................... 119 Power-Saving Features .................................................... 199 Clock Frequency and Switching................................ 199 Program Address Space ..................................................... 47 Construction.............................................................. 105 Data Access from Program Memory Using Program Space Visibility......................... 108 Data Access from Program Memory Using Table Instructions ............................................. 107 Data Access from, Address Generation.................... 106 2009 Microchip Technology Inc. Preliminary DS70591B-page 409 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 PMD (dsPIC33FJ32GS406 and DSPIC33FJ64GS406 Devices) ............................ 99 PMD (dsPIC33FJ32GS606 Devices) .......................... 99 PMD (dsPIC33FJ32GS608 Devices) .......................... 98 PMD (dsPIC33FJ32GS610 Devices) .......................... 97 PMD (dsPIC33FJ64GS608 Devices) .......................... 98 PMD (dsPIC33FJ64GS610 Devices) .......................... 97 PORTA (dsPIC33FJ32GS608 and dsPIC33FJ64GS608 Devices) ............................ 92 PORTA (dsPIC33FJ32GS610 and dsPIC33FJ64GS610 Devices) .................................... 92 PORTB........................................................................ 93 PORTC (dsPIC33FJ32GS406/606 and DSPIC33FJ64GS406/606 Devices) ..................... 93 PORTC (dsPIC33FJ32GS608 and dsPIC33FJ64GS608 Devices) ............................ 93 PORTC (dsPIC33FJ32GS610 and dsPIC33FJ64GS610 Devices) ............................ 93 PORTD (dsPIC33FJ32GS406/606 and DSPIC33FJ64GS406/606 Devices) ..................... 94 PORTD (dsPIC33FJ32GS608/610 and dsPIC33FJ64GS608/610 Devices) ..................... 94 PORTE (dsPIC33FJ32GS406/606 and DSPIC33FJ64GS406/606 Devices) ..................... 94 PORTE (dsPIC33FJ32GS608/610 and dsPIC33FJ64GS608/610 Devices) ..................... 94 PORTF (dsPIC33FJ32GS406/606 and DSPIC33FJ64GS406/606 Devices) ..................... 95 PORTF (dsPIC33FJ32GS608 and dsPIC33FJ64GS608 Devices) ............................ 95 PORTF (dsPIC33FJ32GS610 and dsPIC33FJ64GS610 Devices) ............................ 95 PORTG (dsPIC33FJ32GS406/606 and DSPIC33FJ64GS406/606 Devices) ..................... 96 PORTG (dsPIC33FJ32GS608 and dsPIC33FJ64GS608 Devices) ............................ 96 PORTG (dsPIC33FJ32GS610 and dsPIC33FJ64GS610 Devices) ............................ 95 Quadrature Encoder Interface (QEI) 1 ........................ 72 Quadrature Encoder Interface (QEI) 2 ........................ 72 SPI1 ............................................................................ 83 SPI2 ............................................................................ 83 System Control ........................................................... 96 Timers ......................................................................... 71 UART1 ........................................................................ 82 UART2 ........................................................................ 82 Registers A/D Control Register (ADCON)................................. 311 A/D Convert Pair Control Register 0 (ADCPC0) ....... 316 A/D Convert Pair Control Register 1 (ADCPC1) ....... 318 A/D Convert Pair Control Register 2 (ADCPC2) ....... 320 A/D Convert Pair Control Register 3 (ADCPC3) ....... 322 A/D Convert Pair Control Register 4 (ADCPC4) ....... 324 A/D Convert Pair Control Register 5 (ADCPC5) ....... 326 A/D Convert Pair Control Register 6 (ADCPC6) ....... 328 A/D Port Configuration Register (ADPCFG) ............. 315 A/D Status Register (ADSTAT) ................................. 313 ACLKCON (Auxiliary Clock Divisor Control) ............. 196 ADBASE (A/D Base) ................................................. 314 ADCON (A/D Control) ............................................... 311 ADCPC0 (A/D Convert Pair Control 0) ..................... 316 ADCPC1 (A/D Convert Pair Control 1) ..................... 318 ADCPC2 (A/D Convert Pair Control 2) ..................... 320 ADCPC3 (A/D Convert Pair Control 3) ..................... 322 ADCPC4 (A/D Convert Pair Control 4) ..................... 324 ADCPC5 (A/D Convert Pair Control 5) ..................... 326 ADCPC6 (A/D Convert Pair Control 6) ..................... 328 ADPCFG (A/D Port Configuration) ........................... 315 ADPCFG2 (A/D Port Configuration) ......................... 315 ADSTAT (A/D Status) ............................................... 313 ALTDTRx (PWM Alternate Dead Time).................... 242 AUXCONx (PWM Auxiliary Control) ......................... 253 CHOP (PWM Chop Clock Generator) ...................... 235 CiBUFPNT1 (ECAN Filter 0-3 Buffer Pointer) .......... 291 CiBUFPNT2 (ECAN Filter 4-7 Buffer Pointer) .......... 292 CiBUFPNT3 (ECAN Filter 8-11 Buffer Pointer) ........ 292 CiBUFPNT4 (ECAN Filter 12-15 Buffer Pointer) ...... 293 CiCFG1 (ECAN Baud Rate Configuration 1) ............ 289 CiCFG2 (ECAN Baud Rate Configuration 2) ............ 290 CiCTRL1 (ECAN Control 1) ...................................... 282 CiCTRL2 (ECAN Control 2) ...................................... 283 CiEC (ECAN Transmit/Receive Error Count) ........... 289 CiFCTRL (ECAN FIFO Control)................................ 285 CiFEN1 (ECAN Acceptance Filter Enable)............... 291 CiFIFO (ECAN FIFO Status) .................................... 286 CiFMSKSEL1 (ECAN Filter 7-0 Mask Selection)...... 295 CiFMSKSEL2 (ECAN Filter 15-8 Mask Selection).... 296 CiINTE (ECAN Interrupt Enable) .............................. 288 CiINTF (ECAN Interrupt Flag)................................... 287 CiRXFnEID (ECAN Acceptance Filter n Extended Identifier) .......................................... 295 CiRXFnSID (ECAN Acceptance Filter n Standard Identifier) ........................................... 294 CiRXFUL1 (ECAN Receive Buffer Full 1)................. 298 CiRXFUL2 (ECAN Receive Buffer Full 2)................. 298 CiRXMnEID (ECAN Acceptance Filter Mask n Extended Identifier) .......................................... 297 CiRXMnSID (ECAN Acceptance Filter Mask n Standard Identifier) ........................................ 297 CiRXOVF1 (ECAN Receive Buffer Overflow 1)........ 299 CiRXOVF2 (ECAN Receive Buffer Overflow 2)........ 299 CiTRBnSID (ECAN Buffer n Standard Identifier)..... 301, 302, 304 CiTRmnCON (ECAN TX/RX Buffer m Control) ........ 300 CiVEC (ECAN Interrupt Code).................................. 284 CLKDIV (Clock Divisor) ............................................ 193 CMPCONx (Comparator Control) ............................. 331 CMPCPNx (Comparator Control) ............................. 331 CMPDACx (Comparator DAC Control)..................... 332 CORCON (Core Control) .................................... 40, 128 DFLTCON (QEI Control)........................................... 258 DFLTxCON (Digital Filter Control) ............................ 258 DMACS0 (DMA Controller Status 0)......................... 183 DMACS1 (DMA Controller Status 1)......................... 184 DMAxCNT (DMA Channel x Transfer Count) ........... 182 DMAxCON (DMA Channel x Control)....................... 179 DMAxPAD (DMA Channel x Peripheral Address) .... 182 DMAxREQ (DMA Channel x IRQ Select) ................. 180 DMAxSTA (DMA Channel x RAM Start Address A) ............................................... 181 DMAxSTB (DMA Channel x RAM Start Address B) ............................................... 181 DSADR (Most Recent DMA RAM Address) ............. 185 DTRx (PWM Dead Time).......................................... 242 FCLCONx (PWM Fault Current-Limit Control).......... 247 I2CxCON (I2Cx Control) ........................................... 267 I2CxMSK (I2Cx Slave Mode Address Mask) ............ 271 I2CxSTAT (I2Cx Status) ........................................... 269 ICxCON (Input Capture x Control, x = 1, 2).............. 220 ICxCON (Input Capture x Control)............................ 220 IEC0 (Interrupt Enable Control 0) ............................. 141 IEC1 (Interrupt Enable Control 1) ............................. 143 DS70591B-page 410 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 IEC2 (Interrupt Enable Control 2) ............................. 144 IEC3 (Interrupt Enable Control 3) ............................. 145 IEC4 (Interrupt Enable Control 4) ............................. 146 IEC5 (Interrupt Enable Control 5) ............................. 147 IEC6 (Interrupt Enable Control 6) ............................. 148 IEC7 (Interrupt Enable Control 7) ............................. 149 IFS0 (Interrupt Flag Status 0) ................................... 132 IFS1 (Interrupt Flag Status 1) ................................... 134 IFS2 (Interrupt Flag Status 2) ................................... 135 IFS3 (Interrupt Flag Status 3) ................................... 136 IFS4 (Interrupt Flag Status 4) ................................... 137 IFS5 (Interrupt Flag Status 5) ................................... 138 IFS6 (Interrupt Flag Status 6) ................................... 139 IFS7 (Interrupt Flag Status 7) ................................... 140 INTCON1 (Interrupt Control 1).................................. 129 INTCON1 (Interrupt Control Register 1) ................... 129 INTCON2 (Interrupt Control Register 2) ................... 131 INTTREG (Interrupt Control and Status)................... 175 INTTREG Interrupt Control and Status ..................... 175 IOCONx (PWM I/O Control)...................................... 244 IPC0 (Interrupt Priority Control 0) ............................. 150 IPC1 (Interrupt Priority Control 1) ............................. 151 IPC12 (Interrupt Priority Control 12) ......................... 160 IPC13 (Interrupt Priority Control 13) ......................... 161 IPC14 (Interrupt Priority Control 14) ......................... 162 IPC16 (Interrupt Priority Control 16) ......................... 163 IPC17 (Interrupt Priority Control 17) ......................... 164 IPC18 (Interrupt Priority Control 18) ......................... 165 IPC2 (Interrupt Priority Control 2) ............................. 152 IPC20 (Interrupt Priority Control 20) ......................... 166 IPC21 (Interrupt Priority Control 21) ......................... 167 IPC23 (Interrupt Priority Control 23) ......................... 168 IPC24 (Interrupt Priority Control 24) ......................... 169 IPC25 (Interrupt Priority Control 25) ......................... 170 IPC26 (Interrupt Priority Control 26) ......................... 171 IPC27 (Interrupt Priority Control 27) ......................... 172 IPC28 (Interrupt Priority Control 28) ......................... 173 IPC29 (Interrupt Priority Control 29) ......................... 174 IPC3 (Interrupt Priority Control 3) ............................. 153 IPC4 (Interrupt Priority Control 4) ............................. 154 IPC5 (Interrupt Priority Control 5) ............................. 155 IPC6 (Interrupt Priority Control 6) ............................. 156 IPC7 (Interrupt Priority Control 7) ............................. 157 IPC8 (Interrupt Priority Control 8) ............................. 158 IPC9 (Interrupt Priority Control 9) ............................. 159 LEBCONx (Leading-Edge Blanking Control) ............ 251 LEBDLYx (Leading-Edge Blanking Delay)................ 252 MDC (PWM Master Duty Cycle) ............................... 236 NVMCON (Flash Memory Control) ........................... 111 NVMKEY (Non-Volatile Memory Key)....................... 112 NVMKEY (Nonvolatile Memory Key) ........................ 112 OCxCON (Output Compare x Control, x = 1, 2) ....... 223 OSCCON (Oscillator Control) ................................... 192 OSCTUN (Oscillator Tuning) .................................... 195 PDCx (PWM Generator Duty Cycle)......................... 239 PHASEx (PWM Primary Phase Shift) ....................... 240 PLLFBD (PLL Feedback Divisor).............................. 194 PMD1 (Peripheral Module Disable Control 1 ............ 202 PMD1 (Peripheral Module Disable Control 1)........... 202 PMD2 (Peripheral Module Disable Control 2)........... 204 PMD3 (Peripheral Module Disable Control 3)........... 205 PMD4 (Peripheral Module Disable Control 4)........... 205 PMD6 (Peripheral Module Disable Control 6)........... 206 PMD7 (Peripheral Module Disable Control 7)........... 207 PTCON (PWM Time Base Control) .......................... 229 PTCON2 (PWM Clock Divider Select)...................... 231 PTPER (Primary Master Time Base Period) ............ 231 PWMCAPx (Primary PWM Time Base Capture) ...... 254 PWMCONx (PWM Control) ...................................... 237 QEICON (QEI Control) ............................................. 256 QEIxCON (QEIx Control, x = 1 or 2)......................... 256 RCON (Reset Control).............................................. 116 REFOCON (Reference Oscillator Control) ............... 197 SDCx (PWM Secondary Duty Cycle) ....................... 239 SEVTCMP ................................................................ 235 SEVTCMP (Special Event Compare) ....................... 232 SPHASEx (PWM Secondary Phase Shift) ............... 241 SPIxCON1 (SPIx Control 1) ..................................... 261 SPIxCON2 (SPIx Control 2) ..................................... 263 SPIxSTAT (SPIx Status and Control) ....................... 260 SR (CPU STATUS) .................................................. 128 SR (CPU Status) ........................................................ 38 SSEVTCMP (PWM Secondary Special Event Compare) ............................................... 235 STCON (PWM Secondary Master Time Base Control).................................................... 233 STCON2 (PWM Secondary Clock Divider Select) .................................................. 234 STPER (Secondary Master Time Base Period) ....... 234 STRIGx (PWM Secondary Trigger Compare Value) ............................................... 250 T1CON (Timer1 Control) .......................................... 212 TRGCONx (PWM Trigger Control) ........................... 243 TRIGx (PWM Primary Trigger Compare Value) ....... 246 TxCON (Timer Control, x = 2)................................... 216 TyCON (Timer Control, y = 3)................................... 217 UxMODE (UARTx Mode) ......................................... 274 UxSTA (UARTx Status and Control) ........................ 276 Reset Illegal Opcode................................................... 115, 120 Trap Conflict ............................................................. 120 Uninitialized W Register ................................... 115, 120 Reset Sequence ............................................................... 123 Resets .............................................................................. 115 Resources Required for Digital PFC............................. 29, 32 Resources Required for Digital Phase-Shift ZVT Converter ............................................................ 34 S Serial Peripheral Interface (SPI) ....................................... 259 Software RESET Instruction (SWR) ................................. 120 Software Simulator (MPLAB SIM) .................................... 351 Software Stack Pointer, Frame Pointer CALL Stack Frame ................................................... 100 Special Event Compare Register (SEVTCMP)......... 232, 235 Special Features of the CPU ............................................ 333 Symbols Used in Opcode Descriptions ............................ 342 T Temperature and Voltage Specifications AC............................................................................. 362 Timer1 .............................................................................. 211 Timer2/3 ........................................................................... 213 Timing Diagrams A/D Conversion per Input ......................................... 383 Brown-out Situations ................................................ 119 CAN I/O .................................................................... 388 External Clock .......................................................... 363 High-Speed PWM..................................................... 372 High-Speed PWM Fault ............................................ 372 I/O............................................................................. 365 2009 Microchip Technology Inc. Preliminary DS70591B-page 411 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 I2Cx Bus Data (Master Mode) .................................. 378 I2Cx Bus Data (Slave Mode) .................................... 380 I2Cx Bus Start/Stop Bits (Master Mode) ................... 378 I2Cx Bus Start/Stop Bits (Slave Mode) ..................... 380 Input Capture (CAPx)................................................ 370 OC/PWM ................................................................... 371 Output Compare (OCx) ............................................. 370 QEA/QEB Input ......................................................... 385 QEI Module Index Pulse ........................................... 386 Reset, Watchdog Timer, Oscillator Start-up Timer and Power-up Timer ............................... 366 SPIx Master Mode (CKE = 0).................................... 373 SPIx Master Mode (CKE = 1).................................... 374 SPIx Slave Mode (CKE = 0)...................................... 375 SPIx Slave Mode (CKE = 1)...................................... 376 Timer1, 2, 3 External Clock....................................... 368 TimerQ (QEI Module) External Clock ....................... 387 Timing Requirements External Clock ........................................................... 363 I/O ............................................................................. 365 Input Capture ............................................................ 370 Timing Specifications 10-bit A/D Conversion Requirements ....................... 383 CAN I/O Requirements ............................................. 388 High-Speed PWM Requirements .............................. 372 I2Cx Bus Data Requirements (Master Mode) ........... 379 I2Cx Bus Data Requirements (Slave Mode) ............. 381 Output Compare Requirements ................................ 370 PLL Clock.................................................................. 364 QEI External Clock Requirements ............................ 387 QEI Index Pulse Requirements................................. 387 Quadrature Decoder Requirements .......................... 386 Reset, Watchdog Timer, Oscillator Start-up Timer, Power-up Timer and Brown-out Reset Requirements ......................................... 367 Simple OC/PWM Mode Requirements ..................... 371 SPIx Master Mode (CKE = 0) Requirements ............ 373 SPIx Master Mode (CKE = 1) Requirements ............ 374 SPIx Slave Mode (CKE = 0) Requirements .............. 375 SPIx Slave Mode (CKE = 1) Requirements .............. 377 Timer1 External Clock Requirements ....................... 368 Timer2 External Clock Requirements ....................... 369 Timer3 External Clock Requirements ....................... 369 U Universal Asynchronous Receiver Transmitter (UART).... 273 Using the RCON Status Bits ............................................. 121 V Voltage Regulator (On-Chip)............................................. 336 W Watchdog Time-out Reset (WDTO) .................................. 120 Watchdog Timer (WDT) ............................................ 333, 337 Programming Considerations ................................... 337 WWW Address.................................................................. 413 WWW, On-Line Support...................................................... 18 DS70591B-page 412 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 THE MICROCHIP WEB SITE Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers. Accessible by using your favorite Internet browser, the web site contains the following information: * Product Support - Data sheets and errata, application notes and sample programs, design resources, user's guides and hardware support documents, latest software releases and archived software. * General Technical Support - Frequently Asked Questions (FAQ), technical support requests, online discussion groups, Microchip consultant program member listing. * Business of Microchip - Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives. CUSTOMER SUPPORT Users of Microchip products can receive assistance through several channels: * * * * Distributor or Representative Local Sales Office Field Application Engineer (FAE) Technical Support Customers should contact their distributor, representative or field application engineer (FAE) for support. Local sales offices are also available to help customers. A listing of sales offices and locations is included in the back of this document. Technical support is available through the web site at: http://support.microchip.com CUSTOMER CHANGE NOTIFICATION SERVICE Microchip's customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com, click on Customer Change Notification and follow the registration instructions. 2009 Microchip Technology Inc. Preliminary DS70591B-page 413 dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document. To: RE: Technical Publications Manager Reader Response Total Pages Sent ________ From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ Application (optional): Would you like a reply? Y N Literature Number: DS70591B FAX: (______) _________ - _________ Device: dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 Questions: 1. What are the best features of this document? 2. How does this document meet your hardware and software development needs? 3. Do you find the organization of this document easy to follow? If not, why? 4. What additions to the document do you think would enhance the structure and subject? 5. What deletions from the document could be made without affecting the overall usefulness? 6. Is there any incorrect or misleading information (what and where)? 7. How would you improve this document? DS70591B-page 414 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GS406/606/608/610 and DSPIC33FJ64GS406/606/608/610 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. dsPIC 33 FJ 32 GS4 06 T E / PT - XXX Microchip Trademark Architecture Flash Memory Family Program Memory Size (KB) Product Group Pin Count Tape and Reel Flag (if applicable) Temperature Range Package Pattern Examples: a) dsPIC33FJ32GS406-E/PT: SMPS dsPIC33, 32 KB program memory, 64-pin, Extended temp., TQFP package. Architecture: Flash Memory Family: Product Group: 33 FJ = = 16-bit Digital Signal Controller Flash program memory, 3.3V GS4 GS6 06 08 10 I E = = = = = = = Switch Mode Power Supply (SMPS) family Switch Mode Power Supply (SMPS) family 64-pin 80-pin 100-pin -40C to+85C (Industrial) -40C to+125C (Extended) Pin Count: Temperature Range: Package: PT PT PF MR = = = = Plastic Thin Quad Flatpack - 10x10x1 mm body (TQFP) Plastic Thin Quad Flatpack - 12x12x1 mm body (TQFP) Plastic Thin Quad Flatpack - 14x14x1 mm body (TQFP) Plastic Quad Flat, No Lead Package - 9x9x0.9 mm body (QFN) 2009 Microchip Technology Inc. Preliminary DS70591B-page 415 Worldwide Sales and Service AMERICAS Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://support.microchip.com Web Address: www.microchip.com Atlanta Duluth, GA Tel: 678-957-9614 Fax: 678-957-1455 Boston Westborough, MA Tel: 774-760-0087 Fax: 774-760-0088 Chicago Itasca, IL Tel: 630-285-0071 Fax: 630-285-0075 Cleveland Independence, OH Tel: 216-447-0464 Fax: 216-447-0643 Dallas Addison, TX Tel: 972-818-7423 Fax: 972-818-2924 Detroit Farmington Hills, MI Tel: 248-538-2250 Fax: 248-538-2260 Kokomo Kokomo, IN Tel: 765-864-8360 Fax: 765-864-8387 Los Angeles Mission Viejo, CA Tel: 949-462-9523 Fax: 949-462-9608 Santa Clara Santa Clara, CA Tel: 408-961-6444 Fax: 408-961-6445 Toronto Mississauga, Ontario, Canada Tel: 905-673-0699 Fax: 905-673-6509 ASIA/PACIFIC Asia Pacific Office Suites 3707-14, 37th Floor Tower 6, The Gateway Harbour City, Kowloon Hong Kong Tel: 852-2401-1200 Fax: 852-2401-3431 Australia - Sydney Tel: 61-2-9868-6733 Fax: 61-2-9868-6755 China - Beijing Tel: 86-10-8528-2100 Fax: 86-10-8528-2104 China - Chengdu Tel: 86-28-8665-5511 Fax: 86-28-8665-7889 China - Hong Kong SAR Tel: 852-2401-1200 Fax: 852-2401-3431 China - Nanjing Tel: 86-25-8473-2460 Fax: 86-25-8473-2470 China - Qingdao Tel: 86-532-8502-7355 Fax: 86-532-8502-7205 China - Shanghai Tel: 86-21-5407-5533 Fax: 86-21-5407-5066 China - Shenyang Tel: 86-24-2334-2829 Fax: 86-24-2334-2393 China - Shenzhen Tel: 86-755-8203-2660 Fax: 86-755-8203-1760 China - Wuhan Tel: 86-27-5980-5300 Fax: 86-27-5980-5118 China - Xiamen Tel: 86-592-2388138 Fax: 86-592-2388130 China - Xian Tel: 86-29-8833-7252 Fax: 86-29-8833-7256 China - Zhuhai Tel: 86-756-3210040 Fax: 86-756-3210049 ASIA/PACIFIC India - Bangalore Tel: 91-80-3090-4444 Fax: 91-80-3090-4080 India - New Delhi Tel: 91-11-4160-8631 Fax: 91-11-4160-8632 India - Pune Tel: 91-20-2566-1512 Fax: 91-20-2566-1513 Japan - Yokohama Tel: 81-45-471- 6166 Fax: 81-45-471-6122 Korea - Daegu Tel: 82-53-744-4301 Fax: 82-53-744-4302 Korea - Seoul Tel: 82-2-554-7200 Fax: 82-2-558-5932 or 82-2-558-5934 Malaysia - Kuala Lumpur Tel: 60-3-6201-9857 Fax: 60-3-6201-9859 Malaysia - Penang Tel: 60-4-227-8870 Fax: 60-4-227-4068 Philippines - Manila Tel: 63-2-634-9065 Fax: 63-2-634-9069 Singapore Tel: 65-6334-8870 Fax: 65-6334-8850 Taiwan - Hsin Chu Tel: 886-3-6578-300 Fax: 886-3-6578-370 Taiwan - Kaohsiung Tel: 886-7-536-4818 Fax: 886-7-536-4803 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350 EUROPE Austria - Wels Tel: 43-7242-2244-39 Fax: 43-7242-2244-393 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 France - Paris Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 Germany - Munich Tel: 49-89-627-144-0 Fax: 49-89-627-144-44 Italy - Milan Tel: 39-0331-742611 Fax: 39-0331-466781 Netherlands - Drunen Tel: 31-416-690399 Fax: 31-416-690340 Spain - Madrid Tel: 34-91-708-08-90 Fax: 34-91-708-08-91 UK - Wokingham Tel: 44-118-921-5869 Fax: 44-118-921-5820 03/26/09 DS70591B-page 416 Preliminary 2009 Microchip Technology Inc. |
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