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NLSX3013 8-Bit 100 Mb/s Configurable Dual-Supply Level Translator
The NLSX3013 is a 8-bit configurable dual-supply bidirectional level translator without a direction control pin. The I/O VCC- and I/O VL-ports are designed to track two different power supply rails, VCC and VL respectively. The VCC supply rail is configurable from 1.3 V to 4.5 V while the VL supply rail is configurable from 0.9 V to (VCC - 0.4) V. This allows lower voltage logic signals on the VL side to be translated into higher voltage logic signals on the VCC side, and vice-versa. Both I/O ports are auto-sensing; thus, no direction pin is required. The Output Enable (EN) input, when Low, disables both I/O ports by putting them in 3-state. This significantly reduces the supply currents from both VCC and VL. The EN signal is designed to track VL.
Features http://onsemi.com MARKING DIAGRAM for NLSX3013FCT1G
3013F AYWW G
for NLSX3013BFCT1G A1 20 PIN FLIP-CHIP 3013B CASE 766AK AYWW G
A Y WW G = Assembly Location = Year = Work Week = Pb-Free Package
* Wide High-Side VCC Operating Range: 1.3 V to 4.5 V * * * * * *
Wide Low-Side VL Operating Range: 0.9 V to (VCC - 0.4) V High-Speed with 100 Mb/s Guaranteed Date Rate for VL > 1.8 V Low Bit-to-Bit Skew Overvoltage Tolerant Enable and I/O Pins Non-preferential Powerup Sequencing Small packaging: 2.03 mm x 2.54 mm 20 Pin Flip-Chip This is a Pb-Free Device
LOGIC DIAGRAM
EN VL VCC GND
I/O VL1
I/O VCC1
Typical Applications
* Mobile Phones, PDAs, Other Portable Devices * PC and Laptops * ESD Protection for All Pins: Human Body Model (HBM) > 6000 V
I/O VL2
I/O VCC2
I/O VL3
I/O VCC3
I/O VL4
I/O VCC4
I/O VL5
I/O VCC5
I/O VL6
I/O VCC6
I/O VL7
I/O VCC7
I/O VL8
I/O VCC8
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 9 of this data sheet.
(c) Semiconductor Components Industries, LLC, 2009
March, 2009 - Rev. 2
1
Publication Order Number: NLSX3013/D
NLSX3013
VL +1.8V +3.6V P One-Shot VCC
VL +1.8 V System
NLSX3013
VCC +3.6 V System I/O VL N One-Shot I/O VCC
I/O1 I/On GND EN
I/O VL1
I/O VCC1
I/O1 I/On GND
I/O VLn I/O VCCn EN GND
P One-Shot
N One-Shot
Figure 1. Typical Application Circuit
Figure 2. Simplified Functional Diagram (1 I/O Line) (EN = 1) FUNCTION TABLE
PIN ASSIGNMENT
Pins VCC VL GND EN I/O VCCn I/O VLn Description VCC Input Voltage VL Input Voltage Ground Output Enable I/O Port, Referenced to VCC I/O Port, Referenced to VL
EN L H
Operating Mode Hi-Z I/O Buses Connected
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1 2 3 4 5
A
I/O VL2
I/O VL4
VL
EN
I/O VL6
B
I/O VL1
I/O VL3
I/O VL5
I/O VL7
I/O VL8
C
I/O VCC1
I/O VCC3
I/O VCC5
I/O VCC7
I/O VCC8
D
I/O VCC2
I/O VCC4
VCC
GND
I/O VCC6
Figure 3. 20 Flip-Chip (2.54 mm x 2.03 mm)
(Top View)
PIN ASSIGNMENT
Pin A1 A2 A3 A4 A5 B1 B2 B3 B4 B5 C1 C2 C3 C4 C5 D1 D2 D3 D4 D5 Name I/O VL2 I/O VL4 VL EN I/O VL6 I/O VL1 I/O VL3 I/O VL5 I/O VL7 I/O VL8 I/O VCC1 I/O VCC3 I/O VCC5 I/O VCC7 I/O VCC8 I/O VCC2 I/O VCC4 VCC GND I/O VCC6 I/O Port 2, Referenced to VL I/O Port 4, Referenced to VL VL Input Voltage Output Enable I/O Port 6, Referenced to VL I/O Port 1, Referenced to VL I/O Port 3, Referenced to VL I/O Port 5, Referenced to VL I/O Port 7, Referenced to VL I/O Port 8, Referenced to VL I/O Port 1, Referenced to VCC I/O Port 3, Referenced to VCC I/O Port 5, Referenced to VCC I/O Port 7, Referenced to VCC I/O Port 8, Referenced to VCC I/O Port 2, Referenced to VCC I/O Port 4, Referenced to VCC VCC Input Voltage Ground I/O Port 6, Referenced to VCC Description
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MAXIMUM RATINGS
Symbol VCC VL I/O VCC I/O VL VEN IIK IOK ICC IL IGND TSTG VCC Supply Voltage VL Supply Voltage VCC-Referenced DC Input/Output Voltage VL-Referenced DC Input/Output Voltage Enable Control Pin DC Input Voltage Input Diode Clamp Current Output Diode Clamp Current DC Supply Current Through VCC DC Supply Current Through VL DC Ground Current Through Ground Pin Storage Temperature Parameter Value -0.5 to +5.5 -0.5 to +5.5 -0.5 to (VCC + 0.3) -0.5 to (VL + 0.3) -0.5 to +5.5 -50 -50 $100 $100 $100 -65 to +150 VI < GND VO < GND Condition Unit V V V V V mA mA mA mA mA C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
Symbol VCC VL VEN VIO TA DI/DV VCC Supply Voltage VL Supply Voltage Enable Control Pin Voltage Bus Input/Output Voltage Operating Temperature Range Input Transition Rise or Rate VI, VIO from 30% to 70% of VCC; VCC = 3.3 V $ 0.3 V I/O VCC I/O VL Parameter Min 1.3 0.9 GND GND GND -40 0 Max 4.5 VCC - 0.4 4.5 4.5 4.5 +85 10 Unit V V V V C ns
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DC ELECTRICAL CHARACTERISTICS
-405C to +855C Symbol VIHC VILC VIHL VILL VIH VIL VOHC VOLC VOHL VOLL Parameter I/O VCC Input HIGH Voltage I/O VCC Input LOW Voltage I/O VL Input HIGH Voltage I/O VL Input LOW Voltage Control Pin Input HIGH Voltage Control Pin Input LOW Voltage I/O VCC Output HIGH Voltage I/O VCC Output LOW Voltage I/O VL Output HIGH Voltage I/O VL Output LOW Voltage TA = +25C TA = +25C I/O VCC Source Current = 20 mA I/O VCC Sink Current = 20 mA I/O VL Source Current = 20 mA I/O VL Sink Current = 20 mA Test Conditions (Note 1) VCC (V) (Note 2) 1.3 to 4.5 1.3 to 4.5 1.3 to 4.5 1.3 to 4.5 1.3 to 4.5 1.3 to 4.5 1.3 to 4.5 1.3 to 4.5 1.3 to 4.5 1.3 to 4.5 VL (V) (Note 3) 0.9 to (VCC - 0.4) 0.9 to (VCC - 0.4) 0.9 to (VCC - 0.4) 0.9 to (VCC - 0.4) 0.9 to (VCC - 0.4) 0.9 to (VCC - 0.4) 0.9 to (VCC - 0.4) 0.9 to (VCC - 0.4) 0.9 to (VCC - 0.4) 0.9 to (VCC - 0.4) Min 0.8 * VCC - 0.8 * VL - 0.8 * VL - 0.8 * VCC - 0.8 * VL - Typ (Note 4) - - - - - - - - - - Max - 0.2 * VCC - 0.2 * VL - 0.2 * VL - 0.2 * VCC - 0.2 * VL Unit V V V V V V V V V V
1. Normal test conditions are VEN = 0 V, CIOVCC = 15 pF and CIOVL = 15 pF, unless otherwise specified. 2. VCC is the supply voltage associated with the high voltage port, and VCC ranges from +1.3 V to 4.5 V under normal operating conditions. 3. VL is the supply voltage associated with the low voltage port. VL must be less than or equal to (VCC - 0.4) V during normal operation. However, during startup and shutdown conditions, VL can be greater than (VCC - 0.4) V. 4. Typical values are for VCC = +2.8 V, VL = +1.8 V and TA = +25C. All units are production tested at TA = +25C. Limits over the operating temperature range are guaranteed by design.
POWER CONSUMPTION
Symbol IQ-VCC IQ-VL Parameter Test Conditions (Note 5) VCC (V) (Note 6) VL (V) (Note 7) -405C to +855C Min - - - Typ - - - Max 1.0 1.0 2.0 Unit mA mA
Supply Current from EN = VL; I/O VCCn = 0 V, I/O VLn = 0 V, 1.3 to 3.6 0.9 to (VCC - 0.4) VCC I/O VCCn = VCC or I/O VLn = VL and Io = 0 Supply Current from EN = VL; I/O VCCn = 0 V, I/O VLn = 0 V, 1.3 to 3.6 0.9 to (VCC - 0.4) VL I/O VCCn = VCC or I/O VLn = VL and Io = 0 EN = VL, I/O VCCn = 0 V, I/O VLn = 0 V, I/O VCCn = VCC or I/O VLn = (VCC - 0.2 V) and Io = 0 < (VCC - 0.2)
ITS-VCC
VCC Tristate Output Mode Supply Current VL Tristate Output Mode Supply Current I/O Tristate Output Mode Leakage Current Output Enable Pin Input Current
EN = 0 V
1.3 to 3.6 0.9 to (VCC - 0.4)
-
-
1.0
mA
ITS-VL
EN = 0 V EN = 0 V EN = 0 V EN = 0 V -
1.3 to 3.6 0.9 to (VCC - 0.4) VCC - 0.2 1.3 to 3.6 0.9 to (VCC - 0.4) VCC - 0.2 1.3 to 3.6 0.9 to (VCC - 0.4)
- - - - -
- - - - -
0.2 2.0 0.15 2.0 1.0
mA
IOZ
mA
IEN
mA
5. Normal test conditions are VEN = 0 V, CIOVCC = 15 pF and CIOVL = 15 pF, unless otherwise specified. 6. VCC is the supply voltage associated with the high voltage port, and VCC ranges from +1.3 V to 4.5 V under normal operating conditions. 7. VL is the supply voltage associated with the low voltage port. VL must be less than or equal to (VCC - 0.4) V during normal operation. However, during startup and shutdown conditions, VL can be greater than (VCC - 0.4) V.
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TIMING CHARACTERISTICS
-405C to +855C Symbol tR-VCC tF-VCC tR-VL tF-VL ZO-VCC ZO-VL Parameter I/O VCC Rise Time (Output = I/O_VCC) I/O VCC Falltime (Output = I/O_VCC) I/O VL Risetime (Output = I/O_VL) I/O VL Falltime (Output = I/O_VL) I/O VCC One-Shot Output Impedance I/O VL One-Shot Output Impedance CIOVCC = 15 pF Test Conditions (Note 8) CIOVCC = 15 pF CIOVCC = 15 pF CIOVL = 15 pF CIOVL = 15 pF VCC (V) (Note 9) 1.3 to 4.5 1.3 to 4.5 1.3 to 4.5 1.3 to 4.5 1.3 to 4.5 1.3 to 4.5 1.3 to 4.5 VL (V) (Note 10) 0.9 to (VCC - 0.4) 0.9 to (VCC - 0.4) 0.9 to (VCC - 0.4) 0.9 to (VCC - 0.4) 0.9 to (VCC - 0.4) 0.9 to (VCC - 0.4) 0.9 to (VCC - 0.4) Min Typ (Note 11) 0.7 0.5 1.0 0.6 30 30 4.5 9.3 Max 2.4 1.0 3.8 1.2 Unit ns ns ns ns W W ns
tPD_VL-VCC Propagation Delay (Output = I/O_VCC, tPHL, tPLH) tPD_VCC-VL Propagation Delay (Output = I/O_VL, tPHL, tPLH) tSK VL-VCC Channel-to-Channel Skew (Output = I/O_VCC)
CIOVL = 15 pF
1.3 to 4.5
0.9 to (VCC - 0.4)
3.0
6.5
ns
CIOVCC = 15 pF
1.3 to 4.5
0.9 to (VCC - 0.4)
0.2
0.3
nS
tSK_VCC-VL Channel-to-Channel Skew (Output = I/O_VL) Maximum Data Rate
CIOVCC = 15 pF
1.3 to 4.5
0.9 to (VCC - 0.4)
0.2
0.3
nS
(Output = I/O_VCC, CIOVCC = 15 pF) (Output = I/O_VL, CIOVL = 15 pF)
1.3 to 4.5 > 2.2
0.9 to (VCC - 0.4) > 1.8
110 140
Mb/s
8. Normal test conditions are VEN = 0 V, CIOVCC = 15 pF and CIOVL = 15 pF, unless otherwise specified. 9. VCC is the supply voltage associated with the high voltage port, and VCC ranges from +1.3 V to 4.5 V under normal operating conditions. 10. VL is the supply voltage associated with the low voltage port. VL must be less than or equal to (VCC - 0.4) V during normal operation. However, during startup and shutdown conditions, VL can be greater than (VCC - 0.4) V. 11. Typical values are for VCC = +2.8 V, VL = +1.8 V and TA = +25C. All units are production tested at TA = +25C. Limits over the operating temperature range are guaranteed by design.
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NLSX3013
ENABLE / DISABLE TIME MEASUREMENTS
-405C to +855C Symbol tEN-VCC Parameter Turn-On Enable Time (Output = I/O_VCC, tpZH) Turn-On Enable Time (Output = I/O_VCC, tpZL) tEN-VL Turn-On Enable Time (Output = I/O_VL, tpZH) Turn-On Enable Time (Output = I/O_VL, tpZL) tDIS-VCC Turn-Off Disable Time (Output = I/O_VCC, tpHZ) Propagation Delay (Output = I/O_VCC, tPLZ) tDIS-VL Turn-Off Disable Time (Output = I/O_VL, tpHZ) Propagation Delay (Output = I/O_VL, tPLZ) Test Conditions (Note 12) CIOVCC = 15 pF CIOVL = 15 pF CIOVCC = 15 pF CIOVL = 15 pF CIOVCC = 15 pF CIOVL = 15 pF CIOVCC = 15 pF CIOVL = 15 pF VCC (V) (Note 13) 1.3 to 4.5 1.3 to 4.5 1.3 to 4.5 1.3 to 4.5 1.3 to 4.5 1.3 to 4.5 1.3 to 4.5 1.3 to 4.5 VL (V) (Note 14) 0.9 to (VCC - 0.4) 0.9 to (VCC - 0.4) 0.9 to (VCC - 0.4) 0.9 to (VCC - 0.4) 0.9 to (VCC - 0.4) 0.9 to (VCC - 0.4) 0.9 to (VCC - 0.4) 0.9 to (VCC - 0.4) Min Typ (Note 15) 130 100 95 70 175 150 180 160 Max 180 150 185 110 250 190 250 220 Unit ns ns ns ns ns ns ns ns
12. Normal test conditions are VEN = 0 V, CIOVCC = 15 pF and CIOVL = 15 pF, unless otherwise specified. 13. VCC is the supply voltage associated with the high voltage port, and VCC ranges from +1.3 V to 4.5 V under normal operating conditions. 14. VL is the supply voltage associated with the low voltage port. VL must be less than or equal to (VCC - 0.4) V during normal operation. However, during startup and shutdown conditions, VL can be greater than (VCC - 0.4) V. 15. Typical values are for VCC = +2.8 V, VL = +1.8 V and TA = +25 C. All units are production tested at TA = +25 C. Limits over the operating temperature range are guaranteed by design. NLSX3013 EN Source I/O VL I/O VCC CIOVCC I/O VL CIOVL Source I/O VL 90% 50% 10% tPD_VL-VCC I/O VCC 90% 50% 10% tF-VCC tR-VCC tRISE/FALL v 3 ns I/O VCC 90% 50% 10% tPD_VL-VCC tPD_VCC-VL I/O VL 90% 50% 10% tF-VL tR-VL tPD_VCC-VL tRISE/FALL v 3 ns NLSX3013 EN I/O VCC
VL
VCC
VL
VCC
Figure 4. Driving I/O VL Test Circuit and Timing
Figure 5. Driving I/O VCC Test Circuit and Timing
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VCC R1 CL RL 2xVCC OPEN
PULSE GENERATOR RT
DUT
Test tPZH, tPHZ tPZL, tPLZ
Switch Open 2 x VCC
CL = 15 pF or equivalent (Includes jig and probe capacitance) RL = R1 = 50 kW or equivalent RT = ZOUT of pulse generator (typically 50 W)
Figure 6. Test Circuit for Enable/Disable Time Measurement
tR Input tPLH Output 90% 50% 10% 90% 50% 10% tR tPHL tF 50% VL GND HIGH IMPEDANCE 10% 90% VOL VOH HIGH IMPEDANCE
VCC GND
EN
tPZL Output 50% tPZH Output 50%
tPLZ
tF
tPHZ
Figure 7. Timing Definitions for Propagation Delays and Enable/Disable Measurement
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IMPORTANT APPLICATIONS INFORMATION
Level Translator Architecture Enable Input (EN)
The NLSX3013 auto sense translator provides bi-directional voltage level shifting to transfer data in multiple supply voltage systems. This device has two supply voltages, VL and VCC, which set the logic levels on the input and output sides of the translator. When used to transfer data from the VL to the VCC ports, input signals referenced to the VL supply are translated to output signals with a logic level matched to VCC. In a similar manner, the VCC to VL translation shifts input signals with a logic level compatible to VCC to an output signal matched to VL. The NLSX3013 consists of four bi-directional channels that independently determine the direction of the data flow without requiring a directional pin. The one-shot circuits are used to detect the rising or falling input signals. In addition, the one shots decrease the rise and fall time of the output signal for high-to-low and low-to-high transitions.
Input Driver Requirements
The NLSX3013 has an Enable pin (EN) that provides tri-state operation at the I/O pins. Driving the Enable pin to a low logic level minimizes the power consumption of the device and drives the I/O VCC and I/O VL pins to a high impedance state. Normal translation operation occurs when the EN pin is equal to a logic high signal. The EN pin is referenced to the VL supply and has Over-Voltage Tolerant (OVT) protection.
Uni-Directional versus Bi-Directional Translation
Auto sense translators such as the NLSX3013 have a wide bandwidth, but a relatively small DC output current rating. The high bandwidth of the bi-directional I/O circuit is used to quickly transform from an input to an output driver and vice versa. The I/O ports have a modest DC current output specification so that the output driver can be over driven when data is sent to in the opposite direction. For proper operation, the input driver to the auto sense translator should be capable of driving 20 mA of peak output current with an output impedance less than 25 W. The bi-directional configuration of the translator results in both input stages being active for a very short time period. Although the peak current from the input signal circuit is relatively large, the average current is small and consistent with a standard CMOS input stage.
Output Load Requirements
The NLSX3013 can function as a non-inverting uni-directional translator. One advantage of using the translator as a uni-directional device is that each I/O pin can be configured as either an input or output. The configurable input or output feature is especially useful in applications such as SPI that use multiple uni-directional I/O lines to send data to and from a device. The flexible I/O port of the auto sense translator simplifies the trace connections on the PCB.
Power Supply Guidelines
The NLSX3013 is designed to drive CMOS inputs. Resistive pullup or pulldown loads of less than 50 kW should not be used with this device. The NLSX3373 or NLSX3378 open-drain auto sense translators are alternate translator options for an application such as the I2C bus that requires pullup resistors.
ORDERING INFORMATION
Device NLSX3013FCT1G NLSX3013BFCT1G Package 20 Pin Flip-Chip (Pb-Free)
During normal operation, supply voltage VL should be less than or equal to VCC. The sequencing of the power supplies will not damage the device during the power up operation. The enable pin should be used to enter the low current tri-state mode, rather than setting either the VL or VCC supplies to 0 V. The NLSX3013 will not be damaged if either VL or VCC is equal to 0 V while the other supply voltage is at a nominal operating value; however, the operation of the translator cannot be guaranteed during single supply operation. For optimal performance, 0.01 to 0.1 mF decoupling capacitors should be used on the VL and VCC power supply pins. Ceramic capacitors are a good design choice to filter and bypass any noise signals on the power supply voltage lines to the ground plane of the PCB. The noise immunity will be maximized by placing the capacitors as close as possible to the supply and ground pins, along with minimizing the PCB connection traces.
Shipping 3000 / Tape & Reel 3000 / Tape & Reel
20 Pin Flip-Chip (Backside Laminate Coating) (Pb-Free)
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
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NLSX3013
PACKAGE DIMENSIONS
20 PIN FLIP-CHIP CSP CASE 766AK-01 ISSUE O
D
PIN A1 REFERENCE 2X
AB
E
NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. COPLANARITY APPLIES TO SPHERICAL CROWNS OF SOLDER BALLS. DIM A A1 A2 b D D1 E E1 e MILLIMETERS MIN MAX --0.66 0.21 0.27 0.33 0.39 0.29 0.34 2.54 BSC 2.00 BSC 2.03 BSC 1.50 BSC 0.50 BSC
0.10 C
2X
0.10 C
0.10 C A2
20X
0.05 C
NOTE 3
20X
b
D C B A 1 2 3 4
0.05 C A B 0.03 C
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
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I I
TOP VIEW SIDE VIEW D1 e
5
A1 A C
SEATING PLANE
e/2 E1
BOTTOM VIEW
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NLSX3013/D

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