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SSM40P03GH,J
P-CHANNEL ENHANCEMENT-MODE POWER MOSFET
D Low gate-charge Simple drive requirement Fast switching G S
BV DSS R DS(ON) ID
-30V 28m -30A
Description
The SSM40P03H is in a TO-252 package, which is widely used for commercial and industrial surface mount applications, and is well suited for low voltage applications such as DC/DC converters. The through-hole version, the SSM40P03J in TO-251, is available for low-footprint vertical mounting. These devices are manufactured with an advanced process, providing improved on-resistance and switching performance.
GD S
TO-252 (H)
Pb-free lead finish (second-level interconnect)
G
D
S
TO-251 (J)
Absolute Maximum Ratings
Symbol VDS VGS ID @ TC=25C ID @ TC=100C IDM PD @ TC=25C TSTG TJ Parameter Drain-Source Voltage Gate-Source Voltage Continuous Drain Current, VGS @ 10V Continuous Drain Current, VGS @ 10V Pulsed Drain Current
1
Rating -30 20 -30 -18 -120 31.3 0.25 -55 to 150 -55 to 150
Units V V A A A W W/C C C
Total Power Dissipation Linear Derating Factor Storage Temperature Range Operating Junction Temperature Range
Thermal Data
Symbol Rthj-c Rthj-a Parameter Thermal Resistance Junction-case Thermal Resistance Junction-ambient Max. Max. Value 4.0 110 Units C/W C/W
2/16/2005 Rev.2.2
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SSM40P03GH,J
Electrical Characteristics @ Tj=25oC (unless otherwise specified)
Symbol BVDSS Parameter Drain-Source Breakdown Voltage Test Conditions VGS=0V, ID=-250uA
2
Min. -30 -1 -
Typ. -0.02 20 14 3 9 12 56 30 57 915 280 195
Max. Units 28 50 -1 -25 100 22 1465 V V/C m m V S uA uA nA nC nC nC ns ns ns ns pF pF pF
BV DSS/Tj
RDS(ON)
Breakdown Voltage Temperature Coefficient Reference to 25C, ID=-1mA
Static Drain-Source On-Resistance
VGS=-10V, ID=-18A VGS=-4.5V, ID=-14A
VGS(th) gfs IDSS IGSS Qg Qgs Qgd td(on) tr td(off) tf Ciss Coss Crss
Gate Threshold Voltage Forward Transconductance
Drain-Source Leakage Current (Tj=25 C) Drain-Source Leakage Current (Tj=150 C)
o o
VDS=VGS, ID=-250uA VDS=-10V, ID=-18A VDS=-30V, VGS=0V VDS=-24V, VGS=0V VGS= 20V ID=-18A VDS=-24V VGS=-4.5V VDS=-15V ID=-18A RG=3.3 , VGS=-10V RD=0.8 VGS=0V VDS=-25V f=1.0MHz
Gate-Source Leakage Total Gate Charge
2
Gate-Source Charge Gate-Drain ("Miller") Charge Turn-on Delay Time Rise Time Turn-off Delay Time Fall Time Input Capacitance Output Capacitance Reverse Transfer Capacitance
2
Source-Drain Diode
Symbol VSD trr Qrr Parameter Forward On Voltage
2 2
Test Conditions IS=-18A, VGS=0V IS=-18A, VGS=0V, dI/dt=-100A/s
Min. -
Typ. 30 21
Max. Units -1.2 V ns nC
Reverse Recovery Time
Reverse Recovery Charge
Notes:
1.Pulse width limited by safe operating area. 2.Pulse width <300us , duty cycle <2%.
2/16/2005 Rev.2.2
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SSM40P03GH,J
120
100
-10V
100
-10V TA=150oC
80
T A = 25 C
o
-7.0V -ID , Drain Current (A)
-7.0V
-ID , Drain Current (A)
80
60
60
-5.0V -4.5V
-5.0V
40
40
-4.5V
20
20
V G = -3.0 V
0
0 2 4 6 8 0 2 4 6
V G = -3.0 V
0
8
-V DS , Drain-to-Source Voltage (V)
-V DS , Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
50
1.6
45
I D = -14 A T C =25C Normalized R DS(ON)
1.4
I D =-1 8 A V G =-10V
40
RDS(ON) (m )
1.2
35
1.0
30
0.8
25
20
0.6 2 4 6 8 10 -50 0 50 100 150
-V GS , Gate-to-Source Voltage (V)
T j , Junction Temperature ( C)
o
Fig 3. On-Resistance vs. Gate Voltage
Fig 4. Normalized On-Resistance vs. Junction Temperature
2.5
18
15 2.0
12
Normalized -VGS(th) (V)
-IS(A)
1.5
9
T j =150 C
o
T j =25 C
o
1.0
6
0.5 3
0 0 0.2 0.4 0.6 0.8 1 1.2 1.4
0.0 -50 0 50 100 150
-V SD , Source-to-Drain Voltage (V)
T j , Junction Temperature ( o C)
Fig 5. Forward Characteristic of Reverse Diode
2/16/2005 Rev.2.2
Fig 6. Gate Threshold Voltage vs. Junction Temperature
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SSM40P03GH,J
f=1.0MHz
12
10000
-VGS , Gate to Source Voltage (V)
10
V DS =- 24 V I D =-1 8 A
8
6
C (pF)
1000
C iss
4
2
C oss C rss
100
0 5 10 15 20 25 30 1 5 9 13 17 21 25 29
0
Q G , Total Gate Charge (nC)
-V DS , Drain-to-Source Voltage (V)
Fig 7. Gate Charge Characteristics
Fig 8. Typical Capacitance Characteristics
1000.0
1
Normalized Thermal Response (Rthjc)
Duty factor=0.5
100.0
100us 1ms
10.0
0.2
0.1
-ID (A)
0.1
0.05
10ms
1.0
PDM
t
0.02
T c =25 o C Single Pulse
100ms 1s DC
T
0.01 Single Pulse
Duty factor = t/T Peak Tj = PDM x Rthjc + TC
0.1 0.1 1 10 100
0.01
0.00001
0.0001
0.001
0.01
0.1
1
-V DS , Drain-to-Source Voltage (V)
t , Pulse Width (s)
Fig 9. Maximum Safe Operating Area
Fig 10. Effective Transient Thermal Impedance
VDS 90%
VG QG -4.5V QGS QGD
10% VGS td(on) tr td(off) tf Charge Q
Fig 11. Switching Time Waveform
2/16/2005 Rev.2.2
Fig 12. Gate Charge Waveform
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SSM40P03GH,J
Information furnished by Silicon Standard Corporation is believed to be accurate and reliable. However, Silicon Standard Corporation makes no guarantee or warranty, express or implied, as to the reliability, accuracy, timeliness or completeness of such information and assumes no responsibility for its use, or for infringement of any patent or other intellectual property rights of third parties that may result from its use. Silicon Standard reserves the right to make changes as it deems necessary to any products described herein for any reason, including without limitation enhancement in reliability, functionality or design. No license is granted, whether expressly or by implication, in relation to the use of any products described herein or to the use of any information provided herein, under any patent or other intellectual property rights of Silicon Standard Corporation or any third parties.
2/16/2005 Rev.2.2
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