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DATA SHEET
4GB Registered DDR3 SDRAM DIMM
EBJ41HE4BAFA (512M words x 72 bits, 2 Ranks)
Specifications
* Density: 4GB * Organization 512M words x 72 bits, 2 ranks * Mounting 36 pieces of 1G bits DDR3 SDRAM sealed in FBGA * Package: 240-pin socket type dual in line memory module (DIMM) PCB height: 30.5mm (max.) Lead pitch: 1.0mm Lead-free (RoHS compliant) * Power supply: VDD = 1.5V 0.075V * Data rate: 1333Mbps/1066Mbps/800Mbps (max.) * Eight internal banks for concurrent operation (components) * Interface: SSTL_15 * Burst lengths (BL): 8 and 4 with Burst Chop (BC) * /CAS Latency (CL): 6, 7, 8, 9 * /CAS write latency (CWL): 5, 6, 7 * Precharge: auto precharge option for each burst access * Refresh: auto-refresh, self-refresh * Refresh cycles Average refresh period 7.8s at 0C TC +85C 3.9s at +85C < TC +95C * Operating case temperature range TC = 0C to +95C
Features
* Double-data-rate architecture; two data transfers per clock cycle * The high-speed data transfer is realized by the 8 bits prefetch pipelined architecture * Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver * DQS is edge-aligned with data for READs; centeraligned with data for WRITEs * Differential clock inputs (CK and /CK) * DLL aligns DQ and DQS transitions with CK transitions * Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS * Posted /CAS by programmable additive latency for better command and data bus efficiency * On-Die-Termination (ODT) for better signal quality Synchronous ODT Dynamic ODT Asynchronous ODT * Multi Purpose Register (MPR) for temperature read out * ZQ calibration for DQ drive and ODT * Programmable Partial Array Self-Refresh (PASR) * /RESET pin for Power-up sequence and reset function * SRT range: Normal/extended Auto/manual self-refresh * Programmable Output driver impedance control * 1 piece of registering clock driver and 1 piece of serial EEPROM (256 bytes EEPROM) for Presence Detect (PD) * Class B temperature sensor functionality with EEPROM Note: Warranty void if removed DIMM heat spreader.
Document No. E1256E40 (Ver. 4.0) Date Published December 2008 (K) Japan Printed in Japan URL: http://www.elpida.com Elpida Memory, Inc. 2007-2008
EBJ41HE4BAFA
Ordering Information
Component 1 JEDEC speed bin* Data rate Mbps(max.) (CL-tRCD-tRP) 1333 1066 DDR3-1333H (9-9-9) DDR3-1066F (7-7-7) Contact pad Gold
Part number EBJ41HE4BAFA-DJ-E EBJ41HE4BAFA-AE-E
Package 240-pin DIMM (lead-free)
Mounted devices EDJ1104BASE-DG-E EDJ1104BASE-DJ-E EDJ1104BASE-DG-E EDJ1104BASE-DJ-E EDJ1104BASE-AE-E EDJ1104BASE-DG-E EDJ1104BASE-DJ-E EDJ1104BASE-AE-E EDJ1104BASE-AG-E EDJ1104BASE-8A-E EDJ1104BASE-8C-E
EBJ41HE4BAFA-8C-E
800
DDR3-800E (6-6-6)
Note: 1. Module /CAS latency = component CL + 1.
Data Sheet E1256E40 (Ver. 4.0)
2
EBJ41HE4BAFA
Pin Configurations
Front side 1 pin 48 pin 49 pin 120 pin
121 pin
168 pin 169 pin Back side
240 pin
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
Pin name VREFDQ VSS DQ0 DQ1 VSS /DQS0 DQS0 VSS DQ2 DQ3 VSS DQ8 DQ9 VSS /DQS1 DQS1 VSS DQ10 DQ11 VSS DQ16 DQ17 VSS /DQS2 DQS2 VSS DQ18 DQ19 VSS DQ24 DQ25 VSS /DQS3 DQS3 VSS DQ26
Pin No. 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96
Pin name A2 VDD CK1 /CK1 VDD VDD VREFCA Par_In VDD A10(AP) BA0 VDD /WE /CAS VDD /CS1 ODT1 VDD NC VSS DQ32 DQ33 VSS /DQS4 DQS4 VSS DQ34 DQ35 VSS DQ40 DQ41 VSS /DQS5 DQS5 VSS DQ42
Pin No. 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156
Pin name VSS DQ4 DQ5 VSS DQS9 /DQS9 VSS DQ6 DQ7 VSS DQ12 DQ13 VSS DQS10 /DQS10 VSS DQ14 DQ15 VSS DQ20 DQ21 VSS DQS11 /DQS11 VSS DQ22 DQ23 VSS DQ28 DQ29 VSS DQS12 /DQS12 VSS DQ30 DQ31
Pin No. 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216
Pin name A1 VDD VDD CK0 /CK0 VDD /EVENT A0 VDD BA1 VDD /RAS /CS0 VDD ODT0 A13 VDD NC VSS DQ36 DQ37 VSS DQS13 /DQS13 VSS DQ38 DQ39 VSS DQ44 DQ45 VSS DQS14 /DQS14 VSS DQ46 DQ47
Data Sheet E1256E40 (Ver. 4.0)
3
EBJ41HE4BAFA
Pin No. 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 Pin name DQ27 VSS CB0 CB1 VSS /DQS8 DQS8 VSS CB2 CB3 VSS VTT VTT CKE0 VDD BA2 /Err_Out VDD A11 A7 VDD A5 A4 VDD Pin No. 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 Pin name DQ43 VSS DQ48 DQ49 VSS /DQS6 DQS6 VSS DQ50 DQ51 VSS DQ56 DQ57 VSS /DQS7 DQS7 VSS DQ58 DQ59 VSS SA0 SCL SA2 VTT Pin No. 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 Pin name VSS CB4 CB5 VSS DQS17 /DQS17 VSS CB6 CB7 VSS NC /RESET CKE1 VDD A15 A14 VDD A12 A9 VDD A8 A6 VDD A3 Pin No. 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 Pin name VSS DQ52 DQ53 VSS DQS15 /DQS15 VSS DQ54 DQ55 VSS DQ60 DQ61 VSS DQS16 /DQS16 VSS DQ62 DQ63 VSS VDDSPD SA1 SDA VSS VTT
Data Sheet E1256E40 (Ver. 4.0)
4
EBJ41HE4BAFA
Pin Description
Pin name A0 to A15 A10 (AP) A12 (/BC) BA0, BA1, BA2 DQ0 to DQ63 CB0 to CB7 /RAS /CAS /WE /CS0, /CS1 CKE0, CKE1 CK0, CK1 /CK0, /CK1 DQS0 to DQS17, /DQS0 to /DQS17 SCL SDA SA0, SA1, SA2 VDD VDDSPD VREFCA VREFDQ VSS VTT /RESET ODT0, ODT1 Par_In /Err_Out /Event NC Function Address input Row address Column address Auto precharge Burst chop Bank select address Data input/output Check bit (Data input/output) Row address strobe command Column address strobe command Write enable Chip select Clock enable Clock input Differential clock input Input and output data strobe Clock input for serial PD Data input/output for serial PD Serial address input Power for internal circuit Power for serial EEPROM Reference voltage for CA Reference voltage for DQ Ground Termination Voltage Set DRAM to known state ODT control Parity bit for the Address and Control bus Parity error found on the Address and Control bus Temperature event pin No connection A0 to A13 A0 to A9, A11
Data Sheet E1256E40 (Ver. 4.0)
5
EBJ41HE4BAFA
Serial PD Matrix
Byte No. Function described 0 1 2 3 4 5 6 7 8 9 10 11 12 Number of serial PD bytes written/SPD device size/CRC coverage SPD revision Key byte/DRAM device type Key byte/module type SDRAM density and banks SDRAM addressing Module nominal voltage, VDD Module organization Module memory bus width Fine timebase (FTB) dividend/divisor Medium timebase (MTB) dividend Medium timebase (MTB) divisor SDRAM minimum cycle time (tCK (min.)) -DJ -AE -8C 13 14 Reserved SDRAM /CAS latencies supported, LSB -DJ -AE -8C 15 16 SDRAM /CAS latencies supported, MSB SDRAM minimum /CAS latencies time (tAA (min.)) -DJ, -AE -8C 17 18 SDRAM write recovery time (tWR) SDRAM minimum /RAS to /CAS delay (tRCD) -DJ, -AE -8C 19 Bit7 Bit6 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 1 1 1 Bit5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 1 1 1 1 1 0 1 1 Hex Bit4 Bit3 Bit2 Bit1 Bit0 value 1 1 0 0 0 1 0 0 0 1 0 0 0 0 1 0 1 1 0 0 0 1 1 0 1 1 1 1 0 1 0 0 1 0 0 0 0 1 1 0 0 1 1 1 0 0 1 1 0 0 1 1 1 1 1 0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 1 1 1 0 0 0 0 0 0 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 0 1 0 0 1 0 0 0 0 0 0 1 0 0 1 0 0 0 0 1 0 92H 10H 0BH 01H 02H 12H 00H 08H 0BH 52H 01H 08H 0CH 0FH 14H 00H 3CH 1CH 04H 00H 69H 78H 78H 69H 78H 30H 3CH 50H 69H 78H Comments 176/256/0-116 Revision 1.0 DDR3 SDRAM Registered 1G bits, 8 banks 14 rows, 11 columns 1.5V 2 ranks/x4 bits 72 bits / ECC 5/2 1 8 1.5ns 1.875ns 2.5ns -- CL = 6, 7, 8, 9 CL = 6, 7, 8 CL = 6 -- 13.125ns 15ns 15ns 13.125ns 15ns 6ns 7.5ns 10ns 13.125ns 15ns
SDRAM minimum row active to row active delay (tRRD) 0 -DJ -AE -8C 0 0 0 0
20
SDRAM minimum row precharge time (tRP) -DJ, -AE -8C
Data Sheet E1256E40 (Ver. 4.0)
6
EBJ41HE4BAFA
Byte No. Function described 21 22 SDRAM upper nibbles for tRAS and tRC
Bit7 Bit6 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit5 0 1 1 0 0 1 1 0 1 1 0 0 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0
Hex Bit4 Bit3 Bit2 Bit1 Bit0 value 1 0 0 0 1 0 1 0 1 1 0 0 1 0 0 0 0 0 0 0 1 1 0 0 0 0 0 1 1 0 1 0 0 0 0 1 1 0 0 0 0 1 1 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 1 0 0 1 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 1 1 1 0 0 0 1 0 0 0 1 0 0 1 0 0 0 1 0 0 0 1 1 0 0 0 0 1 0 1 0 0 0 1 1 1 1 0 0 11H 20H 2CH 8CH 95H A4H 70H 03H 3CH 3CH 00H 01H F0H 2Ch 40H 83H 81H 80H 00H 00H 10H 33H 04H 09H 80H 04H 80H B3H 97H 03H 1DH 00H 00H
Comments
SDRAM minimum active to precharge time (tRAS), LSB 0 -DJ -AE, -8C 0 1 1 1 0 0 0 0 0 0 1 0 0 1 1 1 0 0 0 0 0 0 1 0 1 1 1 0 0 0 0 SDRAM minimum active to active /autorefresh time (tRC), LSB -DJ -AE -8C
36ns 37.5ns 49.5ns 50.625ns 52.5ns 110ns 110ns 7.5ns 7.5ns 30ns 37.5ns 30ns 37.5ns 40ns DLL-off, RZQ/6, 7 PASR / 2X refresh rate at +85C to +95C Incorporated Standard -- 30 < height 31mm
23
24 25 26 27 28
SDRAM minimum refresh recovery time delay (tRFC), LSB SDRAM minimum refresh recovery time delay (tRFC), MSB SDRAM minimum internal write to read command delay (tWTR) SDRAM minimum internal read to precharge command delay (tRTP) Upper nibble for tFAW -DJ -AE, -8C Minimum four activate window delay time (tFAW) -DJ -AE -8C
29
30 31 32 33
SDRAM output drivers supported SDRAM refresh options Module thermal sensor SDRAM device type
34 to 59 Reserved 60 61 62 63 64 65 Module nominal height Module maximum thickness Reference Raw Card Used DIMM module attributes Heat Spreader Solution Register vender ID (LSB) (Inphi) (TI) 66 Register vender ID (MSB) (Inphi) (TI) 67 Register revision (Inphi) (TI) 68 69 Register Type Register control word function (RC0, 1)
Raw Card E 2row/1register Incorporated Naming bank=5 Naming bank=1 Actual ID
Rev.4 Rev. 3.1 SSTE32882 Default
Data Sheet E1256E40 (Ver. 4.0)
7
EBJ41HE4BAFA
Byte No. Function described 70 71 72 73 74 75 76 77 to 116 117 118 119 120 121 122 to 125 126 Register control word function (RC2, 3) Register control word function (RC4, 5) Register control word function (RC6, 7) Register control word function (RC8, 9)
Bit7 Bit6 0 0 0 0 1 1 0 0 0 0 0 0 0 1 x x x x 0 0 0 0 0 0 0 1 0 1 1 0
Bit5 0 0 0 0 0 0 0 0 0 1 x x x x 0 0 1 1 1 1 1 0 1 0 1 0
Hex Bit4 Bit3 Bit2 Bit1 Bit0 value 1 1 0 0 0 0 0 0 0 1 x x x x 1 0 0 1 1 0 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 x x x x 0 1 0 1 1 0 0 1 0 1 1 0 0 1 0 0 0 0 0 0 0 1 x x x x 0 1 1 0 1 0 0 1 0 1 0 1 0 0 0 0 0 0 0 0 1 1 x x x x 0 1 0 1 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 x x x x 1 0 0 1 0 1 0 1 1 0 0 1 50H 55H 00H 00H 00H 00H 00H 00H 02H FEH xx xx xx xx 91H 0EH A4H 3BH 3CH A3H B0H CDH A1H DCH F8H 85H
Comments Default Default Default Default Default Default Default -- Elpida Memory Elpida Memory
Register control word function (RC10, 11) 0 Register control word function (RC12, 13) 0 Register control word function (RC14, 15) 0 Module specific section Module ID: manufacturer's JEDEC ID code, LSB Module ID: manufacturer's JEDEC ID code, MSB Module ID: manufacturing location Module ID: manufacturing date Module ID: manufacturing date Module ID: module serial number Cyclical redundancy code (CRC) -DJ (Inphi) (TI) -AE (Inphi) (TI) -8C (Inphi) (TI) 0 0 1 x x x x 1 0 1 0 0 1 1 1 1 1 1 1
Year code (BCD) Week code (BCD)
127
Cyclical redundancy code (CRC) -DJ (Inphi) (TI) -AE (Inphi) (TI) -8C (Inphi) (TI)
Data Sheet E1256E40 (Ver. 4.0)
8
EBJ41HE4BAFA
Byte No. Function described 128 129 130 131 132 133 134 135 136 137 138 139 140 141 Module part number Module part number Module part number Module part number Module part number Module part number Module part number Module part number Module part number Module part number Module part number Module part number Module part number Module part number -DJ -AE -8C 142 Module part number -DJ -AE -8C 143 144 145 146 147 148 149 150 to 175 176 to 255 Module part number Module part number Module part number Module revision code Module revision code SDRAM manufacturer's JEDEC ID code, LSB SDRAM manufacturer's JEDEC ID code, MSB Manufacturer's specific data Open for customer use
Bit7 Bit6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 0 1 1 1 0 1 0 0 0 0 1 0
Bit5 0 0 0 1 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 1 0 1 1 1 0 1 0
Hex Bit4 Bit3 Bit2 Bit1 Bit0 value 0 0 0 1 1 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 1 0 0 0 1 0 0 1 0 0 0 0 0 0 1 0 0 1 1 0 0 1 0 0 0 0 0 1 0 1 0 0 1 0 0 1 1 0 0 1 0 1 1 0 0 0 1 0 1 1 0 0 0 0 1 0 0 1 1 0 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 0 0 0 0 1 1 0 1 0 0 0 1 0 1 0 0 1 0 1 1 0 1 0 0 1 1 1 1 0 0 0 0 0 0 45H 42H 4AH 34H 31H 48H 45H 34H 42H 41H 46H 41H 2DH 44H 41H 38H 4AH 45H 43H 2DH 45H 20H 30H 20H 02H FEH 00H
Comments E B J 4 1 H E 4 B A F A -- D A 8 J E C -- E (Space) Initial (Space) Elpida Memory Elpida Memory
Data Sheet E1256E40 (Ver. 4.0)
9
VSS
VSS
DQS17
DQS10
DQS12
DQS0
/DQS17
DQS11
/DQS10
/DQS12
/DQS11
/DQS0
DQS14
VSS
/DQS14
DQS16
DQS7 DQS4 4 4
Rs1 Rs1 Rs1 Rs1 Rs1 Rs1 Rs1 Rs1 Rs1 Rs1 Rs1 Rs1 Rs1 Rs1 Rs1 Rs1 Rs1
VSS 4 DQ44 to DQ47
DQ32 to DQ35
DQ28 to DQ31
VSS DQ20 4 to DQ23
VSS DQ12 4 to DQ15
/DQS16
CB4 4 to CB7
VSS DQ0 4 to DQ3
/DQS7 /DQS4
Rs1 Rs1 Rs1 Rs1 Rs1 Rs1 Rs1 Rs1
VSS 4 DQ60 to DQ63
Block Diagram
VSS 4 DQ56 to DQ59
DQS DQS DQS DQS DQS DM /DQS /DQS /DQS /DQS /DQS DQS DQS DQS DM DQ0 to DQ3 DM DQ0 to DQ3 DM DQ0 to DQ3 DM DQ0 to DQ3 DM DQ0 to DQ3 /DQS /DQS /DQS DM DQ0 to DQ3 DM DQ0 to DQ3 DQ0 to DQ3
Rs3
Rs1
Rs1
Rs1
DQS
/DQS
DM DQ0 to DQ3
Rs3
VTT
Rs3 Rs3 Rs3
VTT
Data Sheet E1256E40 (Ver. 4.0)
17 3 17 3
Rs3 Rs3
Rs3
D7
Rs3
D4
D0
D16
D14
D11
D10
D12
D17
Rs3
/CS ODT CKE Address BA Command
Rs4
/CS ODT CKE Address BA Command
/CS ODT CKE Address BA Command
/CS ODT CKE Address BA Command
/RCS1_B RODT1_B RCKE1_B [Address, BA]_B Rcommand_B
/CS ODT CKE Address BA Command /CS ODT CKE Address BA Command /CS ODT CKE Address BA Command /CS ODT CKE Address BA Command
/CS ODT CKE Address BA Command
/RCS0_A RODT0_A RCKE0_A [Address, BA]_A Rcommand_A
ZQ
CK /CK
Rs3
Rs4
ZQ
ZQ
ZQ
ZQ
ZQ
ZQ
CK /CK
Rs5
ZQ
Rs5 Rs5 Rs5 Rs5 Rs5 Rs5 Rs5
CK /CK
ZQ DM
CK /CK
CK /CK
PCK0_B /PCK0_B
CK /CK CK /CK CK /CK CK /CK
PCK0_A /PCK0_A
Rs5
/DQS
DQS DQS DQS DQS /DQS /DQS /DQS
DQS
DQS
DQS
DQS
DQS
DQ0 to DQ3
/DQS DM DQ0 to DQ3 DM DQ0 to DQ3 DM DQ0 to DQ3
Rs3 Rs3 Rs3
/DQS
/DQS
/DQS
/DQS
DM DQ0 to DQ3
DM DQ0 to DQ3
DM DQ0 to DQ3
DM DQ0 to DQ3
DM DQ0 to DQ3
VTT
VTT
Rs3 Rs3
/CS ODT CKE Address BA Command
/CS ODT CKE Address BA Command
/CS ODT CKE Address BA Command
/CS ODT CKE Address BA Command
/RCS0_B RODT0_B RCKE0_B
/CS ODT CKE Address BA Command /CS ODT CKE Address BA Command /CS ODT CKE Address BA Command
/CS ODT CKE Address BA Command
/CS ODT CKE Address BA Command
/RCS1_A RODT1_A RCKE1_A
D34 D18 D28
D29
D30
D35
D25 D22 D32
Rs4
Rs4
ZQ
ZQ
ZQ
ZQ
ZQ
CK /CK
Rs5
ZQ
Rs5 Rs5 Rs5 Rs5 Rs5
CK /CK
ZQ
CK /CK
ZQ
CK /CK
ZQ
PCK1_B /PCK1_B
CK /CK CK /CK CK /CK
Rs5
CK /CK
CK /CK
Rs5
PCK1_A /PCK1_A
Rs5
Block Diagram (1)
10
DQS9 /DQS9 VSS DQS13 DQS5 DQS15 /DQS13 /DQS5 /DQS15 VSS 4 DQ8 to DQ11 DQ40 to DQ43 VSS DQ4 4 to DQ7 VSS 4 DQ36 to DQ39 VSS 4 DQ52 to DQ55 4
Rs1 Rs1 Rs1 Rs1 Rs1 Rs1 Rs1 Rs1 Rs1 Rs1 Rs1 Rs1 Rs1
VSS
DQS1
DQS8
DQS2
DQS3
DQ24 to DQ27
/DQS1
/DQS8
/DQS2
/DQS3
DQS6
/DQS6
DM DQS DQS DQS DQS /DQS /DQS /DQS /DQS DM DQ0 to DQ3 DM DQ0 to DQ3 DQ0 to DQ3 DM DQ0 to DQ3
VSS DQ16 4 to DQ19
DQ48 VSS to DQ51
VSS CB0 4 to CB3
4
4
Rs1
Rs1
Rs1
Rs1
Rs1
Rs1
Rs1
Rs1
Rs1
Rs1
Rs1
Rs1
Rs1
Rs1
DQS
DQS
DQS
DQS
DQS
/DQS
/DQS
/DQS
/DQS
/DQS
DM DQ0 to DQ3
DM DQ0 to DQ3
DM DQ0 to DQ3
DM DQ0 to DQ3
DM DQ0 to DQ3
Rs3 Rs3
VTT
17 3
Rs3
VTT
Rs3 Rs3
Rs3 Rs3 Rs3
17 3
Rs3
D6
D5
D9
D1
D2
D3
D8
D15
D13
Rs3
/CS ODT CKE Address BA Command
Rs4
/CS ODT CKE Address BA Command
/CS ODT CKE Address BA Command
/CS ODT CKE Address BA Command
/RCS1_B RODT1_B RCKE1_B [Address, BA]_B Rcommand_B PCK0_B /PCK0_B
/CS ODT CKE Address BA Command
/CS ODT CKE Address BA Command
/CS ODT CKE Address BA Command
/CS ODT CKE Address BA Command
/CS ODT CKE Address BA Command
/RCS0_A RODT0_A RCKE0_A [Address, BA]_A Rcommand_A
ZQ ZQ ZQ ZQ ZQ
CK /CK CK /CK
Rs5
Rs3
Rs4
ZQ
CK /CK
Rs5
ZQ ZQ
Rs5 Rs5 Rs5
CK /CK
ZQ DM
CK /CK
CK /CK
CK /CK
Rs5
CK /CK
Rs5
CK /CK
Rs5
PCK0_A /PCK0_A
Rs5
/DQS
DQS
DQS
DQS
DQS
DQS
DQS
DQS
DQS
DQS
DQ0 to DQ3
/DQS
/DQS
/DQS
/DQS
/DQS
/DQS
/DQS
/DQS
DM DQ0 to DQ3
DM DQ0 to DQ3
DM DQ0 to DQ3
DM DQ0 to DQ3
DM DQ0 to DQ3
DM DQ0 to DQ3
DM DQ0 to DQ3
DM DQ0 to DQ3
Rs3
EBJ41HE4BAFA
VTT
VTT
Rs3 Rs3
/CS ODT CKE Address BA Command
/CS ODT CKE Address BA Command
/CS ODT CKE Address BA Command
/CS ODT CKE Address BA Command
/RCS0_B RODT0_B RCKE0_B
Rs3 Rs3
/CS ODT CKE Address BA Command
/CS ODT CKE Address BA Command
/CS ODT CKE Address BA Command
/CS ODT CKE Address BA Command
/CS ODT CKE Address BA Command
/RCS1_A RODT1_A RCKE1_A
D33
D24 D23
D26
D27
D19
D20
D21
D31
Rs4
Rs4
CK /CK
Rs5
ZQ
Rs5 Rs5
CK /CK
ZQ
CK /CK
ZQ
CK /CK
Rs5
ZQ
PCK1_B /PCK1_B
CK /CK
Rs5
ZQ
CK /CK
Rs5
ZQ
CK /CK
Rs5
ZQ
CK /CK
Rs5
ZQ
CK /CK
Rs5
ZQ
PCK1_A /PCK1_A
EBJ41HE4BAFA
/CS0 /CS1 BA Address Command CKE0 CKE1 ODT0 ODT1
RS2 RS2
/RCS0_A -> /CS0: SDRAMs D0 to D3, D8 to D12, D17 /RCS0_B -> /CS0: SDRAMs D22 to D25, D31 to D34 /RCS1_A -> /CS1: SDRAMs D18 to D21, D26 to D30, D35 /RCS1_B -> /CS1: SDRAMs D4 to D7, D13 to D16 RBA_A -> BA0 to BA2: SDRAMs D0 to D3, D8 to D12, D17 to D21, D26 to D30, D35 RBA_B -> BA0 to BA2: SDRAMs D4 to D7, D13 to D16, D22 to D25, D31 to D34 RAddress_A -> A0 to A13: SDRAMs D0 to D3, D8 to D12, D17 to D21, D26 to D30, D35 RAddress_B -> A0 to A13: SDRAMs D4 to D7, D13 to D16, D22 to D25, D31 to D34 RCommand_A -> /RAS, /CAS, /WE: SDRAMs D0 to D3, D8 to D12, D17 to D21, D26 to D30, D35 RCommand_B -> /RAS, /CAS, /WE: SDRAMs D4 to D7, D13 to D16, D22 to D25, D31 to D34
RS2 RS2
RS2
RS2 RS2
RS2 RS2
R E G I S T E R /
RCKE0_A -> CKE: SDRAMs D0 to D3, D8 to D12, D17 RCKE0_B -> CKE: SDRAMs D22 to D25, D31 to D34 RCKE1_A -> CKE: SDRAMs D18 to D21, D26 to D30, D35 RCKE1_B -> CKE: SDRAMs D4 to D7, D13 to D16 RODT0_A -> ODT: SDRAMs D0 to D3, D8 to D12, D17 RODT0_B -> ODT: SDRAMs D22 to D25, D31 to D34 RODT1_A -> ODT: SDRAMs D18 to D21, D26 to D30, D35 RODT1_B -> ODT: SDRAMs D4 to D7, D13 to D16 PCK0_A -> CK: PCK0_B -> CK: PCK1_A -> CK: PCK1_B -> CK: /PCK0_A -> /CK: /PCK0_B -> /CK: /PCK1_A -> /CK: /PCK1_B -> /CK: /Err_Out SDRAMs D0 to D3, D8 to D12, D17 SDRAMs D4 to D7, D13 to D16 SDRAMs D18 to D21, D26 to D30, D35 SDRAMs D22 to D25, D31 to D34 SDRAMs D0 to D3, D8 to D12, D17 SDRAMs D4 to D7, D13 to D16 SDRAMs D18 to D21, D26 to D30, D35 SDRAMs D22 to D25, D31 to D34
CK0
RS4
P L L
/CK0
Par_In /RESET
RS2
/RESET
/RESET: SDRAMs D0 to D35 CK1 /CK1 VTT VDDSPD VREFCA VREFDQ VDD VSS
RS4
Teminated at near card edge
Note : 1. DQ wiring may be changed within a nibble. * D0 to D35: 1G bits DDR3 SDRAM Address, BA: A0 to A15, BA0 to BA2 Command: /RAS, /CAS, /WE U1: 256 bytes EEPROM Rs1: 159 Rs2: 229 Rs3: 369 Rs4: 1209 Rs5: 2409 Register: SSTE32882
SPD SDRAMs (D0 to D35) SDRAMs (D0 to D35) SDRAMs (D0 to D35) SDRAMs (D0 to D35), SPD
Serial PD SCL SA0 SA1 SA2 SCL A0 A1 A2 SDA SDA
U1
/EVENT /EVENT
VTT
D18
D28
D29
D30
D35
D32
D22
D34
D25
VTT
D27 D19
D20
D21
D26
D31
D23
D33
D24
VTT
D9
D1
D2
D3
D8
D13
D5
D15
D6
VTT
D0
D10
D11
D12
D17
D14
D4
D16
D7
Address, command and control line
Block Diagram (2)
Data Sheet E1256E40 (Ver. 4.0)
11
VTT
VTT
Register
VTT
VTT
EBJ41HE4BAFA
Electrical Specifications
* All voltages are referenced to VSS (GND). Absolute Maximum Ratings
Parameter Power supply voltage Input voltage Output voltage Reference voltage Reference voltage for DQ Storage temperature Power dissipation Short circuit output current Symbol VDD VIN VOUT VREFCA VREFDQ Tstg PD IOUT Value -0.4 to +1.975 -0.4 to +1.975 -0.4 to +1.975 -0.4 to 0.6 x VDD -0.4 to 0.6 x VDDQ -55 to +100 18 50 Unit V V V V V C W mA 1, 4 Notes 1, 3, 4 1, 4 1, 4 3, 4 3, 4 1, 2, 4
Notes: 1. Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Storage temperature is the case surface temperature on the center/top side of the DRAM. 3. VDD and VDDQ must be within 300mV of each other at all times; and VREF must be not greater than 0.6 x VDDQ, When VDD and VDDQ are less than 500mV; VREF may be equal to or less than 300mV. 4. DDR3 SDRAM component specification. Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability.
Operating Temperature Condition
Parameter Operating case temperature Symbol TC Rating 0 to +95 Unit C Notes 1, 2, 3
Notes: 1. Operating temperature is the case surface temperature on the center/top side of the DRAM. 2. The Normal Temperature Range specifies the temperatures where all DRAM specifications will be supported. During operation, the DRAM case temperature must be maintained between 0C to +85C under all operating conditions. 3. Some applications require operation of the DRAM in the Extended Temperature Range between +85C and +95C case temperature. Full specifications are guaranteed in this range, but the following additional conditions apply: a) Refresh commands must be doubled in frequency, therefore reducing the refresh interval tREFI to 3.9s. (This double refresh requirement may not apply for some devices.) b) If Self-refresh operation is required in the Extended Temperature Range, then it is mandatory to either use the Manual Self-Refresh mode with Extended Temperature Range capability (MR2 bit [A6, A7] = [0, 1]) or enable the optional Auto Self-Refresh mode (MR2 bit [A6, A7] = [1, 0]).
Data Sheet E1256E40 (Ver. 4.0)
12
EBJ41HE4BAFA
Recommended DC Operating Conditions (TC = 0C to +85C) (DDR3 SDRAM Component Specification)
Parameter Supply voltage Symbol VDD, VDDQ VSS VDDSPD Input reference voltage Input reference voltage for DQ Termination voltage VREFCA (DC) VREFDQ (DC) VTT min. 1.425 0 3.0 0.49 x VDDQ 0.49 x VDDQ VDDQ/2 - TBD typ. 1.5 0 3.3 max. 1.575 0 3.6 Unit V V V V V V 1, 4, 5 1, 4, 5 Notes 1, 2, 3 1
0.50 x VDDQ 0.51 x VDDQ 0.50 x VDDQ 0.51 x VDDQ TBD VDDQ/2 + TBD
Notes: 1. 2. 3. 4.
DDR3 SDRAM component specification. Under all conditions VDDQ must be less than or equal to VDD. VDDQ tracks with VDD. AC parameters are measured with VDD and VDDQ tied together. The AC peak noise on VREF may not allow VREF to deviate from VREF(DC) by more than 1% VDD (for reference: approx 15 mV). 5. For reference: approx. VDD/2 15 mV.
Data Sheet E1256E40 (Ver. 4.0)
13
EBJ41HE4BAFA
DC Characteristics 1 (TC = 0C to +85C, VDD = 1.5V 0.075V, VSS = 0V)
Parameter Operating current (ACT-PRE) Operating current (ACT-READ-PRE) Symbol IDD0 Data rate (Mbps) 1333 1066 800 1333 1066 800 1333 1066 800 1333 1066 800 1333 1066 800 1333 1066 800 1333 1066 800 1333 1066 800 1333 1066 800 1333 1066 800 1333 1066 800 max. 2680 2540 2350 2970 2810 2630 1830 1710 1590 1470 1410 1340 2130 1960 1790 2130 1960 1790 1780 1670 1540 2310 2100 1880 3890 3390 2860 4300 3720 3130 6090 5750 5640 1350 1333 1066 800 6230 5270 4850 Unit mA Notes
IDD1
mA
IDD2PF Precharge power-down standby current IDD2PS
mA
Fast PD Exit
mA
Slow PD Exit
Precharge quiet standby current
IDD2Q
mA
Precharge standby current Active power-down current (Always fast exit) Active standby current Operating current (Burst read operating) Operating current (Burst write operating) Burst refresh current Self-refresh current normal temperature range All bank interleave read current
IDD2N
mA
IDD3P
mA
IDD3N
mA
IDD4R
mA
IDD4W
mA
IDD5B IDD6 IDD7R
mA mA mA
Data Sheet E1256E40 (Ver. 4.0)
14
EBJ41HE4BAFA
AC Timing for IDD Test Conditions For purposes of IDD testing, the following parameters are to be utilized.
DDR3-1333 Parameter CL (IDD) tCK min.(IDD) tRCD min. (IDD) tRC min. (IDD) tRAS min.(IDD) tRP min. (IDD) tFAW (IDD)-x4/x8 tRRD (IDD)-x4/x8 tRFC (IDD) 9-9-9 9 1.5 13.5 49.5 36 13.5 30 6.0 110 DDR3-1066 7-7-7 7 1.875 13.13 50.63 37.5 13.13 37.5 7.5 110 DDR3-800 6-6-6 6 2.5 15 52.5 37.5 15 40 10 110 Unit tCK ns ns ns ns ns ns ns ns
DC Characteristics 2 (TC = 0C to +85C, VDD, VDDQ = 1.5V 0.075V) (DDR3 SDRAM Component Specification)
Parameter Input leakage current Output leakage current Symbol ILI ILO Value 2 5 Unit A A Notes VDD VIN VSS DDQ VOUT VSS
Data Sheet E1256E40 (Ver. 4.0)
15
EBJ41HE4BAFA
Pin Functions
CK, /CK (input pin) CK and /CK are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK and negative edge of /CK. Output (read) data is referenced to the crossings of CK and /CK (both directions of crossing). /CS (input pin) All commands are masked when /CS is registered high. /CS provides for external rank selection on systems with multiple ranks. /CS is considered part of the command code. /RAS, /CAS, and /WE (input pins) /RAS, /CAS and /WE (along with /CS) define the command being entered. A0 to A15 (input pins) Provided the row address for active commands and the column address for read/write commands to select one location out of the memory array in the respective bank. (A10(AP) and A12(/BC) have additional functions, see below) The address inputs also provide the op-code during mode register set commands. [Address Pins Table]
Address (A0 to A13) Row address (RA) AX0 to AX13 Column address (CA) AY0 to AY9, A11 Notes
A10(AP) (input pin) A10 is sampled during read/write commands to determine whether auto-precharge should be performed to the accessed bank after the read/write operation. (high: auto-precharge; low: no auto-precharge) A10 is sampled during a precharge command to determine whether the precharge applies to one bank (A10 = low) or all banks (A10 = high). If only one bank is to be precharged, the bank is selected by bank addresses (BA). A12 (/BC) (input pin) A12 is sampled during read and write commands to determine if burst chop (on-the-fly) will be performed. (A12 = high: no burst chop, A12 = low: burst chopped.) BA0 to BA2 (input pins) BA0, BA1 and BA2 define to which bank an active, read, write or precharge command is being applied. BA0 and BA1 also determine if a mode register is to be accessed during a MRS cycle. [Bank Select Signal Table]
BA0 Bank 0 Bank 1 Bank 2 Bank 3 Bank 4 Bank 5 Bank 6 Bank 7 L H L H L H L H BA1 L L H H L L H H BA2 L L L L H H H H
Remark: H: VIH. L: VIL.
Data Sheet E1256E40 (Ver. 4.0)
16
EBJ41HE4BAFA
CKE (input pin) CKE high activates, and CKE low deactivates, internal clock signals and device input buffers and output drivers. Taking CKE low provides precharge power-down and self-refresh operation (all banks idle), or active power-down (row active in any bank). CKE is asynchronous for self-refresh exit. After VREF has become stable during the power-on and initialization sequence, it must be maintained for proper operation of the CKE receiver. For proper self-refresh entry and exit, VREF must be maintained to this input. CKE must be maintained high throughout read and write accesses. Input buffers, excluding CK, /CK, ODT and CKE are disabled during power-down. Input buffers, excluding CKE, are disabled during self-refresh. DQ and CB (input and output pins) Bi-directional data bus. DQS and /DQS (input and output pin) Output with read data, input with write data. Edge-aligned with read data, centered in write data. The data strobe DQS is paired with differential signals /DQS to provide differential pair signaling to the system during READs and WRITEs. ODT (input pins) ODT (registered high) enables termination resistance internal to the DDR3 SDRAM. When enabled, ODT is only applied to each DQ, DQS, /DQS, DM. The ODT pin will be ignored if the mode register (MR1) is programmed to disable ODT. VDD (power supply pins) 1.5V is applied. (VDD is for the internal circuit.) VDDSPD (power supply pin) 3.3V is applied (For serial EEPROM). VSS (power supply pin) Ground is connected. VTT (power supply pin) Termination supply. VREFDQ (power supply) Reference voltage for DQ. VREFCA (power supply) Reference voltage for CA. SCL (input pin) Clock input for serial PD. SDA (input and output pins) Data input/output for serial PD. SA (input pin) Serial address input. /RESET (input pin) /RESET is negative active signal (active low) and is referred to GND.
Data Sheet E1256E40 (Ver. 4.0)
17
EBJ41HE4BAFA
Par_In (input pin) Parity bit for the Address and Control bus. /Err_Out (output pin) Parity error found on the Address and Control bus. /Event (output pin) Temperature alert output.
Detailed Operation Part, Electrical Characteristics and Timing Waveforms
Refer to the EDJ1104BASE, EDJ1108BASE, EDJ1116BASE datasheet (E1128E). DM pins of component device fixed to VSS level on the module board. DIMM /CAS latency = component CL + 1 for registered type.
Data Sheet E1256E40 (Ver. 4.0)
18
EBJ41HE4BAFA
Physical Outline
Unit: mm
Front side
8.50 max
(DATUM -A-)
(Front)
1
120
B
A
47.00
133.35
71.00
1.27 0.10
Back side
9.50
121
240
17.30
4.00 min
DIMM heat spreader
DIMM heat spreader
(Back)
C
Detail A
Detail B
Detail C
(DATUM -A-)
2.50 0.20
1.00
0.20 0.15
(R0.65)
2.50
R0.75
0.80 0.05
3.80
5.00
1.50 0.10
ECA-TS2-0245-02
Data Sheet E1256E40 (Ver. 4.0)
19
3.00
2.10 0.15
30.50 max
EBJ41HE4BAFA
CAUTION FOR HANDLING MEMORY MODULES
When handling or inserting memory modules, be sure not to touch any components on the modules, such as the memory ICs, chip capacitors and chip resistors. It is necessary to avoid undue mechanical stress on these components to prevent damaging them. In particular, do not push module cover or drop the modules in order to protect from mechanical defects, which would be electrical defects. When re-packing memory modules, be sure the modules are not touching each other. Modules in contact with other modules may cause excessive mechanical stress, which may damage the modules.
MDE0202
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR MOS DEVICES
Exposing the MOS devices to a strong electric field can cause destruction of the gate oxide and ultimately degrade the MOS devices operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it, when once it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. MOS devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. MOS devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor MOS devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS DEVICES
No connection for CMOS devices input pins can be a cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. The unused pins must be handled in accordance with the related specifications.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Power-on does not necessarily define initial status of MOS devices. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the MOS devices with reset function have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. MOS devices are not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for MOS devices having reset function.
CME0107
Data Sheet E1256E40 (Ver. 4.0)
20
EBJ41HE4BAFA
The information in this document is subject to change without notice. Before using this document, confirm that this is the latest version.
No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Elpida Memory, Inc. Elpida Memory, Inc. does not assume any liability for infringement of any intellectual property rights (including but not limited to patents, copyrights, and circuit layout licenses) of Elpida Memory, Inc. or third parties by or arising from the use of the products or information listed in this document. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of Elpida Memory, Inc. or others. Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of the customer's equipment shall be done under the full responsibility of the customer. Elpida Memory, Inc. assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. [Product applications] Be aware that this product is for use in typical electronic equipment for general-purpose applications. Elpida Memory, Inc. makes every attempt to ensure that its products are of high quality and reliability. However, users are instructed to contact Elpida Memory's sales office before using the product in aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment, medical equipment for life support, or other such application in which especially high quality and reliability is demanded or where its failure or malfunction may directly threaten human life or cause risk of bodily injury. [Product usage] Design your application so that the product is used within the ranges and conditions guaranteed by Elpida Memory, Inc., including the maximum ratings, operating supply voltage range, heat radiation characteristics, installation conditions and other related characteristics. Elpida Memory, Inc. bears no responsibility for failure or damage when the product is used beyond the guaranteed ranges and conditions. Even within the guaranteed ranges and conditions, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating Elpida Memory, Inc. products does not cause bodily injury, fire or other consequential damage due to the operation of the Elpida Memory, Inc. product. [Usage environment] Usage in environments with special characteristics as listed below was not considered in the design. Accordingly, our company assumes no responsibility for loss of a customer or a third party when used in environments with the special characteristics listed below. Example: 1) Usage in liquids, including water, oils, chemicals and organic solvents. 2) Usage in exposure to direct sunlight or the outdoors, or in dusty places. 3) Usage involving exposure to significant amounts of corrosive gas, including sea air, CL 2 , H 2 S, NH 3 , SO 2 , and NO x . 4) Usage in environments with static electricity, or strong electromagnetic waves or radiation. 5) Usage in places where dew forms. 6) Usage in environments with mechanical vibration, impact, or stress. 7) Usage near heating elements, igniters, or flammable items. If you export the products or technology described in this document that are controlled by the Foreign Exchange and Foreign Trade Law of Japan, you must follow the necessary procedures in accordance with the relevant laws and regulations of Japan. Also, if you export products/technology controlled by U.S. export control regulations, or another country's export control laws or regulations, you must follow the necessary procedures in accordance with such laws or regulations. If these products/technology are sold, leased, or transferred to a third party, or a third party is granted license to use these products, that third party must be made aware that they are responsible for compliance with the relevant laws and regulations.
M01E0706
Data Sheet E1256E40 (Ver. 4.0)
21

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