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P r o d u c t In n o v a t i nnova PA50, IPA50A o n FFr roomm
PA50 * PA50A PA50 * PA50A
Power Operational Amplifier
FEATURES
* HIGHINTERNALDISSIPATION--400Watts * HIGHCURRENT--40AContinuous,100APEAK * HIGHSLEWRATE--50V/s * OPTIONALBOOSTVOLTAGEINPUTS
APPLICATIONS
* SEMI-CONDUCTORTESTING
DESCRIPTION
The PA50 is a MOSFET power operational amplifier that extends the performance limits of power amplifiers in slew rate and power bandwidth, while maintaining high current and power dissipation ratings. Boost voltage inputs allow the small signal portion of the amplifier to operate at a higher voltage than the high current output stage. The amplifier is then biased to achieve close linear swings to the supply rails at high currents for extra efficient operation.
12-PINDIP PACKAGESTYLECR
The JEDEC MO-127 12-pin Power DipTM package (see Package Outlines) is hermetically sealed and isolated from the internal circuits. The use of compressible thermal washers and/or improper mounting torque will void the product warranty. Please see "General Operating Considerations" .
EQUIVALENTSCHEMATIC
EXTERNALCONNECTIONS
-Vb
1 2 3 4 5 6 TOP VIEW 12 11 10 9 8 7
-IN +IN -Vs -Vs -OUT -OUT
+Vb +Vs +Vs +OUT +OUT
PA50U
http://www.cirrus.com
Copyright (c) Cirrus Logic, Inc. 2009 (All Rights Reserved)
MAY 2009 1 APEX - PA50UREVG
PA50 * PA50A
ABSOLUTEMAXIMUMRATINGS
P r o d u c t I n n o v a t i o nF r o m
SPECIFICATIONS
PARAMETER INPUT OFFSET VOLTAGE, initial OFFSET VOLTAGE, vs. temperature OFFSET VOLTAGE, vs. supply BIAS CURRENT, initial BIAS CURRENT vs. supply OFFSET CURRENT, initial INPUT IMPEDANCE, DC IMPUT CAPACITANCE COMMON MODE VOLTAGE RANGE COMMON MODE REJECTION,DC INPUT NOISE GAIN OPEN LOOP,@ 15Hz GAIN BANDWIDTH PRODUCT POWER BANDWIDTH OUTPUT VOLTAGE SWING VOLTAGE SWING, PA50 VOLTAGE SWING, PA50A CURRENT, peak SETTLING TIME TO.1% SLEW RATE RESISTANCE POWER SUPPLY VOLTAGE, VBOOST VOLTAGE, VS CURRENT,quiescent, boost supply CURRENT, quiescent, total THERMAL RESISTANCE,AC,junction to case3 RESISTANCE,DC,junction to case RESISTANCE, junction to air TEMPERATURE RANGE, case
SUPPLY VOLTAGE, +VS to -VS BOOST VOLTAGE, +Vb to -Vb OUTPUT CURRENT, within SOA POWER DISSIPATION, internal INPUT VOLTAGE, differential INPUT VOLTAGE, common mode TEMPERATURE, pin solder - 10s TEMPERATURE, junction2 TEMPERATURE, storage OPERATING TEMPERATURE RANGE, case TEST CONDITIONS1 MIN PA50 TYP 5 20 10 10 .01 10 10" 13 100 10 102 3 200 MAX 10 50 30 50 50 MIN
100V 130V 100A 400W 20V Vb 300C 150C -65 to +150C -55 to +125C PA50A TYP 2 * * * * * * * * * * * * * MAX 5 * * * * UNITS mV V/V V/V pA pA/V pA pF V dB Vrms dB MHz kHz
Full temperature range
Full temperature range Full temp, range, VCM= 20V 100KHZ BW, Rs=1K Full temperature range RL=10 RL=4, Vo=80VP-P, Av=-10 Full temperature range Io=40A VBOOST=VS10V, Io=40A VBOOST=VS10V, Io=50A 3ms 10% Duty Cycle AV= -10,10V STEP,RL=4 AV=-10 IO=0, NO LOAD, 2MHZ Full temperature range Full temperature range
-VB +12 +VB -14 90
*
94
*
100 50
1 2.5 15 26 30 .2 .25 12 65 50 32 36 .25 .31 85
* *
* * * * * * * * * * * * * * *
+14, -12 3
* *
Full temperature range, F>60HZ Full temperature range, F>60HZ Full temperature range Meets full range specification
-25
*
NOTES: * The specification of PA50A is identical to the specification for PA50 in applicable column to the left 1. Unless otherwise noted: TC = 25C, DC input specifications are value given. Power supply voltage is typical rating. VBOOST = VS. 2. Long term operation at the maximum junction temperature will result in reduced product life. Derate internal power dissipation to achieve high MTTF. For guidance, refer to the heatsink data sheet. 3. Rating applies if the output current alternates between both output transistors at a rate faster than 60 Hz.
CAUTION
The PA50 is constructed from MOSFET transistors. ESD handling procedures must be observed. The internal substrate contains beryllia (BeO). Do not break the seal. If accidentally broken, do not crush, machine, or subject to temperatures in excess of 850C to avoid generating toxic fumes.
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VS VS
9.5 VS 8.0 5.8 VS 4.0
* VS
* 5.8 VS 5.0
V V V A s V/s V V mA mA C/W C/W C/W C
PA50U
P r o d u c t I n n o v a t i o nF r o m
PA50 * PA50A
POWER SUPPLY REJECTION, PSR (dB)
500
VOLTAGE DROP FROM SUPPLY, VS - VO (V)
INTERNAL POWER DISSIPATION, P(W)
POWER DERATING
100 80 60 40 20
POWER SUPPLY REJECTION
10 8 6 4 2 0
OUTPUT VOLTAGE SWING
400 T = TC 300 200 100 0
V BOOS
T
= VS
V BOO
0
ST
=V
S
+1
0V
0
25 50 75 TEMPERATURE, T (C)
100
0 10
100 1K 10K 100K 1M 10M FREQUENCY F (Hz)
10 20 30 40 OUTPUT CURRENT, IO (A)
50
OPEN LOOP GAIN RESPONSE, A (dB)
120
SMALL SIGNAL GAIN
OPEN LOOP PHASE, ()
0 -45 -90
SMALL SIGNAL PHASE
OUTPUT VOLTAGE, VO (VP-P)
RL = 4
80
100 90 80 70 60 50 40 30
POWER RESPONSE
40
-135
0 1
RL = 4 10 100 1K 10K 100K 1M 10M FREQUENCY, Ff (Hz)
-180 1 10 100 1K 10K 100K 1M 10M FREQUENCY, F (Hz)
20
100K FREQUENCY, F (Hz)
1M
COMMON MODE REJECTION, CMR (dB)
NORMALIZED QUIESCENT CURRENT, IQ (X)
100 80 60 40 20
COMMON MODE REJECTION
1.125 1.1 1.075 1.05 1.025
QUIESCENT CURRENT
VS = VB
OUTPUT CURRENT, (A)
100
SAFE OPERATING AREA
t= 1m s t= DC 10 DC T ms C T = 25 DC C= 85 C T C C= 12 5 C
10
1
0 10
100 1K 10K 100K FREQUENCY, F (Hz)
1M
1 40 60 80 20 100 TOTAL SUPPLY VOLTAGE, VS (V)
0.1
1 10 100 SUPPLY TO OUTPUT DIFFERENTIAL, (V)
PA50U
3
PA50 * PA50A
GENERAL
P r o d u c t I n n o v a t i o nF r o m
Please read Application Note 1 "General Operating Considerations" which covers stability, supplies, heat sinking, mounting, current limit, SOA interpretation, and specification interpretation. Visit www.Cirrus.com for design tools that help automate tasks such as calculations for stability, internal power dissipation, current limit; heat sink selection; Apex Precision Power's complete Application Notes library; Technical Seminar Workbook; and Evaluation Kits.
the high current output stage. An additional 10V on the VBOOST pins is sufficient to allow the small signal stages to drive the output transistors into saturation and improve the output voltage swing for extra efficient operation when required. When close swings to the supply rails is not required the +VBOOST and +VS pins must be strapped together as well as the -VBOOST and -VS pins. The boost voltage pins must not be at a voltage lower than the VS pins.
CURRENTLIMIT
There is no internal circuit provision for current limit in the PA50. However, the PA50 circuit board in the PA50 evaluation kit does provide a means whereby the output current can be sensed. An external circuit current limit can thereby be implemented if needed.
COMPENSATION
Compensation is internally fixed for a gain of 3 or more and is not adjustable by the user. The PA50 therefore is not unity gain stable.
POWERSUPPLYBYPASSING
Proper and sufficient power supply bypassing is crucial to proper operation of the PA50. Bypass the +Vb and -Vb supply pins with a minimum .1F ceramic capacitors directly at the supply pins. On the +Vs and -Vs pins use a combination of ceramic and electrolytic capacitors. Use 1F ceramic capacitors and an electrolytic capacitor at least 10F for each amp of output current required.
BOOSTOPERATION
With the VBOOST feature the small signal stages of the amplifier are operated at higher supply voltages than the amplifier's high current output stage. +VBOOST (pin 11) and -VBOOST (pin 12) are connected to the small signal circuitry of the amplifier. +VS (pin 9,10) and -VS (pin 3,4) are connected to
ContACtinG CiRRUs LoGiC sUPPoRt
For all Apex Precision Power product questions and inquiries, call toll free 800-546-2739 in North America. For inquiries via email, please contact apex.support@cirrus.com. International customers can also request support by contacting their local Cirrus Logic Sales Representative. To find the one nearest to you, go to www.cirrus.com
IMPORTANT NOTICE Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED TO BE SUITABLE FOR USE IN PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER'S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, and the Cirrus Logic logo designs, Apex Precision Power, Apex and the Apex Precision Power logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners.
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PA50U

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