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ispLSI 1016E
(R)
In-System Programmable High Density PLD Functional Block Diagram
Features
* HIGH-DENSITY PROGRAMMABLE LOGIC -- 2000 PLD Gates -- 32 I/O Pins, Four Dedicated Inputs -- 96 Registers -- High-Speed Global Interconnect -- Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc. -- Small Logic Block Size for Random Logic * HIGH-PERFORMANCE E2CMOS(R) TECHNOLOGY -- fmax = 125 MHz Maximum Operating Frequency --
Output Routing Pool
A2 A3 A4 A5 A6 A7
Logic Array
tpd = 7.5 ns Propagation Delay
-- TTL Compatible Inputs and Outputs -- Electrically Erasable and Reprogrammable -- Non-Volatile -- 100% Tested at Time of Manufacture -- Unused Product Term Shutdown Saves Power * IN-SYSTEM PROGRAMMABLE -- In-System Programmable (ISPTM) 5V Only -- Increased Manufacturing Yields, Reduced Time-toMarket and Improved Product Quality
D
Global Routing Pool (GRP)
EW
-- Reprogram Soldered Device for Faster Prototyping
-- Enhanced Pin Locking Capability
-- Three Dedicated Clock Input Pins
I1 01
6E
* OFFERS THE EASE OF USE AND FAST SYSTEM SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY OF FIELD PROGRAMMABLE GATE ARRAYS -- Complete Programmable Device Can Combine Glue Logic and Structured Designs
The ispLSI 1016E is a High Density Programmable Logic Device containing 96 Registers, 32 Universal I/O pins, four Dedicated Input pins, three Dedicated Clock Input pins, one Global OE input pin and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. The ispLSI 1016E offers 5V non-volatile in-system programmability of the logic, as well as the interconnect to provide truly reconfigurable systems. A functional superset of the ispLSI 1016 architecture, the ispLSI 1016E device adds a new global output enable pin. The basic unit of logic on the ispLSI 1016E device is the Generic Logic Block (GLB). The GLBs are labeled A0, A1...B7 (see Figure 1). There are a total of 16 GLBs in the ispLSI 1016E device. Each GLB has 18 inputs, a programmable AND/OR/Exclusive OR array, and four outputs which can be configured to be either combinatorial or registered. Inputs to the GLB come from the GRP and dedicated inputs. All of the GLB outputs are brought back into the GRP so that they can be connected to the inputs of any other GLB on the device.
-- Synchronous and Asynchronous Clocks
-- Flexible Pin Placement
-- Lead-Free Package Options
U
Copyright (c) 2006 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SE
is p
-- Optimized Global Routing Pool Provides Global Interconnectivity
LS
-- Programmable Output Slew Rate Control to Minimize Switching Noise
A
FO
R
N
Description
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
1016e_09
1
ES IG N
DQ
B5 B4 B3 B2 B1 B0
DQ
GLB
DQ
CLK
August 2006
Output Routing Pool
A1
DQ
B6
S
0139C1-isp
A0
B7
Specifications ispLSI 1016E
Functional Block Diagram
Figure 1. ispLSI 1016E Functional Block Diagram
B7 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 SDI/IN 0 SDO/IN 1 A0 A1 B6 B5 B4 B3 B2 B1 B0
Output Routing Pool (ORP)
Output Routing Pool (ORP)
Input Bus
EW
A3 A4 A5 A6 A7
Global Routing Pool (GRP)
lnput Bus
A2
N
FO
R
Clock Distribution Network
Megablock
ispEN
16
EA
*Note: Y1 and RESET are multiplexed on the same pin
10
U SE
The device also has 32 I/O cells, each of which is directly connected to an I/O pin. Each I/O cell can be individually programmed to be a combinatorial input, registered input, latched input, output or bi-directional I/O pin with 3-state control. The signal levels are TTL compatible voltages and the output drivers can source 4 mA or sink 8 mA. Each output can be programmed independently for fast or slow output slew rate to minimize overall output switching noise.
is pL
The GRP has, as its inputs, the outputs from all of the GLBs and all of the inputs from the bi-directional I/O cells. All of these signals are made available to the inputs of the GLBs. Delays through the GRP have been equalized to minimize timing skew. Clocks in the ispLSI 1016E device are selected using the Clock Distribution Network. Three dedicated clock pins (Y0, Y1 and Y2) are brought into the distribution network, and five clock outputs (CLK 0, CLK 1, CLK 2, IOCLK 0 and IOCLK 1) are provided to route clocks to the GLBs and I/O cells. The Clock Distribution Network can also be driven from a special clock GLB (B0 on the ispLSI 1016E device). The logic of this GLB allows the user to create an internal clock from a combination of internal signals within the device.
Eight GLBs, 16 I/O cells, two dedicated inputs and one ORP are connected together to make a Megablock (see Figure 1). The outputs of the eight GLBs are connected to a set of 16 universal I/O cells by the ORP. Each ispLSI 1016E device contains two Megablocks.
SI
2
Y0 Y1/RESET* SCLK/Y2
D ES IG N
GOE 0/IN 3 MODE/IN 2 I/O 31 I/O 30 I/O 29 I/O 28 I/O 27 I/O 26 I/O 25 I/O 24 I/O 23 I/O 22 I/O 21 I/O 20 I/O 19 I/O 18 I/O 17 I/O 16
CLK 0 CLK 1 CLK 2 IOCLK 0 IOCLK 1
Generic Logic Blocks (GLBs)
0139B(1a)-isp
S
Specifications ispLSI 1016E
Absolute Maximum Ratings 1
Supply Voltage VCC ................................. -0.5 to +7.0V Input Voltage Applied ........................ -2.5 to VCC +1.0V Off-State Output Voltage Applied ..... -2.5 to VCC +1.0V Storage Temperature ................................ -65 to 150C
Max. Junction Temp. (TJ) with Power Applied ... 150C
1. Stresses above those listed under the "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specification is not implied (while programming, follow the programming specifications).
DC Recommended Operating Conditions
SYMBOL PARAMETER Supply Voltage Input Low Voltage Input High Voltage Commercial Industrial
EW
D ES IG N
MIN. 4.75 4.5 0 2.0 MAX. 5.25 5.5 0.8 Vcc+1
Case Temp. with Power Applied .............. -55 to 125C
VCC VIL VIH
TA = 0C to + 70C
N
TA = -40C to + 85C
R
Capacitance (TA=25oC, f=1.0 MHz)
SYMBOL PARAMETER
EA
FO
Table 2-0005/1016E
TYPICAL 8 12
UNITS pf pf
TEST CONDITIONS VCC = 5.0V, VPIN = 2.0V VCC = 5.0V, VPIN = 2.0V
Table 2-0006/1016E
C1 C2
Y0 Clock Capacitance
Data Retention Specifications
PARAMETER Erase/Reprogram Cycles
SI
10
16
Dedicated Input, I/O, Y1, Y2, Y3, Clock Capacitance (Commercial/Industrial)
MINIMUM 20 10000
MAXIMUM - -
UNITS Years Cycles
Table 2-0008/1016E
U SE
is pL
Data Retention
3
S
UNITS V V V V
Specifications ispLSI 1016E
Switching Test Conditions
Input Pulse Levels Input Rise and Fall Time 10% to 90% Input Timing Reference Levels Output Timing Reference Levels Output Load 3-state levels are measured 0.5V from steady-state active level. GND to 3.0V -125 -100, -80 1.5V 1.5V See Figure 2
Table 2-0003/1016E
Figure 2. Test Load
2 ns 3 ns
+ 5V R1
Output Load Conditions (see Figure 2)
TEST CONDITION A B Active High Active Low Active High to Z at VOH -0.5V Active Low to Z at VOL +0.5V R1 470 470 470 R2 390 390 390 390 390 CL 35pF 35pF 35pF 5pF 5pF
*CL includes Test Fixture and Probe Capacitance.
DC Electrical Characteristics
SYMBOL PARAMETER Output Low Voltage Output High Voltage Input or I/O Low Leakage Current
Over Recommended Operating Conditions
FO
R
Table 2-0004/1016E
N
C
EW
Output Short Circuit Current Operating Power Supply Current
SI
VOL VOH IIL IIH IIL-isp IIL-PU IOS1 ICC2, 4
EA
CONDITION
IOL= 8 mA IOH = -4 mA 0V VIN VIL (Max.) 3.5V VIN VCC 0V VIN VIL 0V VIN VIL VCC = 5V, VOUT = 0.5V VIL = 0.5V, VIH = 3.0V fCLOCK = 1 MHz Commercial Industrial
D ES IG N
R2 CL*
MIN. - 2.4 - - - - - - - TYP. - - - - - - - 90 90
3
Device Output
MAX. UNITS 0.4 - -10 10 -150 -150 -200 - - V V A A A A mA mA mA
ispEN Input Low Leakage Current I/O Active Pull-Up Current
is pL
10
Input or I/O High Leakage Current
16
Table 2-0007/1016E
U SE
1. One output at a time for a maximum duration of one second. VOUT = 0.5V was selected to avoid test problems by tester ground degradation. Characterized but not 100% tested. 2. Measured using four 16-bit counters. 3. Typical values are at VCC = 5V and TA= 25C. 4. Maximum I CC varies widely with specific device configuration and operating frequency. Refer to the Power Consumption section of this data sheet and Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM to estimate maximum ICC .
4
S
Test Point
0213a
Specifications ispLSI 1016E
External Timing Parameters
Over Recommended Operating Conditions
PARAMETER TEST 2 # COND. A A A - - - A - - - - A - B C B C - - - -
4
DESCRIPTION
1
-125 - - 125
1 tsu2 + tco1
-100 - - 100 77.0 125 7.0 - 0.0 8.0 - 0.0 - 6.5 - - - - 4.0 4.0 3.5 0.0 10.0 13.0 - - - - -
-80 UNITS ns ns MHz MHz MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 15.0 18.5 - - - - - -
MIN. MAX. MIN. MAX. MIN. MAX. 7.5 10.0 - - - - 4.5 - - 5.5 - -
EA
tpd1 tpd2 fmax fmax (Ext.) fmax (Tog.) tsu1 tco1 th1 tsu2 tco2 th2 tr1 trw1 tptoeen tptoedis tgoeen tgoedis twh twl tsu3 th3
1. 2. 3. 4.
1 Data Prop. Delay, 4PT Bypass, ORP Bypass 2 Data Prop. Delay, Worst Case Path 3 Clk. Frequency with Int. Feedback 5 Clk. Frequency, Max. Toggle(
3
84.0 57.0 100 8.5 -
4 Clk. Frequency with Ext. Feedback(
)
100 167 5.0 - 0.0 5.5 - 0.0 -
1 twh + tw1
)
6 GLB Reg. Setup Time before Clk., 4 PT Bypass 7 GLB Reg. Clk. to Output Delay, ORP Bypass 8 GLB Reg. Hold Time after Clk., 4 PT Bypass 9 GLB Reg. Setup Time before Clk. 10 GLB Reg. Clk. to Output Delay 11 GLB Reg. Hold Time after Clk. 12 Ext. Reset Pin to Output Delay 13 Ext. Reset Pulse Duration 14 Input to Output Enable 15 Input to Output Disable 16 Global OE Output Enable 17 Global OE Output Disable
EW
10.0 12.0 12.0 7.0 7.0 - - - -
N
5.0 - - - -
R
FO
18 Ext. Sync. Clk. Pulse Duration, High 19 Ext. Sync. Clk. Pulse Duration, Low
3.0 3.0 0.0
20 I/O Reg. Setup Time before Ext. Sync. Clk. (Y2, Y3) 3.0 21 I/O Reg. Hold Time after Ext. Sync. Clk. (Y2, Y3)
16
U SE
is pL
SI
10
Unless noted otherwise, all parameters use the GRP, 20 PTXOR path, ORP and Y0 clock. Refer to Timing Model in this data sheet for further details. Standard 16-bit counter using GRP feedback. Reference Switching Test Conditions Section.
5
D ES IG N
- 5.0 - - - 13.5 - 15.0 15.0 9.0 9.0 - - - - 8.0 0.0 - 9.5 6.0 9.5 - 17.0 - 20.0 20.0 10.5 10.5 - - - - 0.0 - 10.0 - - - - 5.0 5.0 4.5 0.0
Table 2-0030-16/125,100, 80
S
Specifications ispLSI 1016E
Internal Timing Parameters1
PARAMETER #
2
DESCRIPTION
-125
-100
-80
MIN. MAX. MIN. MAX. MIN. MAX. - - 3.0 -0.3 - - - - - - - 0.3 1.8 - - 4.0 4.0 2.2 1.8 1.9 2.1 2.4 - - 3.5 - - - -0.4 0.4 2.4 - - - - 4.5 -0.6 - - - - 0.6 3.6 - -
UNITS
Inputs
25 I/O Register Hold Time after Clock 26 I/O Register Clock to Out Delay 27 I/O Register Reset to Out Delay 28 Dedicated Input Delay 29 GRP Delay, 1 GLB Load 30 GRP Delay, 4 GLB Loads 31 GRP Delay, 8 GLB Loads 32 GRP Delay, 16 GLB Loads 34 4 Product Term Bypass Path Delay (Combinatorial) 35 4 Product Term Bypass Path Delay (Registered) 36 1 Product Term/XOR Path Delay 37 20 Product Term/XOR Path Delay 38 XOR Adjacent Path Delay 3 39 GLB Register Bypass Delay
D ES IG N
5.0 5.0 2.6 7.5 7.5 3.9 - 1.9 2.9 - - - - - - - - - 0.2 2.5 - - - - 4.8 - - 2.2 2.5 3.1 5.7 5.6 6.1 6.1 6.6 1.6 - - 1.9 6.3 5.1 7.1 5.3 1.0 0.0 - - - - - - - - - -0.6 4.3 - - - - 6.8 - - 3.3 3.8 4.7 8.1 7.3 7.1 8.2 8.3 1.9 - - 2.9 7.0 7.2 9.7 7.5 1.5 0.0
tiobp tiolat tiosu tioh tioco tior tdin
GRP
22 I/O Register Bypass 23 I/O Latch Delay 24 I/O Register Setup Time before Clock
ns ns ns
EW
tgrp1 tgrp4 tgrp8 tgrp16
GLB
46 GLB Product Term Clock Delay
SI
t4ptbpc t4ptbpr t1ptxor t20ptxor txoradj tgbp tgsu tgh tgco tgro tptre tptoe tptck
ORP
N
- - - - - -
3.9 3.9 4.4 4.4 4.4 1.0 - - 1.8 4.4 3.5 5.5 3.5 1.0 0.0
R
FO
EA
40 GLB Register Setup Time before Clock 42 GLB Register Clock to Output Delay 43 GLB Register Reset to Output Delay 44 GLB Product Term Reset to Register Delay 45 GLB Product Term Output Enable to I/O Cell Delay
0.2 1.5 - - - - 3.2 - -
16
41 GLB Register Hold Time after Clock
10
torp torpbp
is pL
47 ORP Delay 48 ORP Bypass Delay
U SE
1. Internal Timing Parameters are not tested and are for reference only. 2. Refer to Timing Model in this data sheet for further details. 3. The XOR Adjacent path can only be used by Lattice hard macros.
Table 2-0036-16/125,100, 80
6
S
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Specifications ispLSI 1016E
Internal Timing Parameters1
PARAMETER #2 DESCRIPTION -125 -100 -80 UNITS
MIN. MAX. MIN. MAX. MIN. MAX. - - - - - 1.4 10.0 4.3 4.3 2.7 - - - - 1.7 10.0 5.3 5.3 - - - - - 3.0 10.0 6.4 6.4 4.1 2.1 4.4 2.7 0.6 2.7 5.5
Outputs
52 I/O Cell OE to Output Disabled 53 Global Output Enable 54 Clock Delay, Y0 to Global GLB Clock Line (Ref. clock) 55 Clock Delay, Y1 or Y2 to Global GLB Clock Line 56 Clock Delay, Clock GLB to Global GLB Clock Line 57 Clock Delay, Y1 or Y2 to I/O Cell Global Clock Line 58 Clock Delay, Clock GLB to I/O Cell Global Clock Line 59 Global Reset to GLB and I/O Registers
D ES IG N
- 3.7 1.4 2.4 0.8 0.0 0.8 - 1.4 2.9 1.8 0.4 1.8 4.5 2.1 3.6 1.2 0.0 1.2 -
tob tsl toen todis tgoe
Clocks
49 Output Buffer Delay 50 Output Slew Limited Delay Adder 51 I/O Cell OE to Output Enabled
ns ns ns ns ns ns ns ns ns ns ns
Global Reset
N
tgr
EW
tgy0 tgy1/2 tgcp tioy1/2 tiocp
1.3 2.3 0.8 0.0 0.8 -
1.3 2.7 1.8 0.3 1.8
3.2
U SE
is pL
SI
10
16
EA
FO
7
R
1. Internal Timing Parameters are not tested and are for reference only. 2. Refer to Timing Model in this data sheet for further details.
Table 2-0037-16/125,100,80
S
Specifications ispLSI 1016E
ispLSI 1016E Timing Model
I/O Cell GRP Feedback Ded. In Comb 4 PT Bypass #34 Reg 4 PT Bypass #30 GRP Loading Delay #29, 31, 32 #35 20 PT XOR Delays #36-38 #59 D RST Reset #40-43 GLB Reg Bypass #39 GLB Reg Delay Q ORP Bypass #48 ORP Delay #47 #49, 50 #51, 52 I/O Pin (Output) GLB ORP I/O Cell
#28 I/O Reg Bypass #22 Input D Register Q RST #23 - 27
#59
Clock Distribution Y1,2 #55-58
Control RE PTs OE #44-46 CK
Y0 GOE 0
EW
#54 #53
Derivations of tsu, th and tco from the Product Term Clock 1
th
tsu
th
U SE
tco
is pL
= = = 2.9 ns =
Logic + Reg su - Clock (min) (tiobp + tgrp4 + t20ptxor) + (tgsu) - (tgy0(min) + tgco + tgcp(min)) (#22 + #30 + #37) + (#40) - (#54 + #42 + #56) (0.3 + 1.9 + 4.4) + (0.2) - (1.3 + 1.8 + 0.8)
= = = -0.2 ns = = = = 9.1 ns =
Clock (max) + Reg h - Logic (tgy0(max) + tgco + tgcp(max)) + (tgh) - (tiobp + tgrp4 + t20ptxor) (#54 + #42 + #56) + (#41) - (#22 + #30 + #37) (1.3 + 1.8 + 1.8) + (1.5) - (0.3 + 1.9 + 4.4) Clock (max) + Reg co + Output (tgy0(max) + tgco + tgcp(max)) + (tgco) + (torp + tob) (#54 + #42 + #56) + (#42) + (#47 + #49) (1.3 + 1.8 + 1.8) + (1.8) + (1.0 + 1.4)
Table 2-0042-16
1. Calculations are based upon timing specifications for the ispLSI 1016E-125
SI
Derivations of tsu, th and tco from the Clock GLB 1
10
= = = 9.9 ns =
Clock (max) + Reg co + Output (tiobp + tgrp4 + tptck(max)) + (tgco) + (torp + tob) (#22 + #30 + #46) + (#42) + (#47 + #49) (0.3 + 1.9 + 3.5) + (1.8) + (1.0 + 1.4)
16
tco
EA
= = = 0.6 ns =
Clock (max) + Reg h - Logic (tiobp + tgrp4 + tptck(max)) + (tgh) - (tiobp + tgrp4 + t20ptxor) (#22 + #30 + #46) + (#41) - (#22 + #30 + #37) (0.3 + 1.9 + 3.5) + (1.5) - (0.3 + 1.9 + 4.4)
FO
8
R
tsu
= = = 1.4 ns =
Logic + Reg su - Clock (min) (tiobp + tgrp4 + t20ptxor) + (tgsu) - (tiobp + tgrp4 + tptck(min)) (#22 + #30 + #37) + (#40) - (#22 + #30 + #46) (0.3 + 1.9 + 4.4) + (0.2) - (0.3 + 1.9 + 3.2)
N
D ES IG N
0491-16
S
I/O Pin (Input)
Specifications ispLSI 1016E
Maximum GRP Delay vs GLB Loads
3 ispLSI 1016E-80 ispLSI 1016E-100
GRP Delay (ns)
2
1
1
4
8
GLB Load
12
16
16E GRP/GLB.eps
Power Consumption
Power consumption in the ispLSI 1016E device depends on two primary factors: the speed at which the device is operating and the number of Product Terms used. Figure 3. Typical Device Power Consumption vs fmax
130 120 110
Figure 3 shows the relationship between power and operating speed.
ICC (mA)
100 90 80
10
16
0
20
EA
40
FO
ispLSI 1016E
60
80
SI
fmax (MHz)
Notes: Configuration of four 16-bit counters Typical current at 5V, 25C
ICC can be estimated for the ispLSI 1016E using the following equation: ICC(mA) = 23 + (# of PTs * 0.52) + (# of nets * max freq * 0.004)
U SE
Where: # of PTs = Number of product terms used in design # of nets = Number of signals used in device Max freq = Highest clock frequency to the device (in MHz) The ICC estimate is based on typical conditions (VCC = 5.0V, room temperature) and an assumption of four GLB loads on average exists and the device is filled with four 16-bit counters. These values are for estimates only. Since the value of ICC is sensitive to operating conditions and the program in the device, the actual ICC should be verified.
0127B-16-80-isp/1016
is pL
9
R
100 120 140
N
EW
D ES IG N
S
ispLSI 1016E-125
Specifications ispLSI 1016E
Pin Description
NAME
I/O 0 - I/O 3 I/O 4 - I/O 7 I/O 8 - I/O 11 I/O 12 - I/O 15 I/O 16 - I/O 19 I/O 20 - I/O 23 I/O 24 - I/O 27 I/O 28 - I/O 31
PLCC PIN NUMBERS 15, 19, 25, 29, 37, 41, 3, 7, 2 13 16, 20, 26, 30, 38, 42, 4, 8, 17, 21, 27, 31, 39, 43, 5, 9, 18, 22, 28, 32, 40, 44, 6, 10
TQFP PIN NUMBERS 9, 13, 19, 23, 31, 35, 41, 1, 40 7 10, 14, 20, 24, 32, 36, 42, 2, 11, 15, 21, 25, 33, 37, 43, 3, 12, 16, 22, 26, 34, 38, 44, 4
DESCRIPTION
Input/Output Pins - These are the general purpose I/O pins used by the logic array.
GOE 0/IN 32 ispEN
This is a dual function pin. It can be used either as Global Output Enable for all I/O cells or it can be used as a dedicated input pin. Input - Dedicated in-system programming enable input pin. This pin is brought low to enable the programming mode. The MODE, SDI, SDO and SCLK controls become active. Input - This pin performs two functions. When ispEN is logic low, it functions as an input pin to load programming data into the device. It is a dedicated input pin when ispEN is logic high.SDI/IN0 also is used as one of the two control pins for the isp state machine. Input - This pin performs two functions. When ispEN is logic low, it functions as a pin to control the operation of the isp state machine. It is a dedicated input pin when ispEN is logic high.
SDI/IN 01
14
8
MODE/IN 21
36
30
SDO/IN 11
24
18
Y0 Y1/RESET
11 35
5 29
GND VCC
1,
23
10
17, 39 6, 28
16
12, 34
SI
EA
Dedicated Clock input. This clock input is connected to one of the clock inputs of all the GLBs on the device. This pin performs two functions: - Dedicated clock input. This clock input is brought into the Clock Distribution Network, and can optionally be routed to any GLB and/or I/O cell on the device. - Active Low (0) Reset pin which resets all of the GLB and I/O registers in the device. Ground (GND) Vcc
Table 2-0002C-16-isp
U SE
is pL
1. Pins have dual function capability. 2. Pins have dual function capability which is software selectable.
FO
10
R
SCLK/Y21
33
27
Input - This pin performs two functions. When ispEN is logic low, it functions as a clock pin for the Serial Shift Register. It is a dedicated clock input when ispEN is logic high. This clock input is brought into the Clock Distribution Network, and can optionally be routed to any GLB and/or I/O cell on the device.
N
Output/Input - This pin performs two functions. When ispEN is logic low, it functions as an output pin to read serial shift register data. It is a dedicated input pin when ispEN is logic high.
EW
D ES IG N
S
Specifications ispLSI 1016E
Pin Configurations
ispLSI 1016E 44-Pin PLCC Pinout Diagram
GOE 0/IN 32
I/O 27
I/O 26 I/O 25
I/O 24
GND I/O 23
I/O 22
I/O 29 I/O 30 I/O 31 Y0 VCC ispEN
1
9 10 11 12 13 14 15 16 17
38 37 36 35 34 33 32 31 30 29
I/O 17 I/O 16
MODE/IN 21 Y1/RESET VCC SCLK/Y21 I/O 15 I/O 14 I/O 13 I/O 12
ispLSI 1016E
Top View
SDI/IN 0 I/O 0 I/O 1 I/O 2
18 19 20 21 22 23 24 25 26 27 28
GND
I/O 3
I/O 4 I/O 5
I/O 6
I/O 7
1
I/O 8
FO
1. Pins have dual function capability. 2. Pins have dual function capability which is software selectable.
0123A-isp1016
ispLSI 1016E 44-Pin TQFP Pinout Diagram
16
GOE 0/IN 32
I/O 27
I/O 26 I/O 25
I/O 24
EA
GND I/O 23
I/O 22
10
44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 I/O 18 I/O 17 I/O 16 MODE/IN 21 Y1/RESET VCC SCLK/Y21 I/O 15 I/O 14 I/O 13 I/O 12
I/O 28 I/O 29 I/O 30 I/O 31 Y0 VCC ispEN
SI
1 2 3 4 5 6 7 8
is pL
I/O 21 I/O 20 I/O 19
R
1SDO/IN
ispLSI 1016E
Top View
1SDI/IN
0
U SE
I/O 0 I/O 1 I/O 2
9 10 11 12 13 14 15 16 17 18 19 20 21 22
GND 1
I/O 8
1. Pins have dual function capability. 2. Pins have dual function capability which is software selectable.
0851-16E/TQFP
11
1SDO/IN
I/O 9 I/O 10 I/O 11
I/O 3
I/O 4 I/O 5
I/O 6
I/O 7
N
I/O 9 I/O 10 I/O 11
EW
29 28 27 26 25 24 23
D ES IG N
I/O 28
7 8
39
I/O 18
S
6 5 4 3 2 1 44 43 42 41 40
I/O 21 I/O 20 I/O 19
Specifications ispLSI 1016E
Part Number Description
ispLSI 1016E - XXX
Device Family Device Number Speed 125 = 125 MHz fmax 100 = 100 MHz fmax 80 = 84 MHz fmax Package J = PLCC T44 = TQFP JN = Lead-Free PLCC TN44 = Lead-Free TQFP Power L = Low
X
XXX
X Grade Blank = Commercial I = Industrial
ispLSI 1016E Ordering Information Conventional Packaging
COMMERCIAL
FAMILY fmax (MHz) 125 125 ispLSI 100 100 84 84 tpd (ns) 7.5 7.5 10 10 15 15
N
ORDERING NUMBER ispLSI 1016E-125LJ ispLSI 1016E-100LJ ispLSI 1016E-80LJ
EW
R
ispLSI 1016E-125LT44
FO
ispLSI 1016E-100LT44 ispLSI 1016E-80LT44
FAMILY ispLSI
fmax (MHz) 84 84
16
EA
INDUSTRIAL
ORDERING NUMBER ispLSI 1016E-80LJI ispLSI 1016E-80LT44I PACKAGE 44-Pin PLCC 44-Pin TQFP
tpd (ns) 15 15
SI
Lead-Free Packaging
FAMILY fmax (MHz) 125 125 100 84 84
10
COMMERCIAL
ORDERING NUMBER ispLSI 1016E-125LJN ispLSI 1016E-125LTN44 ispLSI 1016E-100LJN ispLSI 1016E-100LTN44 ispLSI 1016E-80LJN ispLSI 1016E-80LTN44 PACKAGE Lead-Free 44-Pin PLCC Lead-Free 44-Pin TQFP Lead-Free 44-Pin PLCC Lead-Free 44-Pin TQFP Lead-Free 44-Pin PLCC Lead-Free 44-Pin TQFP 7.5 7.5 10 10 15 15
ispLSI
U SE
is pL
tpd (ns)
100
INDUSTRIAL
fmax (MHz) 84 84 tpd (ns) 15 15 ORDERING NUMBER ispLSI 1016E-80LJNI ispLSI 1016E-80LTN44I PACKAGE Lead-Free 44-Pin PLCC Lead-Free 44-Pin TQFP
FAMILY ispLSI
12
D ES IG N
PACKAGE 44-Pin PLCC 44-Pin TQFP 44-Pin PLCC 44-Pin TQFP 44-Pin PLCC 44-Pin TQFP
S
Specifications ispLSI 1016E
Revision History
Date -- August 2006 Version 08 09 Previous Lattice release. Updated for lead-free package options. Change Summary
U SE
is pL
SI
10
16
EA
FO
13
R
N
EW
D ES IG N
S

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