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| Product Specification PE42552 Product Description The PE42552 RF Switch is designed for use in Test/ATE, cellular and other wireless applications. This broadband general purpose switch maintains excellent RF performance and linearity from DC through 7500 MHz. The PE42552 integrates on-board CMOS control logic driven by a single-pin, low voltage CMOS control input. It also has a logic select pin which enables changing the logic definition of the control pin. Additional features include a novel user defined logic table, enabled by the on-board CMOS circuitry. The PE42552 also exhibits outstanding isolation of 44 dB at 7500 MHz, fast settling time, and is offered in a tiny 3x3 mm QFN package. The PE42552 is manufactured on Peregrine's UltraCMOSTM process, a patented variation of silicon-on-insulator (SOI) technology on a sapphire substrate, offering the performance of GaAs with the economy and integration of conventional CMOS. Figure 1. Functional Diagram RFC RF1 ESD SPDT UltraCMOSTM RF Switch DC - 7500 MHz Features * * * * * * * * * HaRPTM-Technology-Enhanced * Eliminates Gate and Phase Lag * No insertion loss or phase drift * Fast settling time High linearity: 65 dBm IIP3 Low insertion loss: 0.65 dB at 3.0 GHz, 0.85 dB at 6.0 GHz, 1.0 at 7.5 GHz High isolation of 47 dB at 3.0 GHz, 44 dB at 7.5 GHz 1 dB compression point: +34.5 dBm typ. Logic Select pin to invert logic control High ESD: 1000 V HBM Absorptive switch design Standard 3x3 mm QFN package Figure 2. Package Type 16-lead 3x3 mm QFN ESD RF2 50 CMOS Control Driver 50 LS CTRL Table 1. Target Electrical Specifications Temp = 25C, VDD = 3.3V, VSS = 0V / -3.3V Parameter Operation Frequency MHz Insertion Loss 9 KHz 3000 MHz 6000 MHz 7500 MHz 3000 MHz 6000 MHz 7500 MHz 3000 MHz 6000 MHz 7500 MHz 3000 MHz 6000 MHz 7500 MHz 50% CTRL to 0.05 dB final value (-40 to +85 C) Rising Edge 50% CTRL to 0.05 dB final value (-40 to +85 C) Falling Edge 50% CTRL to 90% or 10% of final value (-40 to +85 C) 800 MHz 7500 MHz 7500 MHz 7500 MHz 45 32 25 44 49 37 Conditions Min 9 kHz Typical 0.6 0.65 0.85 1.0 47 34 28 47 55 44 20 25 15 9 15 5 34.5 34 65 100 Max 7.5 GHz 0.7 0.8 1.0 1.22 Units dB dB dB dB dB dB dB dB dB dB dB dB dB Isolation - RF1 to RF2 Isolation - RFC to RFX Return Loss Settling Time Switching Time Input 1 dB Compression Input IP3 Input IP2 11 45 7 32 s s s dBm dBm dBm dBm Document No. 70-0246-03 www.psemi.com (c)2008 Peregrine Semiconductor Corp. All rights reserved. Page 1 of 9 PE42552 Product Specification Figure 3. Pin Configuration (Top View) CTRL Vdd Vss LS Table 4. Absolute Maximum Ratings Symbol VDD VI Parameter/Conditions Power supply voltage Voltage on any input except for CTRL and LS inputs Voltage on CTRL input Voltage on LS input Storage temperature range Input Power: 9 kHz 1 MHz 1 MHz 7.5 GHz ESD voltage (HBM)1 ESD voltage (Machine Model) Min -0.3 -0.3 Max 4.0 VDD+ 0.3 4.0 4.0 150 fig. 4,5 30 1000 100 Units V V V V C dBm dBm V V 16 15 14 GND RF1 GND GND 13 1 2 3 4 12 11 10 9 GND RF2 GND GND VCTRL VLS TST PIN VESD -65 5 6 7 GND GND GND RFC 8 Note: 1. Human Body Model (HBM, MIL_STD 883 Method 3015.7) Table 2. Pin Descriptions Pin No. 2 1, 3, 4, 5, 6, 8, 9, 10, 12 7 11 13 14 15 16 Pin Name RF1 GND RFC RF2 VSS CTRL LS VDD RF Port 1 Ground Description Exceeding absolute maximum ratings may cause permanent damage. Operation should be restricted to the limits in the Operating Ranges table. Operation between operating range maximum and absolute maximum for extended periods may reduce reliability. RF Common RF Port 2 Negative supply voltage or GND connection (Note 1) CMOS level: Logic Select - Used to determine the definition for the CTRL pin (see Table 5) Nominal 3.3 V supply connection Electrostatic Discharge (ESD) Precautions When handling this UltraCMOSTM device, observe the same precautions that you would use with other ESDsensitive devices. Although this device contains circuitry to protect it from damage due to ESD, precautions should be taken to avoid exceeding the rating specified. Latch-Up Avoidance Unlike conventional CMOS devices, UltraCMOSTM devices are immune to latch-up. Note: 1. Use VSS (pin 13, VSS = -VDD) to bypass and disable internal negative voltage generator. Connect VSS (pin 13) to GND (VSS = 0V) to enable internal negative voltage generator. Table 3. Operating Ranges Parameter VDD Positive Power Supply Voltage VSS Negative Power Supply Voltage (external power supply used) VSS Negative Power Supply Voltage (internal power supply used) IDD Power Supply Current (VSS = 0V, Temp = +85 C) ISS Negative Supply (VSS = -VDD, Temp = 25 C) Control Voltage High Control Voltage Low TOP Operating temperature range RF Power In (PIN): 1 Table 5. Control Logic Truth Table Min 3.0 -3.6 -0.1 Typ 3.3 -3.3 0.0 15 -10 Max 3.6 -3.0 0.0 120 -40 Units V V V A A V V C dBm dBm LS 0 0 1 1 CTRL 0 1 0 1 RFC-RF1 off on on off RFC-RF2 on off off on Logic Select (LS) The Logic Select feature is used to determine the definition for the CTRL pin. 0.7xVDD 0.3xVDD -40 25 85 fig. 4,5 30 Spurious Performance The typical spurious performance of the PE42552 is -116 dBm when VSS=0V (pin 13 = GND). If further improvement is desired, the internal negative voltage generator can be disabled by setting VSS = -VDD. 9 kHz 1 MHz 1 MHz 7.5 GHz Switching Frequency The PE42552 has a maximum 25 kHz switching rate when the internal negative voltage generator is used (pin 13=GND). The rate at which the PE42552 can be switched is only limited to the switching time (Table 1) if an external negative supply is provided at (pin13=VSS). Document No. 70-0246-03 UltraCMOSTM RFIC Solutions Note: 1. Please consult low frequency graphs on page 3 for recommended operating power level. Moisture Sensitivity Level The Moisture Sensitivity Level rating for the PE42552 in the 16-lead 3x3mm QFN package is MSL1. (c)2008 Peregrine Semiconductor Corp. All rights reserved. Page 2 of 9 PE42552 Product Specification Low Frequency Power Handling: ZL = 50 Figure 4 provides guidelines of how to adjust the Vdd and input Power to the 42552 device. The upper limit curve represents the maximum Input Power vs Vdd recommended for this part. Figure 5 shows how the power limit in Figure 4 will increase with frequency. As the frequency increases, the contours and Maximum Power Limit Curve will increase with the increase in power handling shown on the curve. Figure 4. Maximum Operating Power Limit vs. Vdd and Input Power @ 9 KHz Upper Power Limit 8 6 4 Input Power (dBm) 2 0 -2 -4 -6 -8 -10 -12 2.9 3 3.1 3.2 3.3 3.4 3.5 3.6 Vdd (V) Figure 5. Operating Power Offset vs. Frequency (Normalized to 9kHz) 30 Operating Power Offset (dB) 25 20 15 10 5 0 1 10 100 1000 Freq (kHz) Power Handling Examples Example 1: Maximum power handling at 100kHz, Z=50 ohms, VSWR 1:1, and Vdd=3V * The power handling offset for 100kHz from Fig. 5 is 10dB * The max power handling at Vdd = 3V is 5.5dB from Fig. 4 * Derate power under mismatch conditions * Total maximum power handling for this example is 10dB + 5.5dB = 15.5dBm To allow for sustained operation under any load VSWR condition, max power should be kept 6dB lower than max power in 50 Ohm. Document No. 70-0246-03 www.psemi.com (c)2008 Peregrine Semiconductor Corp. All rights reserved. Page 3 of 9 PE42552 Product Specification Performance Plots: Temperature = 25 C, VDD = 3.3 V unless otherwise indicated Figure 6. Nominal Insertion Loss: RF1, RF2 0 -0.2 -0.4 Insertion Loss [-dB] Insertion Loss [-dB] Figure 7. Insertion Loss: RFX @ 3.3 V 0 -0.2 -0.4 -0.6 -0.8 -1 -1.2 -1.4 -1.6 -1.8 -2 +25deg C +85deg C -40deg C -0.6 -0.8 -1 -1.2 -1.4 -1.6 -1.8 -2 0 1 2 3 4 5 6 7 8 9 Frequency [GHz] RF1 Path RF2 Path 0 1 2 3 4 5 6 7 8 9 Frequency [GHz] Figure 8. Insertion Loss: RFX @ 25 C 0 -0.2 -0.4 Insertion Loss [-dB] Figure 9. Isolation: Active Port to Isolated Port @ 3.3 V 0 -10 -20 Isolation [-dB] -30 -40 -50 -60 -70 -80 -90 +25deg C +85deg C -40deg C -0.6 -0.8 -1 -1.2 -1.4 -1.6 -1.8 -2 0 1 2 3 4 5 6 7 8 9 Frequency [GHz] 3.0 V 3.3 V 3.6 V -100 0 1 2 3 4 5 6 7 8 9 Frequency [GHz] Figure 10. Isolation: Active Port to Isolated Port @ 25 C 0 -10 -20 Isolation [-dB] -30 -40 -50 -60 -70 -80 -90 -100 0 1 2 3 4 5 6 7 8 9 Frequency [GHz] 3.0 V 3.3 V Figure 11. Isolation: RFC to Isolated Port @ 3.3 V 0 -10 -20 Isolation [-dB] -30 -40 -50 -60 -70 -80 -90 -100 0 1 2 3 4 5 6 7 8 9 Frequency [GHz] +25deg C +85deg C -40deg C 3.6 V (c)2008 Peregrine Semiconductor Corp. All rights reserved. Page 4 of 9 Document No. 70-0246-03 UltraCMOSTM RFIC Solutions PE42552 Product Specification Performance Plots: Temperature = 25 C, VDD = 3.3 V unless otherwise indicated Figure 12. Isolation: RFC to Isolated Port @ 25 C 0 -10 -20 Isolation [-dB] -30 -40 -50 -60 -70 -80 -90 -100 0 1 2 3 4 5 6 7 8 9 Frequency [GHz] 3.0 V 3.3 V 3.6 V Figure 13. IIP3: Third Order Distortion from 10kHz - 7.5GHz 70 60 3.0 V 50 IIP3 [dBm] 40 30 20 10 0 1.E+04 1.E+05 1.E+06 1.E+07 1.E+08 1.E+09 3.3 V 3.6 V 1.E+10 Frequency [Hz] Figure 14. Return Loss at active port @ 25 C 0 -5 Return Loss [-dB] -10 -15 -20 -25 -30 -35 0 1 2 3 4 5 6 7 8 9 Frequency [GHz] 3.0 V Figure 15. Return Loss at active port @ 3.3 V 0 -5 Return Loss [-dB] -10 -15 -20 -25 -30 0 1 2 3 4 5 6 7 8 9 Frequency [GHz] +25deg C +85deg C -40deg C 3.3 V 3.6 V Document No. 70-0246-03 www.psemi.com (c)2008 Peregrine Semiconductor Corp. All rights reserved. Page 5 of 9 PE42552 Product Specification Evaluation Kit The SPDT switch EK Board was designed to ease customer evaluation of Peregrine's PE42552. The RF common port is connected through a 50 transmission line via the top SMA connector, J1. RF1, RF2, RF3 and RF4 are connected through 50 transmission lines via SMA connectors J3, J5, J2 and J4, respectively. A through 50 transmission is available via SMA connectors J6 and J7. This transmission line can be used to estimate the loss of the PCB over the environmental conditions being evaluated. The evaluation kit board is constructed of four metal layers. The dual clad top RF layer is Rogers RO4003 material with an 8 mil RF core and er = 3.55. The other two dielectric layers are FR4 for DC control and overall board strength with an cumulative board thickness of 60 mils. The RF transmission lines were designed using a Grounded co-planar waveguide with a linewidth of 15 mils and gap of 10 mils. Figure 16. Evaluation Board Layouts Peregrine Specification 101/0334 Figure 17. Evaluation Board Schematic Peregrine Specification 102/0404 J1 142-0761-881/891 2 1 8 7 RFC 6 GND GND 9 J2 142-0761-881/891 GND RFC 5 GND GND RF2 GND CTRL VDD VSS LS U1 QFN50P3X3-16P GND GND RF1 GND 4 3 2 1 RF1 J3 142-0761-881/891 10 RF2 1 2 11 12 1 2 13 14 15 J4 HEADER 14 R1 DNI DNI 2 4 6 8 10 12 14 2 4 6 8 10 12 14 1 3 5 7 9 11 13 1 3 5 7 9 11 13 CTRL LS VDD VSS R4 R3 DNI R2 16 L1 0 OHM 0 OHM C4 68pF C3 22pF C2 22pF L1 WAS INDUCTOR C1 22pF J5 142-0761-881/891 Through Line J6 142-0761-881/891 1 2 1 2 (c)2008 Peregrine Semiconductor Corp. All rights reserved. Page 6 of 9 Document No. 70-0246-03 UltraCMOSTM RFIC Solutions PE42552 Product Specification Figure 18. Package Drawing (mm) 16-lead 3x3 mm QFN QFN 3x3 mm MAX 0.800 0.750 0.700 A NOM MIN Document No. 70-0246-03 www.psemi.com (c)2008 Peregrine Semiconductor Corp. All rights reserved. Page 7 of 9 PE42552 Product Specification Figure 19. Tape and Reel Specifications 16-lead 3x3 mm QFN Tape Feed Direction Pin 1 Top of Device Device Orientation in Tape Table 6. Ordering Information Order Code Part Marking PE42552MLIB PE42552MLIB-Z EK42552-02 42552 42552 PE42552-EK Description PE42552G-16QFN 3x3mm-75A PE42552G-16QFN 3x3mm-3000C PE42552-16QFN 3x3mm-EK Package Green 16-lead 3x3mm QFN Green 16-lead 3x3mm QFN Evaluation Kit Shipping Method Bulk or tape cut from reel 3000 units / T&R 1 / Box (c)2008 Peregrine Semiconductor Corp. All rights reserved. Page 8 of 9 Document No. 70-0246-03 UltraCMOSTM RFIC Solutions PE42552 Product Specification Sales Offices The Americas Peregrine Semiconductor Corporation 9380 Carroll Park Drive San Diego, CA 92121 Tel: 858-731-9400 Fax: 858-731-9499 Peregrine Semiconductor, Asia Pacific (APAC) Shanghai, 200040, P.R. China Tel: +86-21-5836-8276 Fax: +86-21-5836-7652 Peregrine Semiconductor, Korea #B-2607, Kolon Tripolis, 210 Geumgok-dong, Bundang-gu, Seongnam-si Gyeonggi-do, 463-943 South Korea Tel: +82-31-728-3939 Fax: +82-31-728-3940 Europe Peregrine Semiconductor Europe Batiment Maine 13-15 rue des Quatre Vents F-92380 Garches, France Tel: +33-1-4741-9173 Fax : +33-1-4741-9173 Peregrine Semiconductor K.K., Japan Teikoku Hotel Tower 10B-6 1-1-1 Uchisaiwai-cho, Chiyoda-ku Tokyo 100-0011 Japan Tel: +81-3-3502-5211 Fax: +81-3-3502-5213 Hi-Rel and Defense Products Americas: Tel: 858-731-9453 Europe, Asia Pacific: 180 Rue Jean de Guiramand 13852 Aix-En-Provence Cedex 3, France Tel: +33-4-4239-3361 Fax: +33-4-4239-7227 For a list of representatives in your area, please refer to our Web site at: www.psemi.com Data Sheet Identification Advance Information The product is in a formative or design stage. The data sheet contains design target specifications for product development. Specifications and features may change in any manner without notice. The information in this data sheet is believed to be reliable. However, Peregrine assumes no liability for the use of this information. Use shall be entirely at the user's own risk. No patent rights or licenses to any circuits described in this data sheet are implied or granted to any third party. Peregrine's products are not designed or intended for use in devices or systems intended for surgical implant, or in other applications intended to support or sustain life, or in any application in which the failure of the Peregrine product could create a situation in which personal injury or death might occur. Peregrine assumes no liability for damages, including consequential or incidental damages, arising out of the use of its products in such applications. The Peregrine name, logo, and UTSi are registered trademarks and UltraCMOS, HaRP, MultiSwitch and DuNE are trademarks of Peregrine Semiconductor Corp. Preliminary Specification The data sheet contains preliminary data. Additional data may be added at a later date. Peregrine reserves the right to change specifications at any time without notice in order to supply the best possible product. Product Specification The data sheet contains final data. In the event Peregrine decides to change the specifications, Peregrine will notify customers of the intended changes by issuing a DCN (Document Change Notice). Document No. 70-0246-03 www.psemi.com (c)2008 Peregrine Semiconductor Corp. All rights reserved. Page 9 of 9 |
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