View HD151TS206SS_4853784.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

HD151TS206SS
Mother Board Clock Generator for Intel P4+ Chipset (Springdale)
REJ03D0005-0100Z Preliminary Rev.1.00 Apr.28.2003
Description
The HD151TS206SS is Intel CK409 type high-performance, low-skew, low-jitter, PC motherboard clock generator. It is specifically designed for Intel Pentium(R)4+ chipset.
Features
* * * * * * * * * * * 3 differential pairs of current mode control CPU clock 1 differential pairs of Serial Reference Clock (SRC) 6 PCI clocks and 3 PCIF clocks @3.3 V, 33.3 MHz typ. 1 copy of 48 MHz for USB @3.3 V 1 copy of 48 MHz for DOT @3.3 V 4 copies of 3V66 clock @3.3 V,66.6 MHz 1 copy of VCH@3.3 V, 48 MHz Power save and clock stop function. I2CTM serial port programming Programmable Clock Control (Spread Spectrum Percentage, Clock Output Skew, Slew Rate) 48pin SSOP (300 mils)
Note: I2C is a trademark of Philips Corporation. Pentium is registered trademark of Intel Corporation
Rev.1.00, Apr.28.2003, page 1 of 34
HD151TS206SS
Key Specifications
* * * * * Supply Voltages: VDD = 3.3 V5% CPU clock cycle to cycle jitter = |125ps| (SSC Disabled) CPU clock group Skew = 100ps 3V66 clock group Skew = 250psmax PCI clock group Skew = 500psmax
Rev.1.00, Apr.28.2003, page 2 of 34
HD151TS206SS
Pin Arrangement
**FS1/REF0 1 *FS0/REF1 2 VDD/REF 3 XTAL_IN 4 XTAL_OUT 5 VSS_REF 6 **FS2/PCIF_0 7 **FS4/PCIF_1 8 PCIF_2 9 VDD_PCI 10 VSS_PCI 11 **MODE/PCI_0 12 PCI_1 13 PCI_2 14 PCI_3 15 VDD_PCI 16 VSS_PCI 17 **SEL100_200/PCI_4 18 **SEL33_25/PCI_5 19 *PWRDWN#/SAFE_F 20 **SEL48_24/48_24MHz 21 **FS3/48MHz 22 VSS_48 23 VDD_48 24
48 AVDD 47 AVSS 46 IREF 45 CPU_2 44 CPU_2# 43 VSS_CPU 42 CPU_1 41 CPU_1# 40 VDD_CPU 39 CPU_0 38 CPU_0# 37 VSS_CPU 36 SRC 35 SRC# 34 VDD_SRC 33 *VTT_PWRGD# 32 *SDATA 31 *SCLK 30 3V66_0/RESET# 29 3V66_1 28 VSS_3V66 27 VDD_3V66 26 3V66_2 25 **SEL66_48/3V66_3/VCH
(Top view)
(*): (**):
Those pins are 150 k internal pulled-Up. Those pins are 150 k internal pulled-Down.
Rev.1.00, Apr.28.2003, page 3 of 34
HD151TS206SS
Pin Descriptions
Pin name AVSS VSS_CPU VSS_3V66 VSS_PCI VSS_REF VSS_48 AVDD VDD_CPU VDD_SRC VDD_3V66 VDD_PCI VDD_REF VDD_48 **FS1/REF0 *FS0/REF1 XTAL_IN XTAL_OUT No. 47 43,37 28 11,17 6 23 48 40 34 27 10,16 3 24 1 2 4 5 INPUT/OUTPUT INPUT/OUTPUT INPUT OUTPUT Frequency select latch input pin. 3.3 V 14.318 MHz reference clock. Frequency select latch input pin. 3.3 V 14.318 MHz reference clock. 14.318 MHz XTAL input. 14.318 MHz XTAL output. Don't connect when an external clock is applied at XTAL_IN. Frequency select latch input pin. Free running PCI clock 3.3 V output. 33 MHz clocks divided down from 3V66. Frequency select latch input pin. Free running PCI clock 3.3 V output. 33 MHz clocks divided down from 3V66. Free running PCI clock 3.3 V output. 33 MHz clocks divided down from 3V66. Function select latch input pin for pin 30, 1 = Reset#, 0 = clock output. / PCI clock 3.3 V output. 33 MHz clocks divided down from 3V66. PCI clock 3.3 V output. 33 MHz clocks divided down from 3V66. Power 3.3 V Power Supply for PLL 3.3 V Power Supply for outputs Type Ground Description Ground for PLL Ground for outputs
**FS2/PCIF_0
7,
INPUT/OUTPUT
**FS4/PCIF_1
8
INPUT/OUTPUT
PCIF_2 **MODE/PCI_0
9 12
OUTPUT INPUT/OUTPUT
PCI[1:5] Note: (*): (**):
13,14,15, OUTPUT 18,19
Those pins are 150 k internal pull-up. Those pins are 150 k internal pull-down
Rev.1.00, Apr.28.2003, page 4 of 34
HD151TS206SS
Pin Descriptions (cont.)
Pin name **SEL100_200/PCI_4 No. 18 Type INPUT/OUTPUT Description Latched select input for SRC output. 1 = 200 MHz, 0 = 100 MHz /PCI clock 3.3 V output. 33 MHz clock divided down from 3V66. Latched select input for PCI5 output. 1 = 25 MHz, 0 = 33 MHz /PCI clock 3.3 V output. 33 MHz clock divided down from 3V66. Power down pin. All circuits will be powered down. Asynchronous active low input pin used to power down the device into low power state. The internal clocks are disabled and VCO and the crystal are stopped. When Byte15 bit5 = 1 Safe frequency input select. Real time input for frequency jump. Driving this input 'LOW' will cause output to jump to predefined IIC frequency location. Latched select input for 48_24 MHz output 1 = 24 MHz, 0 = 48 MHz / 48_24 MHz clock 3.3 V output. Frequency select latch input pin. 3.3 V Fixed 48 MHz DOT clock output. Latched select input for 3V66/VCH output 1 = 48 MHz, 0 = 66.66 MHz. / 3V66 or VCH clock output. 3.3 V 66.66 MHz clock output. 3.3 V 66.66 MHz clock output / Real time system reset signal for frequency gear ratio change or watchdog timer timeout. This signal is active low and selected by Mode latch input. Clock input for I2C logic. Data input and output for I2C logic. Qualifying input that latches Frequency latch inputs. When this input is at a logic low, Frequency latched. "Complementary" clock of Differential Serial Reference Clock. "True" clock of Differential Serial Reference Clock. "True" clocks of differential pair CPU clock. "Complementary" clocks of differential pair CPU clock. A precision resistor is attached to this pin which is connected to internal current reference.
**SEL33_25/PCI_5
19
INPUT/OUTPUT
*PWRDWN# /SAFE_FREQ
20
INPUT
**SEL48_24/48_24MHz 21
INPUT/OUTPUT
**FS3/48MHz **SEL66_48 /3V66_3/VCH 3V66_2,3V66_1 3V66_0/RESET#
22 25
INPUT/OUTPUT INPUT/OUTPUT
26,29 30
OUTPUT OUTPUT
*SCLK *SDATA *VTT_PWRGD# SRC# SRC CPU[0:2] CPU#[0:2] IREF Note: (*): (**):
31 32 33 35 36 39,42, 45 38,41, 44 46
INPUT INPUT/OUTPUT INPUT OUTPUT OUTPUT OUTPUT OUTPUT INPUT
Those pins are 150 k internal pull-up. Those pins are 150 k internal pull-down
Rev.1.00, Apr.28.2003, page 5 of 34
HD151TS206SS
Block Diagram
3.3 V VDD_48 VSS_48 3.3 V AVDD AVSS 6x 3.3V VDD 6xVSS IREF
XTAL 14.318 MHz OSC
REF[1:0] (14.318MHz) CK2 1/M2 SSC2 1/N2 PLL2 For CPU VCO2 CPU[2:0] CPU[2:0]# SRC SRC# Clock Select 1/M1 SSC1 1/N1 PLL1 For SRC 3V66 PCI PCI[5:0] PCIF[2:0]
PWRDWN#/SAFE_F# Input Clock VTT_PWRGD# Select CK1
VCO1
Clock Divider
Delay Control Stop Control
3V66_0/RESET# 3V66[2:1] 3V66_3/VCH
*MODE *SEL100_200 *SEL66_48 *SEL48_24 *SEL33_25 *FS_4/3/2/1/0 SCLK SDATA
CK0
1/M0 1/N0
USB PLL
VCO0 48MHz 48_24MHz
Control Logic
(*) : Latched Input pin.
Rev.1.00, Apr.28.2003, page 6 of 34
HD151TS206SS
I2C Controlled Register Bit Map
Byte0 Control Register
Bit 7 6 5 4 3 2 1 0 Description Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Contents Type R R R R R R R R Default 0 0 0 0 1 1 X X Note
Byte1 Control Register
Bit 7 6 5 4 3 2 1 0 Description Reserved SRC Output enable Reserved Reserved Reserved CPU2 Output enable CPU1 Output enable CPU0 Output enable 0 = Disabled (tristate) 1 = Enabled 0 = Disabled (tristate) 1 = Enabled 0 = Disabled (tristate) 1 = Enabled 0 = Disabled (tristate) 1 = Enabled Contents Type RW RW RW RW RW RW RW RW Default 0 1 1 1 1 1 1 1 Note
Byte2 Control Register
Bit 7 6 5 4 3 2 1 0 Description SRC_Pwrdwn drive mode Reserved CPU2_Pwrdwn drive mode CPU1_Pwrdwn drive mode CPU0_Pwrdwn drive mode Reserved Reserved Reserved 0 = Driven in power down, 1 = Tristate 0 = Driven in power down, 1 = Tristate 0 = Driven in power down, 1 = Tristate Contents 0 = Driven in power down, 1 = Tristate Type RW RW RW RW RW RW RW RW Default 0 0 0 0 0 0 0 0 Note See Table 2 See Table 1
Rev.1.00, Apr.28.2003, page 7 of 34
HD151TS206SS
I2C Controlled Register Bit Map (cont.)
Table1 CPU Clock Power Management Truth Table
Signal Pin PWRDWN# PWRDWN# Tristate Bit Byte2[5:3] X 0 1 Running Driven @ Iref x2 Tristate See Note1 Note
CPU[2:0] CPU[2:0] CPU[2:0] Note:
1 0 0
1. Iref = VDD/(3Rr) = 3.3/(3x475) = 2.32 mA. Iref x6 = 13.9 mA (Voh @Z: 0.7 V @50 ), Iref x2 = 4.6 mA (Voh @Z: 0.23 V @50 )
Table2 SRC Clock Power Management Truth Table
Signal Pin PWRDWN# PWRDWN# Tristate Bit Byte2[7] X 0 1 Running Driven @ Iref x2 Tristate See Note1 Note
SRC SRC SRC Note:
1 0 0
1. Iref = VDD/(3Rr) = 3.3/(3x475) = 2.32 mA. Iref x6 = 13.9 mA (Voh @Z: 0.7 V @50 ), Iref x2 = 4.6 mA (Voh @Z: 0.23 V @50 )
Byte3 Control Register
Bit 7 6 5 4 3 2 1 0 Description Reserved Reserved PCI_5 Output enable PCI_4 Output enable PCI_3 Output enable PCI_2 Output enable PCI_1 Output enable PCI_0 Output enable 0 = Disabled, 1 = Enabled 0 = Disabled, 1 = Enabled 0 = Disabled, 1 = Enabled 0 = Disabled, 1 = Enabled 0 = Disabled, 1 = Enabled 0 = Disabled, 1 = Enabled Contents Type RW RW RW RW RW RW RW RW Default 1 1 1 1 1 1 1 1 Note
Byte 4 Control Register
Bit 7 6 5 4 3 2 1 0 Description Reserved 48_24MHz Output Enable Reserved Reserved Reserved PCIF_2 Output enable PCIF_1 Output enable PCIF_0 Output enable 0 = Disabled, 1 = Enabled 0 = Disabled, 1 = Enabled 0 = Disabled, 1 = Enabled 0 = Disabled, 1 = Enabled Contents Type RW RW RW RW RW RW RW RW Default 0 1 0 0 0 1 1 1 Note
Rev.1.00, Apr.28.2003, page 8 of 34
HD151TS206SS
I2C Controlled Register Bit Map (cont.)
Byte5 Control Register
Bit 7 6 5 4 3 2 1 0 Description 48MHz Output Enable Reserved VCH Select 66MHz / 48MHz Reserved 3V66_3/VCH Output Enable 3V66_2 Output Enable 3V66_1 Output Enable 3V66_0 Output Enable 0 = Disabled, 1 = Enabled 0 = Disabled, 1 = Enabled 0 = Disabled, 1 = Enabled 0 = Disabled, 1 = Enabled 0 = 3V66 mode 1 = VCH (48MHz) mode Contents 0 = Disabled, 1 = Enabled Type RW RW RW RW RW RW RW RW Default 1 1 0 1 1 1 1 1 Note
Byte6 Control Register
Bit 7 6 5 4 3 2 1 0 Description Test Clock Mode Reserved Reserved SRC Frequency Select Reserved Spread Spectrum Mode REF1 Output Enable REF0 Output Enable 0 = Spread OFF 1 = Spread ON 0 = Disabled, 1 = Enabled 0 = Disabled, 1 = Enabled 0 = 100 MHz, 1 = 200 MHz Contents 0 = Disabled, 1 = Enabled Type RW RW RW RW RW RW RW RW Default 0 0 0 0 0 0 1 1 See B9[7:6] Note
Byte7 Vendor Identification Register
Bit 7 6 5 4 3 2 1 0 Description Revision Code Bit3 Revision Code Bit2 Revision Code Bit1 Revision Code Bit0 Vendor ID Bit3 Vendor ID Bit2 Vendor ID Bit1 Vendor ID Bit0 Contents Vendor Specific Vendor Specific Vendor Specific Vendor Specific Vendor Specific Vendor Specific Vendor Specific Vendor Specific Type R R R R R R R R Default 0 0 0 1 1 1 1 1 Note
Rev.1.00, Apr.28.2003, page 9 of 34
HD151TS206SS
I2C Controlled Register Bit Map (cont.)
Byte8 Read Back Byte Count Register
Bit 7 6 5 4 3 2 1 0 Description Read back byte count Bit7 Read back byte count Bit6 Read back byte count Bit5 Read back byte count Bit4 Read back byte count Bit3 Read back byte count Bit2 Read back byte count Bit1 Read back byte count Bit0 Contents Writing to this register will configure byte Count and how many bytes will be read back. Default is 1Ehex = 30 bytes. Type RW RW RW RW RW RW RW RW Default 0 0 0 1 1 1 1 0 Note
Byte9 Control Register
Bit 7 6 5 4 3 2 1 0 Description SSC2 Enable Bit SSC1 Enable Bit Clock Frequency Control Bit4 Clock Frequency Control Bit3 Clock Frequency Control Bit2 Clock Frequency Control Bit1 Clock Frequency Control Bit0 Frequency Select Mode Bit Contents B6[2] = 0 or B9[7] = 1 : SSC2 = OFF B6[2] = 1 & B9[7] = 0 : SSC2 = ON B6[2] = 0 or B9[6] = 1 : SSC1 = OFF B6[2] = 1 & B9[6] = 0 : SSC1 = ON Latched input FS_4 at Power ON Latched input FS_3 at Power ON Latched input FS_2 at Power ON Latched input FS_1 at Power ON Latched input FS_0 at Power ON 0 = Freq. is selected by latched input FS(4:0) 2 1 = Freq. is selected by I C B9[5:1] Type RW RW RW RW RW RW RW RW Default 0 0 X X X X X 0 See Table3 Note
Rev.1.00, Apr.28.2003, page 10 of 34
HD151TS206SS
I2C Controlled Register Bit Map (cont.)
Table3 Clock Frequency Function Table
No. FS_4 B9[5] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FS_3 B9[4] 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 FS_2 B9[3] 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 FS_1 B9[2] 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 FS_0 B9[1] 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 CPU [MHz] 100.02 200.03 133.36 166.69 200.03 400.07 266.71 333.39 138.69 142.25 145.80 149.36 152.91 156.47 160.03 163.58 167.14 170.70 174.25 177.81 181.36 184.92 186.70 189.36 192.03 194.70 197.37 200.03 202.70 205.37 208.03 210.70 SRC [MHz] 100.02 100.02 100.02 100.02 100.02 100.02 100.02 100.02 100.02 100.02 100.02 100.02 100.02 100.02 100.02 100.02 100.02 100.02 100.02 100.02 100.02 100.02 100.02 100.02 100.02 100.02 100.02 100.02 100.02 100.02 100.02 100.02 3V66 [MHz] 66.68 66.68 66.68 66.68 66.68 66.68 66.68 66.68 66.68 66.68 66.68 66.68 66.68 66.68 66.68 66.68 66.68 66.68 66.68 66.68 66.68 66.68 66.68 66.68 66.68 66.68 66.68 66.68 66.68 66.68 66.68 66.68 PCI [MHz] 33.34 33.34 33.34 33.34 33.34 33.34 33.34 33.34 33.34 33.34 33.34 33.34 33.34 33.34 33.34 33.34 33.34 33.34 33.34 33.34 33.34 33.34 33.34 33.34 33.34 33.34 33.34 33.34 33.34 33.34 33.34 33.34
Rev.1.00, Apr.28.2003, page 11 of 34
HD151TS206SS
I2C Controlled Register Bit Map (cont.)
Byte10 Control Register
Bit 7 6 5 4 3 2 1 0 Backup of latch Input FS_4 at Power ON Backup of latch Input FS_3 at Power ON Backup of latch Input FS_2 at Power ON Backup of latch Input FS_1 at Power ON Backup of latch Input FS_0 at Power ON Description SSC Spread Select Bit[2:0] Contents Bit[2:0] = 000 = -0.500%, 001 = -0.750%, 010 = -1.000%, 011 = -1.500%, 100 = 0.250% 101 = 0.375% 110 = 0.500% 111 = 0.750% Type RW RW RW R R R R R Default 0 0 0 X X X X X Note
When SAFE_F# is Enable (B15[5]=1) PWRDWN#/SAFE_F# pin to "Low", and if B23[1]=0, frequency selection is changed to these setting and PWRDWN#/SAFE_F# pin to "High", frequency selection is changed back to the last mode.
Byte11 Control Register
Bit 7 6 5 4 3 2 1 0 Description Reserved Reserved PWRDWN# Enable Control Bit Backup of B9[5] written by 2 IC Backup of B9[4] written by I2 C Backup of B9[3] written by 2 IC Backup of B9[2] written by 2 IC Backup of B9[1] written by I2 C 0 = Enable, 1 = Disable When SAFE_F# is Enable (B15[5]=1) PWRDWN#/SAFE_F# pin to "Low", and if B23[1]=1, frequency selection is changed to these setting and PWRDWN#/SAFE_F# pin to "High", frequency selection is changed back to the last mode. Contents Type RW RW RW R R R R R Default 0 0 0 X X X X X Note
Rev.1.00, Apr.28.2003, page 12 of 34
HD151TS206SS
I2C Controlled Register Bit Map (cont.)
Byte12 Control Register
Bit 7 6 5 4 3 2 Description Reserved Reserved Reserved Reserved Reserved PLL1 Output (VCO1) Frequency Control Bit (M1/N1 Divider Control Bit) PLL1 : for SRC/3V66/PCI_PLL Contents Type RW RW RW RW RW RW Default 0 0 0 0 0 0 Note
1 0 Note:
0 = Normal mode PLL1 M1[6:0] and N1[9:0] are changed on Table 5 selection decided by FS4/3/2/A/B or B9[5:1] 1 = Over or Down clocking mode PLL1 M1[6:0] and N1[9:0] are changed by B12[1:0] , B13[7:0] and B14[6:0]. B12[1:0] ,B13[7:0] and B14[6:0] are able to be changed at B12[2] = 1. PLL1 N1 Divider Control Bit9 N1[9] RW 0 PLL1 N1 Divider Control Bit8 N1[8] RW 0 1. B12[1:0] ,B13[7:0] and B14[6:0] must be written together (at writing B14) in every case.
See Note1
Byte13 Control Register
Bit 7 6 5 4 3 2 1 0 Note: Description PLL1 N1 Divider Control Bit7 PLL1 N1 Divider Control Bit6 PLL1 N1 Divider Control Bit5 PLL1 N1 Divider Control Bit4 PLL1 N1 Divider Control Bit3 PLL1 N1 Divider Control Bit2 PLL1 N1 Divider Control Bit1 PLL1 N1 Divider Control Bit0 Contents N1[7] N1[6] N1[5] N1[4] N1[3] N1[2] N1[1] N1[0] Type R/W R/W R/W R/W R/W R/W R/W R/W Default 0 1 0 0 1 0 1 1 Note See Note1
1. B12[1:0] ,B13[7:0] and B14[6:0] must be written together (at writing B14) in every case.
Byte14 Control Register
Bit 7 6 5 4 3 2 1 0 Note: Description Contents Type Default Reserved R/W 0 PLL1 M1 Divider Control Bit6 M1[6] R/W 0 PLL1 M1 Divider Control Bit5 M1[5] R/W 0 PLL1 M1 Divider Control Bit4 M1[4] R/W 1 PLL1 M1 Divider Control Bit3 M1[3] R/W 0 PLL1 M1 Divider Control Bit2 M1[2] R/W 0 PLL1 M1 Divider Control Bit1 M1[1] R/W 1 PLL1 M1 Divider Control Bit0 M1[0] R/W 0 1. B12[1:0] ,B13[7:0] and B14[6:0] must be written together (at writing B14) in every case. Note See Note1
Rev.1.00, Apr.28.2003, page 13 of 34
HD151TS206SS
I2C Controlled Register Bit Map (cont.)
Byte15 Control Register
Bit 7 6 5 Description PCI_5 Output Frequency Select Bit 48_24MHz Output Frequency Select Bit SAFE_F# Input mode select Bit Contents 0 = 33.3 MHz , 1 = 25 MHz 0 = 48 MHz , 1 = 24 MHz 0 = PWRDWN# input mode 1 = SAFE_F# input mode Default is PWRDWN# input. SAFE_F# is active "Low" input. When SAFE_F# is "Low", frequency mode is changed to the predefined frequency mode. Predefined frequency mode is selected by B23[1]. 0 = Normal mode Clock dividers are changed by Table 5 selection decided B9[5:1] 1 = Over or Down clocking mode Clock dividers are changed by B15[3:0] and B16[7:0]. B15[3:0] and B16[7:0] are able to be changed at B15[4] = 1. 0001 = 1/1, 0010 = 1/2, 0011 = 1/3, 0100 = 1/4, 0101 = 1/5, 1001 = 1/9 0110 = 1/6, 1010 = 1/10 0111 = 1/7, 1011 = 1/11 1000 = 1/8 Type R/W R/W R/W Default 0 0 0 Note
4
Clock Divider Control Bit
R/W
0
3 2 1 0
CPU Divider Control Bit3 CPU Divider Control Bit2 CPU Divider Control Bit1 CPU Divider Control Bit0
R/W R/W R/W R/W
X X X X
Byte16 Control Register
Bit 7 6 5 4 3 2 1 0 Description 3V66 / PCI / PCIF Divider Control Bit3 3V66 / PCI / PCIF Divider Control Bit2 3V66 / PCI / PCIF Divider Control Bit1 3V66 / PCI / PCIF Divider Control Bit0 SRC Divider Control Bit3 SRC Divider Control Bit2 SRC Divider Control Bit1 SRC Divider Control Bit0 0001 = 1/1, 0010 = 1/2, 0011 = 1/3, 0100 = 1/4, 0101 = 1/5, 1001 = 1/9 0110 = 1/6, 1010 = 1/10 0111 = 1/7, 1011 = 1/11 1000 = 1/8 Contents 3V66 divider ratio = 0010 = 1/2, 0110 = 1/6, 1010 = 1/10 0011 = 1/3, 0111 = 1/4, 1011 = 1/11 0100 = 1/4, 1000 = 1/8, 1100 = 1/12 0101 = 1/5, 1001 = 1/9 PCI / PCIF divider ratio = 3V66 x 1/2 Type R/W R/W R/W R/W R/W R/W R/W R/W Default X X X X X X X X Note
Rev.1.00, Apr.28.2003, page 14 of 34
HD151TS206SS
I2C Controlled Register Bit Map (cont.)
Byte17 Control Register
Bit 7 6 5 4 Description Reserved Reserved Reserved PLL2 Output (VCO2) Frequency Control Bit (M2 / N2 Divider Control Bit) PLL2 : for CPU Contents 1 1 1 0 = Normal mode VCO2 frequency is changed on Table 5 selection decided by FS4/3/2/1/0 or B9[5:1]. 1 = Over or Down clocking mode VCO2 frequency is changed by B17[3:0] and B18[7:0] with decimal. B17[3:0] and B18[7:0] are able to be changed at B17[4] = 1. These bits are 100MHz digit of VCO2 frequency. 0000 = 0, 0001 = 1 .... 1001 = 9 Type R/W R/W R/W R/W Default 0 0 0 0 See Note1 Note
3 2 1 0 Note:
VCO2 Frequency Control Bit11 VCO2 Frequency Control Bit10 VCO2 Frequency Control Bit9 VCO2 Frequency Control Bit8
R/W R/W R/W R/W
0 1 0 0
1. B17[3:0] and B18[7:0] must be written together (at writing B18) in every case.
Byte18 Control Register
Bit 7 6 5 4 3 2 1 0 Note: Description VCO2 Frequency Control Bit7 VCO2 Frequency Control Bit6 VCO2 Frequency Control Bit5 VCO2 Frequency Control Bit4 VCO2 Frequency Control Bit3 VCO2 Frequency Control Bit2 VCO2 Frequency Control Bit1 VCO2 Frequency Control Bit0 These bits are 1MHz digit of VCO2 frequency. 0000 = 0, 0001 = 1 .... 1001 = 9 Contents These bits are 10MHz digit of VCO2 frequency. 0000 = 0, 0001 = 1 .... 1001 = 9 Type R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 Note See Note1
1. B17[3:0] and B18[7:0] must be written together (at writing B18) in every case.
Rev.1.00, Apr.28.2003, page 15 of 34
HD151TS206SS
I2C Controlled Register Bit Map (cont.)
How to set VCO2 frequency to 666 MHz.
Write Byte17 0 0 0 1 0 1 1 0
Byte18 0 1 1 0 0 1 1 0
ON
6
6
6 max 720 min 200
How to read actual frequency of VCO2 and CPU clock
Byte17[4] = 1 Actual VCO2 freq. read back. Byte19 0 1 1 0 0 1 1 0
Byte20 0 1 1 0 1 0 0 0
6
6
6
8
Note:
Case of VCO2 = 666.8 MHz. Other clock frequency are able to read using the same way as shown at upper. Byte19, Byte20 = Read back of VCO2 actual frequency. Byte21, Byte22 = Read back of CPU actual frequency.
Byte19 Control Register
Bit 7 6 5 4 3 2 1 0 Description VCO2 Frequency Read Bit15 VCO2 Frequency Read Bit14 VCO2 Frequency Read Bit13 VCO2 Frequency Read Bit12 VCO2 Frequency Read Bit11 VCO2 Frequency Read Bit10 VCO2 Frequency Read Bit9 VCO2 Frequency Read Bit8 Calculation result of VCO2 frequency. 10 MHz digit 0000 = 0, 0001 = 1 .... 1001 = 9 Contents Calculation result of VCO2 frequency. 100 MHz digit 0000 = 0, 0001 = 1 .... 1001 = 9 Type R R R R R R R R Default 0 0 0 0 0 0 0 0 Note
Rev.1.00, Apr.28.2003, page 16 of 34
HD151TS206SS
I2C Controlled Register Bit Map (cont.)
Byte20 Control Register
Bit 7 6 5 4 3 2 1 0 Description VCO2 Frequency Read Bit7 VCO2 Frequency Read Bit6 VCO2 Frequency Read Bit5 VCO2 Frequency Read Bit4 VCO2 Frequency Read Bit3 VCO2 Frequency Read Bit2 VCO2 Frequency Read Bit1 VCO2 Frequency Read Bit0 Calculation result of VCO2 frequency. 0.1 MHz digit 0000 = 0, 0001 = 1 .... 1001 = 9 Contents Calculation result of VCO2 frequency. 1 MHz digit 0000 = 0, 0001 = 1 .... 1001 = 9 Type R R R R R R R R Default 0 0 0 0 0 0 0 0 Note
Byte 21 Control Register
Bit 7 6 5 4 3 2 1 0 Description CPU Frequency Read Bit15 CPU Frequency Read Bit14 CPU Frequency Read Bit13 CPU Frequency Read Bit12 CPU Frequency Read Bit11 CPU Frequency Read Bit10 CPU Frequency Read Bit9 CPU Frequency Read Bit8 Calculation result of CPU frequency. 10MHz digit 0000 = 0, 0001 = 1 .... 1001 = 9 Contents Calculation result of CPU frequency. 100 MHz digit 0000 = 0, 0001 = 1 .... 1001 = 9 Type R R R R R R R R Default 0 0 0 0 0 0 0 0 Note
Byte22 Control Register
Bit 7 6 5 4 3 2 1 0 Description CPU Frequency Read Bit7 CPU Frequency Read Bit6 CPU Frequency Read Bit5 CPU Frequency Read Bit4 CPU Frequency Read Bit3 CPU Frequency Read Bit2 CPU Frequency Read Bit1 CPU Frequency Read Bit0 Calculation result of CPU frequency. 0.1 MHz digit 0000 = 0, 0001 = 1 .... 1001 = 9 Contents Calculation result of CPU frequency. 1 MHz digit 0000 = 0, 0001 = 1 .... 1001 = 9 Type R R R R R R R R Default 0 0 0 0 0 0 0 0 Note
Rev.1.00, Apr.28.2003, page 17 of 34
HD151TS206SS
I2C Controlled Register Bit Map (cont.)
Byte23 Control Register
Bit 7 6 5 4 3 2 1 Description Watchdog Enable Control Bit RESET# Reverse Control Bit Watchdog Timer Count Bit3 Watchdog Timer Count Bit2 Watchdog Timer Count Bit1 Watchdog Timer Count Bit0 Backup Frequency Select Bit Contents 0 = Disable, Pin22 = 3V66_0 output 1 = Enable, Pin22 = RESET# output 0 = Normal , 1 = Reverse These 4 bits corresponds to how many watchdog timer will wait from becoming "Alarm mode" (B23[0] = 1) to outputting RESET# pin to "Low". Default is 586ms x8 = 4.7s at Power ON 0 = B10[4:0], 1 = B11[4:0] When SAFE_F# is "Low" , frequency mode is changed to the predefined frequency mode decided by B10[4:0] or B11[4:0]. 0 = Normal mode, 1 = Alarm mode Type R/W R/W R/W R/W R/W R/W R/W Default 0 0 1 0 0 0 0 Note
0
Watchdog Status Bit
R/W
0
Byte24 Control Register
Bit 7 6 5 4 3 2 1 0 Description Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Contents Type R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 Note
Rev.1.00, Apr.28.2003, page 18 of 34
HD151TS206SS
I2C Controlled Register Bit Map (cont.)
Byte25 Control Register
Bit 7 6 5 4 3 2 1 0 Note: Description CPU Clock Skew1 Control Bit3 CPU Clock Skew1 Control Bit2 CPU Clock Skew1 Control Bit1 CPU Clock Skew1 Control Bit0 CPU Clock Skew2 Control Bit3 CPU Clock Skew2 Control Bit2 CPU Clock Skew2 Control Bit1 CPU Clock Skew2 Control Bit0 Contents Delay 1000 = +0.00ns, 1001 = +0.25ns, 1010 = +0.50ns, 1011 = +0.75ns, 1100 = +1.00ns, 1101 = +1.25ns, 1110 = +1.50ns, 1111 = +1.75ns, Delay 1000 = +0.0ns, 1001 = +0.1ns, 1010 = +0.2ns, 1011 = +0.3ns, 1100 = +0.4ns, 1101 = +0.5ns, 1110 = +0.6ns, 1111 = +0.7ns, Ahead 0111 = -0.25ns 0110 = -0.50ns 0101 = -0.75ns 0100 = -1.00ns 0011 = -1.25ns 0010 = -1.50ns 0001 = -1.75ns 0000 = -2.00ns Ahead 0111 = -0.1ns 0110 = -0.2ns 0101 = -0.3ns 0100 = -0.4ns 0011 = -0.5ns 0010 = -0.6ns 0001 = -0.7ns 0000 = -0.8ns Type R/W R/W R/W R/W R/W R/W R/W R/W Default 1 0 0 0 1 0 0 0 See Note1 Note See Note1
1. Total CPU Clock Skew is Skew1+Skew2.
Byte26 Control Register
Bit 7 6 5 4 Description PCIF / PCI Clock Skew2 Control Bit3 PCIF / PCI Clock Skew2 Control Bit2 PCIF / PCI Clock Skew2 Control Bit1 PCIF / PCI Clock Skew2 Control Bit0 PCIF / PCI Clock Skew1 Control Bit3 PCIF / PCI Clock Skew1 Control Bit2 PCIF / PCI Clock Skew1 Control Bit1 PCIF / PCI Clock Skew1 Control Bit0 Contents Skew2 is "Late" Skew that is Delay Time from "Normal" Skew1. 0000 = +0.0ns, 1000 = +4.0ns 0001 = +0.5ns, 1001 = +4.5ns 0010 = +1.0ns, 1010 = +5.0ns 0011 = +1.5ns, 1011 = +5.5ns 0100 = +2.0ns, 1100 = +6.0ns 0101 = +2.5ns, 1101 = +6.5ns 0110 = +3.0ns, 1110 = +7.0ns 0111 = +3.5ns, 1111 = +7.5ns Skew1 is "Normal" Skew. Delay Ahead 1000 = +0.0ns, 0111 = -0.5ns 1001 = +0.5ns, 0110 = -1.0ns 1010 = +1.0ns, 0101 = -1.5ns 1011 = +1.5ns, 0100 = -2.0ns 1100 = +2.0ns, 0011 = -2.5ns 1101 = +2.5ns, 0010 = -3.0ns 1110 = +3.0ns, 0001 = -3.5ns 1111 = +3.5ns, 0000 = -4.0ns Type R/W R/W R/W R/W Default 0 0 0 0 Note See Note1
3 2 1 0
R/W R/W R/W R/W
1 0 0 0
See Note1
Note:
1. PCIF / PCI Clock Skew is Skew1 (= Normal) or Skew1+Skew2 (= Late).
Rev.1.00, Apr.28.2003, page 19 of 34
HD151TS206SS
I2C Controlled Register Bit Map (cont.)
Byte27 Control Register
Bit 7 6 5 4 3 2 1 0 Description Reserved PCIF_2 Skew Select Bit PCIF_1 Skew Select Bit PCIF_0 Skew Select Bit 3V66 Clock Skew Control Bit3 3V66 Clock Skew Control Bit2 3V66 Clock Skew Control Bit1 3V66 Clock Skew Control Bit0 Contents Type R/W R/W R/W R/W R/W Default 0 0 0 0 1 0 0 0 Note See Note1
Note:
0 = Normal, 1 = Late 0 = Normal, 1 = Late 0 = Normal, 1 = Late Delay Ahead 1000 = +0.0ns, 0111 = -0.5ns 1001 = +0.5ns, 0110 = -1.0ns R/W 1010 = +1.0ns, 0101 = -1.5ns 1011 = +1.5ns, 0100 = -2.0ns R/W 1100 = +2.0ns, 0011 = -2.5ns 1101 = +2.5ns, 0010 = -3.0ns R/W 1110 = +3.0ns, 0001 = -3.5ns 1111 = +3.5ns, 0000 = -4.0ns 1. Normal = Skew1(B26[3:0]), Late = Skew1(B26[3:0]) + Skew2 (B26[7:4]).
Byte 28 Control Register
Bit 7 6 5 4 3 2 1 0 Note: Description Reserved PCI_6 Skew Select Bit PCI_5 Skew Select Bit PCI_4 Skew Select Bit PCI_3 Skew Select Bit PCI_2 Skew Select Bit PCI_1 Skew Select Bit PCI_0 Skew Select Bit Contents 0 = Normal, 1 = Late 0 = Normal, 1 = Late 0 = Normal, 1 = Late 0 = Normal, 1 = Late 0 = Normal, 1 = Late 0 = Normal, 1 = Late 0 = Normal, 1 = Late 0 = Normal, 1 = Late Type R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 See Note1 Note
1. Normal = Skew1(B26[3:0]), Late = Skew1(B26[3:0]) + Skew2 (B26[7:4]).
Byte29 Control Register
Bit 7 6 5 4 3 2 1 0 Description VCH Slew Rate Control Bit1 VCH Slew Rate Control Bit0 PCI Slew Rate Control Bit1 PCI Slew Rate Control Bit0 PCIF Slew Rate Control Bit1 PCIF Slew Rate Control Bit0 3V66 Slew Rate Control Bit1 3V66 Slew Rate Control Bit0 Contents 00 = Normal, 10 = "++" 01 = "+" , 11 = "-" 00 = Normal, 10 = "++" 01 = "+" , 11 = "-" 00 = Normal, 10 = "++" 01 = "+" , 11 = "-" 00 = Normal, 10 = "++" 01 = "+" , 11 = "-" Type R/W R/W R/W R/W R/W R/W R/W R/W Default 1 0 1 0 1 0 1 0 Note
Rev.1.00, Apr.28.2003, page 20 of 34
HD151TS206SS
Clock Stop Timing Diagram
PWRDWN# Assertion/De-assersion
< 1.8 ms PWRDWN# CPU (Stoppable) CPU (Stoppable) CPU# (Stoppable) 2x Iref (Controled by Byte2[5:3]) Float (Controled by Byte2[5:3]) Float PWRDWN# Assertion/De-assertion Waveforms 6x Iref 6x Iref
PWRDWN# Functionality PWRDWN# 1 0 CPU Normal Iref:2 or Float CPU# SRC Normal Normal Iref:2 Float or Float SRC# Normal Float 3V66 PCIF/PCI 66MHz 33MHz Low Low USB/DOT 48MHz Low REF 14.318MHz Low
Renasas clock generator I2C Serial Interface Operation
1. Write mode 1.1 Controller (host) sends a start bit. 1.2 Controller (host) sends the write address D2 (h). 1.3 Renasas clock generator will acknowledge (Renasas clock gen. sends "Low"). 1.4 Controller (host) sends a begin byte M. 1.5 Renasas clock generator will acknowledge (Renasas clock gen. sends "Low"). 1.6 Controller (host) sends a byte count N. 1.7 Renasas clock generator will acknowledge (Renasas clock gen. sends "Low"). 1.8 Controller (host) sends data from byte M to byte M+N-1. 1.9 Renasas clock generator will acknowledge each byte one at a time. 1.10 Controller (host) sends a stop bit.
1 bit Start bit
7 bits
1 bit 1 bit
8 bits
1 bit
8 bits
1 bit
8 bits
Slave R/W Ack Begin Byte = M Ack Byte Count = N Ack Byte M address D2(h)
1 bit Ack
8 bits Byte M+1
1 bit Ack
8 bits Byte M+N-1
1 bit
1 bit
Ack Stop bit
Rev.1.00, Apr.28.2003, page 21 of 34
HD151TS206SS
Renasas clock generator I2C Serial Interface Operation (cont.)
2. Read mode 2.1 Controller (host) sends a start bit. 2.2 Controller (host) sends the write address D2 (h). 2.3 Renasas clock generator will acknowledge (Renasas clock gen. sends "Low"). 2.4 Controller (host) sends a begin byte M. 2.5 Renasas clock generator will acknowledge (Renasas clock gen. sends "Low"). 2.6 Controller (host) sends a restart bit. 2.7 Controller (host) sends the read address D3 (h). 2.8 Renasas clock generator will acknowledge (Renasas clock gen. sends "Low"). 2.9 Renasas clock generator will send the byte count N. 2.10 Controller (host) will acknowledge. 2.11 Renasas clock generator will send data from byte M to byte M+N-1. 2.12 When Renasas clock generator sends the last byte, controller (host) will not acknowledge. 2.13 Controller (host) sends a stop bit.
1 bit Start bit
7 bits
1 bit 1 bit
8 bits
1 bit
1 bit
7 bits
1 bit
Slave R/W Ack Begin Byte = M Ack Restart bit Slave R/W address D2(h) address D3(h)
1 bit
8 bits
1 bit
8 bits
1 bit
8 bits
1 bit
8 bits
1 bit
1 bit
Ack Begin Count = N Ack Byte M
Ack Byte M+1 Ack
Byte M+N-1 Not Ack Stop bit
Notes: 1. Renasas clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for the verification. 2. The data transfer rate supported by this clock generator is 100k bits/sec or less (standard mode). 3. The input is operating at 3.3 V logic levels. 4. The data byte format is 8 bit bytes. 5. To simplify the clock generator I2C interface, the protocol is set to use only block-write from the controller. 6. The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. The data is loaded until a stop sequence is issued. 7. At power-on, all registers are set to a default condition, as shown.
Rev.1.00, Apr.28.2003, page 22 of 34
HD151TS206SS
Absolute Maximum Ratings
Item Supply voltage Input voltage Output voltage *
1
Symbol VDD VI VO IIK IOK IO
Ratings -0.5 to 4.6 -0.5 to 4.6 -0.5 to VDD +0.5 -50 -50 50 0.7
Unit V V V mA mA mA W C
Conditions
Input clamp current Output clamp current Continuous output current Maximum power dissipation at Ta = 55C (in still air) Storage temperature Notes:
VI < 0 VO < 0 VO = 0 to VDD
Tstg
-65 to +150
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. 1. The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed.
Recommended Operating Conditions
Item Supply voltage Supply voltage DC input signal voltage High level input voltage Low level input voltage Operating temperature VIH VIL Ta Symbol VDD VDDA Min 3.135 3.135 -0.3 2.0 -0.3 0 Type 3.3 3.3 -- -- -- -- Max 3.465 3.465 VDD+0.3 VDD+0.3 0.8 70 Unit V V V V V C Conditions
Rev.1.00, Apr.28.2003, page 23 of 34
HD151TS206SS
DC Electrical Characteristics / Serial Input Port
Ta = 0C to 70C, VDD = 3.3 V
Item Input Low Voltage Input High Voltage Input Current Input capacitance Note: Symbol Min VIL VIH II CI 2.0 -50 Typ *1 10 Max 0.8 +50 Unit V V A pF VI = 0 V or 3.465 V, VDD = 3.465 V SDATA & SCLK Test Conditions
1. For conditions shown as Min or Max, use the appropriate value specified under recommended operating conditions.
AC Electrical Characteristics / Serial Input port
Ta = 0C to 70C, VDD = 3.3 V
Item SCLK Frequency Start Hold Time SCLK Low Time SCLK High Time Data Setup Time Data Hold Time Stop Setup Time BUS Free Time between Stop & Start Condition Symbol FSCLK tSTHD tLOW tHIGH tDSU tDHD tSTSU tSPF Min 4.0 4.7 4.0 250 300 4.0 4.7 Typ Max 100 Unit kHz s s s ns ns s s Test Conditions Normal Mode Notes
Rev.1.00, Apr.28.2003, page 24 of 34
HD151TS206SS
DC Electrical Characteristics CPU/CPU# Clock
Ta = 0C to 70C, VDD = 3.3 V, Iref = 475 Item Output voltage Output Current Output resistance Symbol Min VO IO 3000 Typ *1
2
Max 1.20
Unit V mA
Test Conditions Rp = 49.9 ,VDD = 3.3 V VDD = 3.3 V VO = 1.2 V
I(nom) *
Notes: 1. For conditions shown as Min or Max, use the appropriate value specified under recommended operating conditions 2. I(nom) is output current(Ioh) shown in below. Ioh = VDD/(3Rr) = 3.3/(3x475) = 2.32 mA, Ioh x6 = 13.89 mA (Voh @Z: 0.695 V @50 ), Ioh x2 = 4.63 mA (Voh @Z: 0.232 V @50 )
AC Electrical Characteristics CPU/CPU# Clock (CPU at 0.7V Timing)
Ta = 0C to 70C, VDD = 3.3 V, CL = 2 pF, Rs = 33.2 , Rp = 49.9
Item Cycle to cycle jitter CPU Group Skew (CPU clock out to CPU clock out) Rise time Fall time Clock Duty Cycle CPU clock period(100) CPU clock period(133) CPU clock period(166) CPU clock period(200) Cross point(0.7V) voltage Note: Vcross Symbol tCCS tskS Min Typ |125| |100| Max Unit ps ps Test Conditions Notes Note1
tr tf
175 175 45 0.25
50 9.99 7.49 5.99 4.99
700 700 55 0.55
ps ps % ns ns ns ns V
Vo=0.175V to 0.525V Vo=0.175V to 0.525V
200MHz 200MHz 200MHz
200MHz
1. Difference of cycle time between two adjoining cycles.
Rev.1.00, Apr.28.2003, page 25 of 34
HD151TS206SS
DC Electrical Characteristics SRC/SRC# Clock
Ta = 0C to 70C, VDD = 3.3 V, Iref = 475 Item Output voltage Output Current Output resistance Symbol Min VO IO 3000 Typ *1 I(nom)*
2
Max 1.20
Unit V mA ohm
Test Conditions Rp = 49.9 , VDD = 3.3 V VDD = 3.3 V VO = 1.2 V
Notes: 1. For conditions shown as Min or Max, use the appropriate value specified under recommended operating conditions 2. I(nom) is output current(Ioh) shown in below. Ioh = VDD/(3Rr) = 3.3/(3x475) = 2.32 mA, Ioh x6 = 13.89 mA (Voh @Z: 0.695 V @50 ), Ioh x2 = 4.63 mA (Voh @Z: 0.232 V @50 )
AC Electrical Characteristics SRC/SRC# Clock (SRC at 0.7V Timing)
Ta = 0C to 70C, VDD = 3.3 V, CL = 2 pF, Rs = 33.2 , Rp = 49.9
Item Cycle to cycle jitter Rise time Fall time Clock Duty Cycle SRC clock period(100) SRC clock period(200) Cross point(0.7V) voltage Vcross Note: Symbol tCCS tr tf Min 175 175 45 0.25 Typ |125| 50 9.99 4.99 Max 700 700 55 0.55 Unit ps ps ps % ns ns V 100 MHz VO = 0.175 V to 0.525 V VO = 0.175 V to 0.525 V Test Conditions Notes Note1 100 MHz 100 MHz 100 MHz
1. Difference of cycle time between two adjoining cycles.
Rev.1.00, Apr.28.2003, page 26 of 34
HD151TS206SS
DC Electrical Characteristics / 3V66 Buffer (CK409 Type5 Buffer)
Ta = 0C to 70C, VDD = 3.3 V
Item Output Voltage Symbol VOH VOL Output Current Note: IOH IOL Min 3.1 30 Typ *1 Max 50 -33 Unit V mV mA mA Test Conditions IOH = -1 mA, VDD = 3.3 V IOL = 1 mA, VDD = 3.3 V VOH = 1.0 V VOL = 1.95 V
1. For conditions shown as Min or Max, use the appropriate value specified under recommended operating conditions.
AC Electrical Characteristics / 3V66 Buffer
Ta = 0C to 70C, VDD = 3.3 V, CL = 30 pF
Item Cycle to cycle jitter 3V66 Buffer (3V66 (4:0)) Group Skew Slew rate Clock Period Clock Duty Cycle 3V66 (4:0) leads 33MHz PCI Note: Symbol tCCS tskS Min Typ |250| 0 Max 250 Unit ps ps Test Conditions Notes Fig.1 Rising edge @1.5V to 1.5V Fig.2 0.4V to 2.4V Note1
tSL
1.0 45 1.5
14.9979 50
4.0 55 3.5
V/ns ns % ns
1. Difference of cycle time between two adjoining cycles.
Rev.1.00, Apr.28.2003, page 27 of 34
HD151TS206SS
DC Electrical Characteristics / PCI & PCIF Clock (CK409 Type5 Buffer)
Ta = 0C to 70C, VDD = 3.3 V
Item Output Voltage Symbol VOH VOL Output Current Note: IOH IOL Min 3.1 30 Typ *1 Max 50 -33 Unit V mV mA mA Test Conditions IOH = -1 mA, VDD = 3.3 V IOL = 1 mA, VDD = 3.3 V VOH = 1.0 V VOL = 1.95 V
1. For conditions shown as Min or Max, use the appropriate value specified under recommended operating conditions.
AC Electrical Characteristics / PCI & PCIF Clock
Ta = 0C to 70C, VDD = 3.3 V, CL = 30 pF
Item Cycle to cycle jitter PCI Group Skew Symbol tCCS tskS Min Typ |250| 0 Max 500 Unit ps ps Test Conditions Notes Fig.1 Rising edge @1.5V to 1.5V Fig.2 Note1
Clock Period Slew rate Clock Duty Cycle Note: tSL
1.0 45
29.996 50
4.0 55
ns V/ns % 0.4 V to 2.4 V
1. Difference of cycle time between two adjoining cycles.
Rev.1.00, Apr.28.2003, page 28 of 34
HD151TS206SS
DC Electrical Characteristics / 48_24MHz & VCH 48MHz Clock (CK409 Type3A Buffer)
Ta = 0C to 70C, VDD = 3.3 V
Item Output Voltage Symbol VOH VOL Output Current Note: IOH IOL Min 3.1 29 Typ *1 Max 50 -29 Unit V mV mA mA Test Conditions IOH = -1 mA, VDD = 3.3 V IOL = 1 mA, VDD = 3.3 V VOH = 1.0 V VOL = 1.95 V
1. For conditions shown as Min or Max, use the appropriate value specified under recommended operating conditions.
AC Electrical Characteristics / 48_24MHz & VCH 48MHz Clock
Ta = 0C to 70C, VDD = 3.3 V, CL = 20 pF
Item Cycle to cycle jitter Clock Period Slew rate Clock Duty Cycle Note: tSL Symbol tCCS Min 1.0 45 Typ |350| 20.831 50 Max 2.0 55 Unit ps ns V/ns % 0.4V to 2.4V Test Conditions Notes Fig.1 Note1
1. Difference of cycle time between two adjoining cycles.
Rev.1.00, Apr.28.2003, page 29 of 34
HD151TS206SS
DC Electrical Characteristics / 48MHz Clock (CK409 Type3B Buffer)
Ta = 0C to 70C, VDD = 3.3 V
Item Output Voltage Symbol VOH VOL Output Current Note: IOH IOL Min 3.1 29 Typ *1 Max 50 -29 Unit V mV mA mA Test Conditions IOH = -1 mA, VDD = 3.3 V IOL = 1 mA, VDD = 3.3 V VOH = 1.0 V VOL = 1.95 V
1. For conditions shown as Min or Max, use the appropriate value specified under recommended operating conditions.
AC Electrical Characteristics / 48MHz Clock
Ta = 0C to 70C, VDD = 3.3 V, CL = 10 pF
Item Cycle to cycle jitter Clock Period Slew rate Clock Duty Cycle Note: tSL Symbol tCCS Min 2.0 45 Typ |350| 20.831 50 Max 4.0 55 Unit ps ns V/ns % 0.4V to 2.4V Test Conditions Notes Fig.1 Note1
1. Difference of cycle time between two adjoining cycles.
Rev.1.00, Apr.28.2003, page 30 of 34
HD151TS206SS
DC Electrical Characteristics / REF Clock (CK409 Type5 Buffer)
Ta = 0C to 70C, VDD = 3.3 V
Item Output Voltage Symbol VOH VOL Output Current Note: IOH IOL Min 3.1 30 Typ *1 Max 50 -33 Unit V mV mA mA Test Conditions IOH = -1 mA, VDD = 3.3 V IOL = 1 mA, VDD = 3.3 V VOH = 1.0 V VOL = 1.95 V
1. For conditions shown as Min or Max, use the appropriate value specified under recommended operating conditions.
AC Electrical Characteristics / REF Clock
Ta = 0C to 70C, VDD = 3.3 V, CL = 30 pF
Item Cycle to cycle jitter Clock Period Slew rate Clock Duty Cycle Note: tSL Symbol tCCS Min 1.0 45 Typ |1000| 69.841 50 Max 4.0 55 Unit ps ns V/ns % 0.4V to 2.4V Test Conditions Notes Fig.1 Note1
1. Difference of cycle time between two adjoining cycles.
Rev.1.00, Apr.28.2003, page 31 of 34
HD151TS206SS
Clock Out
tcycle n
tcycle n+1
t CCS = (tcycle n) - (tcycle n+1)
Fig.1 Cycle to Cycle Jitter (3.3V Single Ended Clock Output)
Clock Outx
1.5 V
Clock Outy
1.5 V tskS
Fig.2 Output Clock Skew (3.3V Single Ended Clock Output)
RS = 33.2 CPU
ZLT = ZLC = 50 LT
TS206 RS = 33.2 CPU# LC
RI(ref) = 475
RP = 49.9
RP = 49.9
CL = 2 pF
CL = 2 pF
Fig.3 Load Circuit for CPU/CPU#
Rev.1.00, Apr.28.2003, page 32 of 34
HD151TS206SS
Package Dimensions
Unit: mm
15.85 0.3 48 25
2.65 Max
1 0.78 Max
24
7.50 0.3
0.15 0.05
10.40 0.4 1.45
0 - 10
0.10 Min
0.635 0.25 0.1
0.15 0.13 M
0.60 0.2
Rev.1.00, Apr.28.2003, page 33 of 34
HD151TS206SS
Sales Strategic Planning Div.
Keep safety first in your circuit designs!
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
1. Renesas Technology Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corporation product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corporation or a third party. 2. Renesas Technology Corporation assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corporation or an authorized Renesas Technology Corporation product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corporation assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corporation by various means, including the Renesas Technology Corporation Semiconductor home page (http://www.renesas.com). 4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corporation assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. Renesas Technology Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corporation or an authorized Renesas Technology Corporation product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. The prior written approval of Renesas Technology Corporation is necessary to reprint or reproduce in whole or in part these materials. 7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 8. Please contact Renesas Technology Corporation for further details on these materials or the products contained therein.
http://www.renesas.com
Copyright (c) 2003. Renesas Technology Corporation, All rights reserved. Printed in Japan.
Colophon 0.0
Rev.1.00, Apr.28.2003, page 34 of 34

▲Up To Search▲

Price & Availability of HD151TS206SS

	To Download HD151TS206SS Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .