View 73S8009CN-32IMF_4877650.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

73S8009CN Combo ISO-7816 and USB Universal Smart Card Interface IC
Simplifying System IntegrationTM DS_8009C_026
DATA SHEET
August 2009
FEATURES DESCRIPTION The Teridian 73S8009CN is the world's first single-chip smart card electrical interface circuit that supports all types of smart cards: 5V, 3V and 1.8V, including traditional ISO-7816-3 asynchronous and synchronous type 1 and type 2, as well as USB, ISO-7816-12 cards. The 73S8009CN is ideally suited for applications such as desktop computers, laptops and general purpose smart card readers that require low power operation from a single 2.7V to 6.5V power supply voltage source. A power down mode ("OFF" mode) is available and exhibits a 10nA typical current consumption. The circuit provides control, conversion and regulation of power for the smart card. In addition, the circuit provides a 3.3V-regulated voltage that is used as an internal digital supply voltage to the host interface. It is also made available to supply power to some external circuitry (a host controller for instance). For asynchronous and synchronous smart card operation, the signals for RST, CLK, I/O and auxiliary signals AUX1 and AUX2 are directly controlled from the host processor and are level-shifted by the circuit to the selected VCC value. For more design flexibility, the host processor is responsible for handling the signal timing for smart card activation and deactivation under normal conditions. The power management circuitry allows operation from a single power supply source VPC (2.7V to 6.5V). VPC is converted using an inductive, step-up power converter to the intermediate voltage, VP. VP is used by linear voltage regulators and switches internal to the IC to create the voltages VDD and as required, VCC. VDD is used by the 73S8009CN and is also made available for the companion host processor circuit or for other external circuits. The 73S8009CN features an ON/OFF pin suitable to connect to a "push-on/push-off" main system switch. When the 73S8009CN is "OFF," the typical current drawn from VPC is 10nA. For applications that do not implement any ON/OFF system switch, the ON/OFF input pin can be driven from a digital output of the host processor. * Smart Card Interface: Smart card voltage VCC: o Selectable: 1.8V, 3V or 5V o Generated by an internal voltage regulator o Provides up to 65mA to 3V and 5V cards and up to 40mA to 1.8V cards ISO-7816-3 card emergency deactivation Voltage supervisor detects voltage drop on VCC (card supply) True card over-current detection 150mA max. 1 input for a card presence detection switch Auxiliary I/O lines for synchronous and ISO-7816-12 USB card support Proper isolation of smart card signals depending on smart card type Card CLK clock frequency up to 20MHz 6kV ESD and short circuit protection on the card interface System Controller Interface: Digital logic level: 3.3V 5 signal images of the card signals (RSTIN, CLKIN, I/OUC, AUX1UC and AUX2UC) 1 control signal to switch between synchronous / asynchronous and ISO-7816-12 USB smart card modes 2 inputs activate and select the card voltage (CMDVCC% and CMDVCC#) 2 outputs, interrupt to the system controller (OFF and RDY), to inform the system controller of the card presence / faults and status of the interface 1 Chip Select input 2 handshaking signals (OFF_REQ, OFF_ACK) for proper shutdown sequencing of all smart card signals ON/OFF Input for a Main System Switch DC-DC Step-up Converter: Generates an intermediary voltage VP Requires a single 10H Inductor (rated for 400mA maximum peak current) VDD power supply output available to power up external circuitry: 3.3V 0.3V, 40mA Industrial temperature range (-40 C to +85 C) Small format QFN32 package: 5x5mm RoHS compliant (6/6) lead-free package
*
* *
* * * *
Rev. 1.4
(c) 2009 Teridian Semiconductor Corporation
1
73S8009CN Data Sheet FUNCTIONAL DIAGRAM
DS_8009CN_026
24K Debounce and Latch
ON/OFF
VPC
10uH ON 100K
OFF_REQ
10F 0.1F
LIN VP
Linear/ DC - DC Converter
V1.8ThREF V5.0ThREF V3.0ThREF
OFF
OFF_ACK
CS CMDVCC# CMDVCC% PRES TEST1 TEST2 I/OUC RSTIN CLKIN Card Supply and Control Logic
Analog Mux
+
Delay/ Debounce Circuit
RDY
VCC Regulator
Vcc Status SHUTDOWN
VCC
0.47F
OFF I/O RST Card I/O Buffer and Signal Logic CLK DP AUX1 DM AUX2
AUX1UC
To Internal Digital Logic
AUX2UC SC/USB 3.3V Regulator GND GND GND
VDD
0.1F 0.1F
VP
4.7F
Figure 1: 73S8009CN Block Diagram
2
Rev. 1.4
DS_8009CN_026
73S8009CN Data Sheet
Table of Contents
1 2 Pinout ............................................................................................................................................. 5 Electrical Specifications................................................................................................................ 9 2.1 Absolute Maximum Ratings ..................................................................................................... 9 2.2 Recommended Operating Conditions ...................................................................................... 9 2.3 Smart Card Interface Requirements ...................................................................................... 10 2.4 Digital Signals Characteristics ............................................................................................... 12 2.5 DC Characteristics ................................................................................................................ 13 2.6 Voltage / Temperature Fault Detection Circuits...................................................................... 13 2.7 Thermal Characteristics ........................................................................................................ 13 Applications Information ............................................................................................................. 13 3.1 Example 73S8009CN Schematics ......................................................................................... 13 3.2 Power Supply and Converter ................................................................................................. 16 3.3 Interface Function - ON/OFF Modes...................................................................................... 16 3.4 System Controller Interface ................................................................................................... 18 3.5 Card Power Supply and Voltage Supervision......................................................................... 18 3.6 Activation and De-activation Sequence ................................................................................. 19 3.7 OFF and Fault Detection ....................................................................................................... 20 3.8 Chip Selection ....................................................................................................................... 21 3.9 I/O Circuitry and Timing......................................................................................................... 22 Equivalent Circuits ...................................................................................................................... 24 Mechanical Drawing .................................................................................................................... 28 Ordering Information ................................................................................................................... 29 Related Documentation ............................................................................................................... 29 Contact Information..................................................................................................................... 29
3
4 5 6 7 8
Rev. 1.4
3
73S8009CN Data Sheet
DS_8009CN_026
Figures
Figure 1: 73S8009CN Block Diagram ...................................................................................................... 2 Figure 2: 73S8009CN 32-Pin QFN Pinout ................................................................................................ 5 Figure 3: Typical 73S8009CN Application Schematic with a Main System Switch................................... 14 Figure 4: Typical 73S8009CN Application Schematic without a Main System Switch .............................. 15 Figure 5: Activation Sequence ............................................................................................................... 19 Figure 6: Deactivation Sequence ........................................................................................................... 20 Figure 7: OFF Activity ............................................................................................................................ 20 Figure 8: CS Timing Definitions.............................................................................................................. 21 Figure 9: I/O and I/OUC State Diagram .................................................................................................. 22 Figure 10: I/O - I/OUC Delays - Timing Diagram.................................................................................... 23 Figure 11: On_Off Pin ............................................................................................................................ 24 Figure 12: Open Drain type - OFF and RDY .......................................................................................... 24 Figure 13: Power Input/Output Circuit, VDD, LIN, VPC, VCC, VP ........................................................... 24 Figure 14: USB - DM, DP Pins .............................................................................................................. 25 Figure 15: Smart Card CLK Driver Circuit .............................................................................................. 25 Figure 16: Smart Card RST Driver Circuit .............................................................................................. 25 Figure 17: Smart Card IO, AUX1, and AUX2 Interface Circuit................................................................. 26 Figure 18: Smart Card IOUC, AUX1UC and AUX2UC Interface Circuit .................................................. 26 Figure 19: General Input Circuit ............................................................................................................. 27 Figure 20: OFF_REQ Interface Circuit ................................................................................................... 27 Figure 21: 32-Pin QFN Package Dimensions ......................................................................................... 28
Tables
Table 1: 73S8009CN Pin Definitions ........................................................................................................ 5 Table 2: Absolute Maximum Device Ratings ............................................................................................ 9 Table 3: Recommended Operating Conditions ......................................................................................... 9 Table 4: DC Smart Card Interface Requirements ................................................................................... 10 Table 5: Digital Signals Characteristics .................................................................................................. 12 Table 6: DC Characteristics ................................................................................................................... 13 Table 7: Voltage / Temperature Fault Detection Circuits......................................................................... 13 Table 8: Thermal Characteristics ........................................................................................................... 13 Table 9: Order Numbers and Packaging Marks ...................................................................................... 29
4
Rev. 1.4
DS_8009CN_026
73S8009CN Data Sheet
1 Pinout
The 73S8009CN is supplied as a 32-pin QFN package.
TEST2
GND
GND
VDD
VPC 26
OFF
LIN
32
31
30
29
28
27
I/OUC AUX1UC AUX2UC CMDVCC5 CMDVCC3 RSTIN CLKIN RDY
1 2 3 4 5 6 7 8
25
24 23 22 ON/OFF DM I/O AUX1 AUX2 VCC RST GND 21 20 19 18 17
TERIDIAN 73S8009CN
10
11
12
13
14
15 VP
OFF_ACK
TEST1
OFF_REQ
SC/USB
Figure 2: 73S8009CN 32-Pin QFN Pinout Table 1 describes the pin functions for the device. Table 1: 73S8009CN Pin Definitions Pin Name Card Interface I/O 22 IO Figure 17 Card I/O: Data signal to/from smart card. Includes an 11k pull-up resistor to VCC Will be tri-stated when SC/USB is set low. AUX1: Auxiliary data signal to/from smart card for synchronous smart card operation. Smart card USB DP signal for IS0-7816-12 USB smart card operation. Includes an 11k pull-up resistor to VCC for synchronous / asynchronous operation only. AUX2: Auxiliary data signal to/from smart card for synchronous smart card operation. Smart card USB DM signal for IS0-7816-12 USB smart card operation. Includes an 11k pull-up resistor to VCC for synchronous / asynchronous operation only. Card reset: provides reset (RST) signal to card. RST is the pass through signal on RSTIN. Internal control logic will hold RST low when card is not activated or VCC is too low. Will be tri-stated when SC/USB is set low. 5 Pin Number Type Equivalent Circuit Description
AUX1
21
IO
Figure 17
AUX2
20
IO
Figure 17
RST
18
O
Figure 16
Rev. 1.4
PRES
CLK
CS
16
9
DP
73S8009CN Data Sheet Pin Name CLK Pin Number 16 Equivalent Circuit Figure 15
DS_8009CN_026
Type O
Description Card clock: provides clock signal (CLK) to card. CLK is the pass through of the signal on pin CLKIN. Internal control logic will hold CLK low when card is not activated or VCC is too low. Will be tri-stated when SC/USB is set low. Smart card Presence switch: Active high indicates card is present. Smart card activation will not be permitted unless PRES is active. Card power supply - logically controlled by sequencer, output of LDO regulator. Requires an external 0.47uF low ESR filter capacitor to GND. Card ground.
PRES
14
I
Figure 19
VCC
19
PSO
Figure 13
GND
17
GND
-
Host Processor Interface CS 12 I Figure 19 Chip Select. When CS = 1, the control and signal pins are configured normally. When CS is set low, CMDVCC%, RSTIN, and CMDVCC# are latched. I/OUC, AUX1UC, and AUX2UC are set to high-impedance pull-up mode and do not pass data to or from the smart card. Signals RDY and OFF are disabled to prevent a low output and the internal pull-up resistors are disconnected. Should be tied to VDD when a single 73S8009CN is used. Interrupt signal to the processor. Active Low Multi-function indicating fault conditions and card presence. Open drain output configuration - It includes an internal 20k pull-up to VDD. Pull-up is disabled in Power down state and CS = 0 modes. System controller data I/O to/from the card. Includes an 11k pull-up resistor to VDD. System controller auxiliary data I/O to/from the card for synchronous / asynchronous operation mode. Connection to AUX1 is opened when SC/USB is low. Includes an 11k pull-up resistor to VDD. System controller auxiliary data I/O to/from the card for synchronous / asynchronous operation mode. Connection to AUX2 is opened when SC/USB is low. Includes an 11k pull-up resistor to VDD. Smart Card Interface enable, USB interface disable. Pin is provided with a weak pull-up. When high, the 73S8009CN operates in synchronous / asynchronous operation mode. When low, CLK, RST I/O, AUX1, and AUX2 are tri-stated. Pin AUX1 is connected to pin DP and pin AUX2 is connected to pin DM. USB D+ connection to / from USB controller. When SC/USB is set low, this pin is electrically connected to the AUX1 pin, otherwise it is isolated.
OFF
32
O
Figure 12
I/OUC AUX1UC
1 2
IO IO
Figure 18 Figure 18
AUX2UC
3
IO
Figure 18
SC/USB
13
I
Figure 19
DP
25
IO
Figure 14
6
Rev. 1.4
DS_8009CN_026 Pin Name DM Pin Number 23 Equivalent Circuit Figure 14
73S8009CN Data Sheet
Type IO
Description USB D- connection to / from USB controller. When SC/USB is set low, this pin is electrically connected to the AUX1 pin, otherwise it is isolated. Logic low on one or both of these pins will cause the LDO regulator to ramp the Vcc supply to the smart card and smart card interface to the value described in the following table: CMDVCC% CMDVCC# Vcc Output Voltage 0 0 1.8V 0 1 5.0V 1 0 3.0V 1 1 Vcc Off Note: See Card Power Supply and Voltage Supervision for more details.
CMDVCC% CMDVCC#
4 5
I I
Figure 19
RSTIN RDY
6 8
I O
Figure 19 Figure 12
Reset Input: This signal is the reset command to the card. Signal to controller indicating the 73S8009CN is ready because VCC is above the required value after CMDVCC% and/or CMDVCC# is asserted low. A 20k pull-up resistor to VDD is provided internally. Pull-up is disabled in Power down state and CS=0 modes. Power control pin. Connected to normally open SPST switch to ground. Closing switch for duration greater than de-bounce period will turn 73S8009CN circuit "on". If the 73S8009CN is "on," closing the switch will turn 73S8009CN to "off" state after the de-bounce period and OFF_REQ/OFF_ACK handshake. Can be controlled by a host processor digital output. Digital output. Request to the host system controller to turn the 73S8009CN off. If ON_OFF switch is closed (to ground) for de-bounce duration and circuit is "on," OFF_REQ will go high (request to turn OFF). Connected to OFF_ACK via 100k internal resistor. Setting OFF_ACK high will power "off" all analog functions and disconnect the 73S8009CN from VPC. The pin has an internal 100k resistor connection to OFF_REQ so that when not connected or no host interaction is required, the Acknowledge will be true and the circuit will turn "off" after the deactivation sequence is completed. Clock signal source for the card clock. Factory test pin. This pin must be tied to GND. Factory test pin. This pin must be tied to GND.
ON/OFF
24
I
Figure 11
OFF_REQ
11
O
Figure 19
OFF_ACK
13
I
Figure 19
Miscellaneous CLKIN TEST1 TEST2 7 10 30 I - - Figure 19 - -
Rev. 1.4
7
73S8009CN Data Sheet Pin Name Pin Number Equivalent Circuit
DS_8009CN_026
Type
Description
Power Supply and Ground VDD 29 PSO Figure 13 System interface supply voltage output and supply voltage for companion controller circuit (40mA maximum source capability). Requires a minimum of two 0.1F capacitors to ground for proper decoupling. Power supply source for main voltage converter circuit. A 10F and a 0.1F ceramic capacitor must be connected to this pin. Connection to 10H inductor for internal step up converter. Note: inductor must be rated for 400mA maximum peak current. Intermediate output of main converter circuit. Requires an external 4.7F low ESR filter capacitor to GND. Ground.
VPC
26
PSI
Figure 13
LIN
27
PSI
Figure 13
VP
15
PSO
Figure 13
GND
28, 31
GND
-
8
Rev. 1.4
DS_8009CN_026
73S8009CN Data Sheet
2 Electrical Specifications
This section provides the following: Absolute maximum ratings Recommended operating conditions Smart card interface requirements Digital signals characteristics Voltage / temperature fault detection circuits Thermal characteristics
2.1
Absolute Maximum Ratings
Table 2 lists the maximum operating conditions for the 73S8009CN. Permanent device damage may occur if absolute maximum ratings are exceeded. Exposure to the extremes of the absolute maximum rating for extended periods may affect device reliability. Table 2: Absolute Maximum Device Ratings Parameter Supply Voltage VPC VDD Input Voltage for Digital Inputs Storage Temperature Pin Voltage (except card interface) Pin Voltage (card interface) Pin Voltage, LIN pin ESD Tolerance - Card interface, DP and DM pins ESD Tolerance - Other pins Pin Current, except LIN Pin Current, LIN Rating -0.5 to 7.0 VDC -0.5 to 4.0 VDC -0.3 to (VDD +0.5) VDC -65 to 150C -0.3 to (VDD + 0.5) VDC -0.3 to (VCC + 0.3) VDC 0.3 to 6.5 VDC +/- 6kV +/- 2kV 200 mA + 500 mA in, -200 mA out
2.2
Recommended Operating Conditions
Function operation should be restricted to the recommended operating conditions specified in Table 3. Table 3: Recommended Operating Conditions Parameter Supply voltage VPC Ambient operating temperature Rating 2.7 to 6.5 VDC -40C to +85C
Rev. 1.4
9
73S8009CN Data Sheet
DS_8009CN_026
2.3
Smart Card Interface Requirements
Table 4 lists the 73S8009CN Smart Card interface requirements. Table 4: DC Smart Card Interface Requirements Symbol Parameter Condition Card Power Supply (VCC) Regulator General Conditions: -40C < 85C, 2.7 V < VPC < 6.5 V Inactive mode Inactive mode ICC = 1mA Active mode; ICC <65mA; 5V Active mode; ICC < 65mA; 3V Active mode; ICC < 40mA; 1.8V Active mode; single pulse of 100mA for 2s; 5 volt, fixed load = 25mA Active mode; single pulse of Card supply voltage 100mA for 2s; 3V, fixed load VCC including ripple and noise = 25mA Active mode; current pulses of 40nAs with peak |ICC | <200mA, t <400ns; 5V Active mode; current pulses of 40nAs with peak |ICC | <200mA, t <400ns; 3V Active mode; current pulses of 20nAs with peak |ICC | <100mA, t <400ns; 1.8V VCCrip VCC ripple fRIPPLE = 20KHz - 200MHz ICCmax Card supply output Static load current, VCC>1.65 current Static load current, VCC>4.6 or 2.7 volts as selected ICCF ICC fault current Class A, B (5V and 3V) Class C (1.8V) VS Vcc slew rate, rise and C = 0.5F fall Vrdy Vcc ready voltage (RDY 5V operation, Vcc rising = 1) 3V operation, Vcc rising 1.8V operation, Vcc rising VCCF RDY = 0 VCC = 5V (VCC voltage supervisor threshold) CVPC External filter cap for VPC Cvp External filter cap for VP CF should be ceramic with low External filter capacitor CF ESR (<100m). (VCC to GND) CVDD VDD filter capacitor Min Nom Max Unit
-0.1 -0.1 4.65 2.85 1.68 4.6
- - - - - -
0.1 0.4 5.25 3.15 1.92 5.25
V V V V V V
2.76
-
3.15
V
4.6
-
5.25
V
2.7
-
3.15
V
1.62
-
1.92
V
- - - 75 55 0.10 4.6 2.75 1.65 - - - 0.30 - - - -
350 40 65 150 130 0.70 - - - 4.6
mV mA mA mA mA V/s V V V V
8.0 2.0 0.2 0.2
10.0 4.7 0.47 -
12.0 6.8 1.0 1.0
F F F F
10
Rev. 1.4
DS_8009CN_026
73S8009CN Data Sheet
Symbol Parameter Condition Min Nom Max Unit Interface Requirements - Data Signals: I/O, AUX1, AUX2, and host interfaces: I/OUC, AUX1UC, AUX2UC, DP, DM. ISHORTL, ISHORTH, and VINACT requirements do not pertain to I/OUC, AUX1UC, AUX2UC - VOH Output level, high (I/O, IOH =0 0.9 * VCC VCC+0.1 V AUX1, AUX2) - 0.75 VCC VOH Output level, high (I/OUC, IOH = -40A VCC+0.1 V AUX1UC, AUX2UC) - IOH =0 0.9 VDD VDD+0.1 V - 0.75 VDD VOL Output level, low (I/O, VDD+0.1 V IOH = -40A AUX1, AUX2) - - IOL=1mA 0.15 *VCC V - - VOL Output level, low (I/OUC, IOL=1mA 0.3 V AUX1UC, AUX2UC) - VIH Input level, high (I/O, 0.6 * VCC VCC+0.30 V AUX1, AUX2) - VIH Input level, high (I/OUC, 0.6 * VDD VDD+0.30 V AUX1UC, AUX2UC) - VIL Input level, low (I/O, -0.15 0.2 * VCC V AUX1, AUX2) - VIL Input level, low (I/OUC, -0.15 0.2 * VDD V AUX1UC, AUX2UC) - - VINACT Output voltage when IOL = 0 0.1 V outside of session - - IOL = 1mA 0.3 V - - ILEAK Input leakage VIH = VCC 10 A - Ifloat Input current Input current with -2 +2 A SC/USB = 0 - - IIL Input current, low (I/O, VIL = 0 0.65 mA AUX1, AUX2) - - IIL Input current, low (I/OUC, VIL = 0 0.7 mA AUX1UC, AUX2UC) - - ISHORTL Short circuit output For output low, shorted to 15 mA current VCC through 33 - - ISHORTH Short circuit output For output high, shorted to 15 mA current ground through 33 - - t R, t F Output rise time, fall For I/O, AUX1, AUX2, 100 ns times CL = 80pF, 10% to 90%. For I/OUC, AUX1UC, AUX2UC, CL=50Pf, 10% to 90%. - - tIR, tIF Input rise, fall times 1 s RPU Internal pull-up resistor Output stable for >200ns 8 11 14 k MHz FDMAX Maximum data rate - - 1 TFDIO Edge from master to 60 100 200 ns Delay, I/O to I/OUC, AUX1 to AUX1UC, AUX2 to slave, measured at 50% TRDIO - 15 - ns
AUX2UC,I/OUC to I/O, AUX1UC to AUX1, AUX2UC to AUX2 (respectively falling edge to falling edge and rising edge to rising edge)
CIN Inusboff Rswitch
Input capacitance Input current USB off Resistance D to Aux
0 < Vdm, Vdp <3.3V, VCC=5V, SC/USB =1 0 < Vdm, Vdp < 3.3V, VCC=5V, SC/USB =0
- -2 0.5
- - 2
10 +2 6
pF A
Rev. 1.4
11
73S8009CN Data Sheet
DS_8009CN_026
Symbol Parameter Condition Reset and Clock for card interface, RST, CLK VOH Output level, high IOH =-200A VOL Output level, low IOL=200A VINACT Ifloat Output voltage when outside of session Input current IOL = 0 IOL = 1mA Input current with SC/USB = 0, open circuited
Min 0.9 * VCC 0 - - -5 - - - - 45
Nom - - - - - - - - - -
Max VCC 0.15 *VCC 0.1 0.3 +5 30 70 12 100 55
Unit V V V V A mA mA ns ns %
IRST_LIM ICLK_LIM t R, t F
Output current limit, RST Output current limit, CLK Output rise time, fall time
CL = 35pF for CLK, 10% to 90% CL = 200pF for RST, 10% to 90% CL =35pF, FCLK 20MHz, CLKIN duty cycle is 48% to 52%.
Duty cycle for CLK
2.4
Digital Signals Characteristics
Table 5: Digital Signals Characteristics
Table 5 lists the 73S8009CN digital signals characteristics.
Symbol Digital I/O (except for VIL VILOFFACK VIH VOL VOH ROUT RACK |I IL1 | tSL tDZ tIS tSI tID tDI
Parameter
Condition
Min
Nom
Max
Unit
I/OUC, AUX1UC, AUX2UC; see Smart Card Interface Requirements for those specifications) - Input Low Voltage -0.3 0.8 V - 0.7 V Input low voltage for OFF_REQ pin = VDD -0.3 OFF_ACK pin - Input High Voltage 1.8 VDD + 0.3 V - Output Low Voltage IOL = 2mA 0.45 V - Output High Voltage IOH = -1mA VDD - 0.45 V Pull-up resistor; OFF, RDY 14 20 26 k Resistor between 70 100 130 k OFF_REQ and 0FF_ACK - Input Leakage Current GND < VIN < VDD - 5 A - - Time from CS goes high to 50 ns interface active - - Time from CS goes low to 50 ns interface inactive, Hi-Z - - Set-up time, control 50 ns signals to CS rising edge - Hold time, control signals - 50 ns from CS rising edge - - Set-up time, control 50 ns signals to CS fall - - Hold time, control signals 50 ns from CS fall Rev. 1.4
12
DS_8009CN_026
73S8009CN Data Sheet
2.5
DC Characteristics
Table 6 lists the DC characteristics. Table 6: DC Characteristics Symbol VDD IDDEXT Parameter VDD Voltage VDD Current to External Load Vpc = 2.7V, VCC off, IDD = 0 Vpc = 3.3V, VCC off, IDD = 0 Vpc = 5.0V, VCC off, IDD = 0 OFF mode Condition 2.7v < VPC < 6.5v, IVDDEXT < 40mA. Min 3.0 - - - - - Nom 3.3 - 1.7 1.1 0.7 0.01 Max 3.6 40 - - - 1 Unit V mA mA mA mA A
IVPC
Supply Current
2.6
Voltage / Temperature Fault Detection Circuits
Table 7 lists the voltage /temperature fault detection circuits. Table 7: Voltage / Temperature Fault Detection Circuits Symbol IDDmax ICCF ICCF1P8 Parameter VDD over-current limit Card overcurrent fault Card overcurrent fault Condition Min 40 80 60 Nom - - - Max 100 150 130 Unit mA mA mA
VCC = 1.8V
2.7
Thermal Characteristics
Table 8 lists the thermal characteristics. Table 8: Thermal Characteristics Symbol Tj Parameter Junction temperature Thermal Resistance, Junction-to-Ambient Thermal Resistance, Junction-to-case Condition Min - - - Nom - 70 6 Max 125 - - Unit
ja jc
C C/W C/W
3 Applications Information
This section provides general usage information for the design and implementation of the 73S8009CN. The documents listed in Related Documentation provide more detailed information.
3.1
Example 73S8009CN Schematics
Figure 3 shows a typical application schematic for the implementation of the 73S8009CN with a main system switch. Figure 4 shows a typical application schematic for the implementation of the 73S8009CN without a main system switch. Note that minor changes may occur to the reference material from time to time and the reader is encouraged to contact Teridian for the latest information.
Rev. 1.4
13
73S8009CN Data Sheet
DS_8009_026
VDD
See NOTE 5 0.1F C1 0.1F C2 See NOTE 4 10H
VPC See NOTE 1 0.1F C3 10F C4
VDD_supply_to_uC
USB D- to/from_uC USB D+ to/from_uC OFF_interrupt_to_uC I/OUC_to/from_uC AUX1UC_to/from_uC AUX2UC_to/from_uC CMDVCC%_from_uC CMDVCC#_from_uC RSTIN_from_uC CLKIN_from_uC RDY_status_to_uC OFF_ACK_from_uC OFF_REQ_to_uC VDD SC/USB_from_uC R2 20K 4.7F NOTES: 1) VPC = 2.7V to 6.5V DC 2) Resistor footprint is included in case some filtering is needed on CLK 3) Capacitors C4 and C5 are provisional and their footprints should be added for added noise rejection if necessary. 4) Inductor must be rated for 400 mA maximum peak current. 5) VDD - 3.3V, +/- 0.3V, 40mA max. Schematic assumes VDD supplies power to the host controller. Requires min two 0.1F caps to gnd) 6) The RDY signal is optional. A short delay before releasing RSTIN should suffice for the RDY signal function. C7
Card detection switch is normally closed
25 26 27 28 29 30 31 32 DP VPC LIN GND VDD TEST2 GND OFF
Pushbutton Switch
ON/OFF DM I/O AUX1 AUX2 VCC RST GND 24 23 22 21 20 19 18 17
OFF_ACK TEST1 OFF_REQ CS SC/USB PRES VP CLK
1 2 3 4 5 6 7 8
I/OUC AUX1UC AUX2UC CMDVCC% CMDVCC# RSTIN CLKIN RDY
SW1
27pF C5
See NOTE 3
See NOTE 6
9 10 11 12 13 14 15 16
73S80009CN
32 QFN
See NOTE 2 0 27pF C6 See NOTE 3
0.47F, Low ESR (<100mohms) should be placed near the C8 SC connecter contact
10 9 SW-2 SW-1
C8 I/O VPP GND C4 CLK RST VCC
8 7 6 5 4 3 2 1
CLK track should be routed far from RST, I/O, C4 and C8
Smart Card Connector
Figure 3: Typical 73S8009CN Application Schematic with a Main System Switch
14
Rev. 1.4
DS_8009CN_026
73S8009CN Data Sheet
VDD
See NOTE 5 0.1F C1 0.1F C2 See NOTE 4 10H
VPC See NOTE 1 0.1F C3 10F C4
VDD_monitor_to_uC
ON/OFF_Control_from_uC USB D- to/from_uC USB D+ to/from_uC OFF_interrupt_to_uC
25 26 27 28 29 30 31 32
I/OUC_to/from_uC AUX1UC_to/from_uC AUX2UC_to/from_uC CMDVCC%_from_uC CMDVCC#_from_uC RSTIN_from_uC CLKIN_from_uC RDY_status_to_uC 47K 47K 10K 0 See NOTE 7 1 2 3 4 5 6 7 8
OFF_ACK TEST1 OFF_REQ CS SC/USB PRES VP CLK
I/OUC AUX1UC AUX2UC CMDVCC% CMDVCC# RSTIN CLKIN RDY
73S80009CN
9 10 11 12 13 14 15 16
DP VPC LIN GND VDD TEST2 GND OFF
ON/OFF DM I/O AUX1 AUX2 VCC RST GND
24 23 22 21 20 19 18 17
27pF C5
See NOTE 3
32 QFN
See NOTE 2 0 27pF See NOTE 3
VDD 47K SC/USB_from_uC NOTES: 1) VPC = 2.7V to 6.5V DC See NOTE 6 4.7F C2 R2 20K
Card detection switch is normally closed
C6
2) Resistor footprint is included in case some filtering is needed on CLK 3) Capacitors C5 and C6 are provisional and their footprints should be added for added noise rejection if necessary. 4) Inductor must be rated for 400 mA maximum peak current. 5) VDD - 3.3V, +/- 0.3V, 40mA max. Schematic assumes VDD is monitored by the host controller. Requires min two 0.1F caps to gnd) 6) Resistors are necessary to provide isolation between powered host and "OFF" 73S8009CN. Signals should be driven low in this condition. 7) The RDY signal is optional. A short delay before releasing RSTIN should suffice for the RDY signal function.
0.47F, Low ESR (<100mohms) should be placed near the C7 SC connecter contact
10 9 SW-2 SW-1
C8 I/O VPP GND C4 CLK RST VCC
8 7 6 5 4 3 2 1
CLK track should be routed far from RST, I/O, C4 and C8
Smart Card Connector
Figure 4: Typical 73S8009CN Application Schematic without a Main System Switch
Rev. 1.4
15
73S8009CN Data Sheet
DS_8009CN_001
3.2
Power Supply and Converter
The 73S8009CN power supply and converter circuitry takes power from the VPC input pin. The power supplied to VPC pin is converted to the voltage VP utilizing an inductive, step-up converter. A series power inductor (nominal value = 10H) is connected from pin VPC to pin LIN, and a 10F and a 0.1F filter capacitor must be connected to VPC. Note: When the VPC input voltage exceeds the nominal VP voltage (approximately 5.5V), the switching operation of the converter stops and the converter acts as a pass through for VPC to VP. Switching operation will automatically resume when VPC falls below the nominal VP voltage. VP requires a 4.7F filter capacitor and will have a nominal value of 5.5 volts during normal operation. VP is used by the smart card interface circuits (CLK, RST, I/O, AUX1, and AUX2) and is the source of the regulated smart card supply VCC. VCC can be selected for values of 5V, 3V, and 1.8V. The power supply output VDD is also produced from VP. VDD is used by the 73S8009CN circuit for logic, input / output buffering with the host. In addition, VDD can be used as a 3.3V regulated power supply for some external circuitry provided that no more than 40mA is needed (simultaneously to the 65mA current drawn from VCC).
3.3
Interface Function - ON/OFF Modes
A power ON/OFF function is provided such that the circuit will be inoperative during the "OFF" state, consuming minimum current from VPC. Option 1: 73S8009CN supplies host/system power controlled by push button ON/OFF switch: Refer to Figure 3 for a typical electrical schematic when using an ON/OFF system switch. The ON/OFF pin shall be connected to an SPST switch to ground. If the circuit is OFF and the switch is closed for a de-bounce period of approximately 100ms, the circuit shall go into the "ON" state wherein all functions are operating in normal fashion. If the circuit is in the "ON" state and the ON/OFF pin is connected to ground for a period greater than the de-bounce period, OFF_REQ will be asserted high and held regardless of the state of ON/OFF. Typically, the OFF_REQ signal is presented to a host controller that will assert OFF_ACK high when it has completed all shutdown activities. When OFF_ACK is set high, the circuit will de-activate the smart card interface if required and turn off all analog functions and the VDD supply for the logic and companion circuits. The OFF_ACK pin is connected internally to OFF_REQ with a resistor such that if OFF_ACK is unconnected, the action of OFF_REQ will assert OFF_ACK high. In this configuration, the circuit shall go into the "OFF" state immediately if the interface is deactivated or immediately after deactivation if previously activated.. The default state upon application of power to VPC is the "OFF". Note that at any time, the controller may assert OFF_ACK and the 73S8009CN will go into the "OFF" state (regardless of activity on the ON/OFF main system switch). Option 2: ON/OFF status driven from the host processor (no system switch): Refer to Figure 4 for a typical electrical schematic when controlling the ON/OFF pin via host control. The ON/OFF pin can be connected to a host digital control signal to turn the 73S8009CN on or off. The host should monitor the VDD supply to determine when the switch debounce time has been achieved so the 73S8009CN can switch states (ON or OFF). When the 73S8009CN is OFF, the host should drive the ON/OFF pin low to initiate the turn ON process. The signal must remain low until the VDD supply voltage goes to 3.3V. The 73S8009CN is now ON and the ON/OFF pin should be driven back high. To turn off the 73S8009CN, the host should drive the ON/OFF signal low until the VDD supply goes to 0V. The 73S8009CN is now OFF and the ON/OFF pins should be driven back high. See Note 6.
16
Rev. 1.4
DS_8009CN_026 Important Notes:
73S8009CN Data Sheet
1. When the host is not powered by the VDD supply of the 73S8009CN, special care must be taken as the host signals going to the 73S8009CN can be active when the device is powered OFF. This can create issues such as excessive current drain on the control signals and potentially prohibit proper turn ON of the 73S8009CN. Series resistors on the input signals (except the ON/OFF input) are recommended to provide isolation and prevent any potential problems. The recommended value of these resistors is 47k. It is also necessary for the host to set these input signals to the low state (except for ON/OFF) when the 73S8009CN is OFF. False activation of the card is possible if the CMDVCC# or CMDVCC% inputs are low (with a card inserted) when the 73S8009CN is powered ON. For this reason, the proper sequencing of the 73S8009CN is required. The CMDVCC# or CMDVCC% inputs must be set high immediately before the ON/OFF input is taken low to turn on the 73S8009CN. The time between setting the CMDVCC# or CMDVCC% inputs high and the setting of the ON/OFF input set low should be kept to a minimum as the CMDVCC# or CMDVCC% inputs, when set high with the 73S8009CN OFF, will draw significant current under these conditions. The 47k series resistors will mitigate this current draw. However, some additional current will be drawn through the resistors to the CMDVCC# or CMDVCC% inputs during this time so it should be kept to a minimum. 2. For applications where ON/OFF is controlled by the host, the OFF_REQ and OFF_ACK signals do not need to be connected to the host. When the OFF_ACK pin is left unconnected, the 73S8009CN will turn off properly by the action of the internal resistor connection to OFF_REQ. 3. If the host is capable of selectively monitoring the I/O line, it can be used in place of the VDD supply monitor as it is tied to the VDD supply through a pull up resistor when the smart card interface is not activated. 4. When the 73S8009CN is powered OFF, the host will not be able to detect a card event (card insertion/removal). If this function is necessary, then the host must monitor the card connector switch separately. 5. For systems that do not use VDD to power the host controller, the host interface signals must operate at 3.3V as the 73S8009CN digital logic operates off the VDD (3.3V) supply regardless of the value of the VPC supply. 6. The ON/OFF pin is internally pulled up to VPC through a 24k resistor. Special care must be taken if the host signal controlling the ON/OFF signal is running at a voltage different from VPC. If this is the case, then either the host control signal must be a maximum VPC supply tolerant open drain output or an external circuit should provide some isolation between the host control signal and the ON/OFF pin. 7. For those systems that require low power operation or are battery operated, the host controller circuit firmware should place the 73S8009CN in the OFF state if no card activity is required.
Rev. 1.4
17
73S8009CN Data Sheet
DS_8009CN_026
3.4

System Controller Interface
Five separate digital inputs and two outputs allow direct control of the card interface from the host: Pin CS: Chip select control. Pin CMDVCC# and/or CMDVCC%: When low, starts an activation sequence. Pin RSTIN: controls the card RST signal. Pin SC/USB: Routes AUXx signals to AUXxUC or USB Dx pins and provides proper tri-stating functionality. Pin RDY: Indicates when smart card power supply is stable and ready. Pin OFF: Indicator of card presence and any card fault conditions.
Interrupt output to the host: When the card is not activated, the OFF pin informs the host about the card presence only (Low = No card in the reader, high = card inserted). When CMDVCC (#/% signals) is/are set low (card activation sequence requested from the host), low level on OFF means a fault has been detected (e.g. card removal during card session, or voltage fault, or thermal / over-current fault) that automatically initiates a deactivation sequence. The smart card pass through signals are enabled when the RDY conditions are met.
3.5
Card Power Supply and Voltage Supervision
The 73S8009CN smart card interface IC incorporates an LDO voltage regulator for the card power supply, VCC (VP to VCC conversion uses an internal LDO). The voltage output is controlled by the digital input sequence of CMDVCC# and CMDVCC%. This regulator is able to provide either 1.8V, 3V or 5V card voltage sourced from the VP power supply. Internal digital circuitry is also powered by the VP power supply (except for the ON/OFF circuitry which is powered from VPC). A voltage supervisor checks the value of the voltage VCC. A card deactivation sequence is forced upon fault detected by voltage supervisor, overcurrent condition, or card removal event. The voltage regulator can provide a card current of 65mA in compliance with EMV 4.1 for 3-V and 5-V cards. The signals CMDVCC# and CMDVCC% control the turn-on, output voltage value, and turn-off of VCC. When either signal is asserted low, VCC will ramp to the selected value or if both signals are asserted low (within 400ns of each other), VCC will ramp to 1.8V. These signals are edge triggered. If CMDVCC% is asserted low (to command VCC to be 5V) and at a much later time (greater than 2s, typically), CMDVCC# is asserted low, it will be ignored (and vice versa.) At the assertion (low) of either or both CMDVCC (#/% signals), VCC will rise to the requested value. When VCC rises to an acceptable value, and stays above that value for approximately 20s, RDY will be set high. Approximately 510s after the fall of CMDVCC (#/%), the circuit will check the see if VCC is at or above the required minimum value (indicated by RDY=1) and if not, will begin an emergency deactivation sequence. During the 510s time, card removal, or de-assertion of CMDVCC (#/%) shall also initiate an emergency deactivation sequence. The circuit provides over-current protection and limits Icc to 150mA, maximum for self-protection. When an over-current condition is sensed, the circuit will invoke a deactivation sequence.
18
Rev. 1.4
DS_8009CN_026
73S8009CN Data Sheet
3.6
Activation and De-activation Sequence
The host controller is fully responsible for the activation sequencing of the smart card signals CLK, RST, I/O, AUX1 and AUX2. All these signals are held low by the 73S8009CN when the card is in the deactivated state. Upon card activation (the fall of CMDVCC (#/%)), all the signals are held low by the 73S8009CN until RDY goes high. The host should set the signals RSTIN, I/OUC, CLKIN, AUX1UC and AUX2UC low prior to activating the card and allow RDY to go high before transitioning any of these signals. In order to initiate activation, the card must be present and OFF must be high.
At t1 (500us), if RDY=0 or overcurrent, circuit will de-activate (safety feature) CMDVCC5 or CMDVCC3 VCC I/OUC I/O RDY RSTIN RST CLKIN CLK
CLK=CLKIN if RDY=1 Ignored Ignored RST = RSTIN if RDY=1 Ignored I/O = I/OUC if RDY=1
t1
VCC valid
I/O, AUX1, AUX2, CLK, RST are held LOW until RDY = 1 and CMDVCCx = 0
Figure 5: Activation Sequence Deactivation is initiated either by the system controller by setting both CMDVCC (#/%) high, or automatically in the event of hardware faults or assertion of the OFF_ACK signal. Hardware faults are over-current, under-voltage, and card extraction during the session. The host can manage the I/O signals, CLKIN, RSTIN, and CMDVCC (#/%) to create other de-activation sequences for non-emergency situations. The following steps show the deactivation sequence and the timing of the card control signals when the system controller sets the CMDVCC(x)B high: 1. 2. 3. 4. RST goes low at the end of time t1. De-assert CLK at the end of time t2. I/O goes low at the end of time t3. Exit reception mode. De-assert internal VCC_ON at the end of time t4. After a delay, VCC is de-asserted.
Note: Since the 73S8009CN does not control the waveshape of CLK (it is determined by the input form the host CLKIN), there is no guarantee that the duty cycle of the last CLK high pulse will conform to duty cycle requirements during an emergency deactivation.
Rev. 1.4
19
73S8009CN Data Sheet
DS_8009CN_026
CMDVCC RST CLK
I/O VCC_ON
VCC
t1
t2
t3
t4
t5
Figure 6: Deactivation Sequence
3.7
OFF and Fault Detection
There are two different cases that the system controller can monitor the OFF signal: to query regarding the card presence outside card sessions, or for fault detection during card sessions. Outside a card session: In this condition, CMDVCC (#/%) are always high, OFF is low if the card is not present, and high if the card is present. Because it is outside a card session, no fault detection can occur and it will not act upon the OFF signal. No deactivation is required during this time. During a card session: CMDVCC# and/or CMDVCC% is always low, and OFF falls low if the card is extracted or if any fault detection is detected. At the same time that OFF is set low, the sequencer starts the deactivation process and the host should stop all transitions on the signal lines. Figure 4 shows the timing diagram for the signals CMDVCC (#/%), PRES, and OFF during a card session and outside the card session.
OFF is low by card extracted PRES OFF CMDVCC VCC outside card session within card session
OFF is low by any fault
within card session
Figure 7: OFF Activity
20
Rev. 1.4
DS_8009CN_026
73S8009CN Data Sheet
3.8
Chip Selection
The CS pin allows multiple circuits to operate in parallel, driven from the same host control bus. When CS is high, the pins RSTIN, CMDVCC%, CMDVCC# and CLKIN control the chip as described. The pins I/OUC, AUX1UC, and AUX2UC have 11k pull-up resistors and operate to transfer data to the smart card via I/O, AUX1, and AUX2 when the smart card is activated. The signals OFF and RDY have 20k pull-up resistors. When CS goes low, the states of the pins RSTIN, CMDVCC%, CMDVCC, and CLKIN are latched and held internally. The pull-up for pins I/OUC, AUX1UC, and AUX2UC become a very weak pull-up of approximately 3 microamperes. No transfer of data is possible between I/OUC, AUX1UC, AUX2UC and the smart-card signals I/O, AUX1, and AUX2. The signals OFF and RDY are set to high impedance and the internal pull-up resistors of 20k are disconnected. With regard to de-activation, CS does not affect the operation of the fault sensing circuits and card sense input. CS does not affect the action of SC/USB.
tDZ CS OFF, I/OUC, AUX1UC, AUX2UC tSL
HI-Z STATE HI-Z STATE
FUNCTIONAL
CONTROL SIGNALS
tIS
tSI
tID
tDI
Figure 8: CS Timing Definitions
Rev. 1.4
21
73S8009CN Data Sheet
DS_8009CN_026
3.9
I/O Circuitry and Timing
The states of the I/O, AUX1, and AUX2 pins are low after power on reset and they are in high when the activation sequencer turns on the I/O reception state. See the Activation and De-activation Sequence section for more details on when the I/O reception is enabled. The states of I/OUC, AUX1UC, and AUX2UC are high after power on reset. Within a card session and when the I/O reception state is turned on, the first I/O line on which a falling edge is detected becomes the input I/O line and the other becomes the output I/O line. When the input I/O line rising edge is detected, then both I/O lines return to their neutral state. Figure 6 shows the state diagram of how the I/O and I/OUC lines are managed to become input or output.
Neutral State
No I/O reception Yes
I/O & not I/OUC
No Yes No I/OUC & not I/O Yes I/OUC in No I/OICC in No
I/OUC
I/O
yes
yes
Figure 9: I/O and I/OUC State Diagram
22
Rev. 1.4
DS_8009CN_026 The delay between the I/O signals is shown in Figure 10.
73S8009CN Data Sheet
I/O
I/OUC
tI/O_HL
Delay from I/O to I/OUC: Delay from I/OUC to I/O:
tI/O_LH
tI/O_HL = 100ns tI/OUC_HL = 100ns
tI/OUC_HL
tI/OUC_LH
tI/O_LH = 15ns tI/OUC_LH = 15ns
Figure 10: I/O - I/OUC Delays - Timing Diagram
Rev. 1.4
23
73S8009CN Data Sheet
DS_8009CN_026
4 Equivalent Circuits
This section provides illustrations of circuits equivalent to those described in the Pinout section.
24K
PIN
ESD
VPC
Figure 11: On_Off Pin
VDD
Output Disable
20K
Data From circuit
PIN
ESD
STRONG NFET
Figure 12: Open Drain type - OFF and RDY
PIN
ESD
To Internal circuits
Figure 13: Power Input/Output Circuit, VDD, LIN, VPC, VCC, VP
24
Rev. 1.4
DS_8009CN_026
73S8009CN Data Sheet
PIN
ESD
2 ohms
TO AUX1 or AUX2 PAD
Figure 14: USB - DM, DP Pins
VCC
VERY STRONG PFET
ESD
From circuit
ESD
CLK
PIN VERY STRONG NFET
Figure 15: Smart Card CLK Driver Circuit
VCC
STRONG PFET
ESD
From circuit
ESD
RST
PIN
STRONG NFET
Figure 16: Smart Card RST Driver Circuit
Rev. 1.4
25
73S8009CN Data Sheet
VCC
DS_8009CN_026
ESD
STRONG PFET
400ns DELAY
RL=11K
From circuit
STRONG NFET
IO
PIN
To circuit
CMOS
ESD
Figure 17: Smart Card IO, AUX1, and AUX2 Interface Circuit
VDD
ESD
STRONG PFET
400ns DELAY
RL=11K
From circuit
STRONG NFET
UC
PIN
To circuit
CMOS
ESD
Figure 18: Smart Card IOUC, AUX1UC and AUX2UC Interface Circuit
26
Rev. 1.4
DS_8009CN_026
VDD
73S8009CN Data Sheet
Pull-up Disable
VERY WEAK PFET
ESD
To circuit Pull-down Enable
TTL
PIN
ESD
VERY WEAK NFET
Note:
Pins CMDVCC%, CMDVCC#, CS, SC/USB have the pull-up enabled. Pins RSTIN, CLKIN, PRES, EXT_RST have the pull-down enabled. Pin OFF_ACK has a 100k resistor connected to pin OFF_REQ internally.
Figure 19: General Input Circuit
VDD
STRONG PFET
ESD
Output Disable PIN Data From circuit
ESD
STRONG NFET
100k ohm
To OFF_ACK pad
Notes: Strong PFET or NFET is approximately 100 Very strong PFET or NFET is approximately 50 Medium strength PFET is approximately 1k Very weak PFET or NFET is approximately 1M The diodes represent ESD protection devices that will conduct current if forward biased.
Figure 20: OFF_REQ Interface Circuit
Rev. 1.4
27
73S8009CN Data Sheet
DS_8009CN_026
5 Mechanical Drawing
5 2.5
0.20 REF. 0.85 NOM./ 0.9MAX. 0.00 / 0.005
1 2 3
2.5 5
SEATING PLANE
TOP VIEW
SIDE VIEW
0.35 / 0.45
3.0 / 3.75 0.18 / 0.3 1.5 / 1.875
CHAMFERED 0.30
1 2 3
3.0 / 3.75
0.2 MIN. 0.35 / 0.45
0.25 1.5 / 1.875 0.5
0.5 0.25
BOTTOM VIEW
Figure 21: 32-Pin QFN Package Dimensions
28
Rev. 1.4
DS_8009CN_026
73S8009CN Data Sheet
6 Ordering Information
Table 9 lists the order numbers and packaging marks used to identify 73S8009CN products. Table 9: Order Numbers and Packaging Marks Part Description 73S8009CN-32QFN 32-pin Lead-Free QFN 73S8009CN-32QFN 32-pin Lead-Free QFN Tape / Reel Order Number 73S8009CN-32IM/F 73S8009CN-32IMR/F Packaging Mark S8009CN S8009CN
7 Related Documentation
The following 73S8009CN document is available from Teridian Semiconductor Corporation: 73S8009CN 32QFN Demo Board User's Guide
8 Contact Information
For more information about Teridian Semiconductor products or to check the availability of the 73S8009CN, contact us at: 6440 Oak Canyon Road Suite 100 Irvine, CA 92618-5201 Telephone: (714) 508-8800 FAX: (714) 508-8878 Email: scr.support@teridian.com For a complete list of worldwide sales offices, go to http://www.teridian.com.
Rev. 1.4
29
73S8009CN Data Sheet
DS_8009CN_026
Revision History
Revision 1.0 1.1 Date 10/23/2007 11/6/2007 Description First publication. Added the Related Documentation section and the Contact Information section. Miscellaneous editorial changes. Change the name of the "SC_USB" pin to "SC/USB". Changed the dimension of the bottom view 32-pin QFN package. Added Section 2.5, DC Characteristics. Corrected the document number from "DS_8009CN_001" to "DS_8009CN_026".
1.2 1.3 1.4
1/21/2008 1/31/2008 8/28/2009
Teridian Semiconductor Corporation is a registered trademark of Teridian Semiconductor Corporation. Simplifying System Integration is a trademark of Teridian Semiconductor Corporation. All other trademarks are the property of their respective owners. This Data Sheet is proprietary to Teridian Semiconductor Corporation (TSC) and sets forth design goals for the described product. The data sheet is subject to change. TSC assumes no obligation regarding future manufacture, unless agreed to in writing. If and when manufactured and sold, this product is sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement and limitation of liability. Teridian Semiconductor Corporation (TSC) reserves the right to make changes in specifications at any time without notice. Accordingly, the reader is cautioned to verify that a data sheet is current before placing orders. TSC assumes no liability for applications assistance. Teridian Semiconductor Corp., 6440 Oak Canyon, Suite 100, Irvine, CA 92618 TEL (714) 508-8800, FAX (714) 508-8877, http://www.teridian.com 30 Rev. 1.4

▲Up To Search▲

Price & Availability of 73S8009CN-32IMF

	To Download 73S8009CN-32IMF Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .