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Triple, 200 mA, Low Noise, High PSRR Voltage Regulator ADP320
FEATURES
Bias voltage range (VBIAS): 2.5 V to 5.5 V LDO input voltage range (VIN1/VIN2, VIN3): 1.8 V to 5.5 V Three 200 mA low dropout voltage regulators 16-lead, 3 mm x 3 mm LFCSP Initial accuracy: 1% Stable with 1 F ceramic output capacitors No noise bypass capacitor required 3 independent logic controlled enables Over current and thermal protection Key specifications High PSRR 76 dB PSRR up to 1 kHz 70 dB PSRR 10 kHz 60 dB PSRR at 100 kHz 40 dB PSRR at 1 MHz Low output noise 29 V rms typical output noise at VOUT = 1.2 V 55 V rms typical output noise at VOUT = 2.8 V Excellent transient response Low dropout voltage: 110 mV @ 200 mA load 85 A typical ground current at no load, all LDOs enabled 100 s fast turn-on circuit Guaranteed 200 mA output current per regulator -40C to +125C junction temperature
TYPICAL APPLICATION CIRCUITS
2.5V TO VBIAS 5.5V 1.8V TO VIN1/VIN2 5.5V
ADP320
+ 1F
VBIAS
+
1F EN1
LDO 1
ON OFF
VOUT1 + 1F
EN LD1 VBIAS LDO 2 EN LD2 VBIAS
EN2
ON OFF
VOUT2 + 1F
1.8V TO VIN3 5.5V
+
1F EN3
ON OFF
LDO 3 EN LD3 GND
VOUT3 + 1F
02839-001
Figure 1. Typical Application Circuit
APPLICATIONS
Mobile phones Digital cameras and audio devices Portable and battery-powered equipment Portable medical devices Post dc-to-dc regulation
GENERAL DESCRIPTION
The ADP320 200 mA triple output LDO combines high PSRR, low noise, low quiescent current, and low dropout voltage in a voltage regulator ideally suited for wireless applications with demanding performance and board space requirements. The low quiescent current, low dropout voltage, and wide input voltage range of the ADP320 triple LDO extend the battery life of portable devices. The ADP320 triple LDO maintains power supply rejection greater than 60 dB for frequencies as high as 100 kHz while operating with a low headroom voltage. The ADP320 triple LDO offers much lower noise performance than competing LDOs without the need for a noise bypass capacitor. The ADP320 triple LDO is available in a miniature 16-lead 3 mm x 3 mm LFCSP package and is stable with tiny 1 F 30% ceramic output capacitors, resulting in the smallest possible board area for a wide variety of portable power needs. The ADP320 triple LDO is available in output voltage combinations ranging from 0.8 V to 3.3 V and offers over current and thermal protection to prevent damage in adverse conditions.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2010 Analog Devices, Inc. All rights reserved.
ADP320 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications ....................................................................................... 1 Typical Application Circuits............................................................ 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Input and Output Capacitor, Recommended Specifications .. 4 Absolute Maximum Ratings............................................................ 5 Thermal Resistance ...................................................................... 5 ESD Caution .................................................................................. 5 Pin Configurations and Function Descriptions ........................... 6 Typical Performance Characteristics ..............................................7 Theory of Operation ...................................................................... 14 Applications Information .............................................................. 15 Capacitor Selection .................................................................... 15 Undervoltage Lockout ............................................................... 16 Enable Feature ............................................................................ 16 Current-Limit and Thermal Overload Protection ................. 17 Thermal Considerations............................................................ 17 Printed Circuit Board Layout Considerations ....................... 19 Outline Dimensions ....................................................................... 20 Ordering Guide .......................................................................... 20
REVISION HISTORY
6/10--Revision 0: Initial Version
Rev. 0 | Page 2 of 20
ADP320 SPECIFICATIONS
VIN1/VIN2 = VIN3 = (VOUT + 0.5 V) or 1.8 V (whichever is greater), VBIAS = 2.5 V, EN1, EN2, EN3 = VBIAS, IOUT1 = IOUT2 = IOUT3 = 10 mA, CIN = COUT1 = COUT2 = COUT3 = 1 F, and TA = 25C, unless otherwise noted. Table 1.
Parameter INPUT BIAS VOLTAGE RANGE INPUT LDO VOLTAGE RANGE GROUND CURRENT WITH ALL REGULATORS ON Symbol VBIAS VIN1/VIN2/ VIN3 IGND Conditions TJ = -40C to +125C TJ = -40C to +125C IOUT = 0 A IOUT = 0 A, TJ = -40C to +125C IOUT = 10 mA IOUT = 10 mA, TJ = -40C to +125C IOUT = 200 mA IOUT = 200 mA, TJ = -40C to +125C INPUT BIAS CURRENT SHUTDOWN CURRENT OUTPUT VOLTAGE ACCURACY IBIAS IGND-SD VOUT 100 A < IOUT < 200 mA, VIN = (VOUT + 0.5 V) to 5.5 V, TJ = -40C to +125C VIN = (VOUT + 0.5 V) to 5.5 V VIN = (VOUT + 0.5 V) to 5.5 V, TJ = -40C to +125C IOUT = 1 mA to 200 mA IOUT = 1 mA to 200 mA, TJ = -40C to +125C VOUT = 3.3 V IOUT = 10 mA IOUT = 10 mA, TJ = -40C to +125C IOUT = 200 mA IOUT = 200 mA, TJ = -40C to +125C VOUT = 3.3 V, all VOUT initially off, enable one VOUT = 0.8 V VOUT = 3.3 V, one VOUT initially on, enable second VOUT = 0.8 V TJ = -40C to +125C EN1 = EN2 = EN3 = GND EN1 = EN2 = EN3 = GND, TJ = -40C to +125C -1 -2 0.01 -0.03 0.001 0.005 6 9 110 170 240 100 160 20 360 155 15 1.2 0.4 0.1 1 2.45 2.0 10 Hz to 100 kHz, VIN = 5 V, VOUT = 3.3 V 10 Hz to 100 kHz, VIN = 5 V, VOUT = 2.8 V 10 Hz to 100 kHz, VIN = 3.6 V, VOUT = 2.5 V 10 Hz to 100 kHz, VIN = 3.6 V, VOUT = 1.2 V 180 63 55 50 29 +0.03 Min 2.5 1.8 Typ Max 5.5 5.5 Unit V V A A A A A A A A A A % % %/ V %/ V %/mA %/mA mV mV mV mV mV s s s s mA C C V V A A V V mV V rms V rms V rms V rms
85 160 120 220 250 380 66 140 0.1 2.5 +1 +2
LINE REGULATION LOAD REGULATION 1 DROPOUT VOLTAGE 2
VOUT/VIN VOUT/IOUT VDROPOUT
START-UP TIME 3
TSTART-UP
CURRENT LIMIT THRESHOLD 4 THERMAL SHUTDOWN Thermal Shutdown Threshold Thermal Shutdown Hysteresis EN INPUT EN Input Logic High EN Input Logic Low EN Input Leakage Current UNDERVOLTAGE LOCKOUT Input Bias Voltage (VBIAS) Rising Input Bias Voltage (VBIAS) Falling Hysteresis OUTPUT NOISE
ILIMIT TSSD TSSD-HYS VIH VIL VI-LEAKAGE UVLO UVLORISE UVLOFALL UVLOHYS OUTNOISE TJ rising
250
600
2.5 V VBIAS 5.5 V 2.5 V VBIAS 5.5 V EN1 = EN2 = EN3 = VIN or GND EN1 = EN2 = EN3 = VIN or GND, TJ = -40C to +125C
Rev. 0 | Page 3 of 20
ADP320
Parameter POWER SUPPLY REJECTION RATIO Symbol PSRR Conditions VIN = 1.8 V, VOUT = 0.8 V, IOUT = 100 mA 100 Hz 1 kHz 10 kHz 100 kHz 1 MHz VIN = 3.8 V, VOUT = 2.8 V, IOUT = 100 mA 100 Hz 1 kHz 10 kHz 100 kHz 1 MHz Min Typ 70 70 70 60 40 68 62 68 60 40 Max Unit dB dB dB dB dB dB dB dB dB dB
1 2
Based on an end-point calculation using 1 mA and 200 mA loads. Dropout voltage is defined as the input-to-output voltage differential when the input voltage is set to the nominal output voltage. This applies only for output voltages above 1.8 V. 3 Start-up time is defined as the time between the rising edge of ENx to VOUTx being at 90% of its nominal value. 4 Current-limit threshold is defined as the current at which the output voltage drops to 90% of the specified typical value. For example, the current limit for a 3.0 V output voltage is defined as the current that causes the output voltage to drop to 90% of 3.0 V, or 2.7 V.
INPUT AND OUTPUT CAPACITOR, RECOMMENDED SPECIFICATIONS
Table 2.
Parameter MINIMUM INPUT AND OUTPUT CAPACITANCE 1 CAPACITOR ESR
1
Symbol CMIN RESR
Conditions TA = -40C to +125C TA = -40C to +125C
Min 0.70 0.001
Typ
Max 1
Unit F
The minimum input and output capacitance should be greater than 0.70 F over the full range of operating conditions. The full range of operating conditions in the application must be considered during device selection to ensure that the minimum capacitance specification is met. X7R and X5R type capacitors are recommended, Y5V and Z5U capacitors are not recommended for use with LDOs.
Rev. 0 | Page 4 of 20
ADP320 ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter VIN1/VIN2, VIN3, VBIAS to GND VOUT1, VOUT2 to GND VOUT3 to GND EN1, EN2, EN3 to GND Storage Temperature Range Operating Junction Temperature Range Soldering Conditions Rating -0.3 V to +6.5 V -0.3 V to VIN1/VIN2 -0.3 V to VIN3 -0.3 V to +6.5 V -65C to +150C -40C to +125C JEDEC J-STD-020
Stresses above those listed under absolute maximum ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Junction-to-ambient thermal resistance (JA) of the package is based on modeling and calculation using a 4-layer board. The junction-to-ambient thermal resistance is highly dependent on the application and board layout. In applications where high maximum power dissipation exists, close attention to thermal board design is required. The value of JA may vary, depending on PCB material, layout, and environmental conditions. The specified values of JA are based on a four-layer, 4-inch x 3-inch circuit board. Refer to JEDEC JESD 51-9 for detailed information on the board construction. For additional information, see the AN-617 Application Note, MicroCSPTM Wafer Level Chip Scale Package. JB is the junction to board thermal characterization parameter with units of C/W. JB of the package is based on modeling and calculation using a 4-layer board. The JESD51-12, Guidelines for Reporting and Using Package Thermal Information, states that thermal characterization parameters are not the same as thermal resistances. JB measures the component power flowing through multiple thermal paths rather than a single path as in thermal resistance, JB. Therefore, JB thermal paths include convection from the top of the package as well as radiation from the package; factors that make JB more useful in realworld applications. Maximum junction temperature (TJ) is calculated from the board temperature (TB) and power dissipation (PD) using the following formula TJ = TB + (PD x JB) Refer to JEDEC JESD51-8 and JESD51-12 for more detailed information about JB.
THERMAL DATA
Absolute maximum ratings apply individually only, not in combination. The ADP320 triple LDO can be damaged when the junction temperature limits are exceeded. Monitoring ambient temperature does not guarantee that the junction temperature (TJ) is within the specified temperature limits. In applications with high power dissipation and poor thermal resistance the maximum ambient temperature may have to be derated. In applications with moderate power dissipation and low PCB thermal resistance, the maximum ambient temperature can exceed the maximum limit as long as the junction temperature is within specification limits. The junction temperature (TJ) of the device is dependent on the ambient temperature (TA), the power dissipation of the device (PD), and the junction-to-ambient thermal resistance of the package (JA). Maximum junction temperature (TJ) is calculated from the ambient temperature (TA) and power dissipation (PD) using the following formula: TJ = TA + (PD x JA)
THERMAL RESISTANCE
JA and JB are specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Table 4.
Package Type 16-Lead 3 mm x 3 mm LFCSP JA 49.5 JB 25.2 Unit C/W
ESD CAUTION
Rev. 0 | Page 5 of 20
ADP320 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
16 EN2 15 EN3 14 NC 13 NC
12 GND 11 GND 10 VIN3 9 VIN3
EN1 1 VBIAS 2 VIN1/VIN2 3 VIN1/VIN2 4
ADP320
Figure 2. Pin Configuration
Table 5. Pin Function Descriptions
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 EP Mnemonic EN1 VBIAS VIN1/VIN2 VIN1/VIN2 VOUT1 VOUT2 VOUT3 NC VIN3 VIN3 GND GND NC NC EN3 EN2 EP Description Enable Input for Regulator 1. Drive EN1 high to turn on Regulator 1; drive it low to turn off Regulator 1. For automatic startup, connect EN1 to VBIAS. Input Voltage Bias Supply. Bypass VBIAS to GND with a 1 F or greater capacitor. Regulator Input Supply for Output Voltage 1 and Output Voltage 2. Bypass VIN1/VIN2 to GND with a 1 F or greater capacitor. Regulator Input Supply for Output Voltage 1 and Output Voltage 2. Bypass VIN1/VIN2 to GND with a 1 F or greater capacitor. Regulated Output Voltage 1. Connect a 1 F or greater output capacitor between VOUT1 and GND. Regulated Output Voltage 2. Connect a 1 F or greater output capacitor between VOUT2 and GND. Regulated Output Voltage 3. Connect a 1 F or greater output capacitor between VOUT3 and GND. Not connected internally. Regulator Input Supply for Output Voltage 3. Bypass VIN3 to GND with a 1 F or greater capacitor. Regulator Input Supply for Output Voltage 3. Bypass VIN3 to GND with a 1 F or greater capacitor. Ground Pin. Ground Pin. Not connected internally. Not connected internally. Enable Input for Regulator 3. Drive EN3 high to turn on Regulator 3; drive it low to turn off Regulator 3. For automatic startup, connect EN3 to VBIAS. Enable Input for Regulator 2. Drive EN1 high to turn on Regulator 2; drive it low to turn off Regulator 2. For automatic startup, connect EN2 to VBIAS. Exposed pad for enhanced thermal performance. Connect to copper ground plane.
Rev. 0 | Page 6 of 20
02839-002
TOP VIEW (Not to Scale) NOTES 1. NC = NO CONNECT. 2. CONNECT EXPOSED PAD TO GROUND PLANE.
VOUT3 7
VOUT1 5
VOUT2 6
NC 8
ADP320 TYPICAL PERFORMANCE CHARACTERISTICS
VIN1/VIN2 = VIN3 =VBIAS = 4 V, VOUT1 = 3.3 V, VOUT2 = 1.8 V, VOUT3 = 1.5 V, IOUT = 10 mA, CIN = COUT1 = COUT2 = COUT3 = 1 F, TA = 25C, unless otherwise noted.
3.33
LOAD = 1mA LOAD = 5mA LOAD = 10mA LOAD = 50mA LOAD = 100mA LOAD = 200mA
1.820 1.815 1.810 1.805
VOUT (V)
3.32
LOAD = 1mA LOAD = 5mA LOAD = 10mA LOAD = 50mA LOAD = 100mA LOAD = 200mA
3.31
VOUT (V)
3.30
1.800 1.795
3.29
1.790
3.28
1.785
3.27
02839-003
1.780
-40
-5
25 TJ (C)
85
125
-40
-5
25 TJ (C)
85
125
Figure 3. Output Voltage vs. Junction Temperature
3.320
1.820
Figure 6. Output Voltage vs. Junction Temperature
3.315
1.815
VOUT (V)
VOUT (V)
3.310
1.810
3.305
1.805
02839-004
1
10
100
1000
ILOAD (mA)
ILOAD (mA)
Figure 4. Output Voltage vs. Load Current
3.320
LOAD = 1mA LOAD = 5mA LOAD = 10mA LOAD = 50mA LOAD = 100mA LOAD = 200mA
Figure 7. Output Voltage vs. Load Current
1.820
LOAD = 1mA LOAD = 5mA LOAD = 10mA LOAD = 50mA LOAD = 100mA LOAD = 200mA
3.315
1.815
VOUT (V)
3.310
VOUT (V)
1.810
3.305
1.805
02839-005
2.5
2.9
3.3
3.7 VIN (V)
4.1
4.5
4.9
5.3
VIN (V)
Figure 5. Output Voltage vs. Input Voltage
Figure 8. Output Voltage vs. Input Voltage
Rev. 0 | Page 7 of 20
02839-008
3.300 3.6
3.8
4.0
4.2
4.4
4.6
4.8
5.0
5.2
5.4
1.800 2.1
02839-007
3.300
1.800
1 10 100 1000
02839-006
ADP320
1.520 1.515 1.510 1.505
VOUT (V)
140
LOAD = 1mA LOAD = 5mA LOAD = 10mA LOAD = 50mA LOAD = 100mA LOAD = 200mA
120
GROUND CURRENT (A)
100 80
1.500 1.495 1.490 1.485 1.480 -40C -5C 25C
TJ (C)
60
40 20 LOAD = 1mA LOAD = 5mA LOAD = 10mA LOAD = 50mA LOAD = 100mA LOAD = 200mA
02839-012
85C
125C
02839-009
0 -40 -5 25 TJ (C) 85
125
Figure 9. Output Voltage vs. Junction Temperature
1.510
Figure 12. Ground Current vs. Junction Temperature, Single Output Loaded
120
1.508
GROUND CURRENT (A)
100
80
VOUT (V)
1.506
60
1.504
40
1.502
20
1.500 1 10 ILOAD (mA) 100 1000
02839-010
0 1 10 ILOAD (mA) 100 1000
02839-013
Figure 10. Output Voltage vs. Load Current
1.510
LOAD = 1mA LOAD = 5mA LOAD = 10mA LOAD = 50mA LOAD = 100mA LOAD = 200mA
Figure 13. Ground Current vs. Load Current, Single Output Loaded
120
1.508
100
GROUND CURRENT (A)
80
VOUT (V)
1.506
60
1.504
40
LOAD = 1mA LOAD = 5mA LOAD = 10mA LOAD = 50mA LOAD = 100mA LOAD = 200mA
02839-014
1.502
20
2.20
2.60
3.00
3.40
3.80
4.20
4.60
5.00
5.40
02839-011
1.500 1.80
0 1.8
2.2
2.6
3.0
3.4
3.8
4.2
4.6
5.0
5.4
VIN (V)
VIN (V)
Figure 11. Output Voltage vs. Input Voltage
Figure 14. Ground Current vs. Input Voltage, Single Output Loaded
Rev. 0 | Page 8 of 20
ADP320
350 300
GROUND CURRENT (A)
120
100
BIAS CURRENT (A)
LOAD = 1mA LOAD = 5mA LOAD = 10mA LOAD = 50mA LOAD = 100mA LOAD = 200mA -40 -5 25 TJ (C) 85 125
02839-015
250 200 150 100 50 0
80
60
40 LOAD = 1mA LOAD = 5mA LOAD = 10mA LOAD = 50mA LOAD = 100mA LOAD = 200mA
02839-018
02839-020
20
0 -40 -5 25 TJ (C) 85 125
Figure 15. Ground Current vs. Junction Temperature, All Outputs Loaded Equally
300
Figure 18. Bias Current vs. Junction Temperature, Single Output Loaded
100 90
250
80
BIAS CURRENT (A)
02839-016
GROUND CURRENT (A)
70 60 50 40 30 20
200
150
100
50
10
02839-019
0
1 10 100 1000 TOTAL LOAD CURRENT (mA)
0
1 10 ILOAD (mA) 100 1000
Figure 16. Ground Current vs. Load Current, All Outputs Loaded Equally
300
Figure 19. Bias Current vs. Load Current, Single Output Load
76
250
74
GROUND CURRENT (A)
BIAS CURRENT (A)
200
72
LOAD = 1mA LOAD = 5mA LOAD = 10mA LOAD = 50mA LOAD = 100mA LOAD = 200mA
150
70
100 LOAD = 1mA LOAD = 5mA LOAD = 10mA LOAD = 50mA LOAD = 100mA LOAD = 200mA
02839-017
68
50
66
0 1.7
2.1
2.5
2.9
3.3
3.7 VIN (V)
4.1
4.5
4.9
5.3
64 2.5
2.9
3.3
3.7
4.1 VIN (V)
4.5
4.9
5.3
Figure 17. Ground Current vs. Input Voltage, All Outputs Loaded Equally
Figure 20. Bias Current vs. Input Voltage, Single Output Load
Rev. 0 | Page 9 of 20
ADP320
0.9 0.8 3.6 3.8 4.2 4.4 4.8 5.5
350 300
GROUND CURRENT (A)
SHUTDOWN CURRENT (A)
0.7 0.6 0.5 0.4 0.3 0.2 0.1
250 200 150 100 50 0 3.10
LOAD = 1mA LOAD = 5mA LOAD = 10mA LOAD = 50mA LOAD = 100mA LOAD = 200mA
02839-024 02839-026 02839-025
02839-021
0 -50
-25
0
25
50
75
100
125
3.15
3.20
3.25
3.30 VIN (V)
3.35
3.40
3.45
3.50
TEMPERATURE (C)
Figure 21. Shutdown Current vs. Temperature at Various Input Voltages
100 90 80 70
Figure 24. Ground Current vs. Input Voltage (in Dropout), VOUT1 = 3.3 V
300
250
DROPOUT (mV)
60 50 40 30 20 10 1 10 LOAD (mA) 100 1000
02839-022
DROPOUT (mV)
200
150
100
50
0
0 1 10 LOAD (mA) 100 1000
Figure 22. Dropout Voltage vs. Load Current and Output Voltage, VOUT1 = 3.3 V
3.35 3.30 3.25 3.20 LOAD = 1mA LOAD = 5mA LOAD = 10mA LOAD = 50mA LOAD = 100mA LOAD = 200mA
Figure 25. Dropout Voltage vs. Load Current and Output Voltage, VOUT2 = 1.8 V
1.85 1.80 1.75 1.70
VOUT (V)
VOUT (V)
3.15 3.10 3.05 3.00 2.95 3.10
1.65 1.60 1.55 1.50 1.45 1.70 LOAD = 1mA LOAD = 5mA LOAD = 10mA LOAD = 50mA LOAD = 100mA LOAD = 200mA 1.80 1.90 VIN (V) 2.00 2.10
VIN (V)
Figure 23. Output Voltage vs. Input Voltage (In Dropout), VOUT1 = 3.3 V
02839-023
3.15
3.20
3.25
3.30
3.35
3.40
3.45
3.50
Figure 26. Output Voltage vs. Input Voltage (in Dropout), VOUT2 = 1.8 V
Rev. 0 | Page 10 of 20
ADP320
160 140 120
VRIPPLE = 50mV -10 VIN = 2.5V VOUT = 1.5V -20 COUT = 1F
0
200mA 100mA 10mA 1mA
GROUND CURRENT (A)
-30
PSRR (dB) LOAD = 1mA LOAD = 5mA LOAD = 10mA LOAD = 50mA LOAD = 100mA LOAD = 200mA
02839-027
100 80 60 40 20 0 1.70
-40 -50 -60 -70 -80 -90 10 100 1k 10k 100k 1M 10M
02839-030 02839-032 02839-031
-100
FREQUENCY (Hz)
1.80
1.90 VIN (V)
2.00
2.10
Figure 27. Ground Current vs. Input Voltage in Dropout), VOUT2 = 1.8 V
0 -10 -20 -30 200mA 100mA 10mA 1mA VRIPPLE = 50mV VIN = 2.8V VOUT = 1.8V COUT = 1F
Figure 30. Power Supply Rejection Ratio vs. Frequency, 1.5 V
0 -10 -20 -30
1.8V/200mA 1.8V/100mA 1.8V/10mA 1.2V/200mA 1.2V/100mA 1.2V/10mA VRIPPLE = 50mV 1V HEADROOM 1.8V PSRR 1.2 XTALK
PSRR (dB)
-50 -60 -70 -80 -90 100 1k 10k 100k 1M 10M
02839-028
PSRR (dB)
-40
-40 -50 -60 -70 -80 -90 -100 10
100 1k 10k 100k 1M 10M
-100 10
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 28. Power Supply Rejection Ratio vs. Frequency, 1.8 V
0 -10 -20 -30
PSRR (dB)
Figure 31. Power Supply Rejection Ratio vs. Frequency, Channel to Channel Crosstalk
10 3.3V 1.8V 1.5V
NOISE SPECTRAL DENSITY (nV/Hz)
02839-029
200mA 100mA 10mA 1mA
VRIPPLE = 50mV VIN = 4.3V VOUT = 3.3V COUT = 1F
1
-40 -50 -60 -70 -80 -90 -100 10 100 1k 10k 100k 1M 10M
0.1
0.01 10
100
1k FREQUENCY (Hz)
10k
100k
FREQUENCY (Hz)
Figure 29. Power Supply Rejection Ratio vs. Frequency, 3.3 V
Figure 32. Output Noise Spectral Density, VIN = 5 V, ILOAD = 10 mA
Rev. 0 | Page 11 of 20
ADP320
70 60 50 3.3V 1.8V 1.5V
1
ILOAD2
NOISE (V rms)
40 30
2
VOUT2
20 10
02839-036
02839-038 02839-037
0.01
0.1
1
10
100
1000
02839-033
0 0.001
CH1 200mA
B W
CH2 50mV
B W
M40s T 10.4%
A CH1
84mA
LOAD CURRENT (mA)
Figure 33. Output Noise vs. Load Current and Output Voltage, VIN = 5 V
Figure 36. Load Transient Response, ILOAD2 = 1 mA to 200 mA, COUT2 = 1 F, CH1 = ILOAD2, CH2 = VOUT2
ILOAD3
ILOAD1
1
1
2
VOUT1
2
VOUT3
VOUT2
3 4
VOUT3
CH1 100mA CH3 10mV
02839-034
B W B W
CH2 50mV CH4 10mV
B W B W
M40s A CH1 T 9.8%
44mA
CH1 200mA
B W
CH2 50mV
B W
M40s A CH1 T 10.2%
124mA
Figure 34. Load Transient Response, ILOAD1 = 1 mA to 200 mA, ILOAD2 = ILOAD3 = 1 mA, CH1 = ILOAD1, CH2 = VOUT1, CH3 = VOUT2 , CH4 = VOUT3
ILOAD1
Figure 37. Load Transient Response, ILOAD3 = 1 mA to 200 mA, COUT3 = 1 F, CH1 = ILOAD3, CH2 = VOUT3
VIN
1
1 2
VOUT1
2
VOUT1
VOUT2
3
4
VOUT3
02839-035
CH1 200mA
B W
CH2 50mV
B W
M40s T 10.2%
A CH1
124mA
CH1 1V CH3 10mV
B W B W
CH2 10mV CH4 10mV
B B
W W
M1s T 15%
A CH1
4.62V
Figure 35. Load Transient Response, ILOAD1 = 1 mA to 200 mA, COUT1 = 1 F, CH1 = ILOAD1, CH2 = VOUT1
Figure 38. Line Transient Response, VIN = 4 V to 5 V, ILOAD1 = ILOAD2 = ILOAD3 =100 mA, CH1 = VIN, CH2 = VOUT1, CH3 = VOUT2, CH4 = VOUT3
Rev. 0 | Page 12 of 20
ADP320
VIN
1 1 2
VEN
VOUT1
VOUT1
VOUT2 VOUT3
VOUT2
3
4
VOUT3
2
02839-039
CH1 1V CH3 10mV
B W B W
CH2 10mV CH4 10mV
B W B W
M2s T 12%
A CH1
4.58V
CH1 1V CH3 500mV
B
W B W
CH2 500mV CH4 500mV
B W B W
M100s A CH1 T 10.2%
540mV
Figure 39. Line Transient Response, VIN = 4 V to 5 V, ILOAD1 = ILOAD2 = ILOAD3 =1 mA, CH1 = VIN, CH2 = VOUT1, CH3 = VOUT2, CH4 = VOUT3
Figure 40. Turn On Response, ILOAD1 = ILOAD2 = ILOAD3 =100 mA, CH1 = VEN, CH2 = VOUT1, CH3 = VOUT2, CH4 = VOUT3
Rev. 0 | Page 13 of 20
02839-040
ADP320 THEORY OF OPERATION
The ADP320 triple LDO is a low quiescent current, low dropout linear regulator that operates from 1.8 V to 5.5 V on VIN1/VIN2 and VIN3 and provides up to 200 mA of current from each output. Drawing a low 250 A quiescent current (typical) at full load makes the ADP320 triple LDO ideal for battery-operated portable equipment. Shutdown current consumption is typically 100 nA. Optimized for use with small 1 F ceramic capacitors, the ADP320 triple LDO provides excellent transient performance.
VIN1/VIN2 VOUT1
Internally, the ADP320 triple LDO consist of a reference, three error amplifiers, three feedback voltage dividers, and three PMOS pass transistors. Output current is delivered via the PMOS pass device, which is controlled by the error amplifier. The error amplifier compares the reference voltage with the feedback voltage from the output and amplifies the difference. If the feedback voltage is lower than the reference voltage, the gate of the PMOS device is pulled lower, allowing more current to flow and increasing the output voltage. If the feedback voltage is higher than the reference voltage, the gate of the PMOS device is pulled higher, allowing less current to flow and decreasing the output voltage. The ADP320 triple LDO is available in multiple output voltage options ranging from 0.8 V to 3.3 V. The ADP320 triple LDO uses the EN1, EN2, and EN3 enable pins to enable and disable the VOUT1/VOUT2/VOUT3 pins under normal operating conditions. When the enable pins are high, VOUT1/VOUT2/ VOUT3 turn on; when enable pins are low, VOUT1/VOUT2/ VOUT3 turn off. For automatic startup, the enable pins can be tied to VBIAS.
VBIAS
INTERNAL BIAS VOLTAGES/CURRENTS, UVLO AND THERMAL PROTECT SHUTDOWN VOUT1 SHUTDOWN VOUT2 SHUTDOWN VOUT3
OVERCURRENT 0.5V REF VOUT2
EN1 EN2
OVERCURRENT 0.5V REF VOUT3
EN3
VIN3
GND OVERCURRENT
02839-041
0.5V REF
Figure 41. Internal Block Diagram
Rev. 0 | Page 14 of 20
ADP320 APPLICATIONS INFORMATION
CAPACITOR SELECTION
Output Capacitor
The ADP320 triple LDO is designed for operation with small, space-saving ceramic capacitors, but the parts function with most commonly used capacitors as long as care is taken in regards to the effective series resistance (ESR) value. The ESR of the output capacitor affects stability of the LDO control loop. A minimum of 0.70 F capacitance with an ESR of 1 or less is recommended to ensure stability of the ADP320 triple LDO. Transient response to changes in load current is also affected by output capacitance. Using a larger value of output capacitance improves the transient response of the ADP320 triple LDO to large changes in the load current. Figure 42 show the transient response for an output capacitance value of 1 F.
Input Bypass Capacitor
Connecting a 1 F capacitor from VIN1/VIN2, VIN3, and VBIAS to GND reduces the circuit sensitivity to the PCB layout, especially when long input traces or high source impedance are encountered. If an output capacitance greater than 1 F is required, the input capacitor should be increased to match it.
Input and Output Capacitor Properties
Any good quality ceramic capacitor may be used with the ADP320 triple LDO, as long as the capacitor meets the minimum capacitance and maximum ESR requirements. Ceramic capacitors are manufactured with a variety of dielectrics, each with a different behavior over temperature and applied voltage. Capacitors must have an adequate dielectric to ensure the minimum capacitance over the necessary temperature range and dc bias conditions. X5R or X7R dielectrics with a voltage rating of 6.3 V or 10 V are recommended. Y5V and Z5U dielectrics are not recommended, due to their poor temperature and dc bias characteristics. Figure 43 depicts the capacitance vs. voltage bias characteristic of an 0402 1 F, 10 V, X5R capacitor. The voltage stability of a capacitor is strongly influenced by the capacitor size and voltage rating. In general, a capacitor in a larger package or higher voltage rating exhibits better stability. The temperature variation of the X5R dielectric is about 15% over the -40C to +85C temperature range and is not a function of the package or voltage rating.
1.2
ILOAD1
1
2
VOUT1
VOUT2
3 4
VOUT3
CH1 100mA CH3 10mV
BW
B W
CH2 50mV CH4 10mV
B W B W
M40s T 9.8%
A CH1
44mA
02839-042
1.0
CAPACITANCE (F)
Figure 42. Output Transient Response, ILOAD1 = 1 mA to 200 mA, ILOAD2 = 1 mA, ILOAD3 = 1 mA, CH1 = ILOAD1, CH2 = VOUT1, CH3 = VOUT2 , CH4 = VOUT3
0.8
0.6
0.4
0.2
0
2
4 6 VOLTAGE (V)
8
10
Figure 43. Capacitance vs. Voltage Bias Characteristic
Rev. 0 | Page 15 of 20
02839-043
0
ADP320
Use Equation 1 to determine the worst-case capacitance accounting for capacitor variation over temperature, component tolerance, and voltage. CEFF = CBIAS x (1 - TEMPCO) x (1 - TOL) where: CBIAS is the effective capacitance at the operating voltage. TEMPCO is the worst-case capacitor temperature coefficient. TOL is the worst-case component tolerance. In this example, TEMPCO over -40C to +85C is assumed to be 15% for an X5R dielectric. TOL is assumed to be 10%, and CBIAS is 0.94 F at 1.8 V from the graph in Figure 43. Substituting these values into Equation 1 yields
ENABLE THRESHOLDS
As shown in Figure 44, the ENx pin has built-in hysteresis. This prevents on/off oscillations that can occur due to noise on the ENx pin as it passes through the threshold points. The active/inactive thresholds of the ENx pin are derived from the VBIAS voltage. Therefore, these thresholds vary with changing input voltage. Figure 45 shows typical ENx active/ inactive thresholds when the input voltage varies from 2.5 V to 5.5 V.
1.00 0.95 0.90 0.85 0.80 VEN RISE 0.75 0.70 0.65 0.60 0.55 3.0 3.5 4.0 4.5 5.0 5.5
02839-053
(1)
CEFF = 0.94 F x (1 - 0.15) x (1 - 0.1) = 0.719 F Therefore, the capacitor chosen in this example meets the minimum capacitance requirement of the LDO over temperature and tolerance at the chosen output voltage. To guarantee the performance of the ADP320 triple LDO, it is imperative that the effects of dc bias, temperature, and tolerances on the behavior of the capacitors are evaluated for each application.
VEN FALL
UNDERVOLTAGE LOCKOUT
The ADP320 triple LDO has an internal undervoltage lockout circuit that disables all inputs and the output when the input voltage bias, VBIAS, is less than approximately 2.2 V. This ensures that the inputs of the ADP320 triple LDO and the output behave in a predictable manner during power-up.
0.50 2.5
INPUT VOLTAGE (V)
Figure 45. Typical ENx Pins Thresholds vs. Input Voltage
ENABLE FEATURE
The ADP320 triple LDO uses the ENx pins to enable and disable the VOUTx pins under normal operating conditions. Figure 44 shows a rising voltage on EN crossing the active threshold, then VOUTx turns on. When a falling voltage on ENx crosses the inactive threshold, VOUTx turns off.
The ADP320 triple LDO utilizes an internal soft start to limit the inrush current when the output is enabled. The start-up time for the 2.8 V option is approximately 220 s from the time the ENx active threshold is crossed to when the output reaches 90% of its final value. The start-up time is somewhat dependent on the output voltage setting and increases slightly as the output voltage increases.
VEN
VOUT1
1
1.4 VOUT2 1.2 1.0 0.8
VOUT (V)
VOUT @ 4.5VIN
VOUT3
0.6 0.4 0.2 0 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2
02839-054
2
CH1 1V CH3 500mV
B W B W
CH2 500mV CH4 500mV
B W B W
M100s A CH1 T 10.2%
540mV
Figure 46. Typical Start-Up Time, ILOAD1 = ILOAD2 = ILOAD3 = 100 mA, CH1 = VEN, CH2 = VOUT1, CH3 = VOUT2, CH4 = VOUT3
ENABLE VOLTAGE (V)
Figure 44. Typical ENx Pin Operation
Rev. 0 | Page 16 of 20
02839-046
ADP320
CURRENT-LIMIT AND THERMAL OVERLOAD PROTECTION
The ADP320 triple LDO is protected against damage due to excessive power dissipation by current and thermal overload protection circuits. The ADP320 triple LDO is designed to current limit when the output load reaches 300 mA (typical). When the output load exceeds 300 mA, the output voltage is reduced to maintain a constant current limit. Thermal overload protection is built-in, which limits the junction temperature to a maximum of 155C (typical). Under extreme conditions (that is, high ambient temperature and power dissipation) when the junction temperature starts to rise above 155C, the output is turned off, reducing the output current to zero. When the junction temperature drops below 140C, the output is turned on again and the output current is restored to its nominal value. Consider the case where a hard short from VOUTx to GND occurs. At first, the ADP320 triple LDO current limits, so that only 300 mA is conducted into the short. If self-heating of the junction is great enough to cause its temperature to rise above 155C, thermal shutdown activates turning off the output and reducing the output current to zero. As the junction temperature cools and drops below 140C, the output turns on and conducts 300 mA into the short, again causing the junction temperature to rise above 155C. This thermal oscillation between 140C and 154C causes a current oscillation between 0 mA and 300 mA that continues as long as the short remains at the output. Current and thermal limit protections are intended to protect the device against accidental overload conditions. For reliable operation, device power dissipation must be externally limited so junction temperatures do not exceed 125C. To guarantee reliable operation, the junction temperature of the ADP320 triple LDO must not exceed 125C. To ensure that the junction temperature stays below this maximum value, the user needs to be aware of the parameters that contribute to junction temperature changes. These parameters include ambient temperature, power dissipation in the power device, and thermal resistances between the junction and ambient air (JA). The JA number is dependent on the package assembly compounds used and the amount of copper to which the GND pins of the package are soldered on the PCB. Table 6 shows typical JA values for the ADP320 triple LDO for various PCB copper sizes. Table 6. Typical JA Values
Copper Size (mm2) JEDEC1 100 500 1000
1
ADP320 Triple LDO (C/W) 49.5 83.7 68.5 64.7
Device soldered to JEDEC standard board.
The junction temperature of the ADP320 triple LDO can be calculated from the following equation: TJ = TA + (PD x JA) where: TA is the ambient temperature. PD is the power dissipation in the die, given by PD = [(VIN - VOUT) x ILOAD] + (VIN x IGND) where: ILOAD is the load current. IGND is the ground current. VIN and VOUT are input and output voltages, respectively. Power dissipation due to ground current is quite small and can be ignored. Therefore, the junction temperature equation simplifies to TJ = TA + {[(VIN - VOUT) x ILOAD] x JA} (4) As shown in Equation 4, for a given ambient temperature, input-to-output voltage differential, and continuous load current, there exists a minimum copper size requirement for the PCB to ensure the junction temperature does not rise above 125C. Figure 47 to Figure 50 show junction temperature calculations for different ambient temperatures, total power dissipation, and areas of PCB copper. In cases where the board temperature is known, the thermal characterization parameter, JB, may be used to estimate the junction temperature rise. TJ is calculated from TB and PD using the formula TJ = TB + (PD x JB) The typical JB value for the 16-lead 3 mm x 3 mm LFCSP is 25.2C/W. (5) (3) (2)
THERMAL CONSIDERATIONS
In most applications, the ADP320 triple LDO does not dissipate a lot of heat due to high efficiency. However, in applications with a high ambient temperature and high supply voltage to output voltage differential, the heat dissipated in the package is large enough that it can cause the junction temperature of the die to exceed the maximum junction temperature of 125C. When the junction temperature exceeds 155C, the converter enters thermal shutdown. It recovers only after the junction temperature has decreased below 140C to prevent any permanent damage. Therefore, thermal analysis for the chosen application is very important to guarantee reliable performance over all conditions. The junction temperature of the die is the sum of the ambient temperature of the environment and the temperature rise of the package due to the power dissipation, as shown in Equation 2.
Rev. 0 | Page 17 of 20
ADP320
140 120
JUCTION TEMPERATURE, TJ (C)
140 120
JUCTION TEMPERATURE, TJ (C)
100 80 60 40 20 0 0 0.2 0.4 0.6 0.8 TOTAL POWER DISSIPATION (W)
100 80 60 40 20 0 0 0.2 0.4 0.6 0.8 TOTAL POWER DISSIPATION (W)
02839-047
1.0
1.2
1.0
1.2
Figure 47. Junction Temperature vs. Total Power Dissipation, TA = 25C
140 120
Figure 49. Junction Temperature vs. Total Power Dissipation, TA = 85C
140 120 100 80 60 40 20 0 TB = 25C TB = 50C TB = 85C TJ MAX 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8
02839-050
JUCTION TEMPERATURE, TJ (C)
100 80 60 40 20 0 0 0.2 0.4 0.6 0.8 TOTAL POWER DISSIPATION (W)
1000mm 2 500mm 2 100mm 2 50mm 2 JEDEC TJ MAX
02839-048
1.0
1.2
JUCTION TEMPERATURE, TJ (C)
TOTAL POWER DISSIPATION (W)
Figure 48. Junction Temperature vs. Total Power Dissipation, TA = 50C
Figure 50. Junction Temperature vs. Total Power Dissipation and Board Temperature
Rev. 0 | Page 18 of 20
02839-049
1000mm 2 500mm 2 100mm 2 50mm 2 JEDEC TJ MAX
1000mm 2 500mm 2 100mm 2 50mm 2 JEDEC TJ MAX
ADP320
PRINTED CIRCUIT BOARD LAYOUT CONSIDERATIONS
Heat dissipation from the package can be improved by increasing the amount of copper attached to the pins of the ADP320 triple LDO. However, as can be seen from Table 6, a point of diminishing returns eventually is reached, beyond which an increase in the copper size does not yield significant heat dissipation benefits. Place the input capacitor as close as possible to the VINx and GND pins. Place the output capacitors as close as possible to the VOUTx and GND pins. Use 0402 or 0603 size capacitors and resistors to achieve the smallest possible footprint solution on boards where area is limited.
02839-051
Figure 51. Example of PCB Layout, Top Side
Figure 52. Example of PCB Layout, Bottom Side
Rev. 0 | Page 19 of 20
02839-052
ADP320 OUTLINE DIMENSIONS
PIN 1 INDICATOR 3.10 3.00 SQ 2.90 0.50 BSC 0.30 0.25 0.20
13 12 EXPOSED PAD 16 1
PIN 1 INDICATOR
1.65 1.50 SQ 1.45
4 5
9
TOP VIEW 0.80 0.75 0.70 SEATING PLANE
0.50 0.40 0.30
8
0.20 MIN
BOTTOM VIEW
0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF
FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MO-229.
Figure 53. 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 3 mm x 3 mm Body, Very, Very Thin Quad (CP-16-27) Dimensions shown in millimeters
ORDERING GUIDE
Model 1 ADP320ACPZ331815R7
1 2
Temperature Range
-40C to +125C
Output Voltage (V) 2 3.3, 1.8, 1.5
Package Description
16-Lead LFCSP_WQ
Package Option CP-16-27
091609-A
Branding LGP
Z = RoHS Compliant Part.
For additional voltage options, contact a local sales or distribution representative.
(c)2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D02839-0-6/10(0)
Rev. 0 | Page 20 of 20

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