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STA015
MPEG 2.5 LAYER III AUDIO DECODER WITH ADPCM CAPABILITY
SINGLE CHIP MPEG2 LAYER 3 DECODER SUPPORTING: - All features specified for Layer III in ISO/IEC 11172-3 (MPEG 1 Audio) - All features specified for Layer III in ISO/IEC 13818-3.2 (MPEG 2 Audio) - Lower sampling frequencies syntax extension, (not specified by ISO) called MPEG 2.5 DECODES LAYER III STEREO CHANNELS, DUAL CHANNEL, SINGLE CHANNEL (MONO) SUPPORTING ALL THE MPEG 1 & 2 SAMPLING FREQUENCIES AND THE EXTENSION TO MPEG 2.5: 48, 44.1, 32, 24, 22.05, 16, 12, 11. 025, 8 KHz ACCEPTS MPEG 2.5 LAYER III ELEMENTARY COMPRESSED BITSTREAM WITH DATA RATE FROM 8 Kbit/s UP TO 320 Kbit/s ADPCM CODEC CAPABILITIES: - sample frequency from 8 kHz to 32 kHz - sample size from 8 bits to 32 bits - encoding algorithm: DVI, ITU-G726 pack (G723-24, G721,G723-40) - Tone control and fast-forward capability EASY PROGRAMMABLE GPSO INTERFACE FOR ENCODED DATA UP TO 5Mbit/s (TQFP44 & LFBGA 64) DIGITAL VOLUME CONTROL DIGITAL BASS & TREBLE CONTROL BYPASS MODE FOR EXTERNAL AUDIO SOURCE SERIAL BITSTREAM INPUT INTERFACE EASY PROGRAMMABLE ADC INPUT INTERFACE ANCILLARY DATA EXTRACTION VIA I2C INTERFACE. SERIAL PCM OUTPUT INTERFACE (I2S AND OTHER FORMATS) PLL FOR INTERNAL CLOCK AND FOR OUTPUT PCM CLOCK GENERATION CRC CHECK AND SYNCHRONISATION ERROR DETECTION WITH SOFTWARE
LFBGA64 SO28 TQFP44
ORDERING NUMBER: STA015$ (SO28) STA015T$ (TQFP44) STA015B$ (LFBGA 8x8)
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APPLICATIONS PC SOUND CARDS MULTIMEDIA PLAYERS VOICE RECORDERS DESCRIPTION The STA015 is a fully integrated high flexibility MPEG Layer III Audio Decoder, capable of decoding Layer III compressed elementary streams, as specified in MPEG 1 and MPEG 2 ISO standards. The device decodes also elementary streams compressed by using low sampling rates, as specified by MPEG 2.5. STA015 receives the input data through a Serial input Interface. The decoded signal is a stereo, mono, or dual channel digital output that can be sent directly to a D/A converter, by the PCM Output Interface. This interface is software programmable to adapt the STA015 digital output to the most common DACs architectures used on the market. The functional STA015 chip partitioning is described in Fig.1a and Fig.1b.
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INDICATORS I2C CONTROL BUS LOW POWER 2.4V CMOS TECHNOLOGY WIDE RANGE OF EXTERNAL CRYSTALS FREQUENCIES SUPPORTED
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April 2010
STA015
Figure 1. 1a. Block Diagram for TQFP44 and LFBGA64 package.
SDA 31
SCL 32 35 20 18 STROBE
TQFP44
I2C CONTROL 34 36 38 SERIAL INPUT INTERFACE GPIO INTERFACE DSP BASED
16 14 37 39 41 43 IODATA [7:0]
SDI SCKR BIT_EN
DATA-REQ
27
BUFFER 256 x 8
PARSER
MPEG L III ADPCM CORE
VOLUME & TONE CONTROL
OUTPUT BUFFER PCM OUTPUT INTERFACE
42 44 2 3 4
SDO SCKT LRCKT OCLK
SCK_ADC LRCK_ADC SDI_ADC
40 26 24 ADC INPUT INTERFACE
SYSTEM & AUDIO CLOCKS GPSO INTERFACE 25 RESET 15 XTI 13 XTO 22 TESTEN 12 FILT
1b. BLOCK DIAGRAM for SO28 package
3
SO28
SDI SCKR BIT_EN
5 6 7 SERIAL INPUT INTERFACE
GPSO_SCKR SCK_ADC
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LRCK_ADC SDI_ADC
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28 8 27 25 ADC INPUT INTERFACE
BUFFER 256 x 8
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26 RESET
s) (
PARSER
-O
4 MPEG L III ADPCM CORE
SDA
SCL
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DSP BASED VOLUME & TONE CONTROL
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D99AU1116B
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28 33
GPSO_REQ
GPSO_SCKR GPSO_DATA
(s) ct
I2C CONTROL
9 OUTPUT BUFFER PCM OUTPUT INTERFACE 10 11 12
SDO SCKT LRCKT OCLK
SYSTEM & AUDIO CLOCKS
21 XTI
20 XTO
24 TESTEN
19 FILT
D99AU1117B
STA015
Figure 2. Pin Connection
VDD_1 VSS_1 SDA SCL SDI SCKR BIT_EN SRC_INT/SCK_ADC SDO SCKT LRCKT OCLK VSS_2 VDD_2
1 2 3 4 5 6 7 8 9 10 11 12 13 14
D99AU1061A
SRC_INT/SCK_ADC
28 27 26 25 24 23 22 21 20 19 18 17 16 15
GPSO_SCKR LRCK_ADC RESET SDI_ADC TESTEN VDD_4 VSS_4 XTI XTO FILT PVSS PVDD VDD_3 VSS_3
44
43
42
41
40
39
38
37
36
35
34 33 32 31 30 29 28 27 26 25 24 23
N.C. LRCKT OCLK GPSO_REQ VSS_2 VDD_2 VSS_3 VDD_3 N.C. PVDD PVSS
1 2 3 4 5 6 7 8 9 10 11
GPSO_DATA SCL SDA
VSS_1
8 A B C
7
6
5
4
3
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D
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2 1
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12 13 14 15 16
17
18
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19 20 21
so
N.C.
D99AU1062
VDD_1
GPSO_SCKR
OUT_CLK/DATA_REC LRCK_ADC RESET SDI_ADC
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GPIO/STROBE
IODATA[7]
IODATA[6]
IODATA[5]
IODATA[4]
BIT_EN
(s) ct
SCKR
SCKT
SDO
22
VSS_4
VDD_4
XTO
N.C.
XTI
IODATA[3]
IODATA[2]
IODATA[1]
IODATA[0]
A1 = SDI B2 = SCKR D4 = BIT_EN D1 = SRC_INT E2 = SDO F2 = SCKT H1 = LRCKT H3 = OCLK F3 = VSS_2 E4 = VDD_2 G4 = VSS_3 G5 = VDD_3 F5 = PVDD G6 = PVSS
G7 = FILT G8 = XTO F7 = XTI E7 = VSS_4 C8 = VDD_4 D7 = TESTEN A7 = SDI_ADC B6 = RESET A5 = LRCK_ADC C5 = OUT_CLK/DATA_REQ B5 = VDD_1 B4 = VSS_1 A4 = SDA B3 = SCL
TESTEN
FILT
SDI
C2 = GPIO_STROBE C3 = IODATA [4] E3 = IODATA [5] D2 = IODATA [6] F1 = IODATA [7] G3 = GPSO_REQ F8 = IODATA [3] F6 = IODATA [2] E6 = IODATA [1] C7 = IODATA [0] C6 = GPSO_SCKR A2 = GPSO_DATA
D00AU1149
LFBGA64
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STA015
1.0 OVERVIEW 1.1 MP3 decoder engine The MP3 decoder engine is able to decode any Layer III compliant bitstream: MPEG1, MPEG2 and MPEG2.5 streams are supported. Besides audio data decoding the MP3 engine also performs ANCILLARY data extraction: these data can be retrieved via I2C bus by the application microcontroller in order to implement specific functions. Decoded audio data goes through a software volume control and a two-band equalizer blocks before feeding the output I2S interface. This results in no need for an external audio processor. MP3 bitstream is sent to the decoder using a simple serial input interface (see pins SDI, SCKR, BIT_EN and DATA_REQ), supporting input rate up to 20 Mbit/s. Received data are stored in a 256 bytes long input buffer which provides a feedback line (see DATA_REQ pin) to the bitstream source (tipically an MCU). 1.2 ADPCM encoder/decoder engine
This device also embeds a multistandard ADPCM encoder/decoder supporting different sample rates (from 8 KHz up to 32 KHz) and different sample sizes (from 8 bit to 32 bits).
During encoding process two different interfaces can be used to feed data: the serial input interface (same interface used also to feed MP3 bitstream) or the ADC input interface, which provides a seamless connection with an external A/D converter. The currently used interface is selected via I2C bus.
Also to retrieve encoded data two different interfaces are available: the I2C bus or the faster GPSO output interface. GPSO interface is able to output data with a bitrate up to 5 Mbit/s and its control pins (GPSO_SCKR, GPSO_DATA and GPSO_REQ) can be configured in order to easily fit the target application. 1.3 BYPASS functional mode
In order to allow using the device to post-process auxiliary audio sources a special BYPASS mode is available. When the device is configured in BYPASS mode the embedded DSP will process digital audio data coming through the ADC input interface and will output the resulting data to the external DAC. Available processings include volume and a tone ontrols. THERMAL DATA
Symbol Rth j-amb
Thermal resistance Junction to Ambient
ABSOLUTE MAXIMUM RATINGS
Symbol
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T
VDD Vi
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t(s c
Parameter
-O )
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Value 85
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Unit C/W
Parameter
Value -0.3 to 4 -0.3 to VDD +0.3 -0.3 to VDD +0.3 -40 to +150 -20 to +85
Unit V V V C C
Power Supply
Voltage on Input pins Voltage on output pins Storage Temperature Operative ambient temp
VO
Tstg
oper
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STA015
PIN DESCRIPTION
SO28 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 TQFP44 29 30 31 32 34 36 38 40 42 44 2 3 5 6 7 8 10 11 12 13 15 19 21 22 24 25 26 27 LFBGA64 B5 B4 A4 B3 A1 B2 D4 D1 E2 F2 H1 H3 F3 E4 G4 G5 F5 G6 G7 G8 F7 E7 C8 D7 A7 B6 Pin Name VDD_1 VSS_1 SDA SCL SDI SCKR BIT_EN SRC_INT/ SCK_ADC SDO SCKT LRCKT OCLK VSS_2 VDD_2 VSS_3 VDD_3 PVDD PVSS FILT XTO XTI VSS_4 VDD_4 TESTEN Type Function Supply Voltage Ground i2C Serial Data + Acknowledge I2C Serial Clock Receiver Serial Data Receiver Serial Clock Bit Enable Interrupt Line/ADC Serial Clock Transmitter Serial Data (PCM Data) Transmitter Serial Clock Transmitter Left/Right Clock Oversampling Clock for DAC Ground Supply Voltage Ground Supply Voltage PLL Power PLL Ground PLL Filter Ext. Capacitor Conn. Crystal Output Crystal Input (Clock Input) PAD Description
I/O I I I I I O O O I/O
CMOS Input Pad Buffer CMOS 4mA Output Drive CMOS Input Pad Buffer CMOS Input Pad Buffer CMOS Input Pad Buffer CMOS Input Pad Buffer with pull up CMOS Input Pad Buffer CMOS 4mA Output Drive
CMOS 4mA Output Drive CMOS 4mA Output Drive CMOS Input Pad Buffer CMOS 4mA Output Drive
O O I
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Note:
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20 18 16 14 37 39 41 43 35 4 28 33
A5 C5
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C7 E6 F6 F8 C3 E3 D2 F1 C2 G3 C6 A2
LRCK_ADC IN_CLK/ DATA_REQ IODATA[0] IODATA[1] IODATA[2] IODATA[3] IODATA[4] IODATA[5] IODATA[6] IODATA[7] GPIO_STROBE GPSO_REQ GPSO_SCKR GPSO_DATA
ct
SDI_ADC RESET
)(s
I I I
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(s) ct
CMOS 4mA Output Drive Specific Level Input Pad (see paragraph 2.1)
Ground Supply Voltage Test Enable ADC Data Input System Reset
I O I/O I/O I/O I/O I/O I/O I/O I/O I/O O I O
ADC left/Right Clock Buffered Output Clock/ Data Request Signal GPIO Data Line GPIO Data Line GPIO Data Line GPIO Data Line GPIO Data Line GPIO Data Line GPIO Data Line GPIO Data Line GPIO Strobe Signal GPSO Request Signal GPSO Serial Clock GPSO Serial Data
CMOS Input Pad Buffer with pull up CMOS Input Pad Buffer CMOS Input Pad Buffer with pull up CMOS Output Pad Buffer CMOS 4mA Output Drive CMOS 4mA Schmitt Trigger Bidir Pad Buffer
CMOS Output Pad Buffer CMOS Input Pad Buffer CMOS Output Pad Buffer
In functional mode TESTEN must be connected to VDD,
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STA015
ELECTRICAL CHARACTERISTICS: VDD = 3.3V 0.3V; Tamb = 0 to 70C; Rg = 50 unless otherwise specified DC OPERATING CONDITIONS
Symbol VDD Tj Power Supply Voltage Operating Junction Temperature Parameter Value 2.4 to 3.6V -20 to 125C
GENERAL INTERFACE ELECTRICAL CHARACTERISTICS
Symbol IIL IIH Vesd Parameter Low Level Input Current Without pull-up device High Level Input Current Without pull-up device Electrostatic Protection Test Condition Vi = 0V Vi = VDD Leakage < 1A Min. -10 -10 2000 Typ. Max. 10 10 Unit A A V Note 1 1 2
Notes: 1. The leakage currents are generally very small, < 1nA. The value given here is a maximum that can occur after an electrostatic stress on the pin. 2. Human Body Model.
DC ELECTRICAL CHARACTERISTICS
Symbol VIL VIH Vol Voh Parameter Low Level Input Voltage High Level Input Voltage Low Level Output Voltage High Level Output Voltage Iol = Xma Test Condition
Min.
Notes: 1. Takes into account 200mV voltage drop in both supply lines. 2. X is the source/sink current under worst case conditions and is reflected in the name of the I/O cell according to the drive capability.
Symbol Ipu Rpu
Parameter Pull-up current
Notes: 1. Min. condition: VDD = 2.7V, 125C Min process Max. condition: VDD = 3.6V, -20C Max.
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POWER DISSIPATION
Symbol
ro P e
Equivalent Pull-up Resistance
du
t(s c
-O )
so b
0.8*VDD
Pr ete l
Typ. Max. 0.2*VDD 0.4V Typ. -66 50 Max. -125
du o
Unit V V V V
(s) ct
Note
1, 2 1, 2
0.85*VDD
Test Condition
Min. -25
Unit A k
Note 1
Vi = 0V; pin numbers 7, 24 and 26;
Parameter Power Dissipation @ VDD = 2.4V
Test Condition Sampling_freq 24 kHz Sampling_freq 32 kHz Sampling_freq 48 kHz
Min.
Typ 76 79 85
Max
Unit mW mW mW
Note
STA015
Figure 3. Test Circuit
3 4 9 10 11 12 5 13 16 6 7 25 8 27 21 20 19 17 4.7F 100nF 18 26 RESET 24 TESTEN 470pF VSS PVSS PVDD PVSS SDA SCL SDO SCKT LRCKT OCLK SDI SCKR BIT_EN SDI_ADC SCR_INT LRCK_ADC XTI XTO 10K
OUT_CLK/DATA_REQ VDD 100nF VSS VDD 100nF VSS VDD 100nF VSS VDD 100nF VDD 4.7F PVDD VSS
28 1
2 14
15 23
22
1K
4.7nF
D00AU1143
Figure 4. Test Load Circuit
VDD IOL
Test Load
Output
OUTPUT
VREF CL IOH
2.0 FUNCTIONAL DESCRIPTION 2.1 Clock Signal
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The STA015 input clock is derivated from an external source or from a industry standard crystal oscillator, generating input frequencies of 10, 14.31818 or 14.7456 MHz. Other frequencies may be supported upon request to STMicroelectronics. Each frequency is supported by downloading a specific configuration file, provided by STM XTI is an input Pad with specific levels.
Symbol VIL VIH Parameter Low Level Input Voltage High Level Input Voltage VDD-0.8 Test Condition Min. Typ. Max. VDD-1.8 Unit V V
Pr e
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t(s c
D98AU967
-O )
SDA
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PVSS
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VREF
3.6V 1.5V
(s) ct
IOL
IOH
CL
1mA 100A
100pF 100pF
Other Outputs
100A
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STA015
CMOS compatibility The XTI pad low and high levels are CMOS compatible; XTI pad noise margin is better than typical CMOS pads. TTL compatibility The XTI pad low level is compatible with TTL while the high level is not compatible (for example if VDD = 3V TTL min high level = 2.0V while XTI min high level = 2.2V) 2.2 PLL & Clock Generator System When STA015 receives the input clock, as described in Section 2.1, and a valid layer III input bit stream, the internal PLL locks, providing to the DSP Core the master clock (DCLK), and to the Audio Output Interface the nominal frequencies of the incoming compressed bit stream. The STA015 PLL block diagram is described in Figure 5. The audio sample rates are obtained dividing the oversampling clock (OCLK) by software programmable factors. The operation is done by STA015 embedded software and it is transparent to the user.
The STA015 PLL can drive directly most of the ommercial DACs families, providing an over sampling clock, OCLK, obtained dividing the VCO frequency with a software programmable dividers. Figure 5. PLL and Clocks Generation System
2.3 STA015 Operational Modes
The device can be configured in 4 different operational modes. To select one specific mode a dedicated CHIP_MODE registers is available. For proper operation the following steps must be issued to switch between different modes: - issue a software reset (SOFT_RESET register) - select the desired mode (CHIP_MODE register) - run the device (RUN register) Hereby is a short description of each available mode ADPCM Encoder This mode can be used to encode the incoming bitstream with 4 different compression algorithms. Moreover different sample frequencies and word size are supported. For a detailed escription of this features refer to the related registers. ADPCM Decoder This mode can be used when an ADPCM compressed bitstream must be decoded. The input interface handling and control flow is the same as in the MP3 Mode. BYPASS mode Using this mode it's possible to use the embedded post-processing controls (volume and tone controls) to process an incoming uncompressed stereo audio stream. In this configuration ADC input is the only
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STA015
supported interface. This could be useful, for instance, to process audio data coming from an external tuner or some other auxiliary source. MP3 mode In MP3 Mode (default mode) STA015 decodes the incoming bitstream, acting as a master of the data communication from the source to itself. This control is done by a specific buffer management, controlled by STA015 embedded oftware. The data coming from the serial interface are stored in the input buffer, a 256 bytes long FIFO. The feedback line DATA_REQ actually is the result of the h/w comparison between the writing address of the FIFO and the constant value 252. This means that if the buffer is filled up with more than 252 bytes the DATA_REQ line goes low, requesting MCU to stop transmission: the maximum time to stop transmitting is given by the time required to transmit 4 bytes (this time, in turn, depends on the bitstream speed used to send MP3 data). The input interface can receive data with a speed up to 20Mbit/s. The speed at which the FIFO is emptied is equal to the MP3 nominal bitrate. Provided the FIFO is filled up with 252 bytes the time required to empty it (in worst condition, which is 320kbit/s mpeg stream) is about 6ms. So if no more data is received in this time the buffer will be emptied and this will badly affect the output audio.
In this mode the fractional part of the PLL is disabled and the audio clocks are generated at nominal rates. Fig. 6 describes the default DATA_REQ signal behaviour. Programming STA015 it is possible to invert the polarity of the DATA_REQ line (register REQ_POL). In order to allow proper operation of the device in broadcast applications a special BRAODCAST MP3 decoding mode is available. When configured in BROADCAST mode the device will operate as a slave decoder and no more feedback will be generated to the data source.
The output PCM clock will be automatically adjusted by the embedded DSP in order to follow the incoming bitstream rate and to avoid input buffer underrun/overrun. A special configuration file must be used to enable this operational mode: the file must be downloaded via I2C link after device power-on. Please contact your local ST branch to have more information about. Figure 6. DATA_REQ control line
SOURCE STOPS TRANSMITTING DATA DATA_REQ
2.4 STA015 Decoding States
There are three different decoder states: Idle, Init, and Decode. Commands to change the decoding states are described in the STA015 I2C registers description. Idle Mode
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IIn this mode (entered after a S/W or H/W reset) the decoder is waiting for the RUN command. This mode should be used to initialize the configuration registers of the device. The DAC connected to STA015 can be initialized during this mode (set MUTE to 1). MUTE to 1). PLAY
X X
Pr e
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t(s c
SOURCE SEND DATA TO STA015
-O )
so b
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D00AU1144
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(s) ct
SOURCE STOPS TRANSMITTING DATA
MUTE
0 1
Clock State
Not Running Running
PCM Output
0 0
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Init Mode "PLAY" and "MUTE" changes are ignored in this mode. The internal state of the decoder will be updated only when the decoder changes from the state "init" to the state "decode". The "init" phase ends when the first decoded samples are at the output stage of the device. Decode Mode This mode is completely described by the following table:
PLAY 0 0 1 1 MUTE 0 1 0 1 Clock State Not Running Running Running Running PCM Output 0 0 Decoded Samples 0 Decoding No No Yes Yes
Figure 7. MPEG Decoder Interface
P
XTI XTO FILT IIC
SCL
SDA
DATA_REQ SDI DATA SOURCE SCKR BIT_EN
PLL
IIC
SDO
MPEG DECODER
SERIAL AUDIO INTERFACE RX TX
SCKT
LRCKT
D98AU912
Figure 8. Serial Input Interface Clocks
SDI
SCKR
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SCKR BIT_EN
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t(s c
-O )
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DAC OCLK
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(s) ct
DATA
IGNORED
SCLK_POL=0
SCLK_POL=4
DATA VALID
D98AU968A
DATA IGNORED
3.0 INTERFACE DESCRIPTION 3.1 Serial Input Interface STA015 receives the input data (MSB first) through the Serial Input Interface (Fig.7). It is a serial communication interface connected to the SDI (Serial Data Input) and SCKR (Receiver Serial Clock).
The interface can be configured to receive data sampled on both rising and falling edge of the SCKR clock. The BIT_EN pin, when set to low, forces the bitstream input interface to ignore the incoming data. For
STA015
proper operation BIT_EN line should be toggled only when SCKR is stable low (for both SCLK_POL configuration). The possible configurations are described in Fig. 8. 3.2 GPSO Output Interface In order to retrieve ADPCM encoded data a General Purpose Serial Output interface is available (in TQFP44 and LFBGA64 packages only). The maximum frequency for GPSO_SCKR clock is the DSP system clock frequency divided by 3 (i.e. 8.192 MHz @ 24.58MHz). The interface is based on a simple and configurable 3-lines protocol, as described by figure 10. 3.3 PCM Output Interface The decoded audio data are output in serial PCM format. The interface consists of the following signals: SDO SCKT LRCLK PCM Serial Data Output PCM Serial Clock Output Left/Right Channel Selection Clock
The output samples precision is selectable from 16 to 24 bits/word, by setting the output precision with PCMCONF (16, 18, 20 and 24 bits mode) register. Data can be output either with the most significant bit first (MS) or least significant bit first LS), selected by writing into a flag of the PCMCONF register. Figure 9 gives a description of the several STA015 PCM Output Formats. The sample rates set decoded by STA015 is described in Table 1.
To enable the GPSO interface bit GEN of GPSO_ENABLE register must be set. Using the GPSO_CONF register the protocol can be configured in order to provide outcoming data on rising/ falling edge of GPSO_SCKR input clock; the GPSO_REQ request signal polarity (usually connected to an MCU interrupt line) can be configured as well. Figure 9. PCM Output Formats
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MPEG 1 48 44.1 32
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t(s c
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Table 1. MPEG Sampling Rates (KHz)
MPEG 2 24 22.05 16 MPEG 2.5 12 11.025 8
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STA015
3.4 ADC Inteface Beside the serial input interface based on SDI and SCKR lines a 3 wire flexible and user configurable input interface is also available, suitable to interface with most A/D converters. To configure this interface 4 specific I2C registers are available (ADC_ENABLE, ADC_CONF, ADC_WLEN and ADC_WPOS). Refer to registers description for more details. 3.5 General Purpose I/O Interface A new general purpose I/O interface has been added to this device (TQFP44 and LFBGA64 only). Actually only the strobe line is used in ADPCM encoding mode to provide an interrupt; other pins are reserved for future use. The related configuration register is GPIO_CONF. See the following summary for related pin usage:
Name I/ODATA [0] .................. I/ODATA [7] GPIO_STROBE Description GPIO data line Dir I/O ..... I/O I/O
GPIO strobe line
4.0 ADPCM ENCODING: OVERVIEW
According to the previously described interfaces there are 4 ways to manage ADPCM data stream while encoding. Input interface can be either the serial receiver block (SDI + SCKR + DATA_REQ lines) or the ADC specific interface.
Output interfaces can be either the I2C bus (with or without interrupt line) or the GPSO high-speed serial interface (GPSO_REQ + GPSO_ DATA + GPSO_SCKR lines). This result in the following 4 methods to handle encoding flow:
INPUT (data to encode) ADC I/F (SDI_ADC + LRCK_ADC + SCK_ADC) ADC I/F (SDI_ADC + LRCK_ADC + SCK_ADC) SERIAL I/F (SCKR + SDI + DATA_REQ) Output (encoded data)
GPSO I/F (GPSO_REQ + GPSO_DATA + GPSO_SCKR)
SERIAL I/F (SCKR + SDI + DATA_REQ) (*)
(*) STA013 Compatible mode
Figure 10.
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STA015
I2C + Interrupt (SCL + SDA +DATA_REQ)
GPSO I/F (GPSO_REQ + GPSO_DATA + GPSO_SCKR) I2C (polling) (SCL + SDA)
b O
so
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Available on package TQFP44/LFBGA64 SO28/TQFP44 LFBGA64 TQFP44/LFBGA64 SO28/TQFP44 LFBGA64
GPSO_SCKR GPSO_DATA GPSO_REQ
MCU
GPSO_SCKR
GPSO_REQ
GPSO_DATA
D00AU1145
STA015
Figure 11.
LRCK_ADC SDI_ADC SCK_ADC ADC I/F MUX ENCOD ENGINE SERIAL RECEIVER I2C SDA SCL DATA_REQ
D99AU1064
GPSO_REQ GPSO GPSO_DATA GPSO_SCKR
SDI SCKR DATA_REQ
The following 4 figures (fig. 12, 13, 14, 15) show the available connection diagrams as far as ADPCM encoding function. As shown in the figures some configuration is not available in SO28 package. Figure 12. Input from BITSTREAM, Output from I2C
SDI SCKR DATA_REQ BIT_EN I2C SO28 TQFP44 LFBGA64 LRCKT SCKT SDO
MCU
OCLK
D99AU1121A
STA013 compatible mode
Figure 13. Input from ADC, Output from I2C +IRQ
I2C DATA_REQ
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MCU ADC SLAVE MCU
t(s
-O )
LRCKT SCKT
so b
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DAC
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(s) ct
SDO SDI_ADC
STA015
SO28 TQFP44 LFBGA64
DAC
OCLK
I2C DATA_REQ
LRCKT
STA015
LRCK_ADC SCK_ADC ADC MASTER SDI_ADC SO28 TQFP44 LFBGA64
SCKT DAC SDO OCLK
D99AU1123A
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Figure 14. Input from BITSTREAM, Output from GPSO
GPSO_DATA GPSO_SCKR GPSO_REQ SDI SCKR DATA_REQ BIT_EN I2C
LRCKT SCKT
MCU
STA015
TQFP44 LFBGA64
SDO OCLK
DAC
D99AU1122A
Figure 15. Input from ADC, Output from GPSO
GPSO_DATA MCU GPSO_SCKR GPSO_REQ LRCKT SCKT
STA015
LRCK_ADC SCK_ADC ADC MASTER SDI_ADC TQFP44 LFBGA64
SDO
OCLK
5.0 I2C BUS SPECIFICATION
The STA015 supports the I2C protocol. This protocol defines any device that sends data on to the bus as a transmitter and any device that reads the data as a receiver. The device that controls the data transfer is known as the master and the others as the slave. The master always starts the transfer and provides the serial clock for synchronisation. The STA015 is always a slave device in all its communications. 5.1 COMMUNICATION PROTOCOL 3.1.0 - Data transition or change
Data changes on the SDA line must only occur when the SCL clock is low. SDA transition while the clock is high are used to identify START or STOP condition. 5.1.1 Start condition
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START is identified by a high to low transition of the data bus SDA signal while the clock signal SCL is stable in the high state. A START condition must precede any command for data transfer. 5.1.2 Stop condition
Pr e
du o
t(s c
-O )
so b
Pr ete l
DAC
D99AU1124A
du o
(s) ct
STOP is identified by low to high transition of the data bus SDA signal while the clock signal SCL is stable in the high state. A STOP condition terminates communications between STA015 and the bus master. 5.1.3 Acknowledge bit An acknowledge bit is used to indicate a successful data transfer. The bus transmitter, either master or slave, releases the SDA bus after sending 8 bit of data. During the 9th clock pulse the receiver pulls the SDA bus low to acknowledge the receipt of 8 bits of data.
STA015
5.1.4 Data input During the data input the STA015 samples the SDA signal on the rising edge of the clock SCL. For correct device operation the SDA signal has to be stable during the rising edge of the clock and the data can change only when the SCL line is low. 5.2 DEVICE ADDRESSING To start communication between the master and the STA015, the master must initiate with a start condition. Following this, the master sends onto the SDA line 8 bits (MSB first) corresponding to the device select address and read or write mode. The 7 most significant bits are the device address identifier, corresponding to the I2C bus definition. For the STA015 these are fixed as 1000011. The 8th bit (LSB) is the read or write operation RW, this bit is set to 1 in read mode and 0 for write mode. After a START condition the STA015 identifies on the bus the device address and, if a match is found, it acknowledges the identification on SDA bus during the 9th bit time. The following byte after the device identification byte is the internal space address. 5.3 WRITE OPERATION (see fig. 16)
Following a START condition the master sends a device select code with the RW bit set to 0. The STA015 acknowledges this and waits for the byte of internal address. After receiving the internal bytes address the STA015 again responds with an acknowledge. 5.3.1 Byte write
In the byte write mode the master sends one data byte, this is acknowledged by STA015. The master then terminates the transfer by generating a STOP condition. 5.3.2 Multibyte write
The multibyte write mode can start from any internal address. The transfer is terminated by the master generating a STOP condition. Figure 16. Write Mode Sequence
ACK BYTE WRITE START DEV-ADDR SUB-ADDR
RW
MULTIBYTE WRITE START
DEV-ADDR
Figure 17. Read Mode Sequence
ACK
et ol s
CURRENT ADDRESS READ
RANDOM ADDRESS READ
od Pr e
DEV-ADDR START RW DEV-ADDR START RW DEV-ADDR START DEV-ADDR START RW
ct u
ACK RW
DATA SUB-ADDR
s) (
NO ACK STOP ACK
-O
ACK ACK
so b
DATA IN DATA IN
Pr ete l
STOP DATA IN
du o
(s) ct
ACK
ACK
ACK
SUB-ADDR
D98AU825B
STOP
ACK
ACK DEV-ADDR DATA
NO ACK
START ACK DATA DATA
RW ACK DATA NO ACK
STOP
SEQUENTIAL CURRENT READ
RW= ACK HIGH
STOP ACK ACK SUB-ADDR DEV-ADDR ACK DATA ACK DATA ACK DATA NO ACK
SEQUENTIAL RANDOM READ
START
RW
D98AU826A
STOP
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STA015
5.4 READ OPERATION (see Fig. 17) 5.4.1 Current byte address read The STA015 has an internal byte address counter. Each time a byte is written or read, this counter is incremented. For the current byte address read mode, following a START condition the master sends the device address with the RW bit set to 1. The STA015 acknowledges this and outputs the byte addressed by the internal byte address counter. The master does not acknowledge the received byte, but terminates the transfer with a STOP condition. 5.4.2 Sequential address read This mode can be initiated with either a current address read or a random address read. However in this case the master does acknowledge the data byte output and the STA015 continues to output the next byte in sequence. To terminate the streams of bytes the master does not acknowledge the last received byte, but terminates the transfer with a STOP condition. The output data stream is from consecutive byte addresses, with the internal byte address counter automatically incremented after one byte output. 6.0 I2C REGISTERS The following table gives a description of the MPEG Source Decoder (STA015) register list. The first column (HEX_COD) is the hexadecimal code for the sub-address. The second column (DEC_COD) is the decimal code.
The third column (DESCRIPTION) is the description of the information contained in the register.
The fourth column (RESET) inidicate the reset value if any. When no reset value is specifyed, the default is "undefined". The fifth column (R/W) is the flag to distinguish register "read only" and "read and write", and the useful size of the register itself. Each register is 8 bit wide. The master shall operate reading or writing on 8 bits only. I2C REGISTERS
HEX_COD $00 $01 $05 $06 $07 $0C $0D $0F $10 $13 $14 $16 DEC_COD 0 1 5 6 7 12 VERSION IDENT
DESCRIPTION
PLLCTL [7:0]
PLLCTL [20:16] (MF[4:0]=M) PLLCTL [15:12] (IDF[3:0]=N) REQ_POL SCLK_POL
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Pr e
du o
13 15 16 19 20 22 24 64 65 66 67 68
ct
s) (
-O
so b
Pr ete l
RESET 0xAC 0xA1 0x0C 0x00 0x01 0x04 0x00 0x00 0x01 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
du o
R/W R (8) R (8)
(s) ct
R/W (8) R/W (8) R/W (8) R/W (8) R/W (8) R (8) W (8) R/W(8) R/W(8) R/W(8) R/W(8) R (8) R (8) R (8) R (8) R(8) R(8)
ERROR_CODE
SOFT_RESET PLAY
MUTE CMD_INTERRUPT DATA_REQ_ENABLE ADPCM_DATA_1 to ADPCM_DATA_18 SYNCSTATUS ANCCOUNT_L ANCCOUNT_H HEAD_H[23:16] HEAD_M[15:8]
$18 $40 $41 $42 $43 $44
$40 - $51
64 - 81
STA015
I2C REGISTERS
$45 $46 $47 $48 $49 $4D $4E $50 $51 $52 $52 $53 $54 $55 $56 $61 $63 $64 $65 $67 $68 $69 $6A $71 $72 $77 $78 $79 $7A $7B $7C $7D $7E - B5 $B6 $B8 $B9 69 70 71 72 73 77 78 80 81 82 82 83 84 85 86 97 99 100 101 103 104 105 106 113 114 119 120 121 122 123 124 125 HEAD_L[7:0] DLA DLB DRA DRB CHIP_MODE CRCR MFSDF_441 PLLFRAC_441_L ADPCM_DATA_READY PLLFRAC_441_H ADPCM_SAMPLE_FREQ PCM DIVIDER PCMCONF PCMCROSS MFSDF (X) DAC_CLK_MODE PLLFRAC_L PLLFRAC_H FRAME_CNT_L FRAME_CNT_M FRAME_CNT_H AVERAGE_BITRATE SOFTVERSION RUN 0x00 0x00 0xFF 0x00 0xFF 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x03 0x21 0x00 0x07 0x00 R(8) R/W (8) R/W (8) R/W (8) R/W (8) R/W (2) R/W (1) R/W (8) R/W (8) R/W (1) R/W (8) R/W (4) R/W (8) R/W (8) R/W (8)
TREBLE_FREQUENCY_LOW BASS_FREQUENCY_LOW TREBLE_ENHANCE BASS_ENHANCE TONE_ATTEN ISR
TREBLE_FREQUENCY_HIGH BASS_FREQUENCY_HIGH
et ol s
$BA $BB
$BC $BD $BE $BF $C0 $C1 $C2
ro P e
126 - 181 182 184 185
uc d
s) t(
-O
so b
Pr ete l
0x5B 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x0F 0x00 0x00
0x46
du o
R (8) R (8) R (8) R (8) R (8)
R/W (8)
R/W (8)
(s) ct
R/W (8)
R/W (8)
R/W (8) R/W (8) R/W (8) R/W (8) R/W (8) R/W (8) R/W (8) R/W (8) R (8) R/W (1) R/W (2) R/W (1) R/W (2) R/W (1) R/W (5) R/W (8) R/W (8) R/W (2) R/W (5) R/W (5) R/W (8)
ANC_DATA_1 to ANC_DATA_56 ADPCM_CONFIG GPSO_ENABLE GPSO_CONF ADC_ENABLE ADC_CONF ADPCM_FRAME_SIZE
186 188
187 189
190 191 192 193 194
ADPCM_INT_CFG GPIO_CONF ADC_ WLEN ADC_ WPOS ADPCM_SKIP_FRAME
Notes: 1. The HEX_COD is the hexadecimal adress that the microcontroller has to generate to access the information. 2. RESERVED: register used for production test only, or for future use.
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STA015
6.1 STA015 REGISTERS DESCRIPTION The STA015 device includes 128 I2C registers. In this document, only the user-oriented registers are described. The undocumented registers are reserved. These registers must never be accessed (in Read or in Write mode). The Read-Only registers must never be written. The following table describes the meaning of the abbreviations used in the I2C registers description:
Symbol NA UND NC RO WO R/W R/WS Comment Not Applicable Undefined No Charge Read Only Write Only Read and Write Read, Write in specific mode
VERSION Address: 0x00 (00) Type: RO
MSB b7 V8 b6 V7 b5 V6 b4 V5 b3 V4 b2
The VERSION register is read-only and it is used to identify the IC on the application board. IDENT Address: 0x01 Type: RO Software Reset: 0xAC Hardware Reset: 0xAC
MSB b7 1 b6 0
IDENT is a read-only register and is used to identify the IC on an application board. IDENT always has the value "0xAC"
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PLLCTL
Address: 0x05 Type: R/W
ro P e
b6 XTODIS
du
b5 1
ct
)(s
b4 0
bs O
b3 1
ete ol
V3 b2 1
Pr
b1 V2
du o
LSB b0 V1
(s) ct
LSB b1 0 b0 0
Software Reset: 0x21 Hardware Reset: 0x21
MSB b7 XTO_BUF b5 OCLKEN b4 SYS2OCLK b3 PPLDIS b2 XTI2DSPCLK b1 XTI2OCLK LSB b0 UPD_FRAC
STA015
UPD_FRAC: when is set to 1, update FRAC in the switching circuit. It is set to 1 after autoboot. XTI2OCLK: when is set to 1, use the XTI as input of the divider X instead of VCO output. It is set to 0 on HW reset. XTI2DSPCLK: when is to 1, set use the XTI as input of the divider S instead of VCO output. It is set to 0 on HW reset. PLLDIS: when set to 1, the VCO output is disabled. It is set to 0 on HW reset. SYS2OCLK: when is set to 1, the OCLK frequency is equal to the system frequency. It is useful for testing. It is set to 0 on HW reset. OCLKEN: when is set to 1, the OCLK pad is enable as output pad. It is set to 1 on HW reset. XTODIS: when is set to 1, the XTO pad is disable. It is set to 0 on HW reset. XTO_BUF: when this bit is set, the pin nr. 28 (OUT_CLOCK/DATA_REQ) is enabled. It is set to 0 after autoboot. PLLCTL (M) Address: 0x06 (06) Type: R/W Software Reset: 0x0C Hardware Reset: 0x0C PLLCTL (N) Address: 0x07 (07) Type: R/W Software Reset: 0x00 Hardware Reset: 0x00
The M and N registers are used to configure the STA015 PLL by DSP embedded software. M and N registers are R/W type but they are completely controlled, on STA015, by DSP software. REQ_POL Address: 0x0C (12) Type: R/W Software Reset: 0x01
Hardware Reset: 0x00
The REQ_POL registers is used to program the polarity of the DATA_REQ line.
et ol s
0 0
MSB b7
Pr e
0 0
du o
t(s c
0
-O )
b4 0
so b
Pr ete l
du o
(s) ct
LSB b5 b3 0 b2 0 b1 0 b0 1
b6
Default polarity (the source sends data when the DATA_REQ line is high)
MSB b7 b6 b5 0 b4 0 b3 0 b2 1 b1 0 LSB b0 1
Inverted polarity (the source sends data when the ATA_REQ line is low)
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STA015
SCKL_POL Address: 0x0D (13) Type: R/W Software Reset: 0x04 Hardware Reset: 0x04
MSB b7 X b6 X b5 X b4 X b3 X b2 0 1 b1 0 0 LSB b0 0 0 (1) (2)
X = don't care SCKL_POL is used to select the working polarity of the Input Serial Clock (SCKR).
(1) If SCKL_POL is set to 0x00, the data (SDI) are sent with the falling edge of SCKR and sampled on the rising edge. (2) If SCKL_POL is set to 0x04, the data (SDI) are sent with the rising edge of SCKR and sampled on the falling edge. ERROR_CODE Address: 0x0F (15) Type: RO Software Reset: 0x00 Hardware Reset: 0x00
MSB b7 X b6 X b5 EC5 b4
X = don't care
ERROR_CODE register contains the last error occourred if any. The codes can be as follows:
CODE
et ol s
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ro P e
0x00 0x01 0x02 0x04 0x10 0x2X 0x3X
No error since the last SW or HW Reset
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s) t(
EC4
-O
so b
b3
Pr ete l
b2 EC2 b1 EC1
du o
LSB b0 EC0
(s) ct
EC3
Description
CRC Failure DATA not available
Ancillary data not read Audio synch word not found
MPEG Header error MPEG Decoding errors
STA015
SOFT_RESET Address: 0x10 (16) Type: WO Software Reset: 0x00 Hardware Reset: 0x00
MSB b7 X b6 X b5 X b4 X b3 X b2 X b1 X LSB b0 0 1
X = don't care; 0 = normal operation; 1 = reset
When this register is written, a soft reset occours. The STA015 core command register and the interrupt register are cleared. The decoder goes in to idle mode. PLAY Address: 0x13 (19) Type: R/W Software Reset: 0x01 Hardware Reset: 0x01
MSB b7 X b6 X b5 X b4 X b3
X = don't care; 0 = normal operation; 1 = play
The PLAY command is handled according to the state of the decoder, as described in section 2.5. PLAY only becomes active when the decoder is in DECODE mode. MUTE
Address: 0x14 Type: R/W
Software Reset: 0x00
et ol s
X
Hardware Reset: 0x00
MSB b7
od Pr e
b6 X
ct u
b5 X
)(s
b O
X
so
Pr ete l
b2 X b1 X
du o
LSB b0 0 1
(s) ct
LSB b4 X b3 X b2 X b1 X b0 0 1
X = don't care; 0 = normal operation; 1 = mute The MUTE command is handled according to the state of the decoder, as described in section 2.5. MUTE sets the clock running.
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STA015
CMD_INTERRUPT Address: 0x16 (22) Type: R/W Software Reset: 0x00 Hardware Reset: 0x00
MSB b7 X b6 X b5 X b4 X b3 X b2 X b1 X LSB b0 0 1
X = don't care; 0 = normal operation; 1 = write into I2C/Ancillary Data
The INTERRUPT is used to give STA015 the command to write into the I2C/Ancillary Data Buffer (Registers: 0x7E ... 0xB5). Every time the Master has to extract the new buffer content it writes into this register, setting it to a non-zero value. DATA_REQ_ENABLE Address: 0x18 (24) Type: R/W Software Reset: 0x00 Hardware Reset: 0x00
MSB b7 X X b6 X X b5 X X b4 X X b3 X X
The DATA_REQ_ENABLE register is used to configure Pin n. 28 working as buffered output clock or data request signal, used for multimedia mode. The buffered Output Clock has the same frequency than the input clock (XTI) SYNCSTATUS Type: RO
Address: 0x40 (64)
et ol s
MSB b7 X 22/56
Software Reset: 0x00 Hardware Reset: 0x00
LSB b6 X b5 X b4 X b3 X b2 X b1 SS1 0 0 1 b0 SS0 0 1 0 Research of sync word Wait for Confirmation Synchronised Description
Pr e
du o
t(s c
-O )
0 1
b2
so b
b1 X X
Pr ete l
LSB b0 X X
du o
(s) ct
Description buffered output clock request signal
STA015
ADPCM_DATA BUFFER Address: 0x40 - 0x51 (64 - 81) Type: R/W Software Reset: 0x00 Hardware Reset: 0x00
MSB b7 b6 b5 b4 b3 b2 b1 LSB b0
ENCODED DATA N to N+18
ANCCOUNT_L Address: 0x41 (65) Type: RO Software Reset: 0x00 Hardware Reset: 0x00
MSB b7 AC7 b6 AC6 b5 AC5 b4 AC4 b3 AC3 b2
ANCCOUNT_H Address: 0x42 (66) Type: RO Software Reset: 0x00 Hardware Reset: 0x00 ANCCOUNT_H
MSB b7 AC15 b6 AC14
ANCCOUNT registers are logically concatenated and indicate the number of Ancillary Data bits available at every correctly decoded MPEG frame.
et ol s
X
HEAD_H[23:16]
MSB b7
od Pr e
b6 X
ct u
b5 AC13 b5 X
)(s
b4 AC12
bs O
b3 AC11
ete ol
b2 AC10
AC2
Pr
b1 AC1
du o
LSB b0 AC0
(s) ct
LSB b1 AC9 b0 AC8
LSB b4 H20 b3 H19 b2 H18 b1 H17 b0 H16
x = don't care
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STA015
HEAD_M[15:8]
MSB b7 H15 b6 H14 b5 H13 b4 H12 b3 H11 b2 H10 b1 H9 LSB b0 H8
HEAD_L[7:0]
MSB b7 H7 b6 H6 b5 H5 b4 H4 b3 H3 b2 H2 b1 H1 LSB b0 H0
Address: 0x43, 0x44, 0x45 (67, 68, 69) Type: RO Software Reset: 0x00 Hardware Reset: 0x00 Head[1:0] emphasis Head[2] original/copy Head[3] copyrightHead [5:4] mode extension Head[7:6] mode Head[8] private bit Head[9] padding bit Head[11:10] sampling frequency index Head[15:12] bitrate index Head[16] protection bit Head[18:17] layer Head[19] ID Head[20] ID_ex
The HEAD registers can be viewed as logically concatenated to store the MPEG Layer III Header content. The set of three registers is updated every time the synchronisation to the new MPEG frame is achieved The meaning of the flags are shown in the following tables: MPEG IDs
et ol s
Layer
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Pr e
IDex 0 0 1 1
du o
t(s c
-O )
ID 0 1 0 1
so b
Pr ete l
du o
(s) ct
MPEG 2.5 reserved MPEG 2 MPEG 1
in Layer III these two flags must be set always to "01". Protection_bit It equals "1" if no redundancy has been added and "0" if redundancy has been added.
STA015
Bitrate_index indicates the bitrate (Kbit/sec) depending on the MPEG ID.
bitrate index '0000' '0001' '0010' '0011' '0100' '0101' '0110' '0111' '1000' '1001' '1010' '1011' '1100' '1101' '1110' '1111' ID = 1 free 32 40 48 56 64 80 96 112 128 160 192 224 256 320 forbidden ID = 0 free 8 16 24 32 40 48 56 64 80 96 112 128 144 160
Sampling Frequency
Sampling Frequency '00' '01' '10' '11' MPEG1 44.1 48 32 MPEG2 22.05 24 16
indicates the sampling frequency of the encoded audio signal (KHz) depending on the MPEG ID
Padding bit
if this bit equals '1', the frame contains an additional slot to adjust the mean bitrate to the sampling frequency, otherwise this bit is set to '0'. Private bit
Bit for private use. This bit will not be used in the future by ISO/IEC.
et ol s
Mode
Indicates the mode according to the following table. The joint stereo mode is intensity_stereo and/or ms_stereo.
mode '00' '01' '10' '11' stereo joint stereo (intensity_stereo and/or ms_stereo) dual_channel single_channel (mono) mode specified
od Pr e
ct u
)(s
reserved
b O
so
Pr ete l
forbidden
du o
12 8
(s) ct
MPEG2.5 11.03
reserved
reserved
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STA015
Mode extension These bits are used in joint stereo mode. They indicates which type of joint stereo coding method is applied. The frequency ranges, over which the intensity_stereo and ms_stereo modes are applied, are implicit in the algorithm. Copyright If this bit is equal to '0', there is no copyright on the bitstream, '1' means copyright protected. Original/Copy This bit equals '0' if the bitstream is a copy, '1' if it is original. Emphasis Indicates the type of de-emphasis that shall be used. emphasis
'00' '01' '10' '11' none 50/15 microseconds reserved CCITT J, 17
emphasis specified
DLA Address: 0x46 (70) Type: R/W Software Reset: 0x00 Hardware Reset: 0x00
MSB b7 DLA7 0 0 0 : 0 b6 DLA6 0 0 0 : b5 DLA5 0 0 0 : 1 b4 0 0 0 : 0 DLA4
DLA register is used to attenuate the level of audio output at the Left Channel using the butterfly shown in Fig. 18. When the register is set to 255 (0xFF), the maximum attenuation is achieved.
et ol s
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A decimal unit correspond to an attenuation step of 1 dB. Figure 18. Volume Control and Output Setup
DSP Left Channel DLA X DLB X DRB X DRA DSP Right Channel X + Output Right Channel
D97AU667
ro P e
1
uc d
s) t(
DLA3 0 0 0 : 0
b3
-O
b2 0 0 0 : 0 DLA2
so b
b1 DLA1 0 0 1 : 0
Pr ete l
0 1 0 : 0
du o
(s) ct
LSB b0 Description OUTPUT ATTENUATION NO ATTENUATION -1dB -2dB : -96dB
DLA0
+
Output Left Channel
STA015
DLB Address: 0x47 (71) Type: R/W Software Reset: 0xFF Hardware Reset: 0xFF
MSB b7 DLB7 0 0 0 : 0 b6 DLB6 0 0 0 : 1 b5 DLB5 0 0 0 : 1 b4 DLB4 0 0 0 : 0 b3 DLB3 0 0 0 : 0 b2 DLB2 0 0 0 : 0 b1 DLB1 0 0 1 : 0 LSB b0 DLB0 0 1 0 : 0 Description OUTPUT ATTENUATION NO ATTENUATION -1dB -2dB : -96dB
DLB register is used to re-direct the Left Channel on the Right, or to mix both the Channels. Default value is 0x00, corresponding at the maximum attenuation in the re-direction channel. DRA Address: 0x48 (72) Type: R/W Software Reset: 0X00 Hardware Reset: 0X00
MSB b7 DRA7 0 0 0 : b6 DRA6 0 0 0 : b5 DRA5 0 0 0 : b4
DRA4
et ol s
0
DRA register is used to attenuate the level of audio output at the Right Channel using the butterfly shown in Fig. 11. When the register is set to255 (0xFF), the maximum attenuation is achieved. A decimal unit correspond to an attenuation stepof 1 dB.
od Pr e
1 1
uc
0 0 0 : 0
s) t(
b3 DRA3 0 0 0 : 0
-O
b2 DRA2 0 0 0 : 0
so b
b1 DRA1 0 0 1 : 0
Pr ete l
0 1 0 : 0
du o
(s) ct
LSB b0 Description OUTPUT ATTENUATION NO ATTENUATION -1dB -2dB : -96dB
DRA0
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STA015
DRB Address: 0x49 (73) Type: R/W Software Reset: 0xFF Hardware Reset: 0xFF
MSB b7 DRB7 0 0 0 : 0 b6 DRB6 0 0 0 : 1 b5 DRB5 0 0 0 : 1 b4 DRB4 0 0 0 : 0 b3 DRB3 0 0 0 : 0 b2 DRB2 0 0 0 : 0 b1 DRB1 0 0 1 : 0 LSB b0 DRB0 0 1 0 : 0 Description OUTPUT ATTENUATION NO ATTENUATION -1dB -2dB : -96dB
DRB register is used to re-direct the Right Channel on the Left, or to mix both the Channels. Default value is 0x00, corresponding at the maximum attenuation in the re-direction channel. CHIP_MODE Address: 0x4D (77) Type: R/W Hardware Reset: 0x00 Possible values are: 0x00 - MP3 decoding 0x01 - Reserved 0x02 - ADPCM Encoder 0x03 - ADPCM Decoder 0x04 - BYPASS mode
Using this register it's possible to select which operation will be performed by the DSP.
The DSP will check for the value of this register right after the RUN command has been issued (refer to RUN register). After that no more checks will be performed: therefore a SOFT_RESET must be generated in order to change the device mode. CRCR
Address: 0x4E (78)
et ol s
X 28/56
Type: R/W
Software Reset: 0x00 Hardware Reset: 0x00
MSB b7 b6 X b5 X b4 X b3 X b2 X b1 X LSB b0 CRCEN
Pr e
du o
t(s c
-O )
so b
Pr ete l
du o
(s) ct
The CRC register is used to enable/disable the CRC check. If CRC_EN bit is cleared, the CRC value encoded in the bitstream is checked against the hardware one. If a discrepance occurs, the current frame is skipped and the decoder is muted. The ERROR_CODE register is affected with the value 0x01.
STA015
If CRC_EN bit is set, the result of the CRC check is ignored, but the ERROR_CODE register is nevertheless affected with the value 0x01 if a discrepance has occurred. MFSDF_441 Address: 0x50 (80) Type: R/W Software Reset: 0x00 Hardware Reset: 0x00
MSB b7 X b6 X b5 X b4 M4 b3 M3 b2 M2 b1 M1 LSB b0 M0
This register contains the value for the PLL X driver for the 44.1KHz reference frequency. The VCO output frequency, when decoding 44.1KHz bitstream, is divided by (MFSDF_441 +1) PLLFRAC_441_L Address: 0x51 (81) Type: R/W Software Reset: 0x00 Hardware Reset: 0x00
MSB b7 PF7 b6 PF6 b5 PF5 b4 PF4 b3
ADPCM_DATA_READY Address: 0x52 (82) Type: R/W Software Reset: 0x00 Hardware Reset: 0x00
MSB b7 X
et ol s
ADR: Adpcm Data Ready This bit signal ADPCM encoded data are ready to be retrieved.
Pr e
X
b6
od
ct u
b5 X
)(s
b4 X
b O
b3 X
PF3
so
Pr ete l
b2 b1 PF2 PF1
du o
LSB b0 PF0
(s) ct
LSB b2 X b1 X b0 ADR
PLLFRAC_441_H Address: 0x52 (82) Type: R/W Software Reset: 0x00
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STA015
Hardware Reset: 0x00
MSB b7 PF15 b6 PF14 b5 PF13 b4 PF12 b3 PF11 b2 PF10 b1 PF19 LSB b0 PF8
The registers are considered logically concatenated and contain the fractional values for the PLL, for 44.1KHz reference frequency. (see also PLLFRAC_L and PLLFRAC_H registers) ADPCM_SAMPLE_FREQ Address: 0x53 (83) Type: R/W Software Reset: 0x00 Hardware Reset: 0x00
MSB b7 X b6 X b5 X b4 b3 b2 ADPCM_SF b1
ADPCM_SF: Adpcm Sample Frequency
0x02 0x0A 0x0E 8KHz
PCMDIVIDER Address: 0x54 (84) Type: RW Software Reset: 0x01 Hardware Reset: 0x01
MSB b7
PD7
et ol s
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PCMDIVIDER is used to set the frequency ratio between the OCLK (Oversampling Clock for DACs), and the SCKT (Serial Audio Transmitter Clock). The relation is the following:
OCLK_freq SCKT_freq = --------------------------------------------2 ( 1 + PCM_DIV )
Pr e
b6
PD6
du o
t(s c
-O )
b4 PD4
so b
16KHz 32KHz
Pr ete l
du o
b0
LSB
(s) ct
LSB b3 PD3 b2 PD2 b1 PD1 b0 PD0
b5
PD5
The Oversampling Factor (O_FAC) is related to OCLK and SCKT by the following expression: 1) OCLK_freq = O_FAC * LRCKT_ Freq (DAC relation) 2) OCLK_ Freq = 2 * (1+PCM_DIV) * 32* LRCKT_Freq (when 16 bit PCM mode is used) 3) OCLK_ Freq = 2 * (1+PCM_DIV) * 64* LRCKT_Freq (when 32 bit PCM mode is used)
STA015
4) PCM_DIV = (O_FAC/64) - 1 in 16 bit mode 5) PCM_DIV = (O_FAC/128) - 1 in 32 bit mode Example for setting:
MSB b7 PD7 0 0 0 0 0 0 b6 PD6 0 0 0 0 0 0 b5 PD5 0 0 0 0 0 0 b4 PD4 0 0 0 0 0 0 b3 PD3 0 0 0 0 0 0 b2 PD2 1 1 0 0 0 0 b1 PD1 1 0 1 1 1 0 LSB b0 PD0 1 1 1 1 0 1 16 bit mode 16 bit mode 16 bit mode 32 bit mode 32 bit mode 32 bit mode 512 x Fs 384 x Fs 256 x Fs 512 x Fs 384 x Fs 256 x Fs Description
for 16 bit PCM Mode
O_FAC = 512 ; PCM_DIV = 7 O_FAC = 256 ; PCM_DIV = 3 O_FAC = 384 ; PCM_DIV = 5
for 32 bit PCM Mode
O_FAC = 512 ; PCM_DIV = 3 O_FAC = 256 ; PCM_DIV = 1 O_FAC = 384 ; PCM_DIV = 2
PCMCONF Address: 0x55 (85) Type: R/W Software Reset: 0x21 Hardware Reset: 0x21
MSB b7 X X X X X X b6 ORD 1 0 b5 DIF b4 INV b3
FOR
et ol s
X X X X X X X X
X
ro P e
1
0
du
0 1
t(s c
SCL 0 1 1 0
b2
-O )
b1 PREC (1)
so b
LSB b0
Pr ete l
du o
(s) ct
Description
PREC (1) PCM order the LS bit is transmitted First PCM order the MS bit is transmitted First The word is right aligned The word is left aligned LRCKT Polarity compliant to I2S format LRCKT Polarity inverted I2S format Different formats Data are sent on the rising edge of SCKT Data are sent on the falling edge of SCKT
0 0 1 1
0 1 0 1
16 bit mode (16 slots transmitted) 18 bit mode (32 slots transmitted) 20 bit mode (32 slots transmitted) 24 bit mode (32slots transmitted)
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STA015
PCMCONF is used to set the PCM Output Interface configuration: ORD: PCM order. If this bit is set to'1', the LS Bit is transmitted first, otherwise MS Bit is transmiited first. DIF: PCM_DIFF. It is used to select the position of the valid data into the transmitted word. This setting is significant only in 18/20/24 bit/word mode.If it is set to '0' the word is right-padded, otherwise it is left-padded. INV (fig.13): It is used to select the LRCKT clock polarity. If it is set to '1' the polarity is compliant to I2S format (low -> left , high -> right), otherwise the LRCKT is inverted. The default value is '0'. (if I2S have to be selected, must be set to '1' in the TA013 configuration phase). Figure 19. LRCKT Polarity Selection
LEFT LEFT RIGHT
LRCKT
INV_LRCLK=1
RIGHT
LRCKT
LEFT
LEFT
INV_LRCLK=0
D00AU1192
FOR: FORMAT is used to select the PCM Output Interface format.
After hw and sw reset the value is set to 0 corresponding to I2S format.
SCL (fig.14): used to select the Transmitter Serial Clock polarity. If set to '1' the data are sent on the falling edge and sampled on the rising. This last option is the most commonly used by the commercial DACs. The default configuration for this flag is '0'. Figure 20. SCKT Polarity Selection
PREC [1:0]: PCM PRECISION
It is used to select the PCM samples precision, as follows: '00': 16 bit mode (16 slots transmitted) '01': 18 bit mode (32 slots transmitted) '10': 20 bit mode (32 slots transmitted) '11': 24 bit mode (32 slots transmitted) The PCM samples precision in STA015 can be 16 or 18-20-24 bits. When STA015 operates in 16 (18-20-24) bits mode, the number of bits transmitted during a LRCLT period is 32 (64).
et ol s
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Pr e
du o
t(s c
-O )
so b
Pr ete l
du o
(s) ct
STA015
PCMCROSS Address: 0x56 (86) Type: R/W Software Reset: 0x00 Hardware Reset: 0x00
MSB b7 X X X X b6 X X X X b5 X X X X b4 X X X X b3 X X X X b2 X X X X b1 0 0 1 1 LSB b0 0 1 0 1 Description Left channel is mapped on the left output. Right channel is mapped on the Right output Left channel is duplicated on both Output channels. Right channel is duplicated on both Output channels Right and Left channels are toggled
The default configuration for this register is '0x00'. MFSDF (X) Address: 0x61 (97) Type: R/W Software Reset: 0x07 Hardware Reset: 0x07
MSB b7 X b6 X b5 X b4 M4
The register contains the values for PLL X divider (see Fig. 7). The value is changed by the internal STA015 Core, to set the clocks frequencies, according to the incoming bitstream. This value can be even set by the user to select the PCM interface configuration. The VCO output frequency is divided by (X+1). This register is a reference for 32KHz and 48KHz input bitstream. DAC_CLK_MODE (99) Address: 0x63 Type: RW
et ol s
X
Software Reset: 0x00
Hardware Reset: 0x00
MSB b7 b6 X
od Pr e
ct u
b5 X
)(s
b O
b3 M3
so
Pr ete l
b2 M2 b1 M1
du o
LSB b0 M0
(s) ct
LSB b4 X b3 X b2 X b1 X b0 MODE
This register is used to select the operating mode for OCLK clock signal. If it is set to "1", the OCLK frequency is fixed, and it is mantained to the value fixed by the user even if the sampling frequency of the incoming bitstream changes. It the MODE flag is set to f0f, the OCLK frequency changes, and can be set to (512, 384, 256) * Fs. The default configuration for this mode is 256 * Fs. When this mode is selected,
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STA015
the default OCLK frequency is 12.288 MHz. PLLFRAC_L ([7:0])
MSB b7 PF7 b6 PF6 b5 PF5 b4 PF4 b3 PF3 b2 PF2 b1 PF1 LSB b0 PF0
PLLFRAC_H ([15:8])
MSB b7 PF15 b6 PF14 b5 PF13 b4 PF12 b3 PF11 b2 PF10 b1 PF9 LSB b0 PF8
Address: 0x64 - 0x65 (100 - 101) Type: R/W Software Reset: 0x46 | 0x5B Hardware Reset: 0xNA | 0x5B
The registers are considered logically concatenated and contain the fractional values for the PLL, used to select the internal configuration. After Reset, the values are NA, and the operational setting are done when the MPEG synchronisation is achieved. The following formula describes the relationships among all the STA015 fractional PLL parameters:
1MCLK_Freq OCLK_Freq = ------------ ----------------------------------- M + 1 + FRAC ---------------X+1 N+1 65536
where:
FRAC=256 x FRAC_H + FRAC_L (decimal)
These registers are a reference for 48 / 24 / 12 / 32 / 16 / 8KHz audio. FRAME_CNT_L
MSB b7 FC7
et ol s
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FRAME_CNT_M
MSB b7
ro P e
FC6 b6 FC14 b6 FC22
b6
du
b5
t(s c
-O )
b4 FC4
so b
b3
Pr ete l
du o
(s) ct
LSB b2 FC2 b1 FC1 b0 FC0 FC3
FC5
LSB b5 FC13 b4 FC12 b3 FC11 b2 FC10 b1 FC9 b0 FC8
FC15
FRAME_CNT_H
MSB b7 FC23 b5 FC21 b4 FC20 b3 FC19 b2 FC18 b1 FC17 LSB b0 FC16
STA015
Address: 0x67, 0x68, 0x69 (103 - 104 - 105) Type: RO Software Reset: 0x00 Hardware Reset: 0x00 The three registers are considered logically concatenated and compose the Global Frame Counter as described in the table. It is updated at every decoded MPEG Frame. The registers are reset on both hardware and software reset. AVERAGE_BITRATE Address: 0x6A (106) Type: RO Software Reset: 0x00 Hardware Reset: 0x00
MSB b7 AB7 b6 AB6 b5 AB5 b4 AB4 b3 AB3 b2 AB2 b1 LSB
AVERAGE_BITRATE is a read-only register and it contains the average bitrate of the incoming bitstream divided by two. The value is rounded with an accuracy of 1 Kbit/sec. SOFTVERSION Address: 0x71 (113) Type: RO
MSB b7 SV7 b6 SV6 b5 SV5
After the STA015 boot, this register contains the version code of the embedded software. RUN Type: RW
Address: 0x72 (114)
et ol s
X
Software Reset: 0x00 Hardware Reset: 0x00
MSB b7 b6 X b5 X b4 X b3 X b2 X b1 X LSB b0 RUN
Pr e
du o
t(s c
)b4 SV4
bs O
b3 SV3
ete ol
b2 SV2
ro P
b1 SV1
AB1
du
b0 AB0
(s) ct
LSB b0 SV0
Setting this register to 1, STA015 leaves the idle state, starting the decoding process. The Microcontroller is allowed to set the RUN flag, once all the control registers have been initialized.
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STA015
TREBLE_FREQUENCY_LOW Address: 0x77 (119) Type: RW Software Reset: 0x00 Hardware Reset: 0x00
MSB b7 TF7 b6 TF6 b5 TF5 b4 TF4 b3 TF3 b2 TF2 b1 TF1 LSB b0 TF0
TREBLE_FREQUENCY_HIGH Address: 0x78 Type: RW Software Reset: 0x00 Hardware Reset: 0x00
MSB b7 TF15 b6 TF14 b5 TF13 b4 TF12 b3 TF11
The registers TREBLE_FREQUENCY-HIGH and TREBLE_FREQUENCY-LOW, logically concatenated as a 16 bit wide register, are used to select the frequency, in Hz, where the selected frequency is +12dB respect to the stop band. By setting these registers, the following rule must be kept: Treble_Freq < Fs/2 BASS_FREQUENCY_LOW Address: 0x79 (121) Software Reset: 0x00 Hardware Reset: 0x00
MSB b7 BF7 b6 BF6
BASS_FREQUENCY_HIGH
et ol s
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Address: 0x7A (122) Software Reset: 0x00
Hardware Reset: 0x00
MSB b7 b6 BF14
ro P e
du
b5
BF5
t(s c
-O )
b4 BF4
so b
b3
Pr ete l
b2 b1 TF10 TF9 b2 BF2 b1 BF1
du o
LSB b0 TF8
(s) ct
LSB b0 BF0
BF3
LSB b5 BF13 b4 BF12 b3 BF11 b2 BF10 b1 BF9 b0 BF8
BF15
The registers BASS_FREQUENCY_HIGH and BASS_FREQUENCY_LOW, logically concatenated as a 16 bit wide register, are used to select the frequency, in Hz, where the selected frequency is -12dB respect to the pass-band. By setting the BASS_FREQUENCY registers, the following rules must be kept:
STA015
Bass_Freq <= Treble_Freq Bass_Freq > 0 (suggested range: 20 Hz < Bass_Freq < 750 Hz) Example: Bass = 200Hz Treble = 3kHz TFS
15 0 14 0 13 0 12 0 11 1 10 0 9 1 8 1 7 1 6 0 5 1 4 1 3 1 2 0 1 0 0 0
BFS
15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0 7 1 6 1 5 0 4 0 3 1 2 0 1 0 0 0
TREBLE_ENHANCE Address: 0x7B (123) Software Reset: 0x00 Hardware Reset: 0x00
MSB b7 TE7 b6 TE6 b5 TE5 b4 TE4 b3 TE3
Signed number (2 complement)
This register is used to select the enhancement or attenuation STA015 has to perform on Treble Frequency range at the digital signal. A decrement (increment) of a decimal unit corresponds to a step of attenuation (enhancement) of 1.5dB. The allowed Attenuation/Enhancement range is [-18dB, +18dB].
MSB b7 0 0 0 0
et ol s
0 0 1 1 1 1 1
Pr e
0 0 1 1 1 1 1
b6 0 0 0 0
b5 0 0 0 0
du o
b4 0 0 0 0 0 0 1 0 0 1
t(s c
b3 1 1 1 1 0 0 1
-O )
b2 1 0 0 0 b1 0 1 1 0
so b
LSB b0 0 1 0 1 : : 1 0 1 : : 1 0 0 0
Pr ete l
b2 b1 TE2 TE1
du o
LSB b0 TE0
(s) ct
ENHANCE/ATTENUATION 1.5dB step +18 +16.5 +15 +13.5
0 0 1
0 0 1
+1 0 -1
1 1 1 1
1 1 1 1
0 0 0 0
1 1 1 1
1 1 0 0
+13.5 -15 -16.5 -18
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STA015
BASS_ENHANCE Address: 0x7C (1240 Software Reset: 0x00 Hardware Reset: 0x00
MSB b7 BE7 b6 BE6 b5 BE5 b4 BE4 b3 BE3 b2 BE2 b1 BE1 LSB b0 BE0
Signed number (2 complement) This register is used to select the enhancement or attenuation STA015 has to perform on Bass Frequency range at the digital signal. A decrement (increment) of a decimal unit corresponds to a step of attenuation (enhancement) of 1.5dB. The allowed Attenuation/Enhancement range is [-18dB, +18dB].
MSB b7 0 0 0 0 b6 0 0 0 0 b5 0 0 0 0 b4 0 0 0 0 b3 1 1 1 1 b2 1 0 0 0 b1 0 1 1 0 LSB b0 0 1 0 1 : : 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 ENHANCE/ATTENUATION 1.5dB step +18
+16.5
1 1 1 1
1 1 1 1
1 1 1 1
1 1 1 1
TONE_ATTEN
et ol s
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Address: 0x7D (125) Type: RW Software Reset: 0x00 Hardware Reset: 0x00
MSB b7 TA7 b6 TA6 b5 TA5 b4 TA4 b3 TA3 b2 TA2 b1 TA1 LSB b0 TA0
Pr e
du o
ct
)(s
0 0 0 0 1 1 1 1
b O
1 1 1 0 0
0
so
1 0 1 : : 1 0 0 0
Pr ete l
+15 +1 0 -1 -15
+13.5
du o
(s) ct
+13.5
-16.5 -18
In the digital output audio, the full signal is achieved with 0 dB of attenuation. For this reason, before applying Bass & Treble Control, the user has to set the TONE_ATTEN register to the maximum value of en-
STA015
hancement is going to perform. For example, in case of a 0 dB signal (max. level) only attenuation would be possible. If enhancement is desired, the signal has to be attenuated accordingly before in order to reserve a margin in dB. An increment of a decimal unit corresponds to a Tone Attenuation step of 1.5dB.
MSB b7 0 0 0 0 b6 0 0 0 0 b5 0 0 0 0 b4 0 0 0 0 b3 0 0 1 0 b2 0 0 0 0 b1 0 0 1 1 LSB b0 0 1 0 1 : : 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 1 1 1 0 0 1 0 -15 -16.5 ATTENUATION 1.5dB step 0dB -1.5dB 3dB 4.5dB
ANCILLARY DATA BUFFER Address: 0x7E - 0xB5 (126 - 181) Type: RO Software Reset: 0x00 Hardware Reset: 0x00
The STA015 contains 56 consecutive 8-bit registers corresponding to the maximum number of ancillary data that may be contained in MPEG frame. The ANCCOUNT_L and ANCOUNT_H registers contain the number of ancillary data bits available within the current MPEG frame. To perform ancillary data reading a status register (0xB6 - INTERRUPT_STATUS_REGISTER) is available: bit 0 of this register should be polled by the microcontroller in order to understand when new data are available.
et ol s
ISR
Pr e
du o
t(s c
0x7E ....... ....... ....... 0xB5 0xB6
-O )
so b
....... ....... .......
Pr ete l
-18
du o
(s) ct
ANC_DATA_1
ANC_DATA_56
ISR
Address: 0xB6 (182) Type: R/W Software Reset: 0x00
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STA015
Hardware Reset: 0x00
MSB b7 X b6 X b5 X b4 X b3 X b2 X b1 X LSB b0 0 1
X = don't care; 0 = no ancillary data 1 = Ancillary Data Available The ISR is used by the microcontroller to understand when a new ancillary data block is available. After all ancillary data has been retrieved this bit must be cleared. ADPCM_CONFIG Address: 0xB8 (184) Type: R/W Software Reset: 0x00 Hardware Reset: 0x00
MSB b7 X b6 X b5 X b4 X b3 AA1
This register controls ADPCM engine and how data must be compressed. AFM_EN ADPCM Frame Mode Enable 0 = no frames (raw format) ASM_EN:
1 = select the framed output format for ADPCM encoded data ADPCM Stereo Mode Enable 0 = Disable stereo mode 1 = Enable stereo mode AA0,AA1:
et ol s
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Pr e
AA1 0 0 1 1
ADPCM Algorithm selection The ADPCM encoding/decoding algorithm can be selected according to the following table:
AA0 0 1 0 1 DVI algorithm G723-24 algorithm (24kbp/s) G721 algorithm (32kbp/s) G723-40 algorithm (40kbp/s)
du o
t(s c
-O )
so b
Pr ete l
b2 b1 AA0
du o
LSB b0
(s) ct
ASM_EN
AFM_EN
The above bitrates refers to an 8 KHz 16 bits mono input stream. Please note that 32KHz stereo mode is only available (both in encoding and decoding) with DVI algorithm
STA015
GPSO_ENABLE Address: 0xB9 (185) Type: R/W Software Reset: 0x00 Hardware Reset: 0x00
MSB b7 X b6 X b5 X b4 X b3 X b2 X b1 X LSB b0 GEN
This register enable/disable the GPSO interface. Setting the GEN bit will enable the serial interface for ADPCM data retrieving. Reset GEN bit to disable GPSO interface. GPSO_CONF Address: 0xBA (186) Type: R/W Software Reset: 0x00 Hardware Reset: 0x00
MSB b7 X b6 X b5 X b4 X b3 X
GSP: GPSO clock polarity sing this bit the GPSO_SCKR polarity can be controlled. Clearing GSP bit data on GPSO_DATA line will be provided on the rising edge of GPSO_SCKR (sampling on falling edge). Setting GSP bit data are provided on falling edge of GPSO_SCKR (sampling on rising edge) GRP: GPSO Request Polarity This bit is used to determine the polarity of GPSO_REQ signal. If GRP bit is cleared data are valid on GPSO_REQ signal high. If this bit is set data are valid on GPSO_REQ signal low ADC_ENABLE Type: R/W
Address: 0xBB (187) Software Reset: 0x00
et ol s
X
Hardware Reset: 0x00
MSB b7
od Pr e
b6 X
ct u
b5 X
)(s
b O
so
Pr ete l
b2 X b1 GRP
du o
LSB b0
(s) ct
GSP
LSB b4 X b3 X b2 X b1 X b0 ADCEN
This register controls if the ADPCM data to be encoded comes from A/D interface or from MP3 bitstream input interface. If ADCEN bit is set data to be encoded comes from ADC interface, otherwise data comes from MP3 stream interface
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STA015
ADC_CONF Address: 0xBC (188) Type: R/W Software Reset: 0x00 Hardware Reset: 0x00
MSB b7 X b6 X b5 X b4 ALRCS b3 ALRCP b2 ASCP b1 ADC LSB b0 AIIS
Using this register the ADC input interface can be configured as follow: AIIS: ADC I2S mode 0 = sample word must be aligned with LRCK (no I2S mode) 1 = sample word not aligned with LRCK (I2S compliant mode) ADC: ADC Data Config. 0 = sample word is LSB first 1 = sample word is MSB first ASCP: ADC Serial Clock Polarity 0 = Data is sampled on rising edge 1 = Data is sampled an falling edge ALRCP: ADC Left/Right Clock Polarity ALRCS: ADC Left/Right Clock Start value. This two bits permit to determine Left/Right clock usage according to the following table:
ALRCP 0 1 0 ALRCS 0
et ol s
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1
ro P e
0 1 1
du
t(s c
-O )
so b
Pr ete l
du o
(s) ct
LEFT/RIGHT COUPLE (Data3, Data4) (2, 3) (2, 3) (3, 4)
(Data1, Data2) (0, 1) (0, 1) (1, 2)
LRCK
DATA
DATA 0
DATA 1
DATA 2
DATA 3
DATA 4
D99AU1065
STA015
ADPCM_FRAME_SIZE Address: 0xBD (189) Type: R/W Software Reset: 0x13 Hardware Reset: 0x00
MSB b7 AFS7 b6 AFS6 b5 AFS5 b4 AFS4 b3 AFS3 b2 AFS2 b1 AFS1 LSB b0 AFS0
The ADPCM frame size may be adjusted to match a trade-off between the bitrate overhead and the frame length. The frame size (in bytes) is calculated as follow: FRAME size = (ADPCM_FRAME_SIZE * 90) +108 The frame starts with a 12 bytes header: - 6 bytes for DVI algorithm - 96 bytes for G726 pack algorithms ADPCM_INT_CFG Address: 0xBE (190) Type: R/W Software Reset: 0x0B Hardware Reset: 0x00
MSB b7 INTL6 b6 INTL5 b5 INTL4 b4 INTL3
Using this register the ADPCM interrupt capability can be properly configured. INTL0 - INTL6 Interrupt Length he interrupt length can be programmed, using this bits, from 0 up to 128 system clock cycles GPIO_CONF Address: 0xBF (191) Type: R/W Software Reset: 0x00
Hardware Reset: 0x00
et ol s
X
MSB b7
od Pr e
b6 X
ct u
b5 X
)(s
b4 X
b O
b3
INTL2
so
Pr ete l
b2 b1 INTL1 INTL0
du o
LSB b0 X
(s) ct
LSB b3 X b2 X b1 GOSP b0 GISP
This register controls how data are strobed on the GPIO interface. GISP: GPIO Strobe Polarity in INPUT mode 0 = data strobed an falling edge 1 = data strobed on rising edge GOSP: GPIO Strobe Polarity in OUTPUT mode 0 = non inverted 1 = inverted
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STA015
ADC_WLEN Address: 0xC0 (192) Type: R/W Software Reset: 0x0F Hardware Reset: 0x0F
MSB b7 X b6 X b5 X b4 AWL4 b3 AWL3 b2 AWL2 b1 AWL1 LSB b0 AWL0
To select ADC word length AWL4 through AWL0 bits can be used. This 5 bit value must contain the size of the significant data bits minus one. ADC_WPOS Address: 0xC1 (193) Type: R/W Software Reset: 0x00 Hardware Reset: 0x00
MSB b7 X b6 X b5 X b4 AWP4 b3 AWP3
These bits specify the position of the sample word referred to the LRCK slot boundary.
Bit AWP0 thru AWP4 must be programmed with the number of bits to ignore after the sample word. ADPCM_SKIP_FRAME Address: 0xC2 (194) Type: R/W Software Reset:0x00 Hardware Reset: 0x00
MSB b7
et ol s
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ASF7
This register is useful when decoding ADPCM frame-based streams in order to skip the specified number of frames. The content of the register will automatically be decremented on each new frame and the skip process will continue until the content reaches zero.
Pr e
b6
du o
t(s c
-O )
b4 ASF4
so b
Pr ete l
b2 b1 AWP2 AWP1
du o
LSB b0
(s) ct
AWP0
LSB b3 ASF3 b2 ASF2 b1 ASF1 b0 ASF0
b5
ASF6
ASF5
STA015
6.2 I/O CELL DESCRIPTION (pinout relative to TQFP44 package) 1) CMOS Tristate Output Pad Buffer, 4mA, with Slew Rate Control / Pin numbers 2, 4, 13, 27, 33, 42, 44
EN Z A
D98AU904
OUTPUT PIN Z
MAX LOAD 100pF
2) CMOS Bidir Pad Buffer, 4mA, with Slew Rate Control / Pin numbers 3, 31
EN IO A
INPUT PIN IO
CAPACITANCE 5pF
OUTPUT PIN IO
MAX LOAD 100pF
ZI
D98AU905
3) CMOS Inpud Pad Buffer / Pin numbers 24, 26, 32, 34, 36, 40
A Z
INPUT PIN A
D98AU906
4) CMOS Inpud Pad Buffer with Active Pull-Up / Pin numbers 22, 25, 28, 38
A
5) CMOS Schmitt Trigger Bidir Pad Buffer with active Pull-up, 4mA, with slew rate control/ Pin numbers 14, 16, 18, 20, 35, 37, 39, 41, 43
et ol s
EN
ro P e
du
t(s c
Z
D98AU907
-O )
so b
A
Pr ete l
du o
(s) ct
CAPACITANCE 3.5pF
INPUT PIN
CAPACITANCE 3.5pF
IO
INPUT PIN IO
CAPACITANCE 5pF
OUTPUT PIN IO
MAX LOAD 100pF
A
ZI
D00AU1150
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STA015
6.3 TIMING DIAGRAMS 6.3.1 Audio DAC Interface a) OCLK in output. The audio PLL is used to clock the DAC
OCLK (OUTPUT)
SDO tsdo SCKT tsckt LRCLK tlrclk
D98AU969
tsdo = 3.5 + pad_timing (Cload_SDO) - pad_timing (Cload_ OCLK) tsckt = 4 + pad_timing (Cload_SCKT) - pad_timing (Cload_ OCLK) tlrckt = 3.5 + pad_timing (Cload_LRCCKT) - pad_timing (Cload_ OCLK) Pad-timing versus load
Load (pF) 25 50 75 100
Cload_XXX is the load in pF on the XXX output. pad_timing (Cload_XXX) is the propagation delay added to the XXX pad due to the load. b) OCLK in input.
et ol s
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Pr e
OCLK (INPUT)
du o
t(s c
thi tsdo
-O )
tlo
so b
Pad_timing 2.90ns 3.82ns 4.68ns
Pr ete l
du o
(s) ct
5.52ns
SDO
SCKT tsckt LRCLK tlrclk toclk
D98AU970
STA015
Thi min = 3ns Tlo min = 3ns Toclk min = 25ns tsdo = 5.5 + pad_timing (Cload_SDO) ns tsckt = 6 + pad_timing (Cload_SCKT) ns tlrckt = 5.5 + pad_timing (Cload_LRCKT) ns 6.3.2 Bitstream input interface (SDI, SCKR, BIT_EN) SCL_POL = 0
BIT_EN t_biten tsckr_min_period SCKR tsckr_min_low tsckr_min_high SCLK_POL=0 t_biten
SDI
IGNORED
VALID
IGNORED
tsdi_setup
tsdi_hold
D98AU971A
6.3.3 Bitstream input interface (SDI, SCKR, BIT_EN) SCL_POL = 1
BIT_EN t_biten tsckr_min_period SCKR tsckr_min_high t_biten
SDI
IGNORED
IGNORED
tsdi_setup_min = 2ns tsdi_hold_min = 3ns tsckr_min_hi = 10ns tsckr_min_low = 10ns t_biten (min) = 2ns
tsckr_min_lperiod = 50ns
et ol s
6.3.4 SRC_INT
ro P e
SRC_INT
uc d
s) t(
-O
tsdi_setup
VALID
so b
tsckr_min_low tsdi_hold
Pr ete l
IGNORED
D99AU1038
du o
(s) ct
SCLK_POL=4
This is an asynchronous input used in "broadcast' mode. SRC_INT is active low
t_src_hi t_src_low
D98AU972
t_src_low min duration is 50ns (1DSP clock period) t_src_high min duration is 50ns (1DSP clock period)
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STA015
6.3.5 XTI,XTO and CLK_OUT timings
XTI (INPUT) thi tlo
XTO txto CLK_OUT tclk_out
D98AU973
txto = 1.40 + pad_timing (Cload_XTO) ns tclk_out = 4 + pad_timing (Cload_CLK_OUT) ns
Note: In "multimedia" mode, the CLK_OUT pad is DATA_REQ. In that case, no timing is given between the XTI input and this pad.
6.3.6 RESET The Reset min duration (t_reset_low_min) is 100ns
RESET
treset_low_min
6.4 CONFIGURATION FLOW EXAMPLE
HW RESET
set
PCM-DIVIDER
set
PCM-CONF.
et ol s
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ro P e
du
t(s c
set set
set { PLL FRAC_441_H, PLL FRAC_441_L, PLL FRAC_H, PLL FRAC_L }
-O )
PCM OUTPUT INTERFACE CONFIGURATION
so b
Pr ete l
D98AU974
du o
(s) ct
PLL CONFIGURATION FOR: * { 48, 44.1, 32 29, 22.05, 16 12, 11.025, 8 } KHz * MULTIMEDIA MODE see {TAB 5 to TAB12}
set { MFS DF_441, MFSDF }
PLL CTRL
SCKR_POL
INPUT SERIAL CLOCK POLARITY CONFIGURATION
set
CHIP_MODE
SELECT OPERATIONAL MODE DATA REQUEST POLARITY CONFIGURATION
set
REQ_POL
set
RUN
D00AU1146A
STA015
Table 2. PLL Configuration Sequence For 10MHz Input Clock 256 Oversapling Clock
REGISTER ADDRESS 6 11 97 80 101 82 100 81 5 NAME reserved reserved MFSDF (x) MFSDF-441 PLLFRAC-H PLLFRAC-441-H PLLFRAC-L PLLFRAC-441-L PLLCTRL VALUE 18 3 15 16 169 49 42 60 161
Table 4. PLL Configuration Sequence For 14.31818MHz Input Clock 256 Oversapling Rathio
REGISTER ADDRESS 6 11 97 80 101 82 100 81 5 NAME reserved reserved MFSDF (x) MFSDF-441 PLLFRAC-H PLLFRAC-441-H PLLFRAC-L PLLFRAC-441-L VALUE 12 3 15 16 187 103 58
Table 3. PLL Configuration Sequence For 10MHz Input Clock 384 Oversapling Rathio
REGISTER ADDRESS 6 11 97 80 101 82 NAME reserved reserved MFSDF (x) MFSDF-441 VALUE 17
Table 5.
PLL Configuration Sequence For 14.31818MHz Input Clock 384 Oversapling Rathio
REGISTER ADDRESS 6
PLLFRAC-H
100
et ol s
81 5
ro P e
PLLFRAC-441-H
du
t(s c
9
3
-O )
so b
11 97 80 101 82 100 81 5
Pr ete l
NAME reserved reserved MFSDF (x) MFSDF-441 PLLFRAC-H PLLFRAC-441-H PLLFRAC-L PLLFRAC-441-L PLLCTRL
PLLCTRL
du o
119 161
(s) ct
VALUE 11 3 6 7 3 157 211 157 161
10
110 160 152 186 161
PLLFRAC-L PLLFRAC-441-L PLLCTRL
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STA015
Table 6. PLL Configuration Sequence For 14.31818MHz Input Clock 512 Oversapling Rathio
REGISTER ADDRESS 6 11 97 80 101 82 100 81 5 NAME reserved reserved MFSDF (x) MFSDF-441 PLLFRAC-H PLLFRAC-441-H PLLFRAC-L PLLFRAC-441-L PLLCTRL VALUE 11 3 6 7 3 157 211 157 161
Table 8. PLL Configuration Sequence For 14.7456MHz Input Clock 384 Oversapling Rathio
REGISTER ADDRESS 6 11 97 80 101 82 100 81 5 NAME reserved reserved MFSDF (x) MFSDF-441 PLLFRAC-H PLLFRAC-441-H PLLFRAC-L PLLFRAC-441-L PLLCTRL VALUE 10 3 8 9 64 124 0
Table 7. PLL Configuration Sequence For 14.7456MHz Input Clock 256 Oversapling Rathio
REGISTER ADDRESS 6 11 97 80 101 82 100 81 5 NAME reserved reserved MFSDF (x) MFSDF-441 PLLFRAC-H VALUE 12 3
Table 9.
PLL Configuration Sequence For 14.7456MHz Input Clock 512 Oversapling Rathio
REGISTER ADDRESS 6
PLLFRAC-441-H PLLFRAC-L
et ol s
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ro P e
PLLFRAC-441-L PLLCTRL
du
t(s c
16 85 4 85 0
15
-O )
so b
11 97 80 101 82 100 81 5
Pr ete l
NAME reserved reserved MFSDF (x) MFSDF-441 PLLFRAC-H PLLFRAC-441-H PLLFRAC-L PLLFRAC-441-L PLLCTRL
du o
0 161 VALUE 9 2 5 6 0 184 0 0 161
(s) ct
161
STA015
6.5 STA015 CONFIGURATION FILE FORMAT The STA015 Configuration File is an ASCII format. An example of the file format is the following: 58 1 42 4 128 15 ............ It is a sequence of rows and each one can be interpreted as an I2C command. The first part of the row is the I2C address (register) and the second one is the I2C data (value). To download the STA015 configuration file into the device, a sequence of write operation to STA015 I2C interface must be performed. The following program describes the I2C routine to be implemented for the configuration driver:
42
4
I C REGISTER VALUE I2C SUB-ADDRESS
2
D98AU976
STA015 Configuration Code (pseudo code) download cfg - file { fopen (cfg_file); fp:=1; do { I2C_start_cond; I2C_write_dev_addr; I2C_write_data (fp); I2C_stop_cond; fp++; } while (!EDF) } /*set file pointer to first row */
/* generate I2C start condition for STA015 device address */ /* write STA015 device address /* write data
I2C_write_subaddress (fp); /* write subaddress
et ol s
Note: 1. STA015 is a device based on an integrated DSP core. Some of the I2C registers default values are loaded after an internal DSP boot operation. The bootstrap time is 60 micro second. Only after this time lenght, the data in the register can be considered stable . 2. Refer also to the application note AN1250
ro P e
du
t(s c
/* generate I2C stop condition /* update pointer to new file row
-O )
so b
Pr ete l
du o
*/ */ */ */ */ */ */
(s) ct
/* repeat until End of File /* End routine
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STA015
DIM. MIN. A a1 b b1 C c1 D E e e3 F L S 7.4 0.4 17.7 10 0.1 0.35 0.23
mm TYP. MAX. 2.65 0.3 0.49 0.32 0.5 45 (typ.) 18.1 10.65 1.27 16.51 7.6 1.27 0.291 0.016 0.697 0.394 0.004 0.014 0.009 MIN.
inch TYP. MAX. 0.104 0.012 0.019 0.013 0.020
OUTLINE AND MECHANICAL DATA
0.713 0.419 0.050 0.65 0.299 0.050
8 (max.)
et ol s
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Pr e
du o
t(s c
-O )
so b
Pr ete l
SO-28
du o
(s) ct
STA015
mm DIM. MIN. A A1 A2 B C D D1 D3 E E1 E3 e L L1 k 0.45 11.80 9.80 0.05 1.35 0.30 0.09 11.80 9.80 12.00 10.00 8.00 12.00 10.00 8.00 0.80 0.60 1.00 0.75 0.018 12.20 10.20 0.464 0.386 1.40 0.37 TYP. MAX. 1.60 0.15 1.45 0.45 0.20 12.20 10.20 0.002 0.053 0.012 0.004 0.464 0.386 MIN.
inch TYP. MAX. 0.063 0.006 0.055 0.015 0.057 0.018 0.008 0.472 0.394 0.315 0.472 0.394 0.315 0.031 0.024 0.039 0.030 0.480 0.401 0.480 0.401
OUTLINE AND MECHANICAL DATA
TQFP44 (10 x 10 x 1.4mm)
0(min.), 3.5(typ.), 7(max.)
D D1
33 34
et ol s
od Pr e
44 1
ct u
s) (
23
-O
so b
Pr ete l
A1
0.10mm .004 Seating Plane
du o
A A2
(s) ct
22
E1
B
12 11
E
B
C
e
L
K
TQFP4410
0076922 D
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STA015
mm DIM. MIN. A A1 A2 b D D1 e E E1 f 0.350 0.400 1.100 0.500 8.000 5.600 0.800 8.000 5.600 1.200 TYP. MAX. 1.700 0.450 0.014 MIN.
inch TYP. MAX. 0.067 0.016 0.043 0.20 0.315 0.220 0.031 0.315 0.220 0.047 0.018
OUTLINE AND MECHANICAL DATA
Body: 8 x 8 x 1.7mm
BALL 1 IDENTIFICATION D1 8 A B C D 7 6 5 4 f
et ol s
E F G H
ro P e
e
du
3
2
1
t(s c
f E1
-O )
A
so b
0.15
Pr ete l
LFBGA64
D
du o
(s) ct
A1
E
b (64 PLACES) A2
LFBGA64M
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STA015
7.0 REVISION HISTORY
Date 16-Mar-2004 26-Apr-2010 Revision 4 5 Changes Changed block diagram pin 28, changed legalcy Major revision for revalidation process
et ol s
Pr e
du o
t(s c
-O )
so b
Pr ete l
du o
(s) ct
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STA015
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et ol s
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Pr e
du o
t(s c
-O )
so b
Pr ete l
du o
(s) ct
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